On-chip network design method, device, electronic device and storage medium

Abstract

An on-chip network design method provided by an embodiment of the present application can determine the performance requirements of the on-chip network to be designed; determine the architectural parameters corresponding to the on-chip network based on the performance requirements; for each routing node of the on-chip network, decompose the processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage; construct a first timing model based on the architectural parameters and the number of clock cycles corresponding to all routing nodes; verify the first timing model, and if the verification passes, design the on-chip network based on the first timing model, which can improve the efficiency of designing the on-chip network and reduce the cost of designing the on-chip network.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a network-on-chip (NOC) design method, device, electronic device, and storage medium. Background Art

[0002] Against the backdrop of continuous breakthroughs in integrated circuit technology, systems-on-chip (SoCs) are transitioning toward highly heterogeneous integration, requiring the integration of more heterogeneous components with diverse functions. As the core communication architecture for SoCs, the increasing complexity of networks-on-chip (NOCs) is driving exponential growth in the scale of intra-chip communications, placing higher demands on their design.

[0003] In existing technologies, the design of on-chip networks usually relies on the designer's experience. Designers establish the on-chip network architecture based on their understanding of the technology and judge whether the on-chip network architecture meets expectations. If it seriously does not meet expectations, the previous work needs to be redone, which is risky and costly. Summary of the Invention

[0004] The embodiments of the present application provide a method, device, electronic device, and storage medium for designing a network on a chip (NOC), which can reduce the risks and costs in the process of designing a NOC architecture and improve the efficiency of designing a NOC architecture.

[0005] In a first aspect, an embodiment of the present application discloses a method for designing a network on chip, the method comprising:

[0006] Determine the performance requirements of the network on chip to be designed;

[0007] Determining architecture parameters corresponding to the on-chip network according to the performance requirements;

[0008] For each routing node of the network on chip, decompose the processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage;

[0009] Constructing a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes;

[0010] The first timing model is verified, and if the verification passes, a network on chip is designed according to the first timing model.

[0011] Optionally, constructing a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes includes:

[0012] For each routing node, a timing model of a single routing node is constructed based on the number of clock cycles corresponding to each pipeline stage;

[0013] Constructing a link timing model according to the data transmission cycle corresponding to each link in the on-chip network;

[0014] A first timing model is constructed according to the topological structure of the on-chip network, the timing models corresponding to the respective routing nodes, and the link timing models corresponding to the respective links.

[0015] Optionally, verifying the first timing model includes:

[0016] Obtaining data flow of the first time series model in at least one data mode;

[0017] For each data pattern, injecting the data traffic into the first timing model for simulation to determine the current first network performance of the first timing model; the model parameters of the first timing model adopt the first configuration parameter group;

[0018] According to the first network performance, the first configuration parameter group is adjusted, and the next round of simulation is started. The simulation is stopped when the first network performance meets a preset condition.

[0019] Optionally, adjusting the first configuration parameter group according to the first network performance includes:

[0020] Determining a first flow corresponding to each link in the first timing model;

[0021] In the case that the distribution of the first traffic on each link is uneven, the routing path for communication between each routing node is adjusted by adjusting the hash seed in the routing distribution algorithm.

[0022] Optionally, adjusting the first configuration parameter group according to the first network performance includes:

[0023] Determining the input flow of each routing node of the first timing model;

[0024] Determining at least one first routing node according to the input traffic and a preset threshold;

[0025] For each first routing node, a first configuration parameter corresponding to the first routing node is adjusted.

[0026] Optionally, determining architecture parameters corresponding to the network on chip according to the performance requirement includes:

[0027] Determining a preset range corresponding to each architecture parameter based on the performance requirement; the architecture parameter includes at least one of a topology structure, a flow control mechanism, and an internal structure of a routing node;

[0028] According to the respective impacts of the topology structure, the flow control mechanism, and the internal structure of the routing node on the performance requirement, a first topology structure, a first flow control mechanism, and a first internal structure of the routing node are selected from the preset range.

[0029] In a second aspect, an embodiment of the present application discloses an on-chip network design device, the device comprising:

[0030] A requirement determination module, used to determine the performance requirements of the on-chip network to be designed;

[0031] A parameter determination module, configured to determine architecture parameters corresponding to the on-chip network according to the performance requirements;

[0032] a decomposition module, configured to decompose, for each routing node of the network on chip, a processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage;

[0033] A construction module, configured to construct a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes;

[0034] The design module is configured to verify the first timing model, and if the verification is successful, design an on-chip network according to the first timing model.

[0035] Optionally, the building blocks include:

[0036] The first construction submodule is used to construct a timing model of a single routing node according to the number of clock cycles corresponding to each pipeline stage for each routing node;

[0037] A second construction submodule is configured to construct a link timing model according to a data transmission period corresponding to each link in the on-chip network;

[0038] The third construction submodule is configured to construct a first timing model according to the topological structure of the on-chip network, the timing models corresponding to the respective routing nodes, and the link timing models corresponding to the respective links.

[0039] In a third aspect, an embodiment of the present application discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned on-chip network design method.

[0040] In a fourth aspect, an embodiment of the present application discloses a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the aforementioned on-chip network design method.

[0041] The embodiments of the present application include the following advantages:

[0042] The embodiment of the present application provides a method for designing a network on chip (NOC), which can determine the performance requirements of the NOC to be designed; determine the corresponding architecture parameters of the NOC based on the performance requirements; for each routing node of the NOC, decompose the processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage; construct a first timing model based on the architecture parameters and the number of clock cycles corresponding to all routing nodes; verify the first timing model, and if the verification passes, design the NOC based on the first timing model. By performing system-level modeling before actually establishing the NOC architecture, simulating the system behavior of each component in the entire NOC and the number of clock cycles consumed by the behavior, it is possible to quickly determine whether there is a deviation between the performance of the NOC architecture and the expected target, and modify and verify the working parameters of the NOC architecture to obtain a NOC model that meets the performance requirements, thereby improving the efficiency of designing the NOC and reducing the cost of designing the NOC. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0044] Figure 1 is a flowchart of the steps of an embodiment of a method for designing a network on a chip according to the present invention;

[0045] Figure 2 It is a structural block diagram of a network-on-chip design device of the present invention;

[0046] Figure 3 This is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0048] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0049] Method Example

[0050] Reference Figure 1 , shows a flowchart of an embodiment of a method for designing a network on chip according to the present invention, wherein the method may specifically include the following steps:

[0051] Step 101: Determine the performance requirements of the network on chip to be designed;

[0052] Step 102: Determine architecture parameters corresponding to the on-chip network according to the performance requirements;

[0053] Step 103: For each routing node of the network on chip, decompose the processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage;

[0054] Step 104: construct a first timing model based on the architecture parameters and the number of clock cycles corresponding to all routing nodes;

[0055] Step 105: Verify the first timing model. If the verification passes, design a network on chip based on the first timing model.

[0056] The NoC design method provided in the embodiments of this application performs system-level modeling of the NoC before register transfer level (RTL) design. This system-level model quickly verifies the feasibility and performance of the NoC architecture, reducing the risk of later rework. System-level modeling primarily describes the overall system behavior, such as data flow and performance metrics, while RTL design primarily describes data transfer and logic operations between registers, requiring clear connections between clocks, registers, and combinational logic. System-level modeling verifies the feasibility of the NoC architecture model, for example, whether the topology is reasonable and whether the routing algorithm is deadlock-free. System-level modeling uses high-level languages ​​such as C, SystemC, and Python to describe transaction-level behavior. RTL design, on the other hand, uses hardware description languages ​​such as VHDL and Verilog to describe register-level behavior. System-level modeling facilitates architecture verification, while RTL design facilitates hardware implementation. System-level modeling serves as a preview of RTL design, allowing rapid verification of the feasibility and performance of the designed NoC architecture using high-level languages, reducing the risk of later rework. RTL design is the implementation step, transforming abstract system-level behavior into a hardware description. After completing the RTL code, modifying the architecture's topology or routing algorithm may require rewriting a large amount of code, which is costly. System-level modeling using high-level languages, on the other hand, allows for rapid enumeration and verification of multiple architectural solutions through parameterized design. Therefore, performing system-level modeling before RTL design and verifying the resulting model can quickly verify the feasibility and performance of the designed NoC architecture, improving the efficiency of NoC design and reducing the cost of the process.

[0057] Among them, performance requirements design the fundamental goals and constraints of the on-chip network. Performance requirements define the quantitative indicators of data transmission capabilities that the on-chip network must meet, which are proposed by upper-layer applications. Upper-layer applications can be multi-core processors, AI accelerators, and System on a Chip (SoC). Specifically, performance requirements can include at least one of the following: throughput, latency, and power consumption. Different application scenarios have different performance requirements for on-chip networks. For example, in high-performance computing scenarios such as scientific computing and tensor computing and communication of AI chips, the performance requirements for on-chip networks are high throughput, low latency, and support for parallel data-intensive tasks. In real-time system scenarios such as autonomous driving chips, the performance requirements for on-chip networks are to limit the upper limit of latency, high reliability, and ensure the determinism of event response.

[0058] Architectural parameters are parameters corresponding to the topology and functional components of a network on a chip (NoC). They are used to construct the physical and logical framework of the NoC. Selecting different parameter combinations directly affects the performance, area, and power consumption of the NoC. Architectural parameters can include at least one of the following: topology, routing algorithm, flow control mechanism, router microarchitecture, link characteristics, and network interface. The topology defines how IP modules are interconnected on the chip. IP modules can include computing cores, memory, input / output (I / O), and other systems. Flow control refers to the strategy for allocating buffer and link resources between routing nodes to prevent congestion and deadlock. Router microarchitecture refers to the design and workflow of functional units within a single routing node.

[0059] Before designing a NoC, you can thoroughly analyze the target application scenario, quantify the bandwidth required for each critical path or the entire network, and define latency requirements for key communications. Set power budgets and energy efficiency targets, determine scalability requirements, and assess reliability and fault tolerance requirements. These performance requirements can be documented in a NoC performance requirements specification.

[0060] Decomposing the processing flow of a routing node into at least one pipeline stage involves breaking down the tasks required by the router to process a data slice (flit) into logical steps. Each logical step is mapped to a specific pipeline stage. A logical step may take one or more clock cycles, or multiple steps may be combined into a single cycle. Logic synthesis and timing analysis are performed on each pipeline stage to determine the target number of clock cycles required for each stage to complete its function. In most cases, the target is a cycles per instruction (CPI) of 1 for each pipeline stage (i.e., CPI = 1). However, in some low-power or high-frequency designs, complex stages with long critical paths may require multiple clock cycles (CPI > 1). By integrating architectural parameters with detailed pipeline timing information for each routing node, a first-order timing model is constructed that predicts the timing behavior of network communication. This first-order timing model simulates the behavior of each component in the on-chip network at each clock cycle. Establishing the first timing model may include the following aspects: establishing the topology of the entire on-chip network, modeling the delay of the on-chip network, such as calculating the single-hop delay and the total delay of the multi-hop path, and modeling the delay of the on-chip network, for example, the throughput of the entire on-chip network is equal to the product of the sum of the bandwidths of each link and the bandwidth utilization.

[0061] Verification of the first timing model primarily involves verifying the routing algorithm, timing, power consumption, and throughput. The correctness of the routing algorithm and the timing are verified to meet performance requirements. For example, end-to-end latency is less than or equal to the expected target value. Dynamic and static power consumption on the network-on-chip (NoC) is evaluated using power analysis tools. Specifically, the target workload is used to drive the first timing model, and key performance metrics of the first timing model are measured, such as end-to-end latency, bandwidth utilization, critical path latency, buffer occupancy, and power consumption estimation. The measurement results are rigorously compared to the performance requirements specifications. Verification is considered passed if all key requirements are met in simulation.

[0062] In an embodiment of the present application, the performance requirements of the on-chip network to be designed can be determined; based on the performance requirements, the corresponding architectural parameters of the on-chip network can be determined; for each routing node of the on-chip network, the processing flow of the routing node is decomposed into at least one pipeline stage, and the number of clock cycles corresponding to each pipeline stage is determined; based on the architectural parameters and the number of clock cycles corresponding to all routing nodes, a first timing model is constructed; the first timing model is verified, and if the verification passes, the on-chip network is designed based on the first timing model. By performing system-level modeling before actually establishing the on-chip network architecture, simulating the system behavior of each component in the entire on-chip network and the number of clock cycles consumed by the behavior, it is possible to quickly determine whether there is a deviation between the performance of the on-chip network architecture and the expected target, and modify and verify the working parameters of the on-chip network architecture to obtain an on-chip network model that meets the performance requirements, thereby improving the efficiency of designing the on-chip network and reducing the cost of designing the on-chip network.

[0063] Optionally, constructing a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes includes:

[0064] Step S11: For each routing node, a timing model of a single routing node is constructed according to the number of clock cycles corresponding to each pipeline stage;

[0065] Step S12: constructing a link timing model according to the data transmission period corresponding to each link in the on-chip network;

[0066] Step S13: construct a first timing model according to the topological structure of the on-chip network, the timing models corresponding to the respective routing nodes, and the link timing models corresponding to the respective links.

[0067] Specifically, the tasks required by a router to process a data flit are broken down into logical steps. Typical steps include: buffer write (BW), route calculation (RC), virtual channel allocation (VA), switch allocation (SA), and switch traversal (ST). The number of clock cycles consumed by route calculation, switch arbitration, link traversal, and buffer read and write operations is determined.

[0068] A single-node timing model must specify the total latency of data passing through that node. Based on the number of pipeline stages and the CPI per stage, the minimum or typical hop latency (HopLatency) required for a flit to traverse a router (from input to output) is calculated to establish a routing node latency model. For example, for a four-stage pipeline with a CPI of 1 per stage, the minimum traversal latency is 4 clock cycles (excluding link latency). Based on the link length and physical characteristics (or a simple per-hop link latency estimate, such as 1 or 2 cycles), the time required for a flit to transmit on the link (in clock cycles) is calculated to establish a link timing model. Flow control (such as credit mechanisms and VC allocation contention) and the time a flit waits in the input buffer due to network congestion can also be considered to establish a queuing delay model. Furthermore, the total latency of a packet from the source IP address to the destination IP address is estimated by combining the source / destination network interface latency, the number of router hops along the path, the router latency per hop, the link latency per hop, and the queuing delay along the path to establish an end-to-end latency model. Based on the link bandwidth, the router crossbar bandwidth, and the flow control mechanism, the maximum saturated throughput of the network and the available bandwidth of a specific path are estimated to establish a throughput / bandwidth model.

[0069] In an embodiment of the present application, for each routing node, a timing model for a single routing node is constructed based on the number of clock cycles corresponding to each pipeline stage; a link timing model is constructed based on the data transmission cycle corresponding to each link in the on-chip network; and a first timing model is constructed based on the topological structure of the on-chip network, the timing model corresponding to each routing node, and the link timing model corresponding to each link. By establishing the timing models corresponding to the routing nodes and links respectively, and finally establishing the first timing model based on the topological structure, a first timing model that is closer to real-world application scenarios can be established.

[0070] Optionally, verifying the first timing model includes:

[0071] Step S21: Obtain data flow of the first time series model in at least one data mode;

[0072] Step S22: For each data pattern, inject the data traffic into the first timing model for simulation to determine the current first network performance of the first timing model; the model parameters of the first timing model adopt the first configuration parameter group;

[0073] Step S23: Adjust the first configuration parameter group according to the first network performance, and enter the next round of simulation until the first network performance meets the preset conditions, and then stop the simulation.

[0074] Data patterns refer to typical data transmission patterns encountered by chips in real-world application scenarios, such as matrix operations, memory reads and writes, and video processing. The first timing model is designed based on the project being worked on, which defines the target chip's application scenarios and core functions. Based on the project requirements, the typical data transmission characteristics of the actual chip under different operating scenarios are captured. These characteristics are abstracted into data patterns. For example, if the project being worked on is designing an autonomous driving chip, data patterns may include sensor fusion mode, neural network inference mode, and emergency control mode. Data traffic refers to the transmission characteristics of data packets under specific data patterns. Examples include traffic distribution between nodes, packet size, and bursty or periodic traffic. Data traffic can be obtained through statistical generation based on actual application scenarios or theoretical modeling. For example, a traffic generation tool can generate a sequence of data packets. After acquiring the data traffic, the traffic is injected into the input port of the first timing model through a network interface to simulate the communication behavior of a real computing unit.

[0075] After injecting data traffic into the first timing model, traffic simulation is run through the simulation tool to evaluate the network performance of the on-chip network under a specific configuration parameter group. The first network performance refers to a key indicator for measuring the overall efficiency of the first timing model, and is not the local performance in the first timing model. The first network performance may include: at least one of: latency, throughput, degree of long-tail effect, energy consumption, and congestion level. It should be noted that in the process of constructing the first timing model, some parameters are set to default according to the requirements of the project to be processed. For example, according to the computing power requirements of the project to be processed, the number of CPU cores and the capacity of the cache are set to fixed values. The first configuration parameter group refers to a set of adjustable parameters in the first timing model, mainly including parameters that can affect the communication capability of the first timing model. The first configuration parameter group may include: network scale, link width, buffer depth, number of virtual channels, priority scheduling rules, etc.

[0076] It should be noted that adjusting the configuration parameter group based on network performance is a multi-objective optimization problem. It requires considering the correlation between performance indicators and parameters, identifying configuration parameters with high correlation to performance indicators, and adjusting these parameters accordingly. For example, latency and buffer size are highly correlated, while throughput and link bandwidth are highly correlated. After modifying the parameters, resimulate to verify performance improvement and avoid local optimality. If multiple network performance indicators conflict, for example, if reducing latency results in increased energy consumption, trade-offs should be made based on the expected goals and core requirements of the project being addressed. Furthermore, when adjusting the parameters in the configuration parameter group, adjustments can be made within a pre-set parameter range. For example, if the preset number of virtual channels is between 2 and 14, then when adjusting the number of virtual channels, only those between 2 and 14 should be selected. The preset number of virtual channels can be set based on experience.

[0077] The data traffic of each data mode is injected into the first timing model in turn, and each data mode is simulated independently. For each data mode, the configuration parameter group of the first timing model is adjusted at least once, and after each adjustment, it is verified whether the network performance of the model reaches the expected target corresponding to the data mode. When the network performance meets the preset conditions, the simulation is stopped to obtain the second configuration parameter group corresponding to the data mode, that is, the optimal configuration parameter group under limited conditions. Among them, each data mode has its own corresponding preset conditions, and the preset conditions refer to the requirements for the network performance of the model under the data mode, such as throughput greater than or equal to the preset throughput threshold, and delay less than or equal to the preset time threshold. It should be noted that the expected goals defined by the project to be processed include the preset conditions under each data mode.

[0078] After obtaining the optimal configuration parameter group for each data mode of the first timing model, the priority of each data mode in the project to be processed is weighed, and a final configuration parameter group is determined based on the priority. The chip is then designed based on the final configuration parameter group. The configuration parameter group for a particular data mode can be determined as the reference configuration parameter group for the final chip design. Alternatively, a compromise configuration parameter group can be obtained by comprehensively considering configuration parameter groups for multiple data modes, and this configuration parameter group can be determined as the reference configuration parameter group for the final chip design.

[0079] In an embodiment of the present application, an initial first model is constructed according to performance requirements, and data traffic corresponding to multiple data modes is obtained. The data traffic corresponding to each data mode is input into the first timing model in sequence, and each data mode is simulated independently. During the simulation process, the network performance of the first timing model is evaluated, and the configuration parameter group in the first timing model is adjusted until the network performance meets the preset conditions corresponding to the data mode, and the optimal parameter combination under the data mode is obtained. Compared with engineers determining the design parameters of the on-chip network based on experience, the limitations of traditional design methods are solved through data-driven and system-level verification, which can cope with the on-chip network design of rich and complex scenarios, and can design an on-chip network that better meets the needs of real application scenarios.

[0080] Optionally, adjusting the first configuration parameter group according to the first network performance includes:

[0081] Step S31: determining a first flow corresponding to each link in the first timing model;

[0082] Step S32: When the distribution of the first traffic on each link is uneven, the routing paths for communication between each routing node are adjusted by adjusting the hash seed in the routing distribution algorithm.

[0083] A link is a communication channel connecting two adjacent routing nodes, responsible for transmitting data between them. A routing allocation algorithm determines the logical rules for the path a data packet takes from a source routing node to a destination routing node. For example, hash-based multipath routing maps data packets to multiple paths using a hash function. A routing path is the sequence of links a data packet traverses from a source routing node to a destination routing node. A link is the basic building block of a path.

[0084] In the first timing model, a traffic monitoring module is deployed for each link to record in real time the amount of data passing through each link per unit time. The traffic on the link can also be visualized through a heat map or a line graph. For example, a traffic change curve is drawn in the order of the routing path. If the curve shows a "monotonically decreasing" state, it means that the traffic of each link on the routing path has a gradient reduction phenomenon. The essence of the traffic gradient reduction on each link is that the path selection of the routing allocation algorithm is unbalanced, resulting in overload of some links and underutilization of subsequent links. In the embodiment of the present application, the link load is balanced by adjusting the hash seed to change the path distribution.

[0085] The hash seed is the initial parameter of the hash function. Different seeds change the arrangement of the hash results. By adjusting the hash seed, the hash results are evenly distributed across multiple paths, thereby distributing traffic to different links. In the first time series model, multiple hash seed values ​​are iterated, the hash results are recalculated for each hash seed, and the traffic distribution of each link is statistically analyzed. The smaller the standard deviation of the traffic flow on each link, the smaller the gradient coefficient (the ratio of the link with the highest traffic flow to the link with the lowest traffic flow), and the more even the traffic distribution. Iterate over multiple hash seed values ​​and select the seed that minimizes the traffic standard deviation and the gradient coefficient closest to 1.

[0086] In an embodiment of the present application, a traffic monitoring module is deployed for each link to record the amount of data passing through each link per unit time in real time, and determine the first traffic corresponding to each link in the first timing model; when the distribution of the first traffic on each link is uneven, the routing path for communication between each routing node is adjusted by adjusting the hash seed in the routing allocation algorithm, and the link load is balanced by changing the path distribution by adjusting the hash seed.

[0087] Optionally, adjusting the first configuration parameter group according to the first network performance includes:

[0088] Step S41: Determine the input flow of each routing node of the first time series model;

[0089] Step S42: determining at least one first routing node according to the input traffic and a preset threshold;

[0090] Step S43: For each first routing node, adjust the first configuration parameter corresponding to the first routing node.

[0091] It should be noted that the first timing model in the embodiment of the present application adopts a lossless on-chip network, which is an interconnection architecture designed specifically for internal chip communication. Its core goal is to completely avoid packet loss during data transmission. In steady-state transmission without data loss, that is, the buffer is not saturated and there is no back pressure signal, the long-term average input traffic of the routing node is equal to the output traffic. When the output port of a routing node or the buffer of a downstream node is full, the node will send a "pause" signal to the upstream node to prevent data from continuing to flow in, avoiding buffer overflow and packet loss. Input traffic refers to the amount of data received and forwarded by each routing node, such as the number of packets and bytes.

[0092] Exemplarily, the traffic load of the first routing node is significantly higher than the average level of the first timing model routing node, for example, the preset threshold is 2 times the average traffic. By real-time monitoring of the input traffic of each routing node in the first timing model, when the input traffic of the routing node is greater than or equal to the preset threshold, the routing node is determined to be the first routing node. The preset threshold can be static or dynamic. For example, the preset threshold can be set based on experience and remains unchanged when the first configuration parameter is adjusted; it can also be adjusted in real time according to the input traffic of each routing node in the first timing model. Typically, the first routing node is located in the middle area of ​​the entire first timing model, that is, on the middle public link.

[0093] After injecting the data traffic corresponding to the data pattern into the first timing model, the performance indicators of each routing node can also be monitored and analyzed. The performance indicators may include: buffer occupancy rate and power consumption. The buffer occupancy rate refers to the proportion of used space in the input buffer of the routing node. For example, if the buffer size is 512 bytes and 400 bytes are currently occupied, the buffer occupancy rate is 78%. The power consumption refers to the dynamic power consumption generated by the routing node data processing, such as performing routing calculations and buffer reading and writing. The preset threshold can be set according to the performance target. For example, the preset threshold can be a power consumption threshold of 20mW, and the routing node with a power consumption greater than 20mW is determined as the first routing node.

[0094] Adjusting the first configuration parameters corresponding to the first routing node refers to adjusting the network physical structure parameters corresponding to the first routing node, controlling the traffic passing through the first routing node, adjusting the transmission path of the data packet, reducing the traffic load of the first routing node, and adjusting the network resources allocated to the first routing node. For example, if the data packet queues in the buffer of the first routing node for too long, that is, if the delay exceeds the standard, the input buffer of the first routing node can be expanded; or the routing calculation can be split into a multi-stage pipeline to shorten the single-stage delay. For example, the address resolution and virtual channel selection in the routing calculation process can be separated into a first-stage pipeline. If the power consumption of the first routing node exceeds the standard due to frequent data processing, the complex adaptive routing algorithm can be replaced with a simpler fixed routing to reduce computing power consumption.

[0095] In an embodiment of the present application, during the simulation process, the input traffic of each routing node of the first timing model is monitored in real time, and the routing node whose input traffic is greater than or equal to a preset threshold is determined as the first routing node; wherein the preset threshold can be static and fixed, or it can be dynamically adjusted according to the real-time traffic in the on-chip network model. For each first routing node, the network resources allocated to the first routing node are adjusted, for example, the network physical structure, the transmission path of the data packet. High-fidelity traffic monitoring and threshold strategy accurately perceive the traffic of each routing node, and adjust the parameters taking into account both immediate effects and long-term stability to avoid local hotspots causing global resource waste.

[0096] Optionally, determining architecture parameters corresponding to the network on chip according to the performance requirement includes:

[0097] Step S51: Determine a preset range corresponding to each architecture parameter according to the performance requirement; the architecture parameter includes at least one of a topology structure, a flow control mechanism, and an internal structure of a routing node;

[0098] Step S52: Select a first topology structure, a first flow control mechanism, and a first routing node internal structure from the preset range according to the respective impacts of the topology structure, the flow control mechanism, and the internal structure of the routing node on the performance requirement.

[0099] It should be noted that the preset range for each structural parameter can be determined based on performance requirements, historical experience, and relevant theory. For example, the mapping relationship between architectural parameters and performance requirements can be determined through literature. Based on experience and literature, it is known that virtual channels can resolve the deadlock problem of wormhole routing, but increase area; back pressure mechanisms prevent congestion by suspending data transmission, but may increase latency. Based on this mapping relationship, architectural parameters that clearly do not meet the requirements are eliminated. For example, if the performance requirement is "high throughput (1TB / s)", the ring topology with a small number of links (few links) is excluded, while the mesh topology with a large number of links is retained.

[0100] Furthermore, topology can influence communication patterns and scale, allowing topology selection based on these factors. For example, uniform communication is well-suited to meshes, while strong locality might require clusters or hierarchical structures, and high bandwidth requirements might favor fat trees. Routing algorithms can also be selected based on topology, deadlock avoidance, and load balancing requirements. Simple topologies often use deterministic routing (such as XY), while complex topologies or those requiring load balancing use adaptive routing. Flow control mechanisms can influence latency and throughput, allowing selection based on latency, throughput, buffer cost, and deadlock avoidance requirements. For example, wormhole flow control with multiple virtual channels is often used for low latency.

[0101] In the embodiments of the present application, the preset range corresponding to each structural parameter can be determined based on performance requirements, historical experience, and relevant theories. For example, the mapping relationship between architectural parameters and performance requirements can be determined through literature or simulation tools. Determining the topology, flow control mechanism, and internal structure of routing nodes within the preset range reduces the number of parameters that need to be traversed when designing the on-chip network, thereby improving the efficiency of the on-chip network design.

[0102] In summary, the embodiment of the present application provides a method for designing a network on chip, which can determine the performance requirements of the network on chip to be designed; determine the corresponding architectural parameters of the network on chip based on the performance requirements; for each routing node of the network on chip, decompose the processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage; for each routing node, construct a timing model of a single routing node based on the number of clock cycles corresponding to each pipeline stage; construct a link timing model based on the data transmission cycle corresponding to each link in the network on chip; construct a first timing model based on the topological structure of the network on chip, the timing model corresponding to each routing node, and the link timing model corresponding to each link. The first timing model is verified, and during the verification process, the configuration parameters adopted by the first timing model can be modified multiple times to determine the network performance of the network on chip using each set of configuration parameters, and then determine the target configuration parameter combination that can achieve the expected goal. Designing a network on chip based on the first timing model using the target configuration parameter combination can accurately and quickly determine the network on chip architecture that meets the requirements. By performing system-level modeling before actually establishing the on-chip network architecture and simulating the system behavior of each component in the entire on-chip network and the number of clock cycles consumed by the behavior, it is possible to quickly determine whether there is a deviation between the performance of the on-chip network architecture and the expected goals, and to modify and verify the working parameters of the on-chip network architecture to obtain an on-chip network model that meets performance requirements, thereby improving the efficiency of designing the on-chip network and reducing the cost of designing the on-chip network.

[0103] Device embodiment

[0104] Reference Figure 2 , shows a structural block diagram of an on-chip network design device of the present application, and the device may specifically include:

[0105] A requirement determination module 210 is used to determine the performance requirements of the network on chip to be designed;

[0106] A parameter determination module 220 is configured to determine architecture parameters corresponding to the network on chip according to the performance requirements;

[0107] a decomposition module 230 for decomposing a processing flow of each routing node of the network on chip into at least one pipeline stage and determining a number of clock cycles corresponding to each pipeline stage;

[0108] A construction module 240 is configured to construct a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes;

[0109] The design module 250 is configured to verify the first timing model, and if the verification passes, design an on-chip network according to the first timing model.

[0110] Optionally, the building blocks include:

[0111] The first construction submodule is used to construct a timing model of a single routing node according to the number of clock cycles corresponding to each pipeline stage for each routing node;

[0112] A second construction submodule is configured to construct a link timing model according to a data transmission period corresponding to each link in the on-chip network;

[0113] The third construction submodule is configured to construct a first timing model according to the topological structure of the on-chip network, the timing models corresponding to the respective routing nodes, and the link timing models corresponding to the respective links.

[0114] Optionally, the design module includes:

[0115] an acquisition module, configured to acquire data flow of the first time series model in at least one data mode;

[0116] a simulation module, configured to inject the data traffic into the first timing model for simulation for each data pattern, and determine a current first network performance of the first timing model; model parameters of the first timing model adopt a first configuration parameter group;

[0117] The adjustment module is used to adjust the first configuration parameter group according to the first network performance and enter the next round of simulation until the first network performance meets the preset conditions and stops the simulation.

[0118] Optionally, the adjustment module includes:

[0119] a link traffic determination module, configured to determine a first traffic corresponding to each link in the first timing model;

[0120] The first adjustment submodule is configured to adjust the routing paths for communication between the routing nodes by adjusting the hash seed in the routing allocation algorithm when the distribution of the first traffic on the links is uneven.

[0121] Optionally, the adjustment module includes:

[0122] A node traffic determination module, configured to determine the input traffic of each routing node of the first time series model;

[0123] a node determination module, configured to determine at least one first routing node according to the input traffic and a preset threshold;

[0124] The second adjustment submodule is configured to adjust, for each first routing node, a first configuration parameter corresponding to the first routing node.

[0125] Optionally, the parameter determination module includes:

[0126] a range determination module, configured to determine a preset range corresponding to each structural parameter according to the performance requirement; the structural parameter including at least one of a topology, a flow control mechanism, and an internal structure of a routing node;

[0127] A selection module is used to select a first topology structure, a first flow control mechanism, and a first routing node internal structure from the preset range according to the degree of influence of the topology structure, the flow control mechanism, and the internal structure of the routing node on the performance requirement.

[0128] In summary, the embodiment of the present application provides an on-chip network design device, which can determine the performance requirements of the on-chip network to be designed; determine the corresponding architectural parameters of the on-chip network based on the performance requirements; for each routing node of the on-chip network, decompose the processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage; for each routing node, construct a timing model of a single routing node based on the number of clock cycles corresponding to each pipeline stage; construct a link timing model based on the data transmission cycle corresponding to each link in the on-chip network; construct a first timing model based on the topological structure of the on-chip network, the timing model corresponding to each routing node, and the link timing model corresponding to each link. The first timing model is verified, and during the verification process, the configuration parameters adopted by the first timing model can be modified multiple times to determine the network performance of the on-chip network using each set of configuration parameters, and then determine the target configuration parameter combination that can achieve the expected goal. Designing an on-chip network based on the first timing model using the target configuration parameter combination can accurately and quickly determine the on-chip network architecture that meets the requirements. By performing system-level modeling before actually establishing the on-chip network architecture and simulating the system behavior of each component in the entire on-chip network and the number of clock cycles consumed by the behavior, it is possible to quickly determine whether there is a deviation between the performance of the on-chip network architecture and the expected goals, and to modify and verify the working parameters of the on-chip network architecture to obtain an on-chip network model that meets performance requirements, thereby improving the efficiency of designing the on-chip network and reducing the cost of designing the on-chip network.

[0129] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0130] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0131] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0132] Reference Figure 3 , is a structural block diagram of an electronic device for on-chip network design provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the on-chip network design method of the aforementioned embodiment.

[0133] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0134] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used does not mean that there is only one bus or one type of bus.

[0135] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0136] The embodiment of the present invention further provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figure 1 The on-chip network design method shown.

[0137] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0138] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatuses, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0139] The embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0140] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0142] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0143] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0144] The above is a detailed introduction to the on-chip network design method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for designing a network on a chip, characterized in that: The method comprises: Determine the performance requirements of the network on chip to be designed; Determining architecture parameters corresponding to the on-chip network according to the performance requirements; For each routing node of the network on chip, decompose the processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage; Constructing a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes; Verifying the first timing model, and if the verification passes, designing an on-chip network according to the first timing model; Wherein, the first timing model can simulate the behavior of each component in the on-chip network in each clock cycle; The constructing of the first timing model includes: A topology of the network on chip is established, and a delay of the network on chip is modeled.

2. The method according to claim 1, characterized in that The step of constructing a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes includes: For each routing node, a timing model of a single routing node is constructed based on the number of clock cycles corresponding to each pipeline stage; Constructing a link timing model according to the data transmission cycle corresponding to each link in the on-chip network; A first timing model is constructed according to the topological structure of the on-chip network, the timing models corresponding to the respective routing nodes, and the link timing models corresponding to the respective links.

3. The method according to claim 1, characterized in that The verifying the first timing model includes: Obtaining data flow of the first time series model in at least one data mode; For each data pattern, injecting the data traffic into the first timing model for simulation to determine the current first network performance of the first timing model; the model parameters of the first timing model adopt the first configuration parameter group; According to the first network performance, the first configuration parameter group is adjusted, and the next round of simulation is started. The simulation is stopped when the first network performance meets a preset condition.

4. The method according to claim 3, characterized in that The adjusting the first configuration parameter group according to the first network performance includes: Determining a first flow corresponding to each link in the first timing model; In the case that the distribution of the first traffic on each link is uneven, the routing path for communication between each routing node is adjusted by adjusting the hash seed in the routing distribution algorithm.

5. The method according to claim 3, characterized in that The adjusting the first configuration parameter group according to the first network performance includes: Determining the input flow of each routing node of the first timing model; Determining at least one first routing node according to the input traffic and a preset threshold; For each first routing node, a first configuration parameter corresponding to the first routing node is adjusted.

6. The method according to claim 1, wherein Determining architecture parameters corresponding to the network on chip according to the performance requirements includes: Determining a preset range corresponding to each architecture parameter based on the performance requirement; the architecture parameter includes at least one of a topology structure, a flow control mechanism, and an internal structure of a routing node; According to the respective impacts of the topology structure, the flow control mechanism, and the internal structure of the routing node on the performance requirement, a first topology structure, a first flow control mechanism, and a first internal structure of the routing node are selected from the preset range.

7. A network-on-chip design device, characterized in that: The device comprises: A requirement determination module, used to determine the performance requirements of the on-chip network to be designed; A parameter determination module, configured to determine architecture parameters corresponding to the on-chip network according to the performance requirements; a decomposition module, configured to decompose, for each routing node of the network on chip, a processing flow of the routing node into at least one pipeline stage, and determine the number of clock cycles corresponding to each pipeline stage; A construction module, configured to construct a first timing model according to the architecture parameters and the number of clock cycles corresponding to all routing nodes; A design module, configured to verify the first timing model, and if the verification passes, design an on-chip network according to the first timing model; Wherein, the first timing model can simulate the behavior of each component in the on-chip network in each clock cycle; The building blocks are specifically used for: A topology of the network on chip is established, and a delay of the network on chip is modeled.

8. The device according to claim 7, characterized in that The building blocks include: The first construction submodule is used to construct a timing model of a single routing node according to the number of clock cycles corresponding to each pipeline stage for each routing node; A second construction submodule is configured to construct a link timing model according to a data transmission period corresponding to each link in the on-chip network; The third construction submodule is configured to construct a first timing model according to the topological structure of the on-chip network, the timing models corresponding to the respective routing nodes, and the link timing models corresponding to the respective links.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the on-chip network design method according to any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to perform the on-chip network design method according to any one of claims 1 to 6.

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