Machine learning accelerators and computing devices and methods related thereto

Abstract

Disclosed is a machine learning accelerator including: a first data controller storing original length information indicating an original length, receiving first data having a first length, and decompressing the first data having the first length to output second data having the original length; a second data controller storing the original length information, receiving third data having a second length shorter than the first length, and decompressing the third data having the second length to output fourth data having the original length; a first accelerator core receiving second data having an original length from the first data controller and performing a first machine learning-based operation; and a second accelerator core receiving fourth data having the original length from the second data controller and performing a second machine learning-based operation.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0011143, filed with the Korean Intellectual Property Office on January 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] Embodiments of the present disclosure described herein relate to an electronic device, and more particularly, to a machine learning accelerator having an improved data loading speed, a computing device including the machine learning accelerator, and a method of loading data into the machine learning accelerator.

[0004] A machine learning accelerator is configured to load weight data and perform machine - learning - based operations. As the technology for machine learning develops, the capacity of data loaded into the machine learning accelerator continuously increases. Accordingly, the time taken to load the weight data into the machine learning accelerator also continuously increases.

[0005] The weight data can be compressed to reduce the time taken to load the weight data into the machine learning accelerator. The compressed weight data can be transferred to the machine learning accelerator in a shorter time. Summary of the Invention

[0006] Embodiments of the present disclosure provide a machine learning accelerator capable of loading compressed weight data in a shorter time, a computing device including the machine learning accelerator, and a method of loading data into the machine learning accelerator.

[0007] According to at least one embodiment, a machine learning accelerator includes: a first data controller configured to store original length information indicating an original length of data, receive first data having a first length, generate second data having the original length by decompressing the first data having the first length, and output the second data having the original length; a second data controller configured to store the original length information, receive third data having a second length shorter than the first length, generate fourth data having the original length by decompressing the third data having the second length, and output the fourth data having the original length; a first accelerator core configured to receive the second data having the original length and perform a first machine - learning - based operation using the second data as first weight data; and a second accelerator core configured to receive the fourth data having the original length and perform a second machine - learning - based operation using the fourth data as second weight data, wherein each of the first data controller and the second data controller is configured to monitor a timing at which decompression is completed based on the original length and terminate decompression at the timing at which decompression is completed.

[0008] According to at least one embodiment, a computing device includes: a memory configured to store first data having a first length and second data having a second length shorter than the first length; and a machine learning accelerator configured to receive the first data and third data from the memory, the third data having the first length and including the second data, wherein the machine learning accelerator is configured to generate first weight data by decompressing the first data having the first length, convert the third data having the first length into second data having the second length, generate second weight data by decompressing the second data having the second length, and perform a machine learning-based operation based on the first weight data and the second weight data.

[0009] According to at least one embodiment, a method for a processor to load data into a machine learning accelerator includes: programming two or more direct memory access (DMA) masters at the processor using a first start address and first length information; and reading data from the memory in parallel at the two or more DMA masters based on the first start address and first length information and transferring the parallel-read data to the machine learning accelerator, wherein the machine learning accelerator is configured to generate first weight data by decompressing first data corresponding to the first length information in the parallel-read data, generate third data having a second length by converting second data corresponding to the first length information, the second length being shorter than the first length indicated by the first length information, generate second weight data by decompressing the third data having the second length, and perform a machine learning-based operation based on the first weight data and the second weight data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0011] Figure 1 A computing device according to at least one embodiment of the present disclosure is shown.

[0012] Figure 2 An example of weight data in a compressed form loaded into the accelerator is shown.

[0013] Figure 3 An example of a method in which a computing device loads compressed weight data into the accelerator is shown.

[0014] Figure 4 An example of a method in which a computing device loads compressed weight data from a storage device into the memory is shown.

[0015] Figure 5 Shown depending onFigure 4 An example of the process of loading compressed weight data from a storage device to a memory by the method.

[0016] Figure 6 An example of a method in which a computing device loads compressed weight data into an accelerator is shown.

[0017] Figure 7 A data controller and related components according to at least one embodiment of the present disclosure are shown.

[0018] Figure 8 An example of an operation method of a drain circuit is shown.

[0019] Figure 9 A data controller and related components according to at least one embodiment of the present disclosure are shown.

[0020] Figure 10 A data controller and related components according to at least one embodiment of the present disclosure are shown.

[0021] Figure 11 Shows Figure 10 An example of an operation method of a validity monitor for each of the data controllers.

[0022] Figure 12 Another example of weight data in a compressed form loaded into an accelerator is shown.

[0023] Figure 13 Shows depending on Figure 4 An example of the process of loading compressed weight data from a storage device to a memory by the method.

[0024] Figure 14 A computing device according to another embodiment of the present disclosure is shown. Detailed Description of the Invention

[0025] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that those of ordinary skill in the art can easily implement the present disclosure.

[0026] Figure 1 A computing device 10 according to at least one embodiment of the present disclosure is shown. Referring to Figure 1 , the computing device 10 may include a system bus 110, a processor 120, an accelerator 130, a modem 140, a memory controller 150, a memory 160, a direct memory access controller (DMAC) 170, and a storage device 180.

[0027] The system bus 110 can be configured to enable communication between the components of the computing device 10, for example, by providing a channel between the components of the computing device 10. For example, the system bus 110 can provide a channel based on one or more of various communication protocols such as Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), Dual In-line Memory Module (DIMM), Advanced eXtensible Interface (AXI), etc.

[0028] The processor 120 can be configured to execute an operating system and various applications. The processor 120 can be configured to control the components of the computing device 10 depending on the requests of the operating system and applications. For example, the processor 120 can include a Central Processing Unit (CPU) and / or an Application Processor (AP) including one or more processing cores.

[0029] The accelerator 130 can be a machine learning accelerator that runs a machine learning module or a trained machine learning module based on machine learning training. For example, machine learning can be based on various algorithms including Convolutional Neural Network (CNN), Deep Neural Network (DNN), and Generative Adversarial Network (GAN). In at least some embodiments, for example, the trained machine learning module can be configured to perform speech recognition, text-to-speech, image recognition, image classification, and / or image processing by using a neural network, a tablet device, a smart TV, an Augmented Reality (AR) device, an Internet of Things (IoT) device, a self-driving vehicle, a robot, a medical device, a drone, an Advanced Driver Assistance System (ADAS), an image display device, a data processing server, a measurement device, etc., and / or can be installed in one of various electronic devices.

[0030] The accelerator 130 can include a plurality of accelerator cores "C". In at least one embodiment, the accelerator 130 can include four accelerator cores "C". The accelerator cores "C" can be configured to operate in parallel to perform machine learning operations. The machine learning operations can include at least some of the various operations of the machine learning module, such as learning, inference, and / or classification.

[0031] The accelerator 130 can include data controllers CT respectively corresponding to the accelerator cores "C". For example, the accelerator 130 can include four data controllers CT. The data controllers CT can be configured to operate in parallel. The data controllers CT can decompress the compressed data transmitted to the accelerator 130 and can transmit the decompressed data to the corresponding accelerator cores "C". The data controllers CT can also provide the uncompressed data transmitted to the accelerator 130 to the accelerator cores "C".

[0032] The modem 140 can be configured to communicate with external devices. For example, the modem 140 can communicate with external devices based on various wired and / or wireless communication protocols, such as IEEE 802.11, Ethernet, 5G, and Bluetooth. The modem 140 can send the data stored in the memory 160 to an external device, or can store the data sent from an external device to the modem 140.

[0033] The memory controller 150 can be configured to access the memory 160. For example, the memory controller 150 can access the memory 160 depending on requests from the processor 120 and / or the DMAC 170. For example, the memory controller 150 can write data into the memory 160 or can read data from the memory 160. The memory controller 150 can perform various operations for managing the data stored in the memory 160, for example, including various background operations such as refresh operations and row hammer prevention operations.

[0034] The memory 160 can be a random access memory. For example, the memory 160 can be implemented with one or more of various random access memories, such as dynamic random access memory (DRAM), static RAM (SRAM), phase change RAM (PRAM), magnetic RAM (MRAM), ferroelectric RAM (FRAM), resistive RAM (RRAM), etc.

[0035] The DMAC 170 can be configured to request the memory controller 150 to write the data output from at least one of the components of the computing device 10 into the memory 160 according to the program of the processor 120. For example, the DMAC 170 can request the memory controller 150 to output the data stored in the memory 160 to at least one of the components of the computing device 10 according to the program of the processor 120. The DMAC 170 can include multiple DMA masters "M". In at least one embodiment, the DMAC 170 can include four DMA masters "M". The DMA masters "M" can independently request access to the memory 160 from each other, for example, a read operation or a write operation from the memory controller 150.

[0036] In at least one embodiment, the DMA masters "M" can request read or write operations on the memory 160 from the memory controller 150 in parallel, independently, or simultaneously. Depending on the requests of the DMA masters "M", the memory controller 150 can perform write operations or read operations on the memory 160 in parallel, independently, or simultaneously. For example, multiple channels can be provided between the DMA masters "M" and the memory controller 150 in parallel, independently, or simultaneously. In addition, multiple channels can be provided between the memory controller 150 and the memory 160 in parallel, independently, or simultaneously.

[0037] The storage device 180 can be an auxiliary memory device of the computing device 10. For example, the storage device 180 can be a hard disk drive (HDD), a solid state drive (SSD), an embedded storage device, etc.

[0038] Figure 2 An example of weight data in a compressed form (e.g., compressed weight data) loaded into the accelerator 130 is shown. Refer to Figure 1 and Figure 2 , in at least one embodiment, the accelerator 130 can run a machine learning module including three layers. In addition, although the first compressed layer weight data L1_WD to the third compressed layer weight data L3_WD (corresponding to the three layers) are shown, the example is not limited thereto. For example, in at least one embodiment, the number of layers can be less than or greater than three, and the number of compressed weight data can correspond to the number of layers included in the machine learning module.

[0039] The first compressed layer weight data L1_WD can be the compressed weight data to be used in the first layer of the machine learning module. The first compressed layer weight data L1_WD can include the 1a compressed weight data WD1a, the 1b compressed weight data WD1b, the 1c compressed weight data WD1c, and the 1d compressed weight data WD1d corresponding to four accelerator cores "C", respectively.

[0040] The second compressed layer weight data L2_WD can be the compressed weight data to be used in the second layer of the machine learning module. The second compressed layer weight data L2_WD can include the 2a compressed weight data WD2a, the 2b compressed weight data WD2b, the 2c compressed weight data WD2c, and the 2d compressed weight data WD2d corresponding to four accelerator cores "C", respectively.

[0041] The third compressed layer weight data L3_WD can be the compressed weight data to be used in the third layer of the machine learning module. The third compressed layer weight data L3_WD can include the 3a compressed weight data WD3a, the 3b compressed weight data WD3b, the 3c compressed weight data WD3c, and the 3d compressed weight data WD3d corresponding to four accelerator cores "C", respectively.

[0042] In at least one embodiment, the compression ratio can vary depending on the pattern of the weight data. As the difference between the ratio of 0s and the ratio of 1s in the weight data decreases, the compression ratio of the weight data can decrease. As the difference between the ratio of 0s and the ratio of 1s in the weight data increases, the compression ratio of the weight data can increase. As the values of "0" or "1" are concentrated and placed in the weight data, the compression ratio of the weight data can increase. As the values of "0" or "1" are dispersed and placed in the weight data, the compression ratio of the weight data can decrease.

[0043] When the weight data has different compression ratios, the compressed weight data can have different sizes. Figure 2 An example where the compressed weight data has different sizes is shown.

[0044] The first compressed layer weight data L1_WD, the second compressed layer weight data L2_WD, and the third compressed layer weight data L3_WD can be stored in the storage device 180. For example, the first compressed layer weight data L1_WD, the second compressed layer weight data L2_WD, and the third compressed layer weight data L3_WD can be obtained and stored in the memory 160 (e.g., from an external device via the modem 140) and / or can be stored in the storage device 180. As another example, the first compressed layer weight data L1_WD, the second compressed layer weight data L2_WD, and the third compressed layer weight data L3_WD can be stored in a removable storage device, and the removable storage device can be connected to the computing device 10 as part of the storage device 180.

[0045] The first compressed layer weight data L1_WD can also include first a length information LI1a, first b length information LI1b, first c length information LI1c, and first d length information LI1d indicating the lengths of the first a compressed weight data WD1a, the first b compressed weight data WD1b, the first c compressed weight data WD1c, and the first d compressed weight data WD1d, respectively. The first a length information LI1a, the first b length information LI1b, the first c length information LI1c, and the first d length information LI1d can include information about the start address on the storage device 180 from which the first a compressed weight data WD1a, the first b compressed weight data WD1b, the first c compressed weight data WD1c, and the first d compressed weight data WD1d are stored, and information about the length (or size) of the addresses of the first a compressed weight data WD1a, the first b compressed weight data WD1b, the first c compressed weight data WD1c, and the first d compressed weight data WD1d.

[0046] The second compressed layer weight data L2_WD may also include 2a length information LI2a, 2b length information LI2b, 2c length information LI2c, and 2d length information LI2d indicating the lengths of the 2a compressed weight data WD2a, the 2b compressed weight data WD2b, the 2c compressed weight data WD2c, and the 2d compressed weight data WD2d, respectively. The 2a length information LI2a, the 2b length information LI2b, the 2c length information LI2c, and the 2d length information LI2d may include information about the start address on the storage device 180 from which the 2a compressed weight data WD2a, the 2b compressed weight data WD2b, the 2c compressed weight data WD2c, and the 2d compressed weight data WD2d are stored, and information about the lengths (or sizes) of the addresses of the 2a compressed weight data WD2a, the 2b compressed weight data WD2b, the 2c compressed weight data WD2c, and the 2d compressed weight data WD2d.

[0047] The third compressed layer weight data L3_WD may also include 3a length information LI3a, 3b length information LI3b, 3c length information LI3c, and 3d length information LI3d indicating the lengths of the 3a compressed weight data WD3a, the 3b compressed weight data WD3b, the 3c compressed weight data WD3c, and the 3d compressed weight data WD3d, respectively. The 3a length information LI3a, 3b length information LI3b, 3c length information LI3c, and 3d length information LI3d may include information about a start address on the storage device 180 from which the 3a compressed weight data WD3a, 3b compressed weight data WD3b, 3c compressed weight data WD3c, and 3d compressed weight data WD3d are stored, and information about the lengths (or sizes) of the addresses of the 3a compressed weight data WD3a, 3b compressed weight data WD3b, 3c compressed weight data WD3c, and 3d compressed weight data WD3d.

[0048] Figure 3 An example of a method in which the computing device 10 loads compressed weight data to the accelerator 130 is shown. Figure 1 , Figure 2 and Figure 3, in operation S110, computing device 10 loads the compressed weight data WD from storage device 180 into memory 160 based on the first type of length information. The weight data WD may include the 1a-compressed weight data WD1a, 1b-compressed weight data WD1b, 1c-compressed weight data WD1c, and 1d-compressed weight data WD1d of the first compressed layer weight data L1_WD, the 2a-compressed weight data WD2a, 2b-compressed weight data WD2b, 2c-compressed weight data WD2c, and 2d-compressed weight data WD2d of the second compressed layer weight data L2_WD, and the 3a-compressed weight data WD3a, 3b-compressed weight data WD3b, 3c-compressed weight data WD3c, and 3d-compressed weight data WD3d of the third compressed layer weight data L3_WD.

[0049] The first type of length information may include the 1a-length information LI1a, 1b-length information LI1b, 1c-length information LI1c, and 1d-length information LI1d of the first compressed layer weight data L1_WD, the 2a-length information LI2a, 2b-length information LI2b, 2c-length information LI2c, and 2d-length information LI2d of the second compressed layer weight data L2_WD, and the 3a-length information LI3a, 3b-length information LI3b, 3c-length information LI3c, and 3d-length information LI3d of the third compressed layer weight data L3_WD.

[0050] Processor 120 may read the compressed weight data WD from storage device 180 to load it into memory 160, and / or may program DMAC 170 to read the compressed weight data WD from storage device 180 and load the compressed weight data WD into memory 160.

[0051] In operation S120, computing device 10 loads the compressed weight data WD from memory 160 into accelerator 130 based on the second type of length information. For example, the second type of length information may be a part of the first type of length information. When the compressed weight data WD (using the second type of length information) is loaded into accelerator 130, computing device 10 may increase the speed at which the compressed weight data WD is loaded into accelerator 130 and may reduce the loading time.

[0052] In at least one embodiment, the processor 120 may program the DMAC 170 to read the compressed weight data WD stored in the memory 160 and load the compressed weight data WD into the accelerator 130. The accelerator 130 may receive the compressed weight data WD and may generate weight data by decompressing the compressed weight data WD (or releasing the compression of the compressed weight data WD). The accelerator 130 may load the weight data into the accelerator core "C".

[0053] In operation S130, the computing device 10 runs the accelerator 130. For example, the processor 120 may control the accelerator 130 such that the accelerator 130 performs machine learning operations (e.g., such as learning, inference, or classification). The accelerator core "C" of the accelerator 130 may perform machine learning operations based on machine learning, based on the data transmitted from the processor 120 and the weight data loaded into the accelerator core "C".

[0054] Figure 4 An example of a method in which the computing device 10 loads the compressed weight data WD from the storage device 180 into the memory 160 is shown (e.g., Figure 3 example of operation S110). Figure 5 An example is shown depending on Figure 4 of the process of loading the compressed weight data WD from the storage device 180 into the memory 160.

[0055] Referring to Figure 1 , Figure 4 and Figure 5 , in operation S210, the computing device 10 may read the length information LI. For example, the processor 120 may read the 1a length information LI1a, the 1b length information LI1b, the 1c length information LI1c, the 1d length information LI1d, the 2a length information LI2a, the 2b length information LI2b, the 2c length information LI2c, the 2d length information LI2d, the 3a length information LI3a, the 3b length information LI3b, the 3c length information LI3c, the 3d length information LI3d, and the original length information OLI from the first length information area LIA1 of the storage device 180. The original length information OLI may indicate the length (or size) of each weight data before compression.

[0056] In operation S220, computing device 10 may read the compressed weight data WD. Each of the first 1a length information LI1a, the first 1b length information LI1b, the first 1c length information LI1c, the first 1d length information LI1d, the second 2a length information LI2a, the second 2b length information LI2b, the second 2c length information LI2c, the second 2d length information LI2d, the third 3a length information LI3a, the third 3b length information LI3b, the third 3c length information LI3c, and the third 3d length information LI3d may include information about the start address (represented by an upward arrow) of storage device 180 and the length (represented by left and right arrows) of the associated compressed weight data.

[0057] Processor 120 or DMAC 170 may read the compressed weight data WD from storage device 180 by using the length information LI.

[0058] In operation S230, computing device 10 may load the compressed weight data WD into memory 160 based on the same address. For example, processor 120 and / or DMAC 170 may load the first 1a compressed weight data WD1a, the first 1b compressed weight data WD1b, the first 1c compressed weight data WD1c, and the first 1d compressed weight data WD1d of the first compressed layer weight data L1_WD in parallel into a storage space in memory 160 that starts from the same first start address and has consecutive addresses.

[0059] As Figure 5 shown, the first 1a compressed weight data WD1a, the first 1b compressed weight data WD1b, the first 1c compressed weight data WD1c, and the first 1d compressed weight data WD1d of the first compressed layer weight data L1_WD may have different lengths (or sizes). For example, in this example, the first 1a compressed weight data WD1a, the first 1b compressed weight data WD1b, and the first 1d compressed weight data WD1d may be smaller in length (or size) than the first 1c compressed weight data WD1c.

[0060] Processor 120 and / or DMAC 170 may load the second 2a compressed weight data WD2a, the second 2b compressed weight data WD2b, the second 2c compressed weight data WD2c, and the second 2d compressed weight data WD2d of the second compressed layer weight data L2_WD in parallel into a storage space in memory 160 that starts from the same second start address and has consecutive addresses.

[0061] For example, the second start address can be the address immediately after the end address of the 1c-th compressed weight data WD1c, which has the maximum length (or size) among the 1a-th compressed weight data WD1a, 1b-th compressed weight data WD1b, 1c-th compressed weight data WD1c, and 1d-th compressed weight data WD1d of the first compressed layer weight data L1_WD. In other words, the position of the second start address in the storage space of the memory 160 can be based on the length (or size) of the maximum length (or size) among the 1a-th compressed weight data WD1a, 1b-th compressed weight data WD1b, 1c-th compressed weight data WD1c, and 1d-th compressed weight data WD1d of the first compressed layer weight data L1_WD.

[0062] Therefore, the end address of the 1a-th compressed weight data WD1a can be less than the end address of the 1c-th compressed weight data WD1c. The processor 120 or the DMAC 170 can write dummy data, a random pattern, or a given pattern in the storage space of the memory 160 that ranges from the address immediately after the end address of the 1a-th compressed weight data WD1a to the end address of the 1c-th compressed weight data WD1c, or may not write data therein. The storage space where no data is written can have a fixed value, such as the value "0" or "1".

[0063] As Figure 5 shown, the 2a-th compressed weight data WD2a, 2b-th compressed weight data WD2b, 2c-th compressed weight data WD2c, and 2d-th compressed weight data WD2d in the second compressed layer weight data L2_WD can have different lengths (or sizes). For example, in this example, the 2a-th compressed weight data WD2a, 2b-th compressed weight data WD2b, and 2d-th compressed weight data WD2d can be smaller in length (or size) than the 2c-th compressed weight data WD2c.

[0064] The processor 120 and / or the DMAC 170 can load the 3a-th compressed weight data WD3a, 3b-th compressed weight data WD3b, 3c-th compressed weight data WD3c, and 3d-th compressed weight data WD3d of the third compressed layer weight data L3_WD in parallel onto the storage space of the memory 160 that starts from the same third start address and has consecutive addresses.

[0065] For example, the third start address may be the address immediately after the end address of the 2c-th compressed weight data WD2c having the maximum length (or size) among the 2a-th compressed weight data WD2a, 2b-th compressed weight data WD2b, 2c-th compressed weight data WD2c, and 2d-th compressed weight data WD2d of the second compressed layer weight data L2_WD. In other words, the position of the third start address in the storage space of the memory 160 may be based on the length (or size) of the maximum length (or size) among the 2a-th compressed weight data WD2a, 2b-th compressed weight data WD2b, 2c-th compressed weight data WD2c, and 2d-th compressed weight data WD2d of the second compressed layer weight data L2_WD.

[0066] Therefore, the end address of the 2a-th compressed weight data WD2a may be less than the end address of the 2c-th compressed weight data WD2c. The processor 120 or the DMAC 170 may write pseudo data, a random pattern, a given pattern in the storage space of the memory 160 whose range is from the address immediately after the end address of the 2a-th compressed weight data WD2a to the end address of the 2c-th compressed weight data WD2c, or may not write data therein. The storage space where no data is written may have a fixed value, such as the value "0" or "1".

[0067] As Figure 5 shown, the 3a-th compressed weight data WD3a, 3b-th compressed weight data WD3b, 3c-th compressed weight data WD3c, and 3d-th compressed weight data WD3d may have different lengths (or sizes). For example, in this example, the 3a-th compressed weight data WD3a, 3b-th compressed weight data WD3b, and 3d-th compressed weight data WD3d may be smaller in length (or size) than the 3c-th compressed weight data WD3c.

[0068] The end address of the 3a-th compressed weight data WD3a may be less than the end address of the 3c-th compressed weight data WD3c. The processor 120 and / or the DMAC 170 may write pseudo data, a random pattern, a given pattern in the storage space of the memory 160 whose range is from the address immediately after the end address of the 3a-th compressed weight data WD3a to the end address of the 3c-th compressed weight data WD3c, or may not write data therein. The storage space where no data is written may have a fixed value, such as the value "0" or "1".

[0069] In operation S240, computing device 10 may generate layer length information LLI. The layer length information LLI may include first layer length information LLI1, and the first layer length information LLI1 includes information about the start address (represented by an upward arrow) of the memory 160 from which the first compressed layer weight data L1_WD is stored, or information about the length (represented by a left - right arrow) of the first compressed layer weight data L1_WD.

[0070] The layer length information LLI may include second layer length information LLI2, and the second layer length information LLI2 includes information about the start address (represented by an upward arrow) of the memory 160 from which the second compressed layer weight data L2_WD is stored, or information about the length (represented by a left - right arrow) of the second compressed layer weight data L2_WD.

[0071] The layer length information LLI may further include third layer length information LLI3, and the third layer length information LLI3 includes information about the start address (represented by an upward arrow) of the memory 160 from which the third compressed layer weight data L3_WD is stored, or information about the length (represented by a left - right arrow) of the third compressed layer weight data L3_WD.

[0072] In operation S250, computing device 10 may load the original length information OLI and the layer length information LLI into the memory 160. For example, the processor 120 and / or the DMAC 170 may store the original length information OLI and the layer length information LLI in the second length information area LIA2 of the memory 160.

[0073] Figure 6 An example of a method in which computing device 10 loads the compressed weight data WD into the accelerator 130 is shown (e.g., Figure 3 an example of operation S120). Refer to Figure 1 、 Figure 5 and Figure 6 In operation S310, computing device 10 may read first - type length information and second - type length information from the memory 160. For example, the first - type length information may be the original length information OLI that includes length information for each weight data. The second - type length information may be the layer length information LLI that includes information for each layer. The processor 120 and / or the DMAC 170 may read the first - type length information from the memory 160 and may send the first - type length information to the data controller CT of the accelerator 130.

[0074] In operation S320, computing device 10 may program the DMA master "M" simultaneously. For example, the processor 120 may program the DMA master "M" by using the second - type length information.

[0075] The processor 120 may program the direct memory access (DMA) master "M" to read data from the memory 160 by using the first layer length information LLI1 (see Figure 5 ), and transfer the read data to the accelerator 130. The DMA master "M" may read data in the storage space (starting from the first start address indicated by the first layer length information LLI1 and having the length (or size) indicated by the first layer length information LLI1) in parallel or simultaneously, and may transfer the data to the data controller CT of the accelerator 130 respectively. The data controller CT may convert the data transferred from the memory 160 into the first compressed weight data WD1a, the second compressed weight data WD1b, the third compressed weight data WD1c, and the fourth compressed weight data WD1d based on the original length information OLI.

[0076] In operation S330, the processor 120 may determine whether the data transferred to the accelerator 130 is the last compressed layer weight data L_WD. For example, the processor 120 may determine whether the data transferred to the accelerator 130 is the data including the third compressed layer weight data L3_WD. When the data transferred to the accelerator 130 corresponds to the last compressed layer weight data L_WD, the processor 120 may terminate the loading of the compressed weight data WD to the accelerator 130.

[0077] When the data transferred to the accelerator 130 does not correspond to the last compressed layer weight data L_WD, the processor 120 may load the compressed layer weight data of the next layer to the accelerator 130. For example, the processor 120 may program the DMA master "M" by using the second layer length information LLI2 to load the second compressed layer weight data L2_WD to the accelerator 130. In addition, the processor 120 may program the DMA master "M" by using the third layer length information LLI3 to load the third compressed layer weight data L3_WD to the accelerator 130.

[0078] As described above, the computing device 10 according to at least one embodiment of the present disclosure may load the compressed weight data WD to the accelerator 130 by using multiple DMA masters "M". Therefore, the speed at which the compressed weight data WD is loaded to the accelerator 130 can be increased, and the loading time can be shortened.

[0079] In addition, the computing device 10 according to at least one embodiment of the present disclosure may load the weight data of all layers into the accelerator 130 by using the length information of the weight data having the largest length among the layers with different lengths (sizes). Therefore, since the number of times the DMA master "M" is programmed is reduced, the speed at which the compressed weight data WD is loaded into the accelerator 130 can be increased, and the loading time can be shortened.

[0080] Figure 7 FIGS. illustrate a data controller CT and related components according to at least one embodiment of the present disclosure. Referring to Figure 1 , Figure 5 , Figure 6 and Figure 7 , the DMA master "M" may request the memory controller 150 to read the compressed weight data WD stored in the memory 160. The DMA master "M" may receive data from the memory 160 through the memory controller 150 via a given access unit, and may transfer the received data to the data controller CT. For example, the DMA master "M" may be programmed to read data whose length (or size) corresponds to the layer length information LLI. For example, the DMA master "M" may be programmed by using the same layer length information LLI.

[0081] Each of the data controllers CT may include an evacuation circuit DC, a decompression circuit DCC, and a validity monitor VM (or validity monitor circuit). One DMA master "M" may be connected to one accelerator core "C" through one evacuation circuit DC, one decompression circuit DCC, and one validity monitor VM of one data controller CT. In an embodiment, one DMA master "M", one evacuation circuit DC, one decompression circuit DCC, and one validity monitor VM may form a data chain that converts the data read from the memory 160 (i.e., data including the compressed weight data) into weight data to transfer it to one accelerator core "C".

[0082] Each of the drain circuits DC can receive data from the corresponding DMA master "M" in the DMA master "M". Each of the drain circuits DC can receive a drain signal DS from the corresponding validity monitor VM in the validity monitor VM. When the drain circuit DC is in an inactive state, each of the drain circuits DC can be configured to transfer the data provided from the corresponding DMA master "M" to the corresponding decompression circuit DCC in the decompression circuit DCC. When the drain circuit DC is in an active state, each of the drain circuits DC can be configured to drain the data provided from the corresponding DMA master "M" without transferring the data to the corresponding decompression circuit DCC. For example, when the drain circuit DC is in an active state, each of the drain circuits DC can discard or ignore the data provided from the corresponding DMA master "M".

[0083] Each of the decompression circuits DCC can be configured to perform decompression on the data transferred from the corresponding drain circuit DC. Each of the decompression circuits DCC can transfer the decompressed data (i.e., weight data) to the corresponding validity monitor VM.

[0084] Each of the validity monitors VM can receive weight data (e.g., decompressed weight data) from the corresponding decompression circuit DCC. The validity monitors VM can commonly receive original length information OLI. Each of the validity monitors VM can monitor whether the length (or size) of the data received from the corresponding decompression circuit DCC (e.g., decompressed weight data) reaches the length (or size) indicated by the original length information OLI.

[0085] When the length (or size) of the data received from the corresponding decompression circuit DCC does not reach the length (or size) indicated by the original length information OLI, each of the validity monitors VM can deactivate the drain signal DS and can transfer the data provided from the decompression circuit DCC to the corresponding accelerator core "C" in the accelerator core. When the length (or size) of the data received from the corresponding decompression circuit DCC reaches the length (or size) indicated by the original length information OLI, each of the validity monitors VM can activate the drain signal DS.

[0086] Figure 8 An example of an operation method of the drain circuit DC is shown. Refer to Figure 1 、 Figure 7 and Figure 8 , in operation S410, the drain circuit DC can receive input data. For example, the drain circuit DC can receive data including compressed weight data from the corresponding DMA master "M".

[0087] In operation S420, the drain circuit DC can determine whether the drain signal DS is active. When the drain signal DS is not active, in operation S430, the drain circuit DC can transfer data. For example, the drain circuit DC can transfer the input data received from the corresponding DMA master "M" to the corresponding decompression circuit DCC. Thereafter, operation S450 can be performed.

[0088] When the drain signal DS is active, in operation S440, the drain circuit DC can drain the input data. For example, the drain circuit DC can ignore or discard the input data. Thereafter, operation S450 can be performed.

[0089] In operation S450, the drain circuit DC can determine whether the data has ended. For example, when no more input data is received from the corresponding DMA master "M", the drain circuit DC can determine that the data has ended. When it is determined that the data has ended, the drain circuit DC can terminate the process. When it is determined that the data has not ended, the drain circuit DC can perform operation S410 again.

[0090] As described above, the computing device 10 according to at least one embodiment of the present disclosure can store compressed weight data of different sizes in a storage space of the memory 160 having the same start address and the same layer length information. The computing device 10 can simultaneously program the DMA master "M" by using the same start address and the same layer length information to transfer the weight data to the accelerator 130 in parallel. The drain circuit DC and the validity monitor VM of the data controller CT of the accelerator 130 can extract the decompressed weight data to transfer it to the accelerator core "C". Since the number of times the DMA master "M" is programmed is reduced, the speed at which the computing device 10 loads the compressed weight data into the accelerator 130 can be increased, and the loading time can be reduced.

[0091] Figure 9 A data controller CTa and related components according to another embodiment of the present disclosure are shown. Compared with Figure 8 the data controller CT of Figure 9 the data controller CTa may further include a demultiplexer DX and a multiplexer MX.

[0092] A demultiplexer DX can be provided between the DMA master "M" and the drain circuit DC. A multiplexer MX can be provided between the validity monitor VM and the accelerator core "C". The demultiplexer DX and the multiplexer MX can operate in response to a mode signal MS.

[0093] In at least one embodiment, computing device 10 may provide a compressed mode and an uncompressed mode. In the compressed mode, compressed weight data may be provided to storage device 180. Computing device 10 may load the compressed weight data into accelerator 130 depending on the method described in reference Figures 1 to 8 In the compressed mode, mode signal MS may have a first value. In response to mode signal MS having the first value, demultiplexer DX may transfer the data provided from DMA master "M" to drain circuit DC. In response to mode signal MS having the first value, multiplexer MX may transfer the data provided from validity monitor VM to accelerator core "C".

[0094] In the uncompressed mode, uncompressed weight data may be provided to storage device 180. The uncompressed weight data may have the same size and may be loaded into memory 160. Computing device 10 may program DMA master "M" by using the same start address and the same layer length information. DMA master "M" may transfer the uncompressed weight data stored in memory 160 to accelerator 130.

[0095] In the uncompressed mode, mode signal MS may have a second value different from the first value. In response to mode signal MS having the second value, demultiplexer DX may transfer the data provided from DMA master "M" to multiplexer MX. In response to mode signal MS having the second value, multiplexer MX may transfer the data provided from demultiplexer DX to accelerator core "C".

[0096] Figure 10 Data controller CTb and related components according to at least one embodiment of the present disclosure are shown. Referring to Figure 10 , each of data controllers CTb may include a decompression circuit DCC and a validity monitor VM.

[0097] Each of decompression circuits DCC may decompress the data transferred from the corresponding DMA master in DMA master "M", that is, the data including the compressed weight data. Each of decompression circuits DCC may transfer the decompressed data to the corresponding validity monitor VM in validity monitor VM.

[0098] Each of the validity monitors VM can monitor whether the length (or size) of the data transferred from the corresponding decompression circuit DCC reaches the length (or size) indicated by the original length information OLI. When the length (or size) of the data transferred from the decompression circuit DCC does not reach the length (or size) indicated by the original length information OLI, each of the validity monitors VM can deactivate the reset signal RS. Each of the validity monitors VM can transfer the data provided by the decompression circuit DCC to the corresponding accelerator core "C" in the accelerator core "C".

[0099] When the length (or size) of the data transferred from the decompression circuit DCC reaches the length (or size) indicated by the original length information OLI, each of the validity monitors VM can activate the reset signal RS. The reset signal RS can be transferred to the corresponding DMA master "M" in the DMA master "M". In response to determining that the reset signal RS is activated, the corresponding DMA master "M" can be reset.

[0100] In at least one embodiment, the reset signal RS can also be provided to the decompression circuit DCC. In response to determining that the reset signal RS is activated, the corresponding decompression circuit DCC can be reset.

[0101] In at least one embodiment, as referred to in Figure 9 described, the data controller CTb can include a demultiplexer DX and a multiplexer MX. In the non-compression mode, the demultiplexer DX and the multiplexer MX can bypass the data transferred from the DMA master "M" and transfer it to the accelerator core "C".

[0102] Figure 11 Shows Figure 10 An example of the operation method of the validity monitor VM in each of the data controllers CTb. Refer to Figure 1 、 Figure 10 And Figure 11 In operation S510, the validity monitor VM can receive input data. For example, the validity monitor VM can receive weight data from the corresponding decompression circuit DCC.

[0103] In operation S520, the validity monitor VM can determine whether the data has ended (or whether the end of the data has been reached). For example, when the length (or size) of the received weight data reaches the length (or size) indicated by the original length information OLI, the validity monitor VM can determine that the data has ended. When it is determined that the data has ended, in operation S530, the validity monitor VM can reset the corresponding DMA master "M" in the DMA master "M". After that, the validity monitor VM can terminate the process.

[0104] In operation S540, the validity monitor VM may transfer the input data to the corresponding accelerator core "C" in the accelerator core "C", and may continue to monitor. After that, the validity monitor VM may start again from operation S510.

[0105] As described above, the computing device 10 according to at least one embodiment of the present disclosure may store compressed weight data of different sizes in a storage space of the memory 160 having the same start address and the same layer length information. The computing device 10 may program the DMA master "M" simultaneously by using the same start address and the same layer length information to transfer the weight data to the accelerator 130 in parallel. The validity monitor VM of the data controller CTb of the accelerator 130 may extract the decompressed weight data to transfer it to the accelerator core "C". Since the number of times the DMA master "M" is programmed is reduced, the speed at which the computing device 10 loads the compressed weight data into the accelerator 130 can be increased, and the loading time can be reduced.

[0106] Figure 12 Another example of the weight data (e.g., compressed weight data) in compressed form loaded into the accelerator 130 is shown. Refer to Figure 1 and Figure 12 , in at least one embodiment, the accelerator 130 may run a machine learning module including four layers.

[0107] Each of the fourth compressed weight data WD4, the fifth compressed weight data WD5, the sixth compressed weight data WD6, and the seventh compressed weight data WD7 may correspond to a layer of the machine learning module. The fourth length information LI4 indicating the length of the fourth compressed weight data WD4, the fifth length information LI5 indicating the length of the fifth compressed weight data WD5, the sixth length information LI6 indicating the length of the sixth compressed weight data WD6, and the seventh length information LI7 indicating the length of the seventh compressed weight data WD7 may be stored in the storage device 180 together with the fourth compressed weight data WD4, the fifth compressed weight data WD5, the sixth compressed weight data WD6, and the seventh compressed weight data WD7.

[0108] Figure 13 An example of the process of loading the compressed weight data WD from the storage device 180 to the memory 160 depending on Figure 4 is shown. Refer to Figure 1 , Figure 4 and Figure 13 , the fourth length information LI4, the fifth length information LI5, the sixth length information LI6, the seventh length information LI7, and the original length information OLI may be stored in the third length information area LIA3 of the storage device 180.

[0109] Each of the fourth compressed weight data WD4, the fifth compressed weight data WD5, the sixth compressed weight data WD6, and the seventh compressed weight data WD7 can be stored in a storage space with consecutive addresses.

[0110] The fourth length information LI4 can include information about the start address (represented by an upward arrow) and the length (represented by a left - right arrow) of the fourth compressed weight data WD4. The fifth length information LI5 can include information about the start address (represented by an upward arrow) and the length (represented by a left - right arrow) of the fifth compressed weight data WD5.

[0111] The sixth length information LI6 can include information about the start address (represented by an upward arrow) and the length (represented by a left - right arrow) of the sixth compressed weight data WD6. The seventh length information LI7 can include information about the start address (represented by an upward arrow) and the length (represented by a left - right arrow) of the seventh compressed weight data WD7.

[0112] The processor 120 or the DMAC 170 can load each of the fourth compressed weight data WD4, the fifth compressed weight data WD5, the sixth compressed weight data WD6, and the seventh compressed weight data WD7 in parallel onto a storage space of the memory 160 that starts from the same start address and has consecutive addresses.

[0113] As Figure 13 shown, the fourth compressed weight data WD4, the fifth compressed weight data WD5, and the sixth compressed weight data WD6 can be smaller in length (or size) than the seventh compressed weight data WD7.

[0114] The fourth compressed weight data WD4, the fifth compressed weight data WD5, the sixth compressed weight data WD6, and the seventh compressed weight data WD7 loaded into the memory 160 can be loaded into the accelerator 130 depending on the method described in the reference Figures 1 to 11 described.

[0115] Figure 14 FIG. shows a computing device 20 according to another embodiment of the present disclosure. Reference Figure 14, the computing device 20 may include a system bus 210, a processor 220, an accelerator 230, a modem 240, a memory controller 250, a memory 260, and a storage device 280. The system bus 210, the processor 220, the modem 240, the memory controller 250, the memory 260, and / or the storage device 280 may be the same as and / or substantially similar to the system bus 110, the processor 120, the modem 140, the memory controller 150, the memory 160, the direct memory access controller (DMAC) 170, and / or the storage device 180. Thus, the repetitive description thereof may be omitted.

[0116] The accelerator 230 may include an accelerator core "C", a data controller CT, and a DMA master "M". The DMA master "M" may be dedicated to the accelerator 230. The loading of the compressed weight data into the accelerator 230 may be the same as that described in the reference Figures 1 to 13 , except that the DMA master "M" is included in the accelerator 230.

[0117] In at least one embodiment, the DMA master "M" included in the accelerator 230 may be referred to as an AXI master.

[0118] Some embodiments are described in which the computing device 10 or 20 includes one accelerator 130 or 230. However, the examples are not limited thereto, and the computing device 10 or 20 may include two or more accelerators. The computing device 10 or 20 may load the compressed weight data into at least one of the two or more accelerators by using the DMA master "M" included in at least one of the two or more accelerators. Alternatively, the computing device 10 or 20 may load the compressed weight data into at least one accelerator by using the DMA master "M" of a separate DMA controller.

[0119] In the above embodiments, the components according to the present disclosure are described by using terms such as "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. do not involve any form of order or numerical meaning.

[0120] In the above embodiments, functional components in accordance with embodiments of the present disclosure are described by reference to functional blocks and terms for the functional block elements (e.g., including "processor", "accelerator", etc.). The blocks may be implemented with processing circuitry, such as various hardware devices (such as integrated circuits, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in the hardware devices, software (such as applications), and / or combinations of hardware devices and / or software. In at least some embodiments, the processing circuitry may more specifically be included in (and / or implemented by) a central processing unit (CPU), arithmetic logic unit (ALU), digital signal processor, microcomputer, field programmable gate array (FPGA), system on a chip (SoC), programmable logic unit, microprocessor, application specific integrated circuit (ASIC), etc., but is not limited thereto, and / or may include active and / or passive electrical components, such as transistors, resistors, capacitors, etc., and / or an electronic circuit including one or more of the foregoing components. Further, the blocks may include circuitry implemented with semiconductor elements in an integrated circuit, or circuitry registered as intellectual property (IP). For example, the circuitry may include active and / or passive electrical components, such as transistors, resistors, capacitors, etc.

[0121] According to an embodiment of the present disclosure, a direct memory access (DMA) master of a machine learning accelerator that loads compressed weight data can be programmed simultaneously by using the same start address and the same length information. Accordingly, a machine learning accelerator, a computing device including the machine learning accelerator, and a method of loading data into the machine learning accelerator are provided that can reduce the time taken to load the compressed weight data.

[0122] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A machine learning accelerator, comprising: A first data controller configured to store original length information indicating an original length of data, receive first data having a first length, generate second data having the original length by decompressing the first data having the first length, and output the second data having the original length; A second data controller configured to store the original length information, receive third data having a second length shorter than the first length, generate fourth data having the original length by decompressing the third data having the second length, and output the fourth data having the original length; A first accelerator core configured to receive the second data having the original length and perform a first machine learning-based operation using the second data as first weight data; And A second accelerator core configured to receive the fourth data having the original length and perform a second machine learning-based operation using the fourth data as second weight data, wherein each of the first data controller and the second data controller is configured to: Monitor a timing of decompression completion based on the original length, and Terminate the decompression at the timing of the decompression completion.

2. The machine learning accelerator according to claim 1, wherein The machine learning accelerator is configured to cause the first data controller and the second data controller to: Receive the first data and the second data in parallel, and Output the second data and the fourth data in parallel.

3. The machine learning accelerator according to claim 1, wherein At least one of the first data controller and the second data controller includes: A drain circuit configured to receive corresponding data of the first data and the second data and output the corresponding data when a corresponding drain signal is inactive; A decompression circuit configured to receive the corresponding data from the drain circuit, decompress the corresponding data, and output decompressed data; and A monitor circuit configured to activate the corresponding drain signal when decompression of data indicated by the original length information is completed, and wherein the drain circuit is configured to stop outputting the corresponding data in response to the corresponding drain signal being active.

4. The machine learning accelerator according to claim 3, further comprising at least one of the following: A first direct memory access (DMA) master configured to read the first data having the first length and transfer the first data to the decompression circuit of the first data controller; and A second DMA master configured to read fifth data and transfer the fifth data to the decompression circuit of the second data controller, the fifth data having the first length and including the second data, Among them, The first DMA master and the second DMA master are programmed simultaneously based on the same start address and the first length.

5. The machine learning accelerator according to claim 1, wherein Each of the at least one data controller of the first data controller and the second data controller includes: A decompression circuit, configured to receive corresponding data in the first data and the second data, decompress the corresponding data, and output the decompressed data; and A monitor circuit, configured to activate a reset signal when decompression of the corresponding data indicated by the original length information is completed, and wherein the decompression circuit is configured to stop decompressing the corresponding data in response to determining that the reset signal is active.

6. The machine learning accelerator according to claim 5, wherein The monitor circuit is configured to send the reset signal to a corresponding one of an external first direct memory access (DMA) master and an external second DMA master.

7. The machine learning accelerator according to claim 5, further comprising: A first direct memory access (DMA) master, configured to read the first data having the first length and transfer the first data to the decompression circuit of the first data controller; and A second DMA master, configured to read fifth data and transfer the fifth data to the decompression circuit of the second data controller, the fifth data having the first length and including the second data, wherein the first DMA master is configured to stop reading the first data in response to determining that the reset signal is activated by the monitor circuit of the first data controller, and wherein the second DMA master is configured to stop reading the fifth data in response to determining that the reset signal is activated by the monitor circuit of the second data controller.

8. The machine learning accelerator according to claim 7, wherein The first DMA master and the second DMA master are programmed simultaneously based on the same start address and the first length.

9. A computing device, comprising: A memory, configured to store first data having a first length and second data having a second length shorter than the first length; and A machine learning accelerator, configured to receive the first data and third data from the memory, the third data having the first length and including the second data, wherein the machine learning accelerator is configured to: Generate first weight data by decompressing the first data having the first length, Convert the third data having the first length to the second data having the second length, Generate second weight data by decompressing the second data having the second length, and Perform a machine learning-based operation based on the first weight data and the second weight data.

10. The computing device according to claim 9, further comprising: A first direct memory access (DMA) master and a second DMA master, the first DMA master being configured to read the first data, the second DMA master being configured to read the third data having the first length; and A processor, configured to program the first DMA master and the second DMA master to simultaneously read the first data having the first length and the third data having the first length from the memory.

11. The computing device according to claim 10, wherein, The processor is configured to program the first DMA master and the second DMA master simultaneously based on the first length and the same start address.

12. The computing device according to claim 11, wherein, The third data further includes dummy data, and wherein the second DMA master is configured to read the second data from the memory and then read the dummy data from the memory.

13. The computing device according to claim 12, wherein, The machine learning accelerator is configured to ignore the dummy data after completing the decompression of the second data.

14. The computing device according to claim 9, wherein, The machine learning accelerator includes a first direct memory access (DMA) master and a second DMA master. The first DMA master is configured to read the first data, and the second DMA master is configured to read the third data having the first length, and wherein the computing device further includes: a processor configured to program the first DMA master and the second DMA master to simultaneously read the first data having the first length and the third data having the first length from the memory.

15. The computing device according to claim 9, further comprising: a storage device storing the first data having the first length and the second data having the second length, wherein the computing device is configured to read the first data and the second data from the storage device and thus store the read first data and second data in the memory.

16. The computing device according to claim 15, wherein, The memory is configured to further store third data having a third length and fourth data having a fourth length, and wherein the computing device is configured to store the first data and the second data starting from the same first start address of the memory, and store the third data and the fourth data starting from the same second start address of the memory.

17. The computing device according to claim 16, wherein, The difference between the first start address and the second start address corresponds to the first length.

18. The computing device according to claim 17, wherein, The third data includes the second data and dummy data between the end address of the second data and the second start address.

19. A method in which a processor loads data into a machine learning accelerator, the method comprising: at the processor, programming two or more direct memory access (DMA) masters simultaneously using a first start address and first length information; and at the two or more DMA masters, reading data from a memory in parallel based on the first start address and the first length information and transferring the parallel-read data to the machine learning accelerator, wherein the machine learning accelerator is configured to: generate first weight data by decompressing first data corresponding to the first length information in the parallel-read data, generate third data having a second length shorter than the first length indicated by the first length information by transforming second data corresponding to the first length information, generate second weight data by decompressing the third data having the second length, and Perform a machine learning-based operation based on the first weight data and the second weight data.

20. The method according to claim 19, further comprising: Programming the two or more DMA masters simultaneously using a second start address and second length information; and At the at least two or more DMA masters, reading the next data from the memory in parallel based on the second start address and the second length information, and transmitting the next data read in parallel to the machine learning accelerator.

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