Display panel, display device including display panel, and electronic device

Abstract

A display panel, a display device including the same, and an electronic device are provided. The display panel includes: first to fourth data lines; first to fourth pixel circuits connected to the first to fourth data lines, respectively; and first to fourth light emitting elements connected to the first to fourth pixel circuits, respectively. The first data line and the fourth data line each transmit a first color data signal, the second data line transmits a second color data signal, and the third data line transmits a third color data signal. The first and fourth light-emitting elements emit light of a first color, the second light-emitting element emits light of a second color, and the third light-emitting element emits light of a third color.

Description

[0001] This application claims priority and all benefits derived therefrom to Korean Patent Application No. 10-2024-0010717, filed on January 24, 2024, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display device. Background Art

[0003] Generally, a display device includes a display panel for displaying an image and a driving circuit for driving the display panel. The display panel may include a plurality of scan lines, a plurality of data lines, and a plurality of pixels. The driving circuit may include a data driving circuit that outputs data driving signals to the data lines, a scan driving circuit that outputs scan signals for driving the scan lines, and a driving controller that controls the data driving circuit and the scan driving circuit.

[0004] The display device may display an image by outputting a scan signal to a scan line connected to a pixel for displaying an image and providing a data voltage corresponding to the display image to a data line connected to the pixel.

[0005] Each of the plurality of pixels may emit light of one of various colors, such as red, green, and blue as examples. Each of the plurality of pixels may include a light-emitting element and a pixel circuit for driving the light-emitting element. The plurality of pixels may have various sizes and may be arranged in various ways. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display device having reduced power consumption.

[0007] According to an embodiment, the display panel includes: first to fourth data lines; first to fourth pixel circuits respectively connected to the first to fourth data lines; and first to fourth light-emitting elements respectively connected to the first to fourth pixel circuits. Each of the first data line and the fourth data line transmits a first color data signal, the second data line transmits a second color data signal, and the third data line transmits a third color data signal. The first light-emitting element and the fourth light-emitting element emit light of a first color, the second light-emitting element emits light of a second color, and the third light-emitting element emits light of a third color. The third light-emitting element, the first light-emitting element, the second light-emitting element, and the fourth light-emitting element are sequentially arranged in a first direction.

[0008] The first to fourth light-emitting elements may respectively include first to fourth extension lines, and the first to fourth extension lines may be respectively connected to the first to fourth pixel circuits through first to fourth contact holes.

[0009] The second contact hole and the third contact hole may be disposed between the second light-emitting element and the third light-emitting element.

[0010] Each of the first light-emitting element to the fourth light-emitting element may include an anode and a cathode, and the first extension line to the fourth extension line may extend from the anodes of the first light-emitting element to the fourth light-emitting element, respectively.

[0011] The first extension line, the second extension line, and the fourth extension line may extend from the first light-emitting element, the second light-emitting element, and the fourth light-emitting element, respectively, in a direction opposite to the first direction, and the third extension line may extend from the third light-emitting element in the first direction.

[0012] The first data line and the second data line may be disposed adjacent to each other, and the first contact hole may be disposed between the first data line and the second data line.

[0013] The display panel may further include: a demultiplexer that connects the first output line and the second output line to the first data line and the fourth data line, respectively, in response to a first switching signal, and connects the first output line and the second output line to the second data line and the third data line, respectively, in response to a second switching signal.

[0014] The display panel may further include: a demultiplexer that selectively connects the first output line, the second output line, and the third output line to the first data line to the fourth data line. The demultiplexer may connect the first output line and the third output line to the first data line and the fourth data line, may connect the second output line to the second data line in response to a first switching signal, and may connect the second output line to the third data line in response to a second switching signal.

[0015] The first pixel circuit may include: a first transistor including a first electrode, a second electrode, and a gate electrode; a sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode, and a gate electrode connected to an emission control line; and a connection line connecting the first contact hole and the second electrode of the sixth transistor.

[0016] The display panel may further include: a substrate layer; a circuit element layer on the substrate layer and including the first pixel circuit, the connection line, and a connection electrode disposed on the connection line; and a display element layer disposed on the circuit element layer and including the first light-emitting element. The connection line may be disposed on the second electrode of the sixth transistor and may be electrically connected to the second electrode of the sixth transistor. The connection electrode may be disposed on the connection line and may be connected to the connection line. The first light-emitting element may be connected to the connection line through the first contact hole.

[0017] The second pixel circuit may include: a first transistor including a first electrode, a second electrode, and a gate electrode; a sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode, and a gate electrode connected to an emission control line; and a connection line connecting a second contact hole and the second electrode of the sixth transistor.

[0018] The display panel may further include: a substrate layer; a circuit element layer disposed on the substrate layer and including the second pixel circuit, the connection line, and a connection electrode disposed on the connection line; and a display element layer disposed on the circuit element layer and including a second light-emitting element. The connection line may be disposed on the second electrode of the sixth transistor and may be electrically connected to the second electrode of the sixth transistor. The connection electrode may be disposed on the connection line and may be connected to the connection line. The second light-emitting element may be connected to the connection line through the second contact hole.

[0019] According to an embodiment, an electronic device includes a display panel and a data driving circuit electrically connected to the display panel. The display panel includes: first to fourth data lines; first to fourth pixel circuits respectively connected to the first to fourth data lines; and first to fourth light-emitting elements respectively connected to the first to fourth pixel circuits. The data driving circuit provides a first color data signal to each of the first data line and the fourth data line, provides a second color data signal to the second data line, and provides a third color data signal to the third data line. The first light-emitting element and the fourth light-emitting element emit light of a first color, the second light-emitting element emits light of a second color, and the third light-emitting element emits light of a third color. The third light-emitting element, the first light-emitting element, the second light-emitting element, and the fourth light-emitting element are sequentially arranged in a first direction.

[0020] The first to fourth light-emitting elements may respectively include first to fourth extension lines, and the first to fourth extension lines may be respectively connected to the first to fourth pixel circuits through first to fourth contact holes.

[0021] The first contact hole may be disposed between the first data line and the second data line, and the second contact hole and the third contact hole may be disposed between the second light-emitting element and the third light-emitting element.

[0022] The first extension line, the second extension line, and the fourth extension line may respectively extend from the first light-emitting element, the second light-emitting element, and the fourth light-emitting element in a direction opposite to the first direction, and the third extension line may extend from the third light-emitting element in the first direction.

[0023] According to an embodiment, a display device includes: a display panel including first to fourth data lines; a data driving circuit electrically connected to a first output line and a second output line; and a demultiplexer that connects the first output line and the second output line to the first data line and the fourth data line in response to a first switching signal, and connects the first output line and the second output line to the second data line and the third data line in response to a second switching signal. The display panel includes: first to fourth pixel circuits respectively connected to the first to fourth data lines; and first to fourth light-emitting elements respectively connected to the first to fourth pixel circuits. Each of the first data line and the fourth data line transmits a first color data signal, the second data line transmits a second color data signal, and the third data line transmits a third color data signal. The first light-emitting element and the fourth light-emitting element emit light of a first color, the second light-emitting element emits light of a second color, and the third light-emitting element emits light of a third color. The third light-emitting element, the first light-emitting element, the second light-emitting element, and the fourth light-emitting element are sequentially arranged in a first direction.

[0024] When the first switching signal is at an active level, the data driving circuit may output the first color data signal to the first output line and the second output line; and when the second switching signal is at an active level, the data driving circuit may output the second color data signal and the third color data signal to the first output line and the second output line, respectively.

[0025] The first to fourth light-emitting elements may respectively include first to fourth extension lines. The first to fourth extension lines may be respectively connected to the first to fourth pixel circuits through first to fourth contact holes. The second contact hole and the third contact hole may be provided between the second light-emitting element and the third light-emitting element.

[0026] The first data line and the second data line may be provided adjacent to each other, and the first contact hole may be provided between the first data line and the second data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a view showing a display panel according to an embodiment of the present disclosure.

[0030] Figure 3 is a circuit diagram of a first pixel according to an embodiment of the present disclosure.

[0031] Figure 4 is a circuit diagram of a second pixel and a third pixel according to an embodiment of the present disclosure.

[0032] Figure 5 is a cross-sectional view showing a first light-emitting element and a part of a 21st pixel circuit of a display panel according to an embodiment of the present disclosure.

[0033] Figure 6 is a cross-sectional view showing a third light-emitting element, a 22nd pixel circuit, and a part of a 23rd pixel circuit of a display panel according to an embodiment of the present disclosure.

[0034] Figure 7 is a cross-sectional view showing a second light-emitting element, a 22nd pixel circuit, and a part of a 23rd pixel circuit of a display panel according to an embodiment of the present disclosure.

[0035] Figure 8 is a view showing a data driving circuit and a display panel of a display device according to an embodiment of the present disclosure.

[0036] Figure 9 is a timing diagram for explaining the operation of a display device according to an embodiment of the present disclosure.

[0037] Figure 10 is a view showing a data driving circuit and a display panel of a display device according to an embodiment of the present disclosure.

[0038] Figure 11 is a timing diagram for explaining the operation of a display device according to an embodiment of the present disclosure.

[0039] Figure 12 is a view showing a data driving circuit and a display panel of a display device according to an embodiment of the present disclosure.

[0040] Figure 13 is a timing diagram for explaining the operation of a display device according to an embodiment of the present disclosure.

[0041] Figure 14A and Figure 14B is a plan view of a display panel according to an embodiment of the present disclosure.

[0042] Figure 15 is a view showing a display panel according to an embodiment of the present disclosure.

[0043] Figure 16 is a view showing signal lines and connection lines provided in a display panel according to an embodiment of the present disclosure.

[0044] Figure 17 is a view showing signal lines and connection lines provided in a display panel according to an embodiment of the present disclosure.

[0045] Figure 18 is a view showing signal lines and connection lines provided in a display panel according to an embodiment of the present disclosure.

[0046] Figure 19 is a view showing signal lines and connection lines provided in a display panel according to an embodiment of the present disclosure.

[0047] Figure 20 is a block diagram of an electronic device according to an embodiment of the present disclosure. Detailed Description

[0048] In this specification, when a component (or region, layer, part, etc.) is described as being "on" another component, "connected to" or "coupled to" another component, this means that the component can be directly on the other component, directly connected to or directly coupled to the other component, or there can be a third component therebetween.

[0049] Like reference numerals refer to like components. In some aspects, in the drawings, the thickness, ratio, and dimensions of components are exaggerated for effective description. As used herein, the term "and / or" includes all one or more combinations defined by the related components.

[0050] Terms such as first and second can be used to describe various components, but the components should not be limited by the terms. As used herein, the terms can distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise stated, terms in the singular form can include the plural form.

[0051] In some aspects, terms such as "below", "under", "above", and "over" are used to describe the relationship of components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0052] It should be understood that when terms such as "include", "comprise", and "have" and their variants are used herein, it is specified that there are the stated features, numbers, steps, operations, components, parts, or combinations thereof, but there is no exclusion of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] As used herein, the term "substantially" means approximately or actually. The term "substantially equal" means approximately or actually equal. The term "substantially the same" means approximately or actually the same.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Such terms as defined in a commonly used dictionary shall be interpreted as having a meaning consistent with the context of the relevant art and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined as such in this application.

[0055] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0056] Figure 1 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0057] Referring to Figure 1 , the display device DD includes a driving controller 100, a data driving circuit 200, and a display panel DP.

[0058] The driving controller 100 receives an input image signal RGB and a control signal CTRL. The driving controller 100 generates an output image signal DS by converting the input image signal RGB into an image type suitable for the display panel DP. The driving controller 100 outputs a scan control signal SCS and a data control signal DCS.

[0059] The display panel DP according to an embodiment of the present disclosure may be an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, an example in which the display panel DP is an organic light-emitting display panel will be described herein.

[0060] The display panel DP includes scan lines GL1 to GLn, data lines DL1 to DLm, and pixels PX11 to PXnm.

[0061] The display panel DP includes a display area DA and a non-display area NDA. In an embodiment, the display area DA has a quadrilateral shape. However, the embodiments of the present disclosure are not limited thereto. The non-display area NDA may be in the form of a frame surrounding the display area DA.

[0062] The display panel DP may further include a scan driving circuit 300 and an emission driving circuit 400. The pixels PX11 to PXnm may be disposed in the display area DA, and the scan driving circuit 300 and the emission driving circuit 400 may be disposed in the non-display area NDA.

[0063] The scan lines GL1 to GLn extend from the scan driving circuit 300 in a first direction DR1 and are arranged in a second direction DR2 such that the scan lines GL1 to GLn are spaced apart from each other. The emission control lines EML1 to EMLn extend from the emission driving circuit 400 in a direction opposite to the first direction DR1 and are arranged in the second direction DR2 such that the emission control lines EML1 to EMLn are spaced apart from each other. The data lines DL1 to DLm extend from the data driving circuit 200 in the second direction DR2 and are arranged in the first direction DR1 such that the data lines DL1 to DLm are spaced apart from each other.

[0064] Each of the pixels PX11 to PXnm may be connected to a corresponding scan line among the scan lines GL1 to GLn, a corresponding data line among the data lines DL1 to DLm, and a corresponding emission control line among the emission control lines EML1 to EMLn. In Figure 1 , each of the plurality of pixels PX11 to PXnm is shown connected to one scan line. However, embodiments of the present disclosure are not limited thereto. Each of the plurality of pixels PX11 to PXnm may be electrically connected to two or more scan lines.

[0065] Each of the pixels PX11 to PXnm may include a light-emitting element and a pixel circuit that controls the light emission of the light-emitting element. The light-emitting element and the pixel circuit will be described in detail herein.

[0066] The data driving circuit 200 receives a data control signal DCS and an output image signal DS from the driving controller 100. The data driving circuit 200 converts the output image signal DS into first to third color data signals, and outputs the first to third color data signals to the data lines DL1 to DLm. Each of the first to third color data signals may have a voltage level corresponding to the gray level of the output image signal DS.

[0067] The data driving circuit 200 may be implemented with an integrated circuit (IC). The data driving circuit 200 may be directly mounted in a specific area of the display panel DP. Optionally, the data driving circuit 200 may be mounted on a separate printed circuit board in a chip on film (COF) manner and may be electrically connected to the display panel DP. In an embodiment, the data driving circuit 200 may be formed on the display panel DP by the same process as the process for forming each of the pixel circuits of the pixels PX11 to PXnm.

[0068] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. The scan driving circuit 300 may output scan signals to scan lines GL1 to GLn in response to the scan control signal SCS. In an embodiment, the scan driving circuit 300 may be formed by the same process as the pixel circuits of each of the pixels PX11 to PXnm.

[0069] The emission driving circuit 400 receives an emission driving signal ECS from the driving controller 100. The emission driving circuit 400 may output emission control signals to emission control lines EML1 to EMLn in response to the emission driving signal ECS. In an embodiment, the emission driving circuit 400 may be formed by the same process as the pixel circuits of each of the pixels PX11 to PXnm. Although the emission driving circuit 400 is shown in Figure 1 , embodiments of the present disclosure are not limited thereto. In an embodiment, the emission driving circuit 400 may be included in the scan driving circuit 300.

[0070] The driving controller 100, the data driving circuit 200, the scan driving circuit 300, and the emission driving circuit 400 may be driving circuits for providing first to third color data signals corresponding to an input image signal RGB to the pixels PX11 to PXnm.

[0071] Figure 2 is a view showing a display panel DP according to an embodiment of the present disclosure.

[0072] Referring to Figure 2 , the display panel DP includes data lines DL1 to DL8, first pixel circuits PC11 to PC18, second pixel circuits PC21 to PC28, first light-emitting elements GE11 to GE14 and GE21 to GE24, second light-emitting elements BE15, BE17, BE26, and BE28, and third light-emitting elements RE16, RE18, RE25, and RE27. Figure 2 The sizes, shapes, and arrangement orders of the first light-emitting elements GE11 to GE14 and GE21 to GE24, the second light-emitting elements BE15, BE17, BE26, and BE28, and the third light-emitting elements RE16, RE18, RE25, and RE27 shown in are merely examples for better understanding the description, and embodiments of the present disclosure are not limited thereto.

[0073] The 11th pixel circuit PC11 to the 18th pixel circuit PC18 can be arranged in the first row ROW1 and can be sequentially arranged in the first direction DR1. The 21st pixel circuit PC21 to the 28th pixel circuit PC28 can be arranged in the second row ROW2 and can be sequentially arranged in the first direction DR1.

[0074] The data lines DL1 to DL8 extend in the second direction DR2 and are arranged in the first direction DR1 such that the data lines DL1 to DL8 are spaced apart from each other. Some of the data lines DL1 to DL8 can be arranged adjacent to each other in pairs. That is, the data lines DL1 and DL2 are arranged adjacent to each other, the data lines DL3 and DL4 are arranged adjacent to each other, the data lines DL5 and DL6 are arranged adjacent to each other, and the data lines DL7 and DL8 are arranged adjacent to each other.

[0075] Each of the 11th pixel circuit PC11 to the 18th pixel circuit PC18 is connected to a corresponding one of the data lines DL1 to DL8. Each of the 21st pixel circuit PC21 to the 28th pixel circuit PC28 is connected to a corresponding one of the data lines DL1 to DL8.

[0076] The first light-emitting elements GE11 to GE14, the second light-emitting elements BE15 and BE17, and the third light-emitting elements RE16 and RE18 are arranged in the first row ROW1.

[0077] The second light-emitting element BE15, the first light-emitting element GE11, the third light-emitting element RE16, the first light-emitting element GE12, the second light-emitting element BE17, the first light-emitting element GE13, the third light-emitting element RE18, and the first light-emitting element GE14 can be sequentially arranged in the first direction DR1 in the first row ROW1.

[0078] The first light-emitting elements GE21 to GE24, the second light-emitting elements BE26 and BE28, and the third light-emitting elements RE25 and RE27 are arranged in the second row ROW2.

[0079] The third light-emitting element RE25, the first light-emitting element GE21, the second light-emitting element BE26, the first light-emitting element GE22, the third light-emitting element RE27, the first light-emitting element GE23, the second light-emitting element BE28, and the first light-emitting element GE24 can be sequentially arranged in the first direction DR1 in the second row ROW2.

[0080] In an embodiment, each of the first light-emitting elements GE11 to GE14 and GE21 to GE24 may emit light of a first color, each of the second light-emitting elements BE15, BE17, BE26, and BE28 may emit light of a second color, and each of the third light-emitting elements RE16, RE18, RE25, and RE27 may emit light of a third color.

[0081] In an embodiment, the light of the first color, the light of the second color, and the light of the third color may be lights of different colors.

[0082] In an embodiment, the light of the first color, the light of the second color, and the light of the third color may be green light, blue light, and red light, respectively. However, the embodiments of the present disclosure are not limited thereto. In an embodiment, the light of the first color, the light of the second color, and the light of the third color may be lights of various colors (such as white, cyan, magenta, and yellow, as well as blue, green, and red).

[0083] The first light-emitting elements GE11 to GE14, the second light-emitting elements BE15 and BE17, and the third light-emitting elements RE16 and RE18 in the first row ROW1 may all be electrically connected to the corresponding pixel circuits in the 11th pixel circuit PC11 to the 18th pixel circuit PC18 through the corresponding extension lines (or extension electrodes) EL11 to EL18. The extension lines EL11 to EL18 may extend from the first light-emitting elements GE11 to GE14, the second light-emitting elements BE15 and BE17, and the third light-emitting elements RE16 and RE18 in the first direction DR1 or in a direction opposite to the first direction DR1. For example, the extension lines EL15 and EL17 extend from the second light-emitting elements BE15 and BE17 in the first direction DR1. The extension lines EL11, EL12, EL13, EL14, EL16, and EL18 extend from the first light-emitting elements GE11 to GE14 and the third light-emitting elements RE16 and RE18 in a direction opposite to the first direction DR1.

[0084] In an embodiment, the first light-emitting elements GE11 to GE14, the second light-emitting elements BE15 and BE17, and the third light-emitting elements RE16 and RE18 may be electrically connected to the 11th pixel circuit PC11 to the 18th pixel circuit PC18 through the extension lines EL11 to EL18, respectively.

[0085] The first light-emitting elements GE21 to GE24, the second light-emitting elements BE26 and BE28, and the third light-emitting elements RE25 and RE27 in the second row ROW2 may all be electrically connected to the corresponding pixel circuits in the 21st pixel circuit PC21 to the 28th pixel circuit PC28 through the corresponding extension lines (or extension electrodes) EL21 to EL28.

[0086] In an embodiment, the first light-emitting elements GE21 to GE24 may be electrically connected to the 21st pixel circuit PC21, the 24th pixel circuit PC24, the 25th pixel circuit PC25, and the 28th pixel circuit PC28 through extension lines EL21 to EL24, respectively.

[0087] In an embodiment, the second light-emitting elements BE26 and BE28 may be electrically connected to the 22nd pixel circuit PC22 and the 26th pixel circuit PC26 through extension lines EL26 and EL28, respectively. The third light-emitting elements RE25 and RE27 may be electrically connected to the 23rd pixel circuit PC23 and the 27th pixel circuit PC27 through extension lines EL25 and EL27, respectively.

[0088] The extension lines EL21 to EL28 may extend from the first light-emitting elements GE21 to GE24, the second light-emitting elements BE26 and BE28, and the third light-emitting elements RE25 and RE27 in a first direction DR1 or in a direction opposite to the first direction DR1. For example, the extension lines EL21 to EL28 may extend from the anodes of the first light-emitting elements GE21 to GE24, the second light-emitting elements BE26 and BE28, and the third light-emitting elements RE25 and RE27. In an embodiment, the extension lines EL21 to EL28 may be integrally formed with or formed in the same process as the anodes of the first light-emitting elements GE21 to GE24, the second light-emitting elements BE26 and BE28, and the third light-emitting elements RE25 and RE27. Hereinafter, the anodes of the first light-emitting elements GE21 to GE24, the second light-emitting elements BE26 and BE28, and the third light-emitting elements RE25 and RE27 may be used to refer to both the anodes and their corresponding extension lines. For example, the extension lines EL25 and EL27 extend from the third light-emitting elements RE25 and RE27 in the first direction DR1. The extension lines EL21, EL22, EL23, EL24, EL26, and EL28 extend from the first light-emitting elements GE21 to GE24 and the second light-emitting elements BE26 and BE28 in a direction opposite to the first direction DR1.

[0089] For example, the first light-emitting element GE21 may be electrically connected to the 21st pixel circuit PC21 through the extension line EL21 and the contact hole CT21. In an embodiment, the contact hole CT21 may be provided between the data lines DL1 and DL2.

[0090] For example, the second light-emitting element BE26 may be electrically connected to the 22nd pixel circuit PC22 through the extension line EL26 and the contact hole CT26. The third light-emitting element RE25 may be electrically connected to the 23rd pixel circuit PC23 through the extension line EL25 and the contact hole CT25. In an embodiment, the contact holes CT25 and CT26 may be provided between the second light-emitting element BE26 and the third light-emitting element RE25.

[0091] The data driving circuit 200 (refer to Figure 1 ) outputs the first color data signals GD1, GD4, GD5, and GD8 to data lines DL1, DL4, DL5, and DL8 respectively, outputs the second color data signals BD2 and BD6 to data lines DL2 and DL6 respectively, and outputs the third color data signals RD3 and RD7 to data lines DL3 and DL7 respectively.

[0092] In an embodiment, each of the first color data signals GD1, GD4, GD5, and GD8 may be a green data signal, each of the second color data signals BD2 and BD6 may be a blue data signal, and each of the third color data signals RD3 and RD7 may be a red data signal.

[0093] The data driving circuit 200 may output only the data signals corresponding to a specific color to each of the data lines DL1 to DL8, and thus may reduce power consumption.

[0094] For example, the current corresponding to the first color data signal GD1 provided to the data line DL1 may be transmitted to the first light emitting elements GE11 and GE21 through the 11th pixel circuit PC11 and the 21st pixel circuit PC21.

[0095] The current corresponding to the second color data signal BD2 provided to the data line DL2 may be transmitted to the second light emitting elements BE15 and BE26 through the 12th pixel circuit PC12 and the 22nd pixel circuit PC22.

[0096] The current corresponding to the third color data signal RD3 provided to the data line DL3 may be transmitted to the third light emitting elements RE16 and RE25 through the 13th pixel circuit PC13 and the 23rd pixel circuit PC23.

[0097] The current corresponding to the first color data signal GD4 provided to the data line DL4 may be transmitted to the first light emitting elements GE12 and GE22 through the 14th pixel circuit PC14 and the 24th pixel circuit PC24.

[0098] The current corresponding to the first color data signal GD5 provided to the data line DL5 may be transmitted to the first light emitting elements GE13 and GE23 through the 15th pixel circuit PC15 and the 25th pixel circuit PC25.

[0099] The current corresponding to the second color data signal BD6 provided to the data line DL6 may be transmitted to the second light emitting elements BE17 and BE28 through the 16th pixel circuit PC16 and the 26th pixel circuit PC26.

[0100] The current corresponding to the third color data signal RD7 provided to the data line DL7 can be transmitted to the third light-emitting elements RE18 and RE27 through the 17th pixel circuit PC17 and the 27th pixel circuit PC27.

[0101] The current corresponding to the first color data signal GD8 provided to the data line DL8 can be transmitted to the first light-emitting elements GE14 and GE24 through the 18th pixel circuit PC18 and the 28th pixel circuit PC28.

[0102] In Figure 2 only some of the multiple pixel circuits, multiple light-emitting elements, and multiple data lines provided in the display panel DP are shown. The multiple pixel circuits, multiple light-emitting elements, and multiple data lines provided in the first direction DR1 and the multiple pixel circuits, multiple light-emitting elements, and multiple data lines provided in the second direction DR2 can be repeatedly provided in the same manner as Figure 2 the data lines DL1 to DL8, the 11th pixel circuit PC11 to the 18th pixel circuit PC18, the 21st pixel circuit PC21 to the 28th pixel circuit PC28, the first light-emitting elements GE11 to GE14 and GE21 to GE24, the second light-emitting elements BE15, BE17, BE26, and BE28, and the third light-emitting elements RE16, RE18, RE25, and RE27 shown in

[0103] Figure 3 is a circuit diagram of a first pixel GPX according to an embodiment of the present disclosure. Figure 3 The first pixel GPX shown in Figure 1 can be one of the pixels PX11 to PXnm shown in

[0104] Referring to Figure 3 , the first pixel GPX may include the 21st pixel circuit PC21 and the first light-emitting element GE21. In an embodiment, the first light-emitting element GE21 may be a light-emitting diode. The first light-emitting element GE21 may emit light of a first color (e.g., green light).

[0105] In an embodiment, the 21st pixel circuit PC21 may include at least one transistor and at least one capacitor. Figure 3 The 21st pixel circuit PC21 shown in Figure 3 includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 and a capacitor Cst.

[0106] In this embodiment, among the first transistor T1 to the seventh transistor T7, each of the third transistor T3 and the fourth transistor T4 is an N-type transistor having an oxide semiconductor as a semiconductor layer, and each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is a P-type transistor having low-temperature polysilicon (LTPS) as a semiconductor layer. However, the embodiments of the present disclosure are not limited thereto. In an embodiment, the first transistor T1 to the seventh transistor T7 may all be P-type transistors or N-type transistors. In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the remaining transistors may be P-type transistors.

[0107] In an embodiment, the 21st pixel circuit PC21 may be electrically connected to a data line DL1, four scan lines GIL2, GCL2, GWL2, and GWL3, and an emission control line EML2. Figure 1 Each of the scan lines GL1 to GLn shown in may include a plurality of scan lines. In an embodiment, Figure 1 The scan line GL1 shown in may include four scan lines GIL2, GCL2, GWL2, and GWL3.

[0108] The scan lines GIL2, GCL2, GWL2, and GWL3 may transmit scan signals GI2, GC2, GW2, and GW3, respectively, and the emission control line EML2 may transmit an emission control signal EM2. The data line DL1 transmits a first color data signal GD1. The first color data signal GD1 may have a voltage level corresponding to the input image signal RGB input to the display device DD (refer to Figure 1 ). The first driving voltage line to the fourth driving voltage line VL1, VL2, VL3, and VL4 may transmit a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2, respectively.

[0109] The first transistor T1 includes a first electrode S1 connected to the first driving voltage line VL1 via the fifth transistor T5, a second electrode D1, and a gate electrode G1 connected to one end of the capacitor Cst.

[0110] The second transistor T2 includes a first electrode S2 connected to the data line DL1, a second electrode D2 connected to the first electrode S1 of the first transistor T1, and a gate electrode connected to the scan line GWL2. The second transistor T2 may be turned on in response to the scan signal GW2 transmitted through the scan line GWL2, and may transmit the first color data signal GD1 transmitted from the data line DL1 to the first electrode S1 of the first transistor T1. The first color data signal GD1 transmitted from the data line DL1 may correspond to the first color.

[0111] The third transistor T3 includes a first electrode connected to the gate electrode G1 of the first transistor T1, a second electrode connected to the second electrode D1 of the first transistor T1, and a gate electrode connected to the scan line GCL2. The third transistor T3 can be turned on in response to a scan signal GC2 transmitted through the scan line GCL2, and can diode-connect the first transistor T1 by connecting the gate electrode G1 and the second electrode D1 of the first transistor T1.

[0112] The fourth transistor T4 includes a first electrode connected to the gate electrode G1 of the first transistor T1, a second electrode connected to the third driving voltage line VL3 through which a first initialization voltage VINT1 is transmitted, and a gate electrode connected to the scan line GIL2. The fourth transistor T4 can be turned on in response to a scan signal GI2 transmitted through the scan line GIL2, and can transmit the first initialization voltage VINT1 to the gate electrode G1 of the first transistor T1 to perform an initialization operation of initializing the voltage of the gate electrode G1 of the first transistor T1.

[0113] The fifth transistor T5 includes a first electrode S5 connected to the first driving voltage line VL1, a second electrode D5 connected to the first electrode S1 of the first transistor T1, and a gate electrode connected to the emission control line EML2.

[0114] The sixth transistor T6 includes a first electrode S6 connected to the second electrode D1 of the first transistor T1, a second electrode D6 connected to the anode of the first light-emitting element GE21, and a gate electrode G6 connected to the emission control line EML2. The second electrode D6 of the sixth transistor T6 and the anode of the first light-emitting element GE21 can be connected through a contact hole CT21.

[0115] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously in response to an emission control signal EM2 transmitted through the emission control line EML2. When the fifth transistor T5 and the sixth transistor T6 are turned on, a current path can be formed from the first driving voltage line VL1 through the fifth transistor T5, the first transistor T1, and the sixth transistor T6 to the first light-emitting element GE21. In this case, the current flowing through the first transistor T1 can correspond to the charge stored in the capacitor Cst. Therefore, a current Ig corresponding to the first color data signal GD1 can be transmitted to the first light-emitting element GE21. In other words, the first color data signal GD1 can be converted into a current Ig by the 21st pixel circuit PC21 and provided to the first light-emitting element GE21.

[0116] The seventh transistor T7 includes a first electrode connected to the second electrode D6 of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4, and a gate electrode connected to the scan line GWL3. The seventh transistor T7 can be turned on in response to a scan signal GW3 transmitted through the scan line GWL3, and can initialize the anode of the first light-emitting element GE21 to a second initialization voltage VINT2 from the fourth driving voltage line VL4.

[0117] As described herein, one end of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the first light-emitting element GE21 can be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS.

[0118] Similar to Figure 3 the 21st pixel circuit PC21 shown in Figure 2 the 11th pixel circuit PC11, the 14th pixel circuit PC14, the 15th pixel circuit PC15, the 18th pixel circuit PC18, the 24th pixel circuit PC24, the 25th pixel circuit PC25, and the 28th pixel circuit PC28 shown in

[0119] Figure 4 are circuit diagrams of a second pixel BPX and a third pixel RPX according to an embodiment of the present disclosure.

[0120] Referring to Figure 4 , the second pixel BPX includes the 22nd pixel circuit PC22 and a second light-emitting element BE26. The third pixel RPX includes the 23rd pixel circuit PC23 and a third light-emitting element RE25.

[0121] Figure 4 Each of the 22nd pixel circuit PC22 and the 23rd pixel circuit PC23 shown in Figure 3 may include a circuit configuration similar to that of the 21st pixel circuit PC21 shown in Figure 4 The components of the 22nd pixel circuit PC22 and the 23rd pixel circuit PC23 that are the same as those of the 21st pixel circuit PC21 shown in Figure 3 will be assigned the same reference numerals, and repeated descriptions will be omitted.

[0122] Referring to Figure 2 and Figure 4, the 22nd pixel circuit PC22 can be electrically connected to the second light-emitting element BE26 through the connection line CL26. Therefore, the current Ib corresponding to the second color data signal BD2 provided to the 22nd pixel circuit PC22 can be transmitted to the second light-emitting element BE26. In other words, the second color data signal BD2 can be converted into the current Ib by the 22nd pixel circuit PC22 and provided to the second light-emitting element BE26.

[0123] The 23rd pixel circuit PC23 can be electrically connected to the third light-emitting element RE25 through the connection line CL25. Therefore, the current Ir corresponding to the third color data signal RD3 provided to the 23rd pixel circuit PC23 can be transmitted to the third light-emitting element RE25. In other words, the third color data signal RD3 can be converted into the current Ir by the 23rd pixel circuit PC23 and provided to the third light-emitting element RE25.

[0124] Figure 5 is a cross-sectional view showing a part of the first light-emitting element GE21 and the 21st pixel circuit PC21 of the display panel DP according to an embodiment of the present disclosure.

[0125] Refer to Figure 5 , the display panel DP may include a substrate layer BL, a circuit element layer DP-CL, a display element layer DP-ED, and a thin film encapsulation layer TFE. The display panel DP may further include functional layers, such as a reflectance control layer or a refractive index control layer as an example. The circuit element layer DP-CL at least includes a plurality of insulating layers and circuit elements. Hereinafter, the insulating layer may include an organic layer and / or an inorganic layer.

[0126] The insulating layer, the semiconductor layer, and the conductive layer are formed by a process such as coating or deposition as an example. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned by a photolithography process and an etching process. Semiconductor patterns, conductive patterns, and signal lines are formed by these processes. Patterns provided in the same layer are formed by the same process.

[0127] The substrate layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material of the synthetic resin layer is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a silicone resin, a polyamide resin, and a perylene-based resin. In some aspects, the substrate layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0128] At least one inorganic layer is formed on the upper surface of the substrate layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of multiple layers. At least one of the multiple inorganic layers may constitute the buffer layer BFL.

[0129] The buffer layer BFL improves the adhesion between the substrate layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately with each other.

[0130] The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may be directly disposed on the buffer layer BFL. The semiconductor pattern may include a silicon semiconductor. The semiconductor pattern may include low-temperature polycrystalline silicon. However, without limitation, the semiconductor pattern may include amorphous silicon.

[0131] The semiconductor pattern has different electrical characteristics depending on whether doping is performed. The semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant.

[0132] The doped region has a higher conductivity than the undoped region and basically serves as an electrode or a signal line. The undoped region basically corresponds to the active region (or channel) of the transistor. In other words, a part of the semiconductor pattern may be the active region of the transistor, another part of the semiconductor pattern may be the first electrode (or source electrode) or the second electrode (or drain electrode) of the transistor, and other parts of the semiconductor pattern may be connection electrodes or connection signal lines.

[0133] As Figure 5 shown, the first electrode S1, the active region A1, and the second electrode D1 of the first transistor T1 in the 21st pixel circuit PC21 are formed of the semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the active region A1 in opposite directions. In some aspects, the first electrode S6, the active region A6, and the second electrode D6 of the sixth transistor T6 are formed of the semiconductor pattern. The first electrode S6 and the second electrode D6 of the sixth transistor T6 extend from the active region A6 in opposite directions. Although not shown separately, the first electrode S6 of the sixth transistor T6 may be connected to the second electrode D1 of the first transistor T1.

[0134] As Figure 3 shown, the first electrode S6 of the sixth transistor T6 may be electrically connected to the second electrode D1 of the first transistor T1.

[0135] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is in contact with Figure 2The 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28 shown in the figure are stacked together and cover the semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single silicon oxide layer. Not only the first insulating layer 10 but also the insulating layer of the circuit element layer DP-CL to be described herein may include an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the aforementioned materials.

[0136] The gate electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The gate electrode G1 may be part of a metal pattern. The gate electrode G1 of the first transistor T1 overlaps with the active region A1 of the first transistor T1. The gate electrode G1 of the first transistor T1 serves as a mask in the process of doping the semiconductor pattern.

[0137] The second insulating layer 20 is disposed on the first insulating layer 10 and covers the gate electrode G1. The second insulating layer 20 may overlap with the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28. The second insulating layer 20 may include an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. In this embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0138] The third insulating layer 30 is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single silicon oxide layer.

[0139] The connection line CL21 may be disposed on the third insulating layer 30. The connection line CL21 may be connected to the second electrode D6 of the sixth transistor T6 through a contact hole CT21a penetrating the first insulating layer 10 to the third insulating layer 30.

[0140] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and cover the connection line CL21. The fourth insulating layer 40 may be a single silicon oxide layer. The connection electrode CNE21 may be disposed on the fourth insulating layer 40. The connection electrode CNE21 may be connected to the connection line CL21 through a contact hole CNT21 penetrating the fourth insulating layer 40.

[0141] In an embodiment, similar to the connection electrode CNE21, the data lines DL1 and DL2 may be disposed on the fourth insulating layer 40.

[0142] The fifth insulating layer 50 is disposed on the fourth insulating layer 40 and covers the connection electrode CNE21. The fifth insulating layer 50 may be an organic layer.

[0143] The anode GAE21 is disposed on the fifth insulating layer 50. The anode GAE21 is connected to the connection electrode CNE21 through a contact hole CT21 that penetrates the fifth insulating layer 50. Accordingly, the anode GAE21 can be connected to the second electrode D6 of the sixth transistor T6 through the connection electrode CNE21 and the connection line CL21.

[0144] An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the anode GAE21.

[0145] The emission layer EML is disposed on the anode GAE21. The emission layer EML may be disposed only in a region corresponding to the opening OP. The emission layer EML may be separately formed for each of the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28.

[0146] Although a patterned emission layer EML is shown in this embodiment, the emission layer EML may be commonly disposed in the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28. In this case, the emission layer EML may generate white light or blue light. In some aspects, the emission layer EML may have a multilayer structure. The cathode CE is disposed on the emission layer EML. The cathode CE is commonly disposed in the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28.

[0147] Although not shown in the drawings, a hole control layer may be disposed between the anode GAE21 and the emission layer EML. In some aspects, an electron control layer may be disposed between the emission layer EML and the cathode CE.

[0148] The thin film encapsulation layer TFE is disposed on the cathode CE. The thin film encapsulation layer TFE is commonly disposed in the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28. In this embodiment, the thin film encapsulation layer TFE directly covers the cathode CE. In an embodiment of the present disclosure, a cover layer directly covering the cathode CE may be additionally provided.

[0149] The thin film encapsulation layer TFE includes at least an inorganic layer or an organic layer. In an embodiment of the present disclosure, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. In an embodiment of the present disclosure, the thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers stacked alternately with each other.

[0150] The inorganic layer protects the first light emitting element GE21 from moisture / oxygen, and the organic layer protects the first light emitting element GE21 from foreign substances such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not particularly limited thereto. The organic layer may include an acrylic organic layer, but is not particularly limited.

[0151] Figure 6 It is a cross-sectional view showing a part of the third light emitting element RE25, the 22nd pixel circuit PC22, and the 23rd pixel circuit PC23 of the display panel DP according to an embodiment of the present disclosure.

[0152] Figure 6 The third light emitting element RE25 shown in may include components similar to those of the first light emitting element GE21 shown in Figure 5 Therefore, repeated descriptions will be omitted.

[0153] Figure 6 The first transistor T1 and the sixth transistor T6 of the 22nd pixel circuit PC22 shown in may include components similar to those of the first transistor T1 and the sixth transistor T6 of the 21st pixel circuit PC21 shown in Figure 5 Therefore, repeated descriptions will be omitted.

[0154] In addition, Figure 6 The sixth transistor T6 of the 23rd pixel circuit PC23 shown in may include components similar to those of the sixth transistor T6 of the 21st pixel circuit PC21 shown in Figure 5 Therefore, repeated descriptions will be omitted.

[0155] Referring to Figure 6 , at least a part of the third light emitting element RE25 may be formed to overlap with the 22nd pixel circuit PC22. The anode RAE25 of the third light emitting element RE25 may be electrically connected to the connection line CL25 through the contact hole CT25 and the contact hole CNT25 of the connection electrode CNE25. The connection line CL25 extends from the contact hole CNT25 of the connection electrode CNE25 in the direction where the 23rd pixel circuit PC23 is provided.

[0156] The connection line CL25 can be connected to the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 through a contact hole CT25a that penetrates the first insulating layer 10 to the third insulating layer 30.

[0157] That is, the anode RAE25 of the third light-emitting element RE25 can be electrically connected to the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 through the contact hole CT25, the connection electrode CNE25, and the connection line CL25.

[0158] Figure 7 FIG. is a cross-sectional view showing a part of the second light-emitting element BE26, the 22nd pixel circuit PC22, and the 23rd pixel circuit PC23 of the display panel DP according to an embodiment of the present disclosure.

[0159] Figure 7 The second light-emitting element BE26 shown in may include components similar to those of the Figure 5 first light-emitting element GE21 shown in. Therefore, repeated descriptions will be omitted.

[0160] Figure 7 The first transistor T1 and the sixth transistor T6 of the 23rd pixel circuit PC23 shown in may include components similar to those of the Figure 5 first transistor T1 and the sixth transistor T6 of the 21st pixel circuit PC21 shown in. Therefore, repeated descriptions will be omitted.

[0161] In addition, Figure 7 the sixth transistor T6 of the 22nd pixel circuit PC22 shown in may include components similar to those of the Figure 5 sixth transistor T6 of the 21st pixel circuit PC21 shown in. Therefore, repeated descriptions will be omitted.

[0162] Referring to Figure 7 , at least a part of the second light-emitting element BE26 can be formed to overlap with the 23rd pixel circuit PC23. The anode BAE26 of the second light-emitting element BE26 can be electrically connected to the connection line CL26 through the contact hole CT26 and the contact hole CNT26 of the connection electrode CNE26. The connection line CL26 extends from the contact hole CNT26 of the connection electrode CNE26 in the direction where the 22nd pixel circuit PC22 is provided. The connection line CL26 can be connected to the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 through a contact hole CT26a that penetrates the first insulating layer 10 to the third insulating layer 30.

[0163] That is to say, the anode BAE26 of the second light-emitting element BE26 can be electrically connected to the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 through the contact hole CT26, the connection electrode CNE26, and the connection line CL26.

[0164] Figure 8 It is a view showing a data driving circuit 200a and a display panel DPa of a display device DDa according to an embodiment of the present disclosure.

[0165] Referring to Figure 8 , the data driving circuit 200a converts the output image signal DS provided from the driving controller 100 (referring to Figure 1 ) into first to third color data signals, and outputs the first to third color data signals to the output lines Y1 to Y4. Each of the first to third color data signals may have a voltage level corresponding to the gray level of the output image signal DS. In an embodiment, the number of output lines Y1 to Y4 may be less than the number of data lines DL1 to DL8.

[0166] The display panel DPa includes a demultiplexer DMUX1. The demultiplexer DMUX1 can electrically connect the output lines Y1 to Y4 and the data lines DL1 to DL8 in response to the first switching signal CLA and the second switching signal CLB. In an embodiment, the first switching signal CLA and the second switching signal CLB may be provided from the driving controller 100 shown in Figure 1 .

[0167] In Figure 8 , the demultiplexer DMUX1 is shown as being provided in the display panel DPa. However, the embodiments of the present disclosure are not limited thereto. In an embodiment, the demultiplexer DMUX1 may be included in the data driving circuit 200a. In an embodiment, the demultiplexer DMUX1 may be included in a separate driving circuit or a separate circuit board independent of the display panel DPa and the data driving circuit 200a.

[0168] The demultiplexer DMUX1 includes switching transistors ST11, ST12, ST13, ST14, ST15, ST16, ST17, and ST18.

[0169] The switching transistor ST11 is connected between the output line Y1 and the data line DL1. The switching transistor ST12 is connected between the output line Y1 and the data line DL2. The switching transistor ST13 is connected between the output line Y2 and the data line DL3. The switching transistor ST14 is connected between the output line Y2 and the data line DL4. The switching transistor ST15 is connected between the output line Y3 and the data line DL5. The switching transistor ST16 is connected between the output line Y3 and the data line DL6. The switching transistor ST17 is connected between the output line Y4 and the data line DL7. The switching transistor ST18 is connected between the output line Y4 and the data line DL8.

[0170] The switching transistors ST11, ST14, ST15, and ST18 are turned on in response to the first switching signal CLA, and the switching transistors ST12, ST13, ST16, and ST17 are turned on in response to the second switching signal CLB. For example, the switching transistors ST11, ST14, ST15, and ST18 may be turned on when the first switching signal CLA is equal to or less than a threshold voltage level (i.e., a low level or a low voltage level) (also referred to as an activation level herein), and the switching transistors ST12, ST13, ST16, and ST17 may be turned on when the second switching signal CLB is less than or equal to the threshold voltage level (i.e., a low level or a low voltage level) (also referred to as an activation level herein).

[0171] Figure 9 is a timing diagram for explaining the operation of the display device DDa according to an embodiment of the present disclosure.

[0172] Referring to Figure 1 、 Figure 8 and Figure 9 and, the data driving circuit 200a alternately and sequentially outputs the first color data signal GD1 and the second color data signal BD2 to the demultiplexer DMUX1 through the output line Y1.

[0173] The data driving circuit 200a alternately and sequentially outputs the first color data signal GD4 and the third color data signal RD3 to the demultiplexer DMUX1 through the output line Y2.

[0174] The data driving circuit 200a alternately and sequentially outputs the first color data signal GD5 and the second color data signal BD6 to the demultiplexer DMUX1 through the output line Y3.

[0175] The data driving circuit 200a alternately and sequentially outputs the first color data signal GD8 and the third color data signal RD7 to the demultiplexer DMUX1 through the output line Y4.

[0176] The first switching signal CLA and the second switching signal CLB are sequentially set to a low level (in other words, activated at a low level) in each of the horizontal periods H1, H2, H3, and H4. For example, during the horizontal period H1, the first switching signal CLA is activated at a low level, and thereafter, the second switching signal CLB is activated at a low level. In an embodiment, the low-level section of the first switching signal CLA does not overlap with the low-level section of the second switching signal CLB.

[0177] When the first switching signal CLA is at a low level, the demultiplexer DMUX1 outputs the first color data signals GD1, GD4, GD5, and GD8 from the output lines Y1, Y2, Y3, and Y4 to the data lines DL1, DL4, DL5, and DL8.

[0178] When the second switching signal CLB is at a low level, the demultiplexer DMUX1 outputs the second color data signals BD2 and BD6 and the third color data signals RD3 and RD7 from the output lines Y1, Y2, Y3, and Y4 to the data lines DL2, DL3, DL6, and DL7.

[0179] Therefore, the first color data signal GD1, the second color data signal BD2, the third color data signal RD3, the first color data signal GD4, the first color data signal GD5, the second color data signal BD6, the third color data signal RD7, and the first color data signal GD8 can be provided to the data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, and DL8, respectively.

[0180] In Figure 8 In the example shown, some of the data lines DL1 to DL8 can be arranged adjacent to each other in pairs. That is, the data lines DL1 and DL2 are arranged adjacent to each other, the data lines DL3 and DL4 are arranged adjacent to each other, the data lines DL5 and DL6 are arranged adjacent to each other, and the data lines DL7 and DL8 are arranged adjacent to each other.

[0181] In an example where the third color data signal RD3 is transmitted to the data line DL3 while the data line DL2 in the two adjacent data lines DL2 and DL3 floats, due to the coupling between the data lines DL2 and DL3, the third color data signal RD3 may affect the data line DL2.

[0182] In Figure 8 In the example shown, the demultiplexer DMUX1 simultaneously outputs the first color data signals GD1, GD4, GD5, and GD8 in response to the first switching signal CLA. The demultiplexer DMUX1 simultaneously outputs the second color data signals BD2 and BD6 and the third color data signals RD3 and RD7 in response to the second switching signal CLB.

[0183] That is, the second color data signal BD2 and the third color data signal RD3 are simultaneously transmitted to two adjacent data lines DL2 and DL3. The first color data signals GD4 and GD5 are simultaneously transmitted to two adjacent data lines DL4 and DL5. That is, the second color data signal BD6 and the third color data signal RD7 are simultaneously transmitted to two adjacent data lines DL6 and DL7. Therefore, color data signals can be prevented from being distorted due to coupling between adjacent data lines.

[0184] Figure 10 It is a view showing a data driving circuit 200b-1 and a display panel DPb-1 of a display device DDb-1 according to an embodiment of the present disclosure.

[0185] Referring to Figure 10 , the data driving circuit 200b-1 converts an output image signal DS provided from a driving controller 100 (referring to Figure 1 ) into first to third color data signals, and outputs the first to third color data signals to output lines Y1 to Y6. Each of the first to third color data signals may have a voltage level corresponding to the gray level of the output image signal DS. In an embodiment, the number of output lines Y1 to Y6 may be less than the number of data lines DL1 to DL8.

[0186] In Figure 10 the example shown, some of the data lines DL1 to DL8 may be arranged adjacent to each other in pairs. That is, the data lines DL1 and DL2 are arranged adjacent to each other, the data lines DL3 and DL4 are arranged adjacent to each other, the data lines DL5 and DL6 are arranged adjacent to each other, and the data lines DL7 and DL8 are arranged adjacent to each other.

[0187] The display panel DPb-1 includes a demultiplexer DMUX2. The demultiplexer DMUX2 can electrically connect the output lines Y1 to Y6 and the data lines DL1 to DL8 in response to a first switching signal CLA and a second switching signal CLB. In an embodiment, the first switching signal CLA and the second switching signal CLB may be provided from the Figure 1 driving controller 100 shown.

[0188] In Figure 10 it, the demultiplexer DMUX2 is shown as being provided in the display panel DPb-1. However, an embodiment of the present disclosure is not limited thereto. In an embodiment, the demultiplexer DMUX2 may be included in the data driving circuit 200b-1. In an embodiment, the demultiplexer DMUX2 may be included in a separate driving circuit or a separate circuit board independent of the display panel DPb-1 and the data driving circuit 200b-1.

[0189] The demultiplexer DMUX2 includes switching transistors ST21, ST22, ST23, and ST24.

[0190] In an embodiment, output lines Y1, Y3, Y4, and Y6 may be directly connected to data lines DL1, DL4, DL5, and DL8, respectively.

[0191] The switching transistor ST21 is connected between the output line Y2 and the data line DL2. The switching transistor ST22 is connected between the output line Y2 and the data line DL3. The switching transistor ST23 is connected between the output line Y5 and the data line DL6. The switching transistor ST24 is connected between the output line Y5 and the data line DL7.

[0192] The switching transistors ST21 and ST23 are turned on in response to a first switching signal CLA, and the switching transistors ST22 and ST24 are turned on in response to a second switching signal CLB.

[0193] Figure 11 is a timing diagram for explaining the operation of the display device DDb-1 according to an embodiment of the present disclosure.

[0194] Referring to Figure 1 、 Figure 10 and Figure 11 ,the data driving circuit 200b-1 sequentially outputs a first color data signal GD1 to the demultiplexer DMUX2 through the output line Y1.

[0195] The data driving circuit 200b-1 alternately and sequentially outputs a second color data signal BD2 and a third color data signal RD3 to the demultiplexer DMUX2 through the output line Y2.

[0196] The data driving circuit 200b-1 sequentially outputs a first color data signal GD4 to the demultiplexer DMUX2 through the output line Y3.

[0197] The data driving circuit 200b-1 sequentially outputs a first color data signal GD5 to the demultiplexer DMUX2 through the output line Y4.

[0198] The data driving circuit 200b-1 alternately and sequentially outputs a second color data signal BD6 and a third color data signal RD7 to the demultiplexer DMUX2 through the output line Y5.

[0199] The data driving circuit 200b-1 sequentially outputs a first color data signal GD8 to the demultiplexer DMUX2 through the output line Y6.

[0200] The first switching signal CLA and the second switching signal CLB are sequentially set to a low level (in other words, activated at a low level) in each of the horizontal periods H1, H2, H3, and H4. For example, during the horizontal period H1, the first switching signal CLA is activated at a low level, and thereafter, the second switching signal CLB is activated at a low level. In an embodiment, the low-level section of the first switching signal CLA does not overlap with the low-level section of the second switching signal CLB.

[0201] When the first switching signal CLA is at a low level, the demultiplexer DMUX2 outputs the second color data signals BD2 and BD6 from the output lines Y2 and Y5 to the data lines DL2 and DL6.

[0202] When the second switching signal CLB is at a low level, the demultiplexer DMUX2 outputs the third color data signals RD3 and RD7 from the output lines Y2 and Y5 to the data lines DL3 and DL7.

[0203] Therefore, the first color data signal GD1, the second color data signal BD2, the third color data signal RD3, the first color data signal GD4, the first color data signal GD5, the second color data signal BD6, the third color data signal RD7, and the first color data signal GD8 can be provided to the data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, and DL8, respectively.

[0204] The data driving circuit 200b-1 can output the first color data signals GD1, GD4, GD5, and GD8 to the output lines Y1, Y3, Y4, and Y6 in each of the horizontal periods H1, H2, H3, and H4. Therefore, unnecessary charge and discharge operations in the output lines Y1, Y3, Y4, and Y6 are reduced. Therefore, the power consumption of the data driving circuit 200b-1 can be minimized.

[0205] According to the above connection method of the 11th pixel circuit PC11 to the 18th pixel circuit PC18, the 21st pixel circuit PC21 to the 28th pixel circuit PC28, the first light-emitting elements GE11 to GE14 and GE21 to GE24, the second light-emitting elements BE15, BE17, BE26, and BE28, and the third light-emitting elements RE16, RE18, RE25, and RE27, as Figure 2 shown, the data driving circuit 200 can be directly connected to the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28. In addition, as Figure 8As shown in the figure, the data driving circuit 200a can be connected to the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28 through the demultiplexer DMUX1. In some aspects, as Figure 10 As shown in the figure, the data driving circuit 200b-1 can be connected to the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28 through the demultiplexer DMUX2.

[0206] Figure 12 FIG. is a view showing a data driving circuit 200b-2 and a display panel DPB-2 of a display device DDb-2 according to an embodiment of the present disclosure.

[0207] Referring to Figure 12 , the data driving circuit 200b-2 converts the output image signal DS provided from the driving controller 100 (refer to Figure 1 ) into first to third color data signals, and outputs the first to third color data signals to the output lines Y1 to Y6. Each of the first to third color data signals may have a voltage level corresponding to the gray level of the output image signal DS. In an embodiment, the number of the output lines Y1 to Y6 may be less than the number of the data lines DL1 to DL8.

[0208] Some of the data lines DL1 to DL8 of the display panel DPB-2 may be arranged adjacent to each other in pairs. That is, the data lines DL1 and DL2 are arranged adjacent to each other, the data lines DL3 and DL4 are arranged adjacent to each other, the data lines DL5 and DL6 are arranged adjacent to each other, and the data lines DL7 and DL8 are arranged adjacent to each other.

[0209] The display panel DPB-2 includes a demultiplexer DMUX3. The demultiplexer DMUX3 can electrically connect the output lines Y1 to Y6 and the data lines DL1 to DL8 in response to the first switching signal CLA and the second switching signal CLB. In an embodiment, the first switching signal CLA and the second switching signal CLB may be provided from the Figure 1 shown driving controller 100.

[0210] In Figure 12 , the demultiplexer DMUX3 is shown as being provided in the display panel DPB-2. However, the embodiments of the present disclosure are not limited thereto. In an embodiment, the demultiplexer DMUX3 may be included in the data driving circuit 200b-2. In an embodiment, the demultiplexer DMUX3 may be included in a separate driving circuit or a separate circuit board independent of the display panel DPB-2 and the data driving circuit 200b-2.

[0211] The demultiplexer DMUX3 includes switching transistors ST31, ST32, ST33, and ST34.

[0212] In an embodiment, output lines Y1, Y3, Y4, and Y6 may be directly connected to data lines DL1, DL4, DL5, and DL8, respectively.

[0213] The switching transistor ST31 is connected between the output line Y2 and the data line DL2. The switching transistor ST32 is connected between the output line Y5 and the data line DL3. The switching transistor ST33 is connected between the output line Y2 and the data line DL6. The switching transistor ST34 is connected between the output line Y5 and the data line DL7.

[0214] The switching transistors ST31 and ST32 are turned on in response to the first switching signal CLA, and the switching transistors ST33 and ST34 are turned on in response to the second switching signal CLB.

[0215] Figure 13 is a timing diagram for explaining the operation of the display device DDb-2 according to an embodiment of the present disclosure.

[0216] Referring to Figure 1 、 Figure 12 and Figure 13 and

[0217] The data driving circuit 200b-2 sequentially outputs the first color data signal GD1 to the demultiplexer DMUX3 through the output line Y1.

[0218] The data driving circuit 200b-2 alternately and sequentially outputs the second color data signal BD2 and the second color data signal BD6 to the demultiplexer DMUX3 through the output line Y2.

[0219] The data driving circuit 200b-2 sequentially outputs the first color data signal GD4 to the demultiplexer DMUX3 through the output line Y3.

[0220] The data driving circuit 200b-2 alternately and sequentially outputs the third color data signal RD3 and the third color data signal RD7 to the demultiplexer DMUX3 through the output line Y5.

[0221] The data driving circuit 200b-2 sequentially outputs the first color data signal GD8 to the demultiplexer DMUX3 through the output line Y6.

[0222] The first switching signal CLA and the second switching signal CLB are sequentially set to a low level (in other words, activated at a low level) in each of the horizontal periods H1, H2, H3, and H4. For example, during the horizontal period H1, the first switching signal CLA is activated at a low level, and thereafter, the second switching signal CLB is activated at a low level. In an embodiment, the low-level section of the first switching signal CLA does not overlap with the low-level section of the second switching signal CLB.

[0223] When the first switching signal CLA is at a low level, the demultiplexer DMUX3 outputs the second color data signal BD2 and the third color data signal RD3 from the output lines Y2 and Y5 to the data lines DL2 and DL3.

[0224] When the second switching signal CLB is at a low level, the demultiplexer DMUX3 outputs the second color data signal BD6 and the third color data signal RD7 from the output lines Y2 and Y5 to the data lines DL6 and DL7.

[0225] Therefore, the first color data signal GD1, the second color data signal BD2, the third color data signal RD3, the first color data signal GD4, the first color data signal GD5, the second color data signal BD6, the third color data signal RD7, and the first color data signal GD8 can be provided to the data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, and DL8, respectively.

[0226] The data driving circuit 200b-2 can output the first color data signals GD1, GD4, GD5, and GD8 to the output lines Y1, Y3, Y4, and Y6 in each of the horizontal periods H1, H2, H3, and H4. The data driving circuit 200b-2 can output the second color data signals BD2 and BD6 to the output line Y2 in each of the horizontal periods H1, H2, H3, and H4. The data driving circuit 200b-2 can output the third color data signals RD3 and RD7 to the output line Y5 in each of the horizontal periods H1, H2, H3, and H4.

[0227] Therefore, unnecessary charge and discharge operations in the output lines Y1 to Y6 are reduced. Therefore, the power consumption of the data driving circuit 200b-2 can be minimized.

[0228] Figure 14A and Figure 14B is a plan view of the display panel DP according to an embodiment of the present disclosure.

[0229] Figure 14A is a plan view of the display panel DP in a state where the first light-emitting element to the third light-emitting element are not provided. Figure 14BIt is a plan view of a display panel DP in a state where a first light-emitting element to a third light-emitting element are provided therein.

[0230] Figure 14A and Figure 14B The plan views are illustrative only, and embodiments of the present disclosure are not limited thereto.

[0231] Referring to Figure 5 , Figure 2 , Figure 14A and Figure 14B , the anode GAE21 of the first light-emitting element GE21 can be connected to the connection line CL21 through the contact hole CNT21 of the connection electrode CNE21. In some aspects, the connection line CL21 can be connected to the second electrode D6 of the sixth transistor T6 in the 21st pixel circuit PC21 through the contact hole CT21a. When viewed from above the plane, the contact hole CNT21 can be provided between the data lines DL1 and DL2. Since the contact hole CNT21 is provided between the data lines DL1 and DL2, the degree of freedom in the size and position of the anode GAE21 of the first light-emitting element GE21 can be improved.

[0232] Referring to Figure 6 , Figure 2 , Figure 14A and Figure 14B , the connection electrode CNE25 can be electrically connected to the anode RAE25 of the third light-emitting element RE25 through the contact hole CT25, and can be electrically connected to the connection line CL25 through the contact hole CNT25.

[0233] Referring to Figure 7 , Figure 2 , Figure 14A and Figure 14B , the connection electrode CNE26 can be electrically connected to the anode BAE26 of the second light-emitting element BE26 through the contact hole CT26, and can be electrically connected to the connection line CL26 through the contact hole CNT26.

[0234] In an embodiment, when viewed from above the plane, the contact holes CNT25 and CNT26 can be provided between the data lines DL2 and DL3. That is, the contact holes CNT25 and CNT26 can be provided between the third light-emitting element RE25 and the second light-emitting element BE26.

[0235] Figure 15 It is a view showing a display panel DPc according to an embodiment of the present disclosure.

[0236] Figure 15 The components of the display panel DPc shown in Figure 8 are similar to the components of the display panel DPa shown in Figure 15The components of the display panel DPc shown in [the figure] will be assigned the same reference numerals, and duplicate descriptions will be omitted.

[0237] Figure 8 The first light-emitting elements GE11 to GE14 and GE21 to GE24, the second light-emitting elements BE15, BE17, BE26, and BE28, and the third light-emitting elements RE16, RE18, RE25, and RE27 of the display panel DPa shown in [the figure] have a polygonal shape.

[0238] Figure 15 The first light-emitting elements GE11 to GE14 and GE21 to GE24, the second light-emitting elements BE15, BE17, BE26, and BE28, and the third light-emitting elements RE16, RE18, RE25, and RE27 of the display panel DPc shown in [the figure] have a circular shape.

[0239] As described herein, the shapes of the first light-emitting elements GE11 to GE14 and GE21 to GE24, the second light-emitting elements BE15, BE17, BE26, and BE28, and the third light-emitting elements RE16, RE18, RE25, and RE27 can be modified in various ways.

[0240] Figure 15 The connection relationships between the 11th pixel circuit PC11 to the 18th pixel circuit PC18 and the 21st pixel circuit PC21 to the 28th pixel circuit PC28 shown in [the figure] and the first light-emitting elements GE11 to GE14 and GE21 to GE24, the second light-emitting elements BE15, BE17, BE26, and BE28, and the third light-emitting elements RE16, RE18, RE25, and RE27 can be the same as the connection relationships described with reference to Figure 8 described.

[0241] Figure 16 is a view showing signal lines and connection lines provided in the display panel DP.

[0242] In Figure 16 it shows some signal lines and connection lines provided in Figure 2 the 21st pixel circuit PC21 to the 24th pixel circuit PC24 shown in [the figure]. Figure 16 The signal lines and connection lines shown in [the figure] are merely examples for better understanding of the present disclosure, and the embodiments of the present disclosure are not limited thereto. The arrangement order, line width, and shape of the signal lines and connection lines can be modified in various ways.

[0243] Referring to Figure 2 , Figure 3 and Figure 16, the fourth driving voltage line VL4, the scanning lines GIL2 and GWL2, and the emission control line EML2 extend in a first direction DR1 in each of the 21st to 24th pixel circuits PC21 to PC24. The first driving voltage line VL1 and the data lines DL1, DL2, DL3, and DL4 extend in a second direction DR2.

[0244] In each of the 21st to 24th pixel circuits PC21 to PC24, the first electrode S2 of the second transistor T2 may be connected to a corresponding one of the data lines DL1 to DL4. The second electrode D2 of the second transistor T2 may be connected to the first electrode S1 of the first transistor T1. The first electrode S5 of the fifth transistor T5 may be connected to the first driving voltage line VL1. The second electrode D5 of the fifth transistor T5 may be connected to the first electrode S1 of the first transistor T1. The first electrode S6 of the sixth transistor T6 may be connected to the second electrode D1 of the first transistor T1.

[0245] The second electrode D6 of the sixth transistor T6 in the 21st pixel circuit PC21 may be connected to the anode GAE21 of the first light-emitting element GE21 through the connection line CL21.

[0246] In an embodiment, the 21st pixel circuit PC21 and the 22nd pixel circuit PC22 may have shapes that are symmetric to each other with respect to a virtual reference line extending in the second direction DR2. The 22nd pixel circuit PC22 and the 23rd pixel circuit PC23 may have shapes that are symmetric to each other with respect to a virtual reference line extending in the second direction DR2. The 23rd pixel circuit PC23 and the 24th pixel circuit PC24 may have shapes that are symmetric to each other with respect to a virtual reference line extending in the second direction DR2.

[0247] Referring to Figure 5 and Figure 16 , one end CL21a of the connection line CL21 is connected to the connection electrode CNE21. That is, the connection line CL21 may be connected to the anode GAE21 of the first light-emitting element GE21 through the connection electrode CNE21. The connection line CL21 may be connected to the second electrode D6 of the sixth transistor T6 in the 21st pixel circuit PC21 through the contact hole CT21a.

[0248] Referring to Figure 6 and Figure 16, the connection line CL25 can be connected to the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 through the contact hole CT25a. One end CL25a of the connection line CL25 is connected to the connection electrode CNE25. Therefore, the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 can be connected to the anode RAE25 of the third light-emitting element RE25 through the connection line CL25 and the connection electrode CNE25.

[0249] Referring to Figure 7 and Figure 16 , the connection line CL26 can be connected to the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 through the contact hole CT26a. One end CL26a of the connection line CL26 is connected to the connection electrode CNE26. Therefore, the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 can be connected to the anode BAE26 of the second light-emitting element BE26 through the connection line CL26 and the connection electrode CNE26.

[0250] Figure 17 is a view showing signal lines and connection lines provided in the display panel DPd according to an embodiment of the present disclosure.

[0251] In Figure 17 , some of the signal lines and connection lines provided in the 11th pixel circuit PC11 to the 14th pixel circuit PC14 and the 21st pixel circuit PC21 to the 24th pixel circuit PC24 shown in Figure 2 are shown. Figure 17 The signal lines and connection lines shown in

[0252] are only examples for better understanding of the present disclosure, and the embodiments of the present disclosure are not limited thereto. The arrangement order, line width, and shape of the signal lines and connection lines can be modified in various ways. Figure 17 Among the signal lines and connection lines of the display panel DPd shown in Figure 16 , the signal lines and connection lines that are the same as those of the display panel DP shown in

[0253] will be assigned the same reference numerals, and repeated descriptions will be omitted. Figure 5 and Figure 17, one end CL21a of the connection line CL21 is connected to the connection electrode CNE21. That is to say, the connection line CL21 can be connected to the anode GAE21 of the first light-emitting element GE21 in the second row ROW2 through the connection electrode CNE21. The connection line CL21 can be connected to the second electrode D6 of the sixth transistor T6 in the 11th pixel circuit PC11 in the first row ROW1 through the contact hole CT21a. That is to say, the anode GAE21 of the first light-emitting element GE21 in the second row ROW2 is electrically connected to the 11th pixel circuit PC11 in the first row ROW1.

[0254] Since the first light-emitting element GE21 provided in the second row ROW2 is connected to the 11th pixel circuit PC11 provided in the first row ROW1 as described here, the connection line CL21 can be shorter than the connection line CL21 shown in Figure 16 . In this case, the first light-emitting elements GE21 and GE14 in the first row ROW1 shown in Figure 2 can be dummy elements that do not emit light.

[0255] Referring to Figure 6 and Figure 17 , the connection line CL25 can be connected to the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 through the contact hole CT25a. One end CL25a of the connection line CL25 is connected to the connection electrode CNE25. Therefore, the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 can be connected to the anode RAE25 of the third light-emitting element RE25 through the connection line CL25 and the connection electrode CNE25.

[0256] Referring to Figure 7 and Figure 17 , the connection line CL26 can be connected to the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 through the contact hole CT26a. One end CL26a of the connection line CL26 is connected to the connection electrode CNE26. Therefore, the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 can be connected to the anode BAE26 of the second light-emitting element BE26 through the connection line CL26 and the connection electrode CNE26.

[0257] Figure 18 is a view showing signal lines and connection lines provided in the display panel DPe according to an embodiment of the present disclosure.

[0258] In Figure 18 , some signal lines and connection lines provided in the 21st pixel circuit PC21 to the 24th pixel circuit PC24 shown in Figure 2 are shown. Figure 18The signal lines and connection lines shown are merely examples for better understanding of the present disclosure, and embodiments of the present disclosure are not limited thereto. The arrangement order, line width, and shape of the signal lines and connection lines can be modified in various ways.

[0259] Among the signal lines and connection lines of the display panel DPe shown in Figure 18 and the signal lines and connection lines of the display panel DP shown in Figure 16 the signal lines and connection lines that are the same will be assigned the same reference numerals, and repeated descriptions will be omitted.

[0260] Referring to Figure 2 、 Figure 3 and Figure 18 the fourth driving voltage line VL4, the scan lines GIL2 and GWL2, and the emission control line EML2 extend in the first direction DR1 in each of the 21st pixel circuit PC21 to the 24th pixel circuit PC24. The first driving voltage line VL1 and the data lines DL1, DL2, DL3, and DL4 extend in the second direction DR2.

[0261] In Figure 16 the display panel DP shown in Figure 17 and the display panel DPd shown in

[0262] Figure 18 two data lines are arranged adjacent to each other. That is, the data lines DL1 and DL2 are arranged adjacent to each other, and the data lines DL3 and DL4 are arranged adjacent to each other. In some aspects, one end CL21a of the connection line CL21 is disposed between the data lines DL1 and DL2.

[0263] In an embodiment, the 21st pixel circuit PC21 and the 22nd pixel circuit PC22, and the 23rd pixel circuit PC23 and the 24th pixel circuit PC24 may be symmetric with respect to a virtual reference line extending in the second direction DR2 between the 22nd pixel circuit PC22 and the 23rd pixel circuit PC23.

[0264] In each of the 21st pixel circuit PC21 to the 24th pixel circuit PC24, the first electrode S5 of the fifth transistor T5 may be connected to the first driving voltage line VL1. The second electrode D5 of the fifth transistor T5 may be connected to the data line DL1 and the first electrode S1 of the first transistor T1.

[0265] Referring to Figure 5 and Figure 18 , one end CL21a of the connection line CL21 is connected to the connection electrode CNE21. That is, the connection line CL21 may be connected to the anode GAE21 of the first light-emitting element GE21 through the connection electrode CNE21. The connection line CL21 may be connected to the second electrode D6 of the sixth transistor T6 in the 21st pixel circuit PC21 through the contact hole CT21a.

[0266] Referring to Figure 6 and Figure 18 , the connection line CL25 may be connected to the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 through the contact hole CT25a. One end CL25a of the connection line CL25 is connected to the connection electrode CNE25. Therefore, the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 may be connected to the anode RAE25 of the third light-emitting element RE25 through the connection line CL25 and the connection electrode CNE25.

[0267] Referring to Figure 7 and Figure 18 , the connection line CL26 may be connected to the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 through the contact hole CT26a. One end CL26a of the connection line CL26 is connected to the connection electrode CNE26. Therefore, the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 may be connected to the anode BAE26 of the second light-emitting element BE26 through the connection line CL26 and the connection electrode CNE26.

[0268] Figure 19 is a view showing signal lines and connection lines provided in the display panel DPf according to an embodiment of the present disclosure.

[0269] In Figure 19 , some of the signal lines and connection lines provided in the Figure 2 shown in the 11th pixel circuit PC11 to the 14th pixel circuit PC14 and the 21st pixel circuit PC21 to the 24th pixel circuit PC24 are shown. Figure 19 The signal lines and connection lines shown in

[0270] Among the signal lines and connection lines of the display panel DPf shown in Figure 19 , the signal lines and connection lines that are the same as those of the display panel DP shown in Figure 16 will be assigned the same reference numerals, and repeated descriptions will be omitted.

[0271] Referring to Figure 5 and Figure 19 , one end CL21a of the connection line CL21 is connected to the connection electrode CNE21. That is to say, the connection line CL21 can be connected to the anode GAE21 of the first light-emitting element GE21 in the second row ROW2 through the connection electrode CNE21. The connection line CL21 can be connected to the second electrode D6 of the sixth transistor T6 in the 11th pixel circuit PC11 in the first row ROW1 through the contact hole CT21a. That is to say, the anode GAE21 of the first light-emitting element GE21 in the second row ROW2 is electrically connected to the 11th pixel circuit PC11 in the first row ROW1.

[0272] Since the first light-emitting element GE21 provided in the second row ROW2 is connected to the 11th pixel circuit PC11 provided in the first row ROW1 as described here, the connection line CL21 can be shorter than the connection line CL21 shown in Figure 18 . In this case, the first light-emitting elements GE21 and GE14 in the first row ROW1 shown in Figure 2 can be dummy elements that do not emit light.

[0273] Referring to Figure 6 and Figure 19 , the connection line CL25 can be connected to the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 through the contact hole CT25a. One end CL25a of the connection line CL25 is connected to the connection electrode CNE25. Therefore, the second electrode D6 of the sixth transistor T6 in the 23rd pixel circuit PC23 can be connected to the anode RAE25 of the third light-emitting element RE25 through the connection line CL25 and the connection electrode CNE25.

[0274] Referring to Figure 7 and Figure 19 , the connection line CL26 can be connected to the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 through the contact hole CT26a. One end CL26a of the connection line CL26 is connected to the connection electrode CNE26. Therefore, the second electrode D6 of the sixth transistor T6 in the 22nd pixel circuit PC22 can be connected to the anode BAE26 of the second light-emitting element BE26 through the connection line CL26 and the connection electrode CNE26.

[0275] Figure 20It is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0276] Referring to Figure 20 , the electronic device 10 according to an embodiment of the present disclosure may include a processor PP, a power module PM, a display device DD, and a memory MM.

[0277] The processor PP may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0278] The display device DD may include the same configuration as that shown in Figures 1 to 19 .

[0279] According to an embodiment, Figure 1 the driving controller 100 of the display device DD shown in

[0280] may receive an input image signal RGB and a control signal CTRL from the processor PP. The memory MM may store data information necessary for the operation of the processor PP or the display device DD. When the processor PP executes an application stored in the memory MM, an image data signal and / or an input control signal are transmitted to the display device DD, and the display device DD may process the received signals and output image information through a display screen.

[0281] The power module PM may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power necessary for the operation of the electronic device 10.

[0282] The display device having the above configuration may output only a data signal corresponding to one color to one data line. Therefore, the power consumption of the display device can be reduced.

[0283] In some aspects, the difference in the coupling capacitance between data lines can be minimized, so that the deterioration of the display quality can be prevented.

[0284] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display panel, the display panel comprising: A first data line, a second data line, a third data line, and a fourth data line; A first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, respectively connected to the first data line to the fourth data line; and A first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element, respectively connected to the first pixel circuit to the fourth pixel circuit, Wherein each of the first data line and the fourth data line transmits a first color data signal, the second data line transmits a second color data signal, and the third data line transmits a third color data signal, Wherein the first light-emitting element and the fourth light-emitting element emit light of a first color, the second light-emitting element emits light of a second color, and the third light-emitting element emits light of a third color, and Wherein the third light-emitting element, the first light-emitting element, the second light-emitting element, and the fourth light-emitting element are sequentially arranged in a first direction.

2. The display panel according to claim 1, wherein, The first light-emitting element to the fourth light-emitting element respectively include a first extension line, a second extension line, a third extension line, and a fourth extension line, and Wherein the first extension line to the fourth extension line are respectively connected to the first pixel circuit to the fourth pixel circuit through a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole.

3. The display panel according to claim 2, wherein, The second contact hole and the third contact hole are provided between the second light-emitting element and the third light-emitting element.

4. The display panel according to claim 2, wherein, Each of the first light-emitting element to the fourth light-emitting element includes an anode and a cathode, and Wherein the first extension line to the fourth extension line respectively extend from the anodes of the first light-emitting element to the fourth light-emitting element.

5. The display panel according to claim 2, wherein, The first extension line, the second extension line, and the fourth extension line respectively extend from the first light-emitting element, the second light-emitting element, and the fourth light-emitting element in a direction opposite to the first direction, and Wherein the third extension line extends from the third light-emitting element in the first direction.

6. The display panel according to claim 2, wherein, The first data line and the second data line are arranged adjacent to each other, and the first contact hole is provided between the first data line and the second data line.

7. The display panel according to claim 6, the display panel further comprising: A demultiplexer configured to connect a first output line and a second output line to the first data line and the fourth data line respectively in response to a first switch signal, and connect the first output line and the second output line to the second data line and the third data line respectively in response to a second switch signal.

8. The display panel according to claim 2, the display panel further comprising: A demultiplexer configured to selectively connect a first output line, a second output line, and a third output line to the first data line to the fourth data line, Wherein the demultiplexer: Connects the first output line and the third output line to the first data line and the fourth data line; Connects the second output line to the second data line in response to a first switch signal; and Connect the second output line to the third data line in response to the second switch signal.

9. The display panel according to claim 2, wherein, The first pixel circuit includes: A first transistor including a first electrode, a second electrode, and a gate electrode; A sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode, and a gate electrode connected to an emission control line; and A connection line configured to connect the first contact hole and the second electrode of the sixth transistor.

10. The display panel according to claim 9, wherein, The display panel further includes: A substrate layer; A circuit element layer disposed on the substrate layer, the circuit element layer including the first pixel circuit, the connection line, and a connection electrode disposed on the connection line; and A display element layer disposed on the circuit element layer, the display element layer including the first light-emitting element, wherein the connection line is disposed on the second electrode of the sixth transistor and is electrically connected to the second electrode of the sixth transistor, wherein the connection electrode is disposed on the connection line and is connected to the connection line, and wherein the first light-emitting element is connected to the connection line through the first contact hole.

11. The display panel according to claim 2, wherein, The second pixel circuit includes: A first transistor including a first electrode, a second electrode, and a gate electrode; A sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode, and a gate electrode connected to an emission control line; and A connection line configured to connect the second contact hole and the second electrode of the sixth transistor.

12. The display panel according to claim 11, wherein, The display panel further includes: A substrate layer; A circuit element layer disposed on the substrate layer, the circuit element layer including the second pixel circuit, the connection line, and a connection electrode disposed on the connection line; and A display element layer disposed on the circuit element layer, the display element layer including the second light-emitting element, wherein the connection line is disposed on the second electrode of the sixth transistor and is electrically connected to the second electrode of the sixth transistor, wherein the connection electrode is disposed on the connection line and is connected to the connection line, and wherein the second light-emitting element is connected to the connection line through the second contact hole.

13. An electronic device for providing an image, the electronic device including: A display panel; And A data driving circuit electrically connected to the display panel, wherein the display panel includes: a first data line, a second data line, a third data line, and a fourth data line; a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit respectively connected to the first data line to the fourth data line; and a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element respectively connected to the first pixel circuit to the fourth pixel circuit, wherein the data driving circuit provides a first color data signal to each of the first data line and the fourth data line, provides a second color data signal to the second data line, and provides a third color data signal to the third data line, Wherein, the first light-emitting element and the fourth light-emitting element emit light of a first color, the second light-emitting element emits light of a second color, and the third light-emitting element emits light of a third color, and Wherein, the third light-emitting element, the first light-emitting element, the second light-emitting element, and the fourth light-emitting element are sequentially arranged in a first direction.

14. The electronic device according to claim 13, wherein, The first light-emitting element to the fourth light-emitting element respectively include a first extension line, a second extension line, a third extension line, and a fourth extension line, and Wherein, the first extension line to the fourth extension line are respectively connected to the first pixel circuit to the fourth pixel circuit through a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole.

15. The electronic device according to claim 14, wherein, The first contact hole is disposed between the first data line and the second data line, and Wherein, the second contact hole and the third contact hole are disposed between the second light-emitting element and the third light-emitting element.

16. The electronic device according to claim 14, wherein The first extension line, the second extension line, and the fourth extension line respectively extend from the first light-emitting element, the second light-emitting element, and the fourth light-emitting element in a direction opposite to the first direction, and Wherein, the third extension line extends from the third light-emitting element in the first direction.

17. A display device, the display device comprising: A display panel including a first data line, a second data line, a third data line, and a fourth data line; A data driving circuit electrically connected to a first output line and a second output line; And A demultiplexer configured to connect the first output line and the second output line to the first data line and the fourth data line in response to a first switching signal, and connect the first output line and the second output line to the second data line and the third data line in response to a second switching signal, Wherein, the display panel includes: a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit respectively connected to the first data line to the fourth data line; and a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element respectively connected to the first pixel circuit to the fourth pixel circuit, Wherein, each of the first data line and the fourth data line transmits a first color data signal, the second data line transmits a second color data signal, and the third data line transmits a third color data signal, Wherein, the first light-emitting element and the fourth light-emitting element emit light of a first color, the second light-emitting element emits light of a second color, and the third light-emitting element emits light of a third color, and Wherein, the third light-emitting element, the first light-emitting element, the second light-emitting element, and the fourth light-emitting element are sequentially arranged in a first direction.

18. The display device according to claim 17, wherein, When the first switch signal is at an active level, the data driving circuit outputs the first color data signal to the first output line and the second output line; and when the second switch signal is at the active level, the data driving circuit outputs the second color data signal and the third color data signal to the first output line and the second output line respectively.

19. The display device according to claim 18, wherein, The first light emitting element to the fourth light emitting element respectively include a first extension line, a second extension line, a third extension line, and a fourth extension line. Wherein, the first extension line to the fourth extension line are respectively connected to the first pixel circuit to the fourth pixel circuit through a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole, and wherein, the second contact hole and the third contact hole are provided between the second light emitting element and the third light emitting element.

20. The display device according to claim 19, wherein, The first data line and the second data line are arranged adjacent to each other, and the first contact hole is provided between the first data line and the second data line.

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