Pixel circuit and display panel

Abstract

This application discloses a pixel circuit and a display panel. The pixel circuit includes: a scan control module for writing data signals; a data storage module for storing data signals; and a light-emitting module that drives light-emitting elements based on power flowing through the data storage module. The data storage module includes a memory with a magnetoresistive effect, the data signal modulates the impedance of the memory, and the power supply flowing through the data storage module has a voltage loss corresponding to the data signal. This pixel circuit utilizes a memory with a magnetoresistive effect to store data signals, eliminating the need for capacitors and some switching transistors, significantly reducing the area occupied by the pixel circuit, and effectively improving the pixel density of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a pixel circuit and a display panel. Background Technology

[0002] With the development of display technology, display panels have become an indispensable part of electronic devices, and are widely used in various electronic devices such as televisions, computers, mobile phones, tablets, e-readers, game consoles, automobiles, home appliances, and medical equipment.

[0003] Pixel circuitry is a key component of display panels, consisting of a series of tiny electronic elements (such as transistors) used to control the color and brightness of each pixel in the display panel. With technological advancements and increasing consumer demands, the performance requirements for display panels are also rising. Among these, pixel density (Pixel Per Inch, PPI) is a crucial indicator of display panel sharpness. PPI refers to the number of pixels per inch, measured in ppi. A higher PPI results in more detailed images, richer colors, and better visual effects. However, in some electronic devices, due to size limitations, display panels require very high PPI to meet display requirements. Currently, the PPI of display panels is still not high enough to be used in electronic devices with high PPI display needs.

[0004] Therefore, it is desirable to provide an improved pixel circuit and display panel to solve the above problems. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a pixel circuit and a display panel to reduce the area occupied by the pixel circuit and increase the pixel density of the display panel.

[0006] According to one aspect of the present invention, a pixel circuit is provided, comprising: a scan control module for writing a data signal; a data storage module for storing the data signal; and a light-emitting module for driving a light-emitting element based on a power supply flowing through the data storage module, wherein the data storage module includes a memory having a magnetoresistive effect, the data signal modulates the impedance of the memory, and the power supply has a voltage loss corresponding to the data signal after flowing through the data storage module.

[0007] Optionally, when the data signal is valid, the memory is in a low-impedance state, and the power supply drives the light-emitting element to emit light; when the data signal is invalid, the memory is in a high-impedance state, and the power supply drives the light-emitting element to stop emitting light.

[0008] Optionally, the voltage of the power supply is lower than the high level of the data signal and higher than the low level of the data signal.

[0009] Optionally, the scanning control module includes a first switching transistor, whose first current terminal receives the data signal, and whose second current terminal is connected to the second terminal of the memory. A control terminal receives a scanning signal. The light-emitting module includes a current source and a light-emitting element. The current source is connected between the memory and the light-emitting element, or between the power supply and the memory. The control terminal of the current source receives a reference signal, and the second terminal of the light-emitting element receives a common voltage. The first terminal of the memory is connected to the power supply. When the scanning signal is valid, the data signal is written to the memory. When the scanning signal is invalid, the power supply drives the light-emitting element through the memory. The voltage value of the power supply is higher than the low level of the data signal and lower than the high level of the data signal.

[0010] Optionally, the scanning control module includes a selector, a first terminal of which receives the data signal and a second terminal connected to a second terminal of the memory. The first terminal of the memory receives the scanning signal. The light-emitting module includes a current source and a light-emitting element. A first current terminal of the current source is connected to a second terminal of the memory, and a second current terminal is connected to a first terminal of the light-emitting element. A control terminal receives a reference signal, and a common voltage is received at the second terminal of the light-emitting element. The selector is turned on when the absolute value of the voltage difference between the first and second terminals of the selector is greater than or equal to a threshold voltage. When the scanning signal is valid, the data signal is written to the memory. When the scanning signal is invalid, the power supply drives the light-emitting element through the memory. The scanning signal is valid when it is low and invalid when it is high. The high level of the scanning signal serves as the power supply.

[0011] Optionally, the selector includes a first diode and a second diode, the anode of the first diode being connected to the cathode of the second diode and receiving the data signal, and the anode of the second diode being connected to the cathode of the first diode and connected to a second terminal of the memory.

[0012] Optionally, the data signal is in an active state when it is high and in an inactive state when it is low. The initial state of the memory is a high-impedance state. The high level of the data signal is greater than the low level of the scan signal. When the memory drives the light-emitting element, the low level of the data signal is higher than the difference between the voltage value at the second terminal of the memory and the threshold voltage, and the difference between the high level of the data signal and the threshold voltage is lower than the voltage value at the second terminal of the memory.

[0013] Optionally, the current value of the current source is within the range of the read current of the memory and is less than the write current of the memory.

[0014] Optionally, the memory is formed above or below the first switch, the current source, and / or the third switch, and the memory includes a magnetic tunnel junction.

[0015] According to a second aspect of the present invention, a display panel is provided, comprising the pixel circuit described above.

[0016] The pixel circuit and display panel provided by this invention, through an innovative combination of circuit design and semiconductor devices and processes, apply a memory with magnetoresistive effect to the pixel circuit, eliminating the capacitor in the traditional pixel circuit, greatly reducing the area occupied by the pixel circuit, effectively improving the pixel density of the display panel, and realizing a compact, reliable and low-cost high pixel density (Pixel Per Inch, PPI) display panel.

[0017] In some alternative embodiments, the pixel circuit contains only three switching transistors. If the issue of resetting the light-emitting element is ignored, the pixel circuit contains only two switching transistors. The pixel circuit has low requirements for the number of switching transistors, which can further reduce the area of ​​the pixel circuit and increase the pixel density of the display panel.

[0018] In some alternative embodiments, a selector is used for data writing, so the number of switching transistors in the pixel circuit is only two. If the problem of resetting the light-emitting element is ignored, the number of switching transistors in the pixel circuit is only one. The requirement for the number of switching transistors in the pixel circuit is further reduced, which can further reduce the area of ​​the pixel circuit and increase the pixel density of the display panel.

[0019] In some alternative embodiments, the memory and selectors can be placed above the individual switches as a back-end-of-line (BEOL) process, without occupying the planar area of ​​the pixel circuit. This allows the pixel circuit to achieve high PPI and high reliability. Practical experience has shown that the pixel circuit size can be supported down to 20nm and below. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A block diagram of a pixel circuit according to an embodiment of the present invention is shown;

[0022] Figure 2 A structural diagram of a memory according to an embodiment of the present invention is shown;

[0023] Figure 3 A circuit diagram of a pixel circuit according to a first embodiment of the present invention is shown;

[0024] Figure 4 A circuit diagram of a pixel circuit according to a second embodiment of the present invention is shown;

[0025] Figure 5 A circuit diagram of a pixel circuit according to a third embodiment of the present invention is shown. Detailed Implementation

[0026] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0027] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0028] It should be understood that the connection / coupling of A and B in the embodiments of this application means that A and B can be connected in series or in parallel, or A and B can be connected through other devices. The embodiments of this application do not limit this.

[0029] In a traditional pixel circuit, Dynamic Random Access Memory (DRAM) is used to store data. Each data bit is stored in a separate capacitor, and the capacitor and the connected transistor together form a memory cell. The capacitor stores charge, while the transistor acts as a switch, controlling the reading and storage of charge. In this approach, capacitors are used to directly store the data signal DATA. However, these capacitors are typically large, which is detrimental to reducing the pixel circuit's footprint. Furthermore, the data stored by capacitors is significantly affected by the capacitance value and the leakage current of the switching transistor, resulting in low reliability. In another traditional pixel circuit, Static Random Access Memory (SRAM) is used to store data, employing bistable bipolar flip-flops to store each data bit. The main drawback of SRAM is that it requires six transistors to store each data bit, resulting in a lower storage density than DRAM, further hindering the reduction of the pixel circuit's footprint.

[0030] In this embodiment of the invention, the state of a memory with magnetoresistive effect is changed by a data signal, and the light-emitting element is driven accordingly based on the state of the memory. The memory has a very small feature size, and can achieve a good trade-off in terms of speed, area, number of writes and power consumption. It can also eliminate the capacitor components required by traditional technology, realize display driving with a small number of switching transistors, greatly reduce the area occupied by pixel circuits, and effectively improve the pixel density (Pixel Per Inch, PPI) of the display panel.

[0031] In the following embodiments, the pixel circuit is described in detail using an organic light-emitting diode (OLED) as the light-emitting element. It should be understood that in practice, those skilled in the art can replace the organic light-emitting diode in the pixel circuit with other types of light-emitting elements, such as light-emitting diodes (LEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro-LEDs), mini light-emitting diodes (Mini-LEDs), organic laser diodes (OLDs), etc.

[0032] The embodiments of the pixel circuit and display panel provided in this application will now be described with reference to the accompanying drawings.

[0033] Figure 1 A block diagram of a pixel circuit according to an embodiment of the present invention is shown.

[0034] like Figure 1 As shown, the pixel circuit 100 includes a scan control module 110, a data storage module 120, and a light-emitting module 130. The pixel circuit 100 drives the light-emitting element OLED in the light-emitting module 130 to emit light based on at least the data signal DATA, the scan signal SCAN, and the reference signal Vref.

[0035] The scan control module 110 is used to write the data signal DATA, and is controlled by the scan signal SCAN. For example, when the scan signal SCAN is valid, i.e. during the scanning phase, the scan control module 110 conducts the current path from the data signal DATA to the data storage module 120, so that the data signal DATA is written to the data storage module 120; when the scan signal SCAN is invalid, i.e. during the light emission phase, the scan control module 110 closes the current path from the data signal DATA to the data storage module 120.

[0036] The data storage module 120 is used to store the data signal DATA. In this embodiment of the invention, the data storage module 120 includes a memory with magnetoresistive effect, such as a magnetic random access memory (MRAM), a novel non-volatile random access memory that utilizes the principle of reading magnetoresistive magnitude. The first terminal of the MRAM is connected to a power supply AVDD, and the second terminal is connected to the scan control module 110 and the light-emitting module 130, respectively. During the scanning phase, the data signal DATA is written to the data storage module 120 via the scan control module 110; during the light-emitting phase, the power supply AVDD flows through the data storage module 120 to drive the light-emitting module 130 to emit light. In some embodiments, the power supply AVDD has the same voltage value during the scanning and light-emitting phases. In other embodiments, the power supply AVDD is an adjustable voltage power supply with different voltage values ​​during the scanning and light-emitting phases.

[0037] In this embodiment of the invention, the impedance of the memory in the data storage module 120 is adjusted using the data signal DATA to achieve the purpose of writing the data signal DATA into the data storage module 120. Therefore, the method of writing data in this invention is to store the data signal by defining the correspondence between the impedance of the memory and the data signal, and by adjusting the impedance of the memory using the data signal. This is completely different from the traditional technology of directly storing data signals using capacitors. For example, if a low-level data signal DATA is defined as active and a high-level data signal DATA is defined as inactive, then the voltage of the power supply AVDD is less than the high level of the data signal DATA and greater than the low level of the data signal DATA. Therefore, when the data signal DATA is active, the memory MRAM is in a first resistive state (e.g., a low-resistance state); when the data signal DATA is inactive, the memory MRAM is in a second resistive state (e.g., a high-resistance state). It should be understood that the embodiments of the present invention are not limited thereto. Those skilled in the art can modify the definitions of the valid and invalid states of data and the correspondence between the resistance state of the memory MRAM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly so that when the data signal DATA is valid, the memory MRAM is in the resistance state corresponding to the data "1", and when the data signal DATA is invalid, the memory MRAM is in the resistance state corresponding to the data "0".

[0038] The light-emitting module 130 includes a current source and a light-emitting element. Power supply AVDD flows sequentially through the data storage module 120 and the light-emitting element. The current source controls the current in the pixel circuit, ensuring it is turned off during the scanning phase and maintains the current in the pixel circuit during the light-emitting phase to prevent changes in the memory state. During the light-emitting phase, the current source maintains the current in the pixel circuit within the range of the memory's read current, which is much smaller than the memory's write current. The current source is controlled by a reference signal Vref, an analog signal used to adjust the current magnitude. In some embodiments, the reference signal Vref is a signal with a constant voltage value, and all pixel circuits 100 in the display panel can share a single reference signal Vref. In other embodiments, to prevent a small current source from mis-enabling the light source during the scanning phase, the voltage value of the reference signal Vref can be adjusted during the scanning phase, causing the current source to be directly turned off. For example, during the scanning phase, the reference signal Vref is invalid, cutting off the current path from the data storage module 120 to the light-emitting module 130. During the light-emitting phase, the reference signal Vref is valid, turning on the current path from the data storage module 120 to the light-emitting module 130 and maintaining the current in the current path within the memory's read current range to prevent the memory's state from flipping. During the light-emitting phase, the power supply AVDD has a voltage loss corresponding to the data signal DATA after flowing through the data storage module 120. Therefore, when driving the light-emitting module 130 to emit light, there is a corresponding voltage loss, allowing the light-emitting element OLED to emit light corresponding to the data signal DATA. For example, when the data signal DATA is valid, the memory MRAM is in a low-resistance state, and the voltage loss after the power supply AVDD flows through the memory MRAM is small, driving the light-emitting element OLED to emit light. When the data signal DATA is invalid, the memory MRAM is in a high-resistance state, and the current from the power supply AVDD cannot flow through the memory MRAM, so the light-emitting element OLED stops emitting light.

[0039] In this embodiment of the invention, during the scanning phase, the scan signal SCAN is valid, and the data signal DATA is written into the data storage module 120 via the scan control module 110. The data signal DATA is stored by adjusting the impedance of the memory MRAM. During the light emission phase, the scan signal SCAN is invalid, and the power supply AVDD, after flowing through the data storage module 120, has a voltage loss corresponding to the data signal DATA. Therefore, when driving the light emission module 130 to emit light, there is a corresponding voltage loss, which enables the light-emitting element OLED to emit light corresponding to the data signal DATA. Therefore, the pixel circuit 100 does not directly use the memory MRAM to store the data signal DATA, but instead uses the data signal DATA to change the state of the memory during the scanning phase, and drives the light-emitting element OLED accordingly based on the state of the memory MRAM during the light emission phase. The pixel circuit 100 uses the memory MRAM with magnetoresistive effect to store the data signal DATA, which can eliminate the switching and capacitor components required by traditional technology, greatly reducing the area occupied by the pixel circuit 100 and effectively improving the pixel density of the display panel.

[0040] Figure 2 A structural diagram of a memory according to an embodiment of the present invention is shown.

[0041] like Figure 2 As shown, the memory MRAM is a magnetic random access memory, which includes a magnetic tunnel junction (MTJ).

[0042] Magnetic random access memory (MRAM) is a novel type of non-volatile random access memory that utilizes the magnitude of read magnetoresistance. Compared to other storage technologies, MRAM achieves a good trade-off in terms of speed, area, write cycles, and power consumption, and is therefore considered by the industry as one of the potential access devices for building next-generation non-volatile caches and main memory.

[0043] The improved performance of magnetic random access memory (MRMH) is attributed to the continuously increasing tunneling magnetoresistance (TMR) of the magnetic tunnel junction 10. The MMH is the basic storage unit, comprising two ferromagnetic layers 11 and 13 and a tunneling barrier layer 12 located between them. Ferromagnetic layers 11 and 13 are conductive layers with a thickness of, for example, 1–2.5 nm, while the tunneling barrier layer 12 is an insulating layer with a thickness of, for example, 1–1.5 nm. The two ferromagnetic layers 11 and 13 and the tunneling barrier layer 12 constitute a sandwich-like nanolayered film. One of the ferromagnetic layers 13 is called the reference layer or pinned layer, and its magnetization remains fixed along the easy magnetization axis. The other ferromagnetic layer 11 is called the free layer, and its magnetization has two stable orientations, parallel or antiparallel to the reference layer, which allows the MMH to be in a low-resistance or high-resistance state; this phenomenon is called the tunneling magnetoresistance effect. The two resistance states of magnetic tunnel junction 10 can represent binary data "0" and "1" respectively, which is the fundamental principle of data storage in magnetic random access memory (MRMH). The tunneling magnetoresistance effect can be explained by spin-dependent tunneling theory. For ferromagnetic metals, the distribution of spin-up and spin-down electronic states is uneven near the Fermi level. When the reference layer and the free layer are magnetized in the same direction, the majority electrons in the two ferromagnetic layers have the same spin direction, resulting in a higher tunneling probability, a larger tunneling current, and a low-resistance state for magnetic tunnel junction 10. Conversely, when the reference layer and the free layer are magnetized in opposite directions, magnetic tunnel junction 10 exhibits a high-resistance state. Wires are connected to the two ferromagnetic layers 11 and 13 to facilitate data writing and reading.

[0044] When writing data to a magnetic random access memory (MRMemory), as current flows from the reference layer to the free layer, it first acquires spin angular momentum in the same direction as the magnetization of the reference layer. This spin-polarized current interacts with the magnetization of the free layer, causing a transfer of the transverse component of the spin-polarized current. Due to the conservation of angular momentum, this transferred transverse component acts as a torque on the free layer, forcing its magnetization direction to approach that of the reference layer. This torque is called the spin-transfer torque. Similarly, for a current in the opposite direction, the reflection of the spin by the reference layer causes the free layer to acquire an opposite torque. Therefore, the magnetization state being written is determined by the direction of the current.

[0045] When reading data from the magnetic random access memory (MRMemory), it is sufficient to detect the potential difference caused by the magnetic tunnel junction 10 after passing a small current. In this embodiment of the invention, the read current of the memory is set to a small current, which can be less than or even much less than the write current of the memory. Due to the tunneling effect, if the magnetic tunnel junction 10 is in a low-resistance state, the potential difference is small; if the tunneling effect does not exist, it proves that the magnetic tunnel junction 10 is in a high-resistance state, and the potential difference is large. By judging the magnitude of the potential difference, the state of the data stored in the magnetic tunnel junction 10 can be determined, and the data can be transmitted to the system. Furthermore, this method of reading data is completely non-destructive and does not affect the stability of the data.

[0046] Magnetic random access memory (MRRAM) distinguishes between "0" and "1" data by the direction of the write current. Those skilled in the art can set the memory direction according to actual needs. For example, in the first and third embodiments of this invention, it is defined that when the current in the MRAM flows from the first terminal to the second terminal (i.e., from top to bottom), the magnetic tunnel junction 10 is in a low-resistance state, and the written data is "1"; conversely, when the current in the MRAM flows from the second terminal to the first terminal (i.e., from bottom to top), the magnetic tunnel junction 10 is in a high-resistance state, and the written data is "0". As another example, in the second embodiment of this invention, it is defined that when the current in the MRAM flows from the second terminal to the first terminal (i.e., from bottom to top), the magnetic tunnel junction 10 is in a low-resistance state, and the written data is "1"; conversely, when the current in the MRAM flows from the first terminal to the second terminal (i.e., from top to bottom), the magnetic tunnel junction 10 is in a high-resistance state, and the written data is "0". It should be understood that the embodiments of the present invention are not limited thereto. Those skilled in the art can change the correspondence between the resistance state of the magnetic tunnel junction 10 and the written data according to actual needs, and adjust the conduction state of the pixel circuit and / or the type of the switching transistor accordingly during the scanning phase.

[0047] Figure 3 A circuit diagram of a pixel circuit according to a first embodiment of the present invention is shown.

[0048] like Figure 3 As shown, in the pixel circuit 200, the scanning control module 210 includes a first switching transistor SW1, the data storage module 220 includes a memory MRAM, and the light-emitting module 230 includes a current source SW2, a third switching transistor SW3, and a light-emitting element OLED.

[0049] Specifically, the first current terminal of the first switch SW1 receives the data signal DATA, and the second current terminal is connected to the second terminal of the memory MRAM. The control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the second terminal of the memory MRAM, and the second current terminal is connected to the first terminal (anode) of the light-emitting element OLED. The control terminal receives the reference signal Vref. The first current terminal of the third switch SW3 is connected to the first terminal of the light-emitting element OLED, and the second current terminal is connected to the reference ground. The control terminal receives the reset signal RESETB. The second terminal (cathode) of the light-emitting element OLED receives the common voltage Vcom. The first terminal of the memory MRAM is connected to the power supply VP, and the second terminal of the memory MRAM is connected to the second current terminal of the first switch SW1 and the first current terminal of the current source SW2, respectively. When the scan signal SCAN is valid or invalid, the data signal DATA is written to the memory MRAM. When the scan signal SCAN is invalid, the power supply VP drives the light-emitting element OLED through the memory MRAM. In some embodiments, the reference signal Vref is valid during both the scanning and light-emitting phases to limit the current value of the current source SW2 to the range of the memory's read current, which is much smaller than the memory's write current. In other embodiments, the reference signal Vref is in an invalid state during the scanning phase, turning off the current source SW2, and the reference signal Vref is in an valid state during the light-emitting phase, so as to limit the current value of the current source SW2 to the range of the memory read current.

[0050] In this embodiment, a low-level data signal DATA is defined as being in an active state, and a high-level data signal DATA is defined as being in an inactive state. The voltage value of the power supply VP is higher than the low level of the data signal DATA but lower than the high level of the data signal DATA. Therefore, when the data signal DATA is active, current flows from the first terminal of the memory MRAM to the second terminal, and the memory MRAM is in a low-resistance state, writing the data "1". When the data signal DATA is inactive, current flows from the second terminal of the memory MRAM to the first terminal, and the memory MRAM is in a high-resistance state, writing the data "0". It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art can modify the definitions of the active and inactive states of data and the correspondence between the resistance state of the memory MRAM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is active, the memory MRAM is in the resistance state corresponding to the data "1", and when the data signal DATA is inactive, the memory MRAM is in the resistance state corresponding to the data "0".

[0051] In the scanning stage, the scanning signal SCAN is valid and the reset signal RESETB is valid. Therefore, the first switching transistor SW1 and the third switching transistor SW3 are turned on. The current source SW2 is turned off in the scanning stage. The reference signal Vref can be in an invalid state or a valid state. When the reference signal Vref is in an invalid state, the current source SW2 is turned off. When the reference signal Vref is in a valid state, the current of the current source SW2 is much smaller than the read current of the memory because it can be considered that the current source SW2 is in an off state. At this time, the first end of the memory MRAM is connected to the power supply VP, the voltage value of the power supply VP is V0, the second end of the memory MRAM receives the data signal DATA, and there is a voltage difference between the first end and the second end of the memory MRAM, so that the memory MRAM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid, that is, the voltage on the data line is the low level VdataL, and V0 > VdataL, the current flows from top to bottom, and the magnetic tunnel junction in the memory MRAM is in a low-resistance state, representing the written data "1"; if the data signal DATA is invalid, that is, the voltage on the data line is the high level VdataH, and V0 < VdataH, the current flows from bottom to top, and the magnetic tunnel junction in the memory MRAM is in a high-resistance state, representing the written data "0". The impedance of the memory MRAM determines whether the light-emitting element OLED can emit light in the light-emitting stage. That is, the data signal DATA is written into the memory MRAM by adjusting the impedance of the memory MRAM. The memory MRAM is disconnected from the light-emitting element OLED. The first end of the light-emitting element OLED is connected to the reference ground to reset the residual charge on the light-emitting element OLED.

[0052] In the light-emitting stage, the scanning signal SCAN is invalid and the reset signal RESETB is invalid. Therefore, the first switching transistor SW1 and the third switching transistor SW3 are turned off, and the current source SW2 is turned on. At this time, the memory MRAM has an impedance corresponding to the data signal DATA, and the power supply VP is connected to the light-emitting element OLED through the memory MRAM. Therefore, after the power supply VP flows through the memory MRAM, there is a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the memory MRAM is in a low-resistance state, and the voltage loss after the power supply VP flows through the memory MRAM is very small or almost zero, and the light-emitting element OLED can be smoothly driven to emit light; if the data signal DATA is invalid, the memory MRAM is in a high-resistance state, and the voltage loss after the power supply VP flows through the memory MRAM is very large, and the light-emitting element OLED cannot be driven to emit light.

[0053] Furthermore, if the light-emitting element OLED in the pixel circuit 200 does not have high requirements for anode reset, the issue of OLED reset can be ignored, and the third switch SW3 can be omitted. In this case, the number of switches in the pixel circuit 200 can be only two (the first switch SW1 and the current source SW2), and the pixel circuit 200 has low requirements for the number of switches.

[0054] In this embodiment, the first switch SW1, the current source SW2, and the third switch SW3 can be transistors of the following types: bipolar junction transistor (BJT), field-effect transistor (FET), insulated gate bipolar transistor (IGBT), etc.

[0055] As an example, the first switch SW1, current source SW2, and third switch SW3 are all P-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to the voltage threshold, i.e., when its control terminal receives a low-level control signal, the current path from its first current terminal to its second current terminal is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, i.e., when its control terminal receives a high-level control signal, the current path from its first current terminal to its second current terminal is turned off. Therefore, a low-level scan signal SCAN, reference signal Vref, and reset signal RESETB are defined as being in an active state, and a high-level scan signal SCAN, reference signal Vref, and reset signal RESETB are defined as being in an inactive state. It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art can modify the types of the first switch SW1, current source SW2, and third switch SW3, and the specific levels of the active and inactive states of the scan signal SCAN, reference signal Vref, and reset signal RESETB according to actual needs.

[0056] In this embodiment, during the light-emitting stage, due to the presence of the current source SW2, the current flowing through the memory is limited to the range of the memory's read current, which is much smaller than the memory's write current, so it will not cause the memory's state to flip.

[0057] Figure 4 A circuit diagram of a pixel circuit according to a second embodiment of the present invention is shown.

[0058] like Figure 4 As shown, in the pixel circuit 300, the scanning control module 310 includes a selector, the data storage module 320 includes a memory MRAM, and the light-emitting module 330 includes a current source SW2, a third switch SW3, and a light-emitting element OLED.

[0059] Specifically, the selector receives the data signal DATA at its first terminal and is connected to the second terminal of the memory MRAM at its second terminal. The current source SW2 has its first current terminal connected to the second terminal of the memory MRAM and its second current terminal connected to the first terminal (anode) of the light-emitting element OLED. The control terminal receives the reference signal Vref. The third switch SW3 has its first current terminal connected to the first terminal of the light-emitting element OLED and its second current terminal connected to ground. The control terminal receives the reset signal RESETB. The second terminal (cathode) of the light-emitting element OLED receives the common voltage Vcom. The first terminal of the memory MRAM is connected to the scan signal SCAN, and its second terminal is connected to both the second terminal of the selector and the first current terminal of the current source SW2. When the scan signal SCAN is active, the data signal DATA is written to the memory MRAM. When the scan signal SCAN is inactive, the high-level scan signal SCAN drives the light-emitting element OLED through the memory MRAM. In some embodiments, the reference signal Vref is active during both the scanning and light-emitting phases to limit the current value of the current source SW2 to the range of the memory's read current, which is much smaller than the memory's write current. In other embodiments, the reference signal Vref is in an invalid state during the scanning phase, turning off the current source SW2, and the reference signal Vref is in an valid state during the light-emitting phase, so as to limit the current value of the current source SW2 to the range of the memory read current.

[0060] In this embodiment, the scan signal SCAN is in an active state when it is low and in an inactive state when it is high. During the light emission stage, the high level of the scan signal SCAN is multiplexed as the power supply VP.

[0061] In this embodiment, the selector has a preset threshold voltage. When the absolute value of the voltage difference between the first and second terminals of the selector is greater than or equal to the threshold voltage, the selector is turned on; when the absolute value of the voltage difference between the first and second terminals of the selector is less than the threshold voltage, the selector is turned off. As an example, the selector includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the cathode of the second diode D2 and receives the data signal DATA. The anode of the second diode D2 is connected to the cathode of the first diode D1 and is connected to the second terminal of the MRAM.

[0062] Specifically, in this selector, when a forward bias voltage greater than the threshold voltage Vd is applied, the impedance is very small, and the selector conducts. When the bias voltage decreases to below the threshold voltage Vd but greater than the negative threshold voltage -Vd, the impedance becomes very large, and the selector turns off. When the bias voltage continues to decrease to below the negative threshold voltage -Vd, the selector turns on again, and the impedance is very small. In some embodiments, the selector can be any combination of conventional diodes such as PN diodes, Schottky diodes, or bipolar junction transistors (BJTs), or it can be an ovonic threshold switch (OTS), which is similar to a phase change memory (PCM), but the difference is that its molecules do not crystallize. An ovonic threshold switch can be implemented by adding other elements (such as arsenic) to the phase change material to prevent crystallization. Each time the voltage is removed and the temperature drops, it returns to an amorphous state and never enters a crystalline state. Therefore, it cannot be used as a memory but can be used as a switch.

[0063] In this embodiment, a high-level data signal DATA is defined as valid, and a low-level data signal DATA is defined as invalid. The low level of the scan signal SCAN is lower than the high level of the data signal DATA, and the initial state of the memory MRAM is a high-impedance state. When the current in the memory MRAM flows from the second terminal to the first terminal, the memory MRAM is in a low-impedance state, and data "1" is written. Conversely, when the current in the memory MRAM flows from the first terminal to the second terminal, the memory MRAM is in a high-impedance state, and data "0" is written. Therefore, when the data signal DATA is valid, the current flows from the second terminal to the first terminal of the memory MRAM, the memory MRAM is in a low-impedance state, and data "1" is written; when the data signal DATA is invalid, the selector is in the off state, the memory MRAM maintains a high-impedance state, and data "0" is written. It should be understood that the embodiments of the present invention are not limited thereto. Those skilled in the art can modify the definitions of the valid and invalid states of data and the correspondence between the resistance state of the memory MRAM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly so that when the data signal DATA is valid, the memory MRAM is in the resistance state corresponding to the data "1", and when the data signal DATA is invalid, the memory MRAM is in the resistance state corresponding to the data "0".

[0064] During the initialization phase, the scan signal SCAN is disabled, and the current source SW2 and the third switch SW3 are turned on. For example, if both the current source SW2 and the third switch SW3 are PMOS transistors, then the reference signal Vref and the reset signal RESETB are both set to low level. Therefore, the first terminal of the memory MRAM is connected to the high-level scan signal SCAN, and the second terminal is connected to the reference ground via the current source SW2 and the third switch SW3. The memory MRAM is initialized to write data "0".

[0065] During the scan phase, the scan signal SCAN is active, the reference signal Vref is inactive, and the reset signal RESETB is active, therefore the third switch SW3 is turned on. Current source SW2 is turned off during the scan phase. The reference signal Vref can be either inactive or active. When Vref is inactive, current source SW2 is off; when Vref is active, the current from current source SW2 is much smaller than the memory read current, so SW2 can be considered off. At this time, the first terminal of the memory MRAM is connected to the low-level scan signal SCAN, with a voltage value of Vp. The second terminal of the memory MRAM receives the data signal DATA. There is a voltage difference between the first and second terminals of the memory MRAM, giving the memory MRAM an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid (i.e., the voltage on the data line is high, VdataH), current flows from bottom to top, and the magnetic tunnel junction in the MRAM is in a low-resistance state, representing the writing of data "1"; if the data signal DATA is invalid (i.e., the voltage on the data line is low, VdataL), the selector is in the off state, and the magnetic tunnel junction in the MRAM maintains its initial state (high-resistance state), representing the writing of data "0". The impedance of the MRAM determines whether the OLED can emit light during the light-emitting phase. That is, the data signal DATA is written into the MRAM by adjusting its impedance. The MRAM is then disconnected from the OLED. The first terminal of the OLED is connected to a reference ground to reset any residual charge on the OLED.

[0066] During the light-emitting phase, the scan signal SCAN is invalid, the reference signal Vref is valid, and the reset signal RESETB is invalid. Therefore, the third switch SW3 is turned off, and the current source SW2 is turned on. At this time, the memory MRAM has an impedance corresponding to the data signal DATA. The high-level scan signal SCAN is connected to the light-emitting element OLED through the memory MRAM. Therefore, the high-level scan signal SCAN, after flowing through the memory MRAM, has a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the memory MRAM is in a low-impedance state, and the voltage loss of the high-level scan signal SCAN after flowing through the memory MRAM is little or almost zero, which can smoothly drive the light-emitting element OLED to emit light; if the data signal DATA is invalid, the memory MRAM is in a high-impedance state, and the voltage loss of the high-level scan signal SCAN after flowing through the memory MRAM is large, which cannot drive the light-emitting element OLED to emit light.

[0067] Furthermore, if the light-emitting element OLED in the pixel circuit 300 does not have high requirements for anode reset, the issue of OLED reset can be ignored, and the third switch SW3 can be omitted. In this case, the number of switches in the pixel circuit 300 can be only one (current source SW2), and the pixel circuit 300 has low requirements for the number of switches.

[0068] In this embodiment, the current source SW2 and the third switch SW3 can be transistors of the following types: bipolar junction transistor (BJT), field-effect transistor (FET), insulated gate bipolar transistor (IGBT), etc.

[0069] As an example, both current source SW2 and the third switch SW3 are P-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to the voltage threshold, i.e., when its control terminal receives a low-level control signal, the current path from its first current terminal to its second current terminal is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, i.e., when its control terminal receives a high-level control signal, the current path from its first current terminal to its second current terminal is turned off. Therefore, a low-level scan signal SCAN and a high-level reset signal RESETB are defined as being in an active state, and a high-level scan signal SCAN and a high-level reset signal RESETB are defined as being in an inactive state. It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art can modify the types of the first switch SW1, current source SW2, and third switch SW3, as well as the specific levels of the active and inactive states of the scan signal SCAN and the reset signal RESETB, according to actual needs.

[0070] In this embodiment, when the memory MRAM drives the light-emitting element OLED, the low level of the data signal DATA is higher than the difference between the voltage value at the second terminal of the memory MRAM and the threshold voltage, and the high level of the data signal DATA is lower than the difference between the voltage value at the second terminal of the memory MRAM. Therefore, the selector will not be turned on, and no additional current will flow through the selector's leakage current. During the light-emitting phase, the current source SW2 limits the current flowing through the memory MRAM to within the range of the memory's read current. The memory's read current is less than / far less than the memory MRAM's write current, thus preventing the memory MRAM from flipping state. The data signal "0" or "1" can be held in the memory MRAM for a long time, which is crucial for the stability of the driving current during display.

[0071] Figure 5 A circuit diagram of a pixel circuit according to a third embodiment of the present invention is shown.

[0072] like Figure 5 As shown, in the pixel circuit 400, the scanning control module includes a first switch SW1, the data storage module includes a memory MRAM, and the light-emitting module includes a current source SW2, a third switch SW3, a fourth switch SW4, and a light-emitting element OLED.

[0073] Specifically, the first current terminal of the first switch SW1 receives the data signal DATA, and the second current terminal is connected to the second terminal of the memory MRAM. The control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the power supply AVDD, and the second current terminal is connected to the first terminal of the memory MRAM. The control terminal receives the reference signal Vref. The first current terminal of the third switch SW3 is connected to the first terminal of the light-emitting element OLED, and the second current terminal is connected to the reference ground. The control terminal receives the reset signal RESETB. The first current terminal of the fourth switch SW4 is connected to the second terminal of the memory MRAM, and the second current terminal is connected to the first terminal (anode) of the light-emitting element OLED. The control terminal receives the control signal EMB. The second terminal (cathode) of the light-emitting element OLED receives the common voltage Vcom. In this embodiment, the first terminal of the memory MRAM is connected to the power supply AVDD via the current source SW2, and the second terminal of the memory MRAM is connected to the second current terminal of the first switch SW1 and the first current terminal of the fourth switch SW4, respectively. When the scan signal SCAN is valid or invalid, the data signal DATA is written to the memory MRAM; when the scan signal SCAN is invalid, the power supply AVDD drives the light-emitting element OLED through the memory MRAM. In this embodiment, both the current source SW2 and the fourth switch SW4 are P-type transistors. During the scanning phase, the reference signal Vref is low, turning on the current source SW2 as a switching switch; the control signal EMB is high, turning off the fourth switch SW4 to prevent the OLED from being turned on. During the light-emitting phase, the reference signal Vref is a predetermined analog signal that adjusts the current of the current source SW2 to limit the voltage across the memory to less than the memory's write voltage; the control signal EMB is low, turning on the fourth switch SW4 to drive the OLED to emit light.

[0074] In this embodiment, a low-level data signal DATA is defined as valid, and a high-level data signal DATA is defined as invalid. The voltage of the power supply AVDD is higher than the low level of the data signal DATA but lower than the high level of the data signal DATA. Therefore, when the data signal DATA is valid, the voltage at the first terminal of the memory MRAM (i.e., the voltage of the power supply AVDD) is higher than the voltage at the second terminal of the memory MRAM (i.e., the low level of the data signal DATA), and the memory MRAM is in a low-impedance state, writing data "1". When the data signal DATA is invalid, the voltage at the first terminal of the memory MRAM (i.e., the voltage of the power supply AVDD) is lower than the voltage at the second terminal of the memory MRAM (i.e., the high level of the data signal DATA), and the memory MRAM is in a high-impedance state, writing data "0". It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art can adjust the orientation of the memory according to actual needs, and accordingly adjust the conduction state of the pixel circuit during the scanning stage, the correspondence between high and low levels at each stage, and / or the type of the switching transistor, so that when the data signal DATA is valid, the memory MRAM is in an impedance state corresponding to data "1", and when the data signal DATA is invalid, the memory MRAM is in an impedance state corresponding to data "0".

[0075] In the scanning stage, the scan signal SCAN is valid, the reset signal RESETB is valid, the reference signal Vref is valid, and the control signal EMB is invalid. Therefore, the first switch SW1, the current source SW2, and the third switch SW3 are turned on, and the fourth switch SW4 is turned off. At this time, the first end of the memory MRAM is connected to the power supply AVDD, the voltage value of the power supply AVDD is V0, the second end of the memory MRAM receives the data signal DATA, and there is a voltage difference between the first end and the second end of the memory MRAM, so that the memory MRAM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid, that is, the voltage on the data line is the low level VdataL, and V0 > VdataL, the voltage at the first end of the memory MRAM (i.e., the voltage value of the power supply AVDD) is higher than the voltage at the second end of the memory MRAM (i.e., the low level of the data signal DATA), and the memory MRAM is in a low-resistance state, representing writing the data "1"; if the data signal DATA is invalid, that is, the voltage on the data line is the high level VdataH, and V0 < VdataH, the voltage at the first end of the memory MRAM (i.e., the voltage value of the power supply AVDD) is lower than the voltage at the second end of the memory MRAM (i.e., the high level of the data signal DATA), and the memory MRAM is in a high-resistance state, representing writing the data "0". The impedance of the memory MRAM determines whether the light-emitting element OLED can emit light in the light-emitting stage. That is, the data signal DATA is written into the memory MRAM by adjusting the impedance of the memory MRAM. In the scanning stage, the memory MRAM is disconnected from the light-emitting element OLED, and the first end of the light-emitting element OLED is connected to the reference ground to reset the residual charge on the light-emitting element OLED.

[0076] In the light-emitting stage, the scan signal SCAN is invalid, the reset signal RESETB is invalid, the reference signal Vref is an analog signal for adjusting the current, and the control signal EMB is valid. Therefore, the first switch SW1 and the third switch SW3 are turned off, the current source SW2 controls the current in the circuit, and the fourth switch SW4 is turned on. At this time, the memory MRAM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light-emitting element OLED through the memory MRAM. Therefore, after the power supply AVDD flows through the memory MRAM, there is a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the memory MRAM is in a low-resistance state, and the voltage loss after the power supply AVDD flows through the memory MRAM is very small or almost zero, and the light-emitting element OLED can be successfully driven to emit light; if the data signal DATA is invalid, the memory MRAM is in a high-resistance state, and the voltage loss after the power supply AVDD flows through the memory MRAM is very large, and the light-emitting element OLED cannot be driven to emit light.

[0077] Furthermore, if the light-emitting element OLED in the pixel circuit 400 does not have high requirements for anode reset, the issue of OLED reset can be ignored, and the third switch SW3 can be omitted. In this case, the number of switches in the pixel circuit 400 can be only three (first switch SW1, current source SW2 and fourth switch SW4), and the pixel circuit 400 has low requirements for the number of switches.

[0078] In this embodiment, the first switch SW1, the current source SW2, the third switch SW3, and the fourth switch SW4 can be transistors of the following types: bipolar junction transistor (BJT), field-effect transistor (FET), insulated gate bipolar transistor (IGBT), etc.

[0079] As an example, the first switch SW1, current source SW2, third switch SW3, and fourth switch SW4 are all P-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to the voltage threshold, i.e., when its control terminal receives a low-level control signal, the current path from its first current terminal to its second current terminal is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, i.e., when its control terminal receives a high-level control signal, the current path from its first current terminal to its second current terminal is turned off. Therefore, a low-level scan signal SCAN, reference signal Vref, reset signal RESETB, and control signal EMB are defined as being in an active state, while a high-level scan signal SCAN, reference signal Vref, reset signal RESETB, and control signal EMB are defined as being in an inactive state. It should be understood that the embodiments of the present invention are not limited thereto. Those skilled in the art can modify the types of the first switch SW1, the current source SW2, the third switch SW3 and the fourth switch SW4, as well as the specific levels of the active and inactive states of the scan signal SCAN, the reference signal Vref, the reset signal RESETB and the control signal EMB, according to actual needs.

[0080] In this embodiment, during the light-emitting stage, due to the presence of the current source SW2, the voltage across the control memory MRAM is much lower than the write voltage, so the state of the memory will not be flipped, and the state of the memory can be stably maintained during the light-emitting stage.

[0081] Furthermore, due to certain deficiencies in the existing MRAM process, the on-resistance of the MRAM is discrete. In this embodiment, the positions of the current source SW2 and the MRAM are swapped, and a fourth switch SW4 is introduced. This can avoid the discreteness of the MRAM on-resistance caused by the discreteness of the process or writing conditions, and further avoid the inconsistency of the driving current of the pixel circuit.

[0082] exist Figure 3 and Figure 4 In this configuration, the MRAM memory can be formed above or below the first switch SW1, the current source SW2, and / or the third switch SW3. Figure 5 In this configuration, the MRAM memory can be formed above or below the first switch SW1, the current source SW2, the third switch SW3, and / or the fourth switch SW4, which can further reduce the area occupied by the pixel circuit.

[0083] In addition, the present invention also provides a display panel, including a plurality of such Figures 3 to 5Any type of pixel circuit in the display panel, multiple pixel circuits are arranged in an array, a column of pixel circuits share a data line, a row of pixel circuits share a scan line, and all pixel circuits can share a common voltage. The display panel can be any of the following types: Low-Temperature Polysilicon Organic Light-Emitting Diode (LTPSOLED) display panel, Micro Organic Light-Emitting Diode (Micro-OLED) display panel, Mini Organic Light-Emitting Diode (Mimi-OLED) display panel, Micro Light-Emitting Diode (Micro-LED) display panel, Passive Matrix Organic Light-Emitting Diode (PassiveMatrix OLED) display panel, Active Matrix Organic Light-Emitting Diode (Active Matrix OLED) display panel, Flexible Organic Light-Emitting Diode (Flexible OLED) display panel, Transparent Organic Light-Emitting Diode (Transparent OLED) display panel, etc., and this application does not limit it in this regard.

[0084] In summary, this invention provides a pixel circuit and a display panel. Through innovative combination of circuit design and semiconductor devices and processes, a memory with magnetoresistive effect is applied to the pixel circuit, eliminating the capacitor in the traditional pixel circuit, greatly reducing the area occupied by the pixel circuit, effectively improving the pixel density of the display panel, and realizing a compact, reliable, and low-cost high PPI display panel.

[0085] In some alternative embodiments, the pixel circuit contains only three switching transistors. If the issue of resetting the light-emitting element is ignored, the pixel circuit contains only two switching transistors. The pixel circuit has low requirements for the number of switching transistors.

[0086] In some alternative embodiments, a selector is used for data writing, so the number of switches in the pixel circuit is only two. If the problem of resetting the light-emitting element is ignored, the number of switches in the pixel circuit is only one, further reducing the requirement for the number of switches in the pixel circuit.

[0087] In some alternative embodiments, the memory and selectors can be placed above the individual switches as a back-end-of-line (BEOL) process, without occupying the planar area of ​​the pixel circuit. This allows the pixel circuit to achieve high PPI and high reliability. Practical experience has shown that the pixel circuit size can be supported down to 20nm and below.

[0088] The foregoing has described some examples of pixel circuits and display panels according to embodiments of the present invention. However, the embodiments of the present invention are not limited thereto, and there may be other extensions and modifications.

[0089] For example, it should be understood that the reference ground potential in the foregoing embodiments may be replaced in alternative embodiments with other non-zero reference potentials (with positive or negative voltage amplitudes) or a controlled-change reference signal.

[0090] Furthermore, those skilled in the art will recognize that the structures and methods described in conjunction with the embodiments disclosed herein can be used with different configuration or adjustment methods to achieve the described functions for each structure or reasonable variations thereof, but such implementations should not be considered beyond the scope of this application. Moreover, it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of this application are illustrative examples and do not impose any limitations on the embodiments of this application.

[0091] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0092] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel circuit, comprising: The scan control module is used to write data signals; A data storage module is used to store the data signal; as well as The light-emitting module includes a light-emitting element and a current source, wherein the light-emitting element is driven by the power flowing through the data storage module. The data storage module includes a memory with magnetoresistive effect. The data signal adjusts the impedance of the memory, and the power supply flowing through the data storage module has a voltage loss corresponding to the data signal. The current source is connected between the memory and the light-emitting element, or the current source is connected between the power supply and the memory.

2. The pixel circuit according to claim 1, wherein, When the data signal is valid, the memory is in a low-impedance state, and the power supply drives the light-emitting element to emit light. When the data signal is invalid, the memory is in a high-impedance state, and the power supply drives the light-emitting element to stop emitting light.

3. The pixel circuit according to claim 1, wherein, The voltage of the power supply is lower than the high level of the data signal and higher than the low level of the data signal.

4. The pixel circuit according to claim 1, wherein, The scanning control module includes a first switching transistor, whose first current terminal receives the data signal, and its second current terminal is connected to the second terminal of the memory. A control terminal receives a scanning signal, the control terminal of the current source receives a reference signal, the second terminal of the light-emitting element receives a common voltage, and the first terminal of the memory is connected to the power supply. When the scan signal is valid, the data signal is written to the memory; when the scan signal is invalid, the power supply drives the light-emitting element through the memory. The voltage of the power supply is higher than the low level of the data signal and lower than the high level of the data signal.

5. The pixel circuit according to claim 1, wherein, The scanning control module includes a selector. A first terminal of the selector receives the data signal, and a second terminal is connected to a second terminal of the memory. The first terminal of the memory receives the scan signal. A first current terminal of the current source is connected to the second terminal of the memory, and a second current terminal is connected to the first terminal of the light-emitting element. A control terminal receives a reference signal, and the second terminal of the light-emitting element receives a common voltage. Specifically, the selector is activated when the absolute value of the voltage difference between the first and second terminals of the selector is greater than or equal to the threshold voltage. When the scan signal is valid, the data signal is written to the memory; when the scan signal is invalid, the power supply drives the light-emitting element through the memory. The scanning signal is in an active state when it is low and in an inactive state when it is high. The high level of the scanning signal serves as the power supply.

6. The pixel circuit according to claim 5, wherein, The selector includes a first diode and a second diode. The anode of the first diode is connected to the cathode of the second diode and receives the data signal. The anode of the second diode is connected to the cathode of the first diode and is connected to the second terminal of the memory.

7. The pixel circuit according to claim 5, wherein, The data signal is in an active state when it is high and in an inactive state when it is low. The initial state of the memory is a high-impedance state, and the high level of the data signal is greater than the low level of the scan signal. When the memory drives the light-emitting element, the low level of the data signal is higher than the difference between the voltage value at the second terminal of the memory and the threshold voltage, and the high level of the data signal is lower than the difference between the voltage value at the second terminal of the memory.

8. The pixel circuit according to claim 4 or 5, wherein, The current value of the current source is within the range of the read current of the memory and is less than the write current of the memory.

9. The pixel circuit according to claim 4, wherein, The light-emitting module also includes a third switching transistor, the first current terminal of which is connected to the first terminal of the light-emitting element, the second current terminal of which is connected to the reference ground, and the control terminal receives a reset signal.

10. The pixel circuit according to claim 9, wherein, The memory is formed above or below the first switch, the current source, and / or the third switch, and the memory includes a magnetic tunnel junction.

11. The pixel circuit according to claim 5, wherein, The light-emitting module also includes a third switching transistor, the first current terminal of which is connected to the first terminal of the light-emitting element, the second current terminal of which is connected to the reference ground, and the control terminal receives a reset signal.

12. The pixel circuit according to claim 11, wherein, The memory is formed above or below the current source and / or the third switch, and the memory includes a magnetic tunnel junction.

13. A display panel comprising the pixel circuitry as described in any one of claims 1 to 12.

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