Bidirectional full-bridge-based equalization circuit, battery management system and control method

Abstract

The invention relates to the technical field of battery equalization, in particular to an equalization circuit based on a bidirectional full bridge, a battery management system and a control method. One end of a primary winding of the transformer T is connected with an inductor L1r and an inductor L1p, the other end of the primary winding of the transformer T is connected with a capacitor C1p, a capacitor C1r1 and a capacitor C1r2, the inductor L1p and the capacitor C1p are connected to form an Lp-Cp series network, the capacitor C1r1 and the capacitor C1r2 are connected to form a resonant capacitor, the capacitor C1r1 is connected with a drain electrode of an MOS tube Q11, a drain electrode of an MOS tube Q13 and a positive electrode of a battery cell V1, the capacitor C1r2 is connected with a source electrode of the MOS tube Q13 and a drain electrode of an MOS tube Q14, and the MOS tube Q14 is connected with a negative electrode of the battery cell V1. The inductor L1r is connected with the source electrode of the MOS tube Q11, the drain electrode of the MOS tube Q12, the source electrode of the MOS tube Q12 is connected with the source electrode of the MOS tube Q14 and the negative electrode of the battery cell V1, and one end of a secondary winding of the transformer T is connected with the inductor L2r and the inductor L2p. Compared with the prior art, the battery management system applies the equalization circuit and the control method thereof, so that the energy loss can be reduced, the circuit size can be reduced, the energy transmission efficiency can be improved, and the battery management system can be widely applied to the field of battery management. The anti-interference capability of the circuit is enhanced, and the reusability is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of battery equalization, and specifically relates to an equalization circuit based on a bidirectional full bridge, a battery management system, and a control method. Background Art

[0002] Currently, for the problem of inconsistent lithium battery cell capacities leading to SOC imbalance, there are mainly two solutions: passive equalization and active equalization. Among them, passive equalization mainly uses resistors to dissipate the excess energy of high-SOC cells; while active equalization transfers the energy of high-SOC cells to low-SOC cells. The key research direction of active equalization is to use a DC-DC DC converter for battery charging equalization. Currently, this technology still has disadvantages such as large circuit volume, large energy loss, and weak anti-interference ability. Summary of the Invention

[0003] To solve the problems raised in the above background art, the present invention provides an equalization circuit based on a bidirectional full bridge, including a transformer T. One end of the primary winding of the transformer T is connected to an inductor L1r and an inductor L1p, and the other end of the primary winding of the transformer T is connected to a capacitor C1p, a capacitor C1r1, and a capacitor C1r2. The inductor L1p and the capacitor C1p are connected to form an Lp-Cp series network. The capacitor C1r1 and the capacitor C1r2 are connected to form a resonant capacitor. The capacitor C1r1 is connected to the drain of the MOS transistor Q11, the drain of the MOS transistor Q13, and the positive electrode of the battery cell V1. The capacitor C1r2 is connected to the source of the MOS transistor Q13, the drain of the MOS transistor Q14. The inductor L1r is connected to the source of the MOS transistor Q11, the drain of the MOS transistor Q12. The source of the MOS transistor Q12 is connected to the source of the MOS transistor Q14 and the negative electrode of the battery cell V1. One end of the secondary winding of the transformer T is connected to an inductor L2r and an inductor L2p, and the other end of the secondary winding of the transformer T is connected to a capacitor C2p, a capacitor C2r1, and a capacitor C2r2. The inductor L2p and the capacitor C2p are connected to form an Lp-Cp series network. The capacitor C2r1 and the capacitor C2r2 are connected to form a resonant capacitor. The capacitor C2r1 is connected to the drain of the MOS transistor Q21, the drain of the MOS transistor Q23, and the positive electrode of the battery cell V2. The capacitor C2r2 is connected to the source of the MOS transistor Q23, the drain of the MOS transistor Q24. The inductor L2r is connected to the source of the MOS transistor Q21, the drain of the MOS transistor Q22. The source of the MOS transistor Q22 is connected to the source of the MOS transistor Q24 and the negative electrode of the battery cell V2.

[0004] The equivalent relationship expression of the resonant capacitor Cr is as follows:

[0005] C r = 2C 1r1 = 2C 1r2 = 2C 2r1 = 2C 2r2 ,

[0006] The equivalent excitation inductance Lmeq of the Lp-Cp series network has the following expression:

[0007]

[0008] f z : Resonant frequency.

[0009] A battery management system includes the described equalization circuit, battery pack, AFE chip, MCU chip, and gate drive unit. The battery pack is connected to the AFE chip, the AFE chip is connected to the MCU chip, the MCU chip is connected to the gate drive unit, the gate drive unit is connected to the equalization circuit, and the equalization circuit is connected to the battery pack.

[0010] The model of the AFE chip used is ADBMS1818.

[0011] The model of the MCU chip used is GD32F307VET6.

[0012] The described gate driving unit includes a chip U1. The chip U1 is provided with an enable pin A, an enable pin B, an output pin A, an output pin B, an input pin A, and an input pin B. The enable pin A is connected to the drain of the MOS transistor Q2. The gate of the MOS transistor Q2 is connected to a resistor R3 and a resistor R4. The other end of the resistor R3 and the source of the MOS transistor Q2 are combined and grounded. The enable pin B is connected to the drain of the MOS transistor Q1. The gate of the MOS transistor Q1 is connected to a resistor R1 and a resistor R2. The other end of the resistor R2 and the source of the MOS transistor Q1 are combined and grounded. The input pin A and the input pin B are connected to the output end of the MCU chip. The control signals of the MCU chip are respectively transmitted to the resistor R1 and the resistor R4. The output pin A is connected to a transistor Q3 and a transistor Q4. One end of the transistor Q3 is connected to the supply voltage. One end of the transistor Q4 is grounded. The other ends of the transistor Q3 and the transistor Q4 are combined and connected to a resistor R5. The resistor R5 is connected to a capacitor C1. The capacitor C1 is connected to one end of the primary winding of the transformer TA. The other end of the primary winding of the transformer TA is grounded. One end of a secondary winding of the transformer TA is connected to a capacitor C2, and the other end is connected to a diode D1, a capacitor C3, a resistor R6, and the source of the MOS transistor Q11. The diode D1, the capacitor C3, the resistor R6, and the gate of the MOS transistor Q11 are combined and connected to the capacitor C2. One end of the other secondary winding of the transformer TA is connected to a capacitor C4, and the other end is connected to a diode D2, a capacitor C5, a resistor R7, and the source of the MOS transistor Q14. The diode D2, the capacitor C5, the resistor R7, and the gate of the MOS transistor Q14 are combined and connected to the capacitor C4. The output pin B is connected to a transistor Q5 and a transistor Q6. One end of the transistor Q5 is connected to the supply voltage. One end of the transistor Q6 is grounded. The other ends of the transistor Q5 and the transistor Q6 are combined and connected to a resistor R8. The resistor R8 is connected to a capacitor C6. The capacitor C6 is connected to one end of the primary winding of the transformer TB. The other end of the primary winding of the transformer TB is grounded. One end of a secondary winding of the transformer TB is connected to a capacitor C7, and the other end is connected to a diode D3, a capacitor C8, a resistor R9, and the source of the MOS transistor Q12. The diode D3, the capacitor C8, the resistor R9, and the gate of the MOS transistor Q12 are combined and connected to the capacitor C7. One end of the other secondary winding of the transformer TB is connected to a capacitor C9, and the other end is connected to a diode D4, a capacitor C10, a resistor R10, and the source of the MOS transistor Q13. The diode D4, the capacitor C10, the resistor R10, and the gate of the MOS transistor Q13 are combined and connected to the capacitor C9.

[0013] When the AFE chip detects that the voltage of a single cell in the battery pack reaches the set threshold, the AFE chip sends the information to the MCU chip. The MCU chip outputs control signals CON1 and CON2 to the gate drive unit and controls the gate drive unit to output pulse signals VgA or VgB to the equalization circuit through the control signals. The pulse signals control the four modes of the equalization circuit to alternate; when the control signals CON1 and CON2 are at high level, the gate drive unit has no output; when the control signals CON1 and CON2 are at low level, the gate drive unit outputs pulse signals VgA and VgB.

[0014] The four modes of the equalization circuit are controlled by the pulse signals to alternate, specifically including the following steps:

[0015] Mode 1: In the dead zone stage before the MOS transistors Q11 and Q14 are turned on, the gate drive unit has no output. The resonant current charges the parallel junction capacitors of the MOS transistors Q12 and Q13, discharges the parallel junction capacitors of the MOS transistors Q11 and Q14 until the voltage reaches zero, and then the resonant current flows through the parallel body diodes of the MOS transistors Q11 and Q14.

[0016] Mode 2: The gate drive unit outputs the VgA pulse signal. The VgA pulse signal controls the MOS transistors Q11 and Q14 to achieve zero-voltage switching conduction. The resonant current of the parallel body diodes of the MOS transistors Q11 and Q14 flows into their channels. The high-voltage side cell applies energy to the resonant network in the positive direction. The parallel body diodes of the low-voltage side MOS transistors Q21 and Q24 conduct naturally, and the energy is transferred to the low-voltage side cell through the transformer, realizing charge equalization between cells.

[0017] Mode 3: In the dead zone stage before the MOS transistors Q12 and Q13 are turned on, the gate drive unit has no output. The resonant current charges the parallel junction capacitors of the MOS transistors Q11 and Q14, discharges the parallel junction capacitors of the MOS transistors Q12 and Q13 until the voltage reaches zero, and then the resonant current flows through the parallel body diodes of the MOS transistors Q12 and Q13.

[0018] Mode 4: The gate drive unit outputs the VgB pulse signal. The VgB pulse signal controls the MOS transistors Q12 and Q13 to achieve zero-voltage switching conduction. The resonant current of the parallel body diodes of the MOS transistors Q12 and Q13 flows into their channels. The high-voltage side cell applies energy to the resonant network in the reverse direction. The parallel body diodes of the low-voltage side MOS transistors Q22 and Q23 conduct naturally, and the energy is transferred to the low-voltage side battery through the transformer, realizing charge equalization between cells.

[0019] When in Mode 2 and Mode 4, it resonates at the main resonance frequency fr; when in Mode 1 and Mode 3, it resonates at the secondary resonance frequency fr1, and the expressions are as follows:

[0020]

[0021] Compared with the prior art, the battery management system of the present invention applies an equalization circuit with a bidirectional full-bridge CLLC resonance topology, which can reduce energy loss, decrease the circuit volume, improve the energy transfer efficiency, enhance the anti-interference ability of the circuit, and strengthen the reusability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the equalization circuit;

[0023] Figure 2 It is a schematic diagram of the battery management system;

[0024] Figure 3 It is a schematic diagram of the gate drive unit;

[0025] Figure 4 It is a schematic diagram of the ideal waveform of the equalization circuit;

[0026] Figure 5 It is a schematic diagram of the energy flow in Mode 1 (t0~t1);

[0027] Figure 6 It is a schematic diagram of the energy flow in Mode 2 (t1~t2);

[0028] Figure 7 It is a schematic diagram of the energy flow in Mode 3 (t2~t3);

[0029] Figure 8 It is a schematic diagram of the energy flow in Mode 4 (t3~t4). DETAILED DESCRIPTION OF THE INVENTION

[0030] The following further describes the present invention with reference to the drawings.

[0031] As Figure 1, A balancing circuit based on a bidirectional full-bridge CLLC resonant topology, including a transformer T. One end of the primary winding of the transformer T is connected to inductor L1r and inductor L1p, and the other end of the primary winding of the transformer T is connected to capacitor C1p, capacitor C1r1, and capacitor C1r2. Inductor L1p and capacitor C1p are connected to form an Lp-Cp series network, and capacitor C1r1 and capacitor C1r2 are connected to form a resonant capacitor. Capacitor C1r1 is connected to the drain of MOS transistor Q11, the drain of MOS transistor Q13, and the positive electrode of battery cell V1. Capacitor C1r2 is connected to the source of MOS transistor Q13, the drain of MOS transistor Q14. Inductor L1r is connected to the source of MOS transistor Q11, the drain of MOS transistor Q12. The source of MOS transistor Q12 is connected to the source of MOS transistor Q14 and the negative electrode of battery cell V1. One end of the secondary winding of the transformer T is connected to inductor L2r and inductor L2p, and the other end of the secondary winding of the transformer T is connected to capacitor C2p, capacitor C2r1, and capacitor C2r2. Inductor L2p and capacitor C2p are connected to form an Lp-Cp series network, and capacitor C2r1 and capacitor C2r2 are connected to form a resonant capacitor. Capacitor C2r1 is connected to the drain of MOS transistor Q21, the drain of MOS transistor Q23, and the positive electrode of battery cell V2. Capacitor C2r2 is connected to the source of MOS transistor Q23, the drain of MOS transistor Q24. Inductor L2r is connected to the source of MOS transistor Q21, the drain of MOS transistor Q22. The source of MOS transistor Q22 is connected to the source of MOS transistor Q24 and the negative electrode of battery cell V2. On the basis of the CLLLC topology, the resonant capacitor Cr is divided into two identical resonant capacitors, and the Lp-Cp series network is used to replace the inherent exciting inductance of the transformer. In order to reduce the volume of the circuit, a nanocrystalline alloy magnetic core can be used to integrate all the inductors in the circuit into a single magnetic core. Replacing the exciting inductance with the Lp-Cp series network can flexibly adjust the impedance to adapt to the operating frequency. The expression of its equivalent exciting inductance Lmeq is:

[0032]

[0033] f z : Resonant frequency,

[0034] The resonant capacitor Cr is divided into two identical capacitors, and its expression is:

[0035] C r =2C 1r1 =2C 1r2 =2C 2r1 =2C 2r2 .

[0036] Such as Figure 2, a battery management system, comprising a balancing circuit, a battery pack, an AFE chip, an MCU chip, a gate drive unit, a fuse, a Hall sensor, a charging MOS transistor, a discharging MOS transistor, a drive processing unit, a communication unit, and an alarm unit. The battery pack is connected to the AFE chip, the AFE chip is connected to the MCU chip, the MCU chip is connected to the gate drive unit, the gate drive unit is connected to the balancing circuit, the balancing circuit is connected to the battery pack, the negative electrode of the battery pack is connected to the fuse, the fuse is connected to the Hall sensor, the Hall sensor is connected to the MCU chip and the charging MOS transistor, the charging MOS transistor is connected to the discharging MOS transistor and the drive processing unit, the discharging MOS transistor is connected to the drive processing unit, the MCU chip is connected to the drive processing unit and the communication unit, and the communication unit is connected to the alarm unit. The Hall sensor is used to detect the current of the battery, convert the current signal into a voltage signal for the MCU chip to monitor and control the current. The MCU controls the on and off of the charging MOS and the discharging MOS through the drive control unit according to the state of the battery and the control logic, so as to realize the charging and discharging control of the battery. When an abnormal situation occurs in the battery system, the MCU will trigger the alarm unit to send out an alarm signal.

[0037] The model of the AFE chip is ADBMS1818.

[0038] The model of the MCU chip is GD32F307VET6.

[0039] Such as Figure 3, the gate driving unit includes chip U1. Chip U1 is provided with an enable pin A, an enable pin B, an output pin A, an output pin B, an input pin A, and an input pin B. The enable pin A is connected to the drain of MOS transistor Q2. The gate of MOS transistor Q2 is connected to resistor R3 and resistor R4. The other end of resistor R3 and the source of MOS transistor Q2 are combined and grounded. The enable pin B is connected to the drain of MOS transistor Q1. The gate of MOS transistor Q1 is connected to resistor R1 and resistor R2. The other end of resistor R2 and the source of MOS transistor Q1 are combined and grounded. The input pin A and the input pin B are connected to the output end of the MCU chip. The control signals of the MCU chip are respectively transmitted to resistor R1 and resistor R4. The output pin A is connected to transistor Q3 and transistor Q4. One end of transistor Q3 is connected to the supply voltage. One end of transistor Q4 is grounded. The other ends of transistor Q3 and transistor Q4 are combined and connected to resistor R5. Resistor R5 is connected to capacitor C1. Capacitor C1 is connected to one end of the primary winding of transformer TA. The other end of the primary winding of transformer TA is grounded. One end of a secondary winding of transformer TA is connected to capacitor C2. The other end is connected to diode D1, capacitor C3, resistor R6, and the source of MOS transistor Q11. The gates of diode D1, capacitor C3, resistor R6, and MOS transistor Q11 are combined and connected to capacitor C2. One end of the other secondary winding of transformer TA is connected to capacitor C4. The other end is connected to diode D2, capacitor C5, resistor R7, and the source of MOS transistor Q14. The gates of diode D2, capacitor C5, resistor R7, and MOS transistor Q14 are combined and connected to capacitor C4. The output pin B is connected to transistor Q5 and transistor Q6. One end of transistor Q5 is connected to the supply voltage. One end of transistor Q6 is grounded. The other ends of transistor Q5 and transistor Q6 are combined and connected to resistor R8. Resistor R8 is connected to capacitor C6. Capacitor C6 is connected to one end of the primary winding of transformer TB. The other end of the primary winding of transformer TB is grounded. One end of a secondary winding of transformer TB is connected to capacitor C7. The other end is connected to diode D3, capacitor C8, resistor R9, and the source of MOS transistor Q12. The gates of diode D3, capacitor C8, resistor R9, and MOS transistor Q12 are combined and connected to capacitor C7. One end of the other secondary winding of transformer TB is connected to capacitor C9. The other end is connected to diode D4, capacitor C10, resistor R10, and the source of MOS transistor Q13. The gates of diode D4, capacitor C10, resistor R10, and MOS transistor Q13 are combined and connected to capacitor C9.

[0040] When the AFE chip detects that the voltage of a single cell in the battery pack reaches the set threshold, the AFE chip sends the information to the MCU chip. The MCU chip outputs control signals CON1 and CON2 to the gate drive unit and controls the gate drive unit to output pulse signals VgA or VgB to the equalization circuit through the control signals. The pulse signals control the four modes of the equalization circuit to alternate; when the control signals CON1 and CON2 are at high level, the gate drive unit has no output; when the control signals CON1 and CON2 are at low level, the gate drive unit outputs pulse signals VgA and VgB.

[0041] Within one switching cycle, the equalization circuit has four working modes, from mode 1 to mode 4. Among them, mode 1 and mode 2 are the working stages corresponding to a group of MOS tubes (Q11, Q14, Q21, Q24), and mode 3 and mode 4 are the working stages corresponding to another group of MOS tubes (Q12, Q13, Q22, Q23). In addition, mode 1 and mode 3 are dead time stages, and mode 2 and mode 4 are resonance and energy transfer stages. The schematic diagram of the ideal waveform of the bidirectional full bridge is as Figure 4 shown.

[0042] The pulse signals control the four modes of the equalization circuit to alternate:

[0043] As Figure 5 , in mode 1, in the dead time stage before MOS tubes Q11 and Q14 are turned on, the gate drive unit has no output, the high-voltage side cell does not transfer energy to the low-voltage side cell, and there is a reverse resonance current on the high-voltage side. The resonance current charges the parallel junction capacitors of MOS tubes Q12 and Q13, discharges the parallel junction capacitors of MOS tubes Q11 and Q14 until the voltage is zero, and then the resonance current flows through the parallel body diodes of MOS tubes Q11 and Q14, creating conditions for the realization of ZVS of MOS tubes Q11 and Q14 in the next step;

[0044] As Figure 6 , in mode 2, the gate drive unit outputs the VgA pulse signal, and MOS tubes Q11 and Q14 achieve zero voltage switching (ZVS) conduction. Since the channel conduction resistance of the MOS tube is less than the equivalent conduction resistance of its parallel body diode, the resonance current of the parallel body diodes of MOS tubes Q11 and Q14 flows to their channels. The high-voltage side cell applies energy positively to the resonance network, the resonance current rises linearly, and the parallel body diodes of the low-voltage side MOS tubes Q21 and Q24 conduct naturally, and the energy is transferred to the low-voltage side cell through the transformer, realizing the charging balance between cells;

[0045] As Figure 7, in Mode 3, in the dead time stage before the MOS transistors Q12 and Q13 are turned on, the gate drive unit has no output, the high-voltage side battery cell does not transfer energy to the low-voltage side battery cell, and there is a reverse resonant current in the high-voltage side. The resonant current charges the parallel junction capacitors of the MOS transistors Q11 and Q14, discharges the parallel junction capacitors of the MOS transistors Q12 and Q13 until the zero voltage, and then the resonant current flows through the parallel body diodes of the MOS transistors Q12 and Q13, creating conditions for the realization of ZVS of the MOS transistors Q12 and Q13 in the next step;

[0046] Such as Figure 8 , in Mode 4, the gate drive unit outputs a VgB pulse signal, the MOS transistors Q12 and Q13 achieve zero-voltage switching (ZVS) conduction, the resonant current of the parallel body diodes of the MOS transistors Q12 and Q13 flows into their channels, the high-voltage side battery cell reversely applies energy to the resonant network, the resonant current linearly increases, the parallel body diodes of the low-voltage side MOS transistors Q22 and Q23 naturally conduct, and the energy is transferred to the low-voltage side battery through the transformer, realizing the charging balance between the battery cells.

[0047] When in Mode 2 and Mode 4, resonance occurs at the main resonance frequency fr; when in Mode 1 and Mode 3, resonance occurs at the secondary resonance frequency fr1, and the expressions are as follows:

[0048]

[0049] Lr is the value of the resonant inductor, Cr is the value of the resonant capacitor, and Lm is the value of the exciting inductor.

[0050] This circuit is based on a bidirectional DC-DC circuit, and by realizing the ZVS of the MOS transistors, the conduction loss and switching loss in the balancing process can be reduced; by changing the resonant capacitor, its current ripple and effective current value are relatively low, and at the same time, the voltage stress of the capacitor is reduced, improving the electromagnetic interference characteristics of the balancing circuit; using an Lp-Cp series network to replace the inherent exciting inductor of the transformer can effectively reduce the circulating current loss in the resonant circuit, and further, the energy transfer efficiency of this balancing circuit can reach up to 93%.

Claims

1. A balancing circuit based on a bidirectional full bridge, comprising a transformer T, characterized in that: One end of the primary winding of the transformer T is connected to the inductors L1r and L1p, and the other end of the primary winding of the transformer T is connected to the capacitors C1p, C1r1, and C1r2. The inductor L1p and the capacitor C1p are connected to form an Lp-Cp series network. The capacitors C1r1 and C1r2 are connected to form a resonant capacitor. The capacitor C1r1 is connected to the drain of the MOS transistor Q11, the drain of the MOS transistor Q13, and the positive electrode of the battery cell V1. The capacitor C1r2 is connected to the source of the MOS transistor Q13, the drain of the MOS transistor Q14. The inductor L1r is connected to the source of the MOS transistor Q11, the drain of the MOS transistor Q12. The source of the MOS transistor Q12 is connected to the source of the MOS transistor Q14 and the negative electrode of the battery cell V1. One end of the secondary winding of the transformer T is connected to the inductors L2r and L2p, and the other end of the secondary winding of the transformer T is connected to the capacitors C2p, C2r1, and C2r2. The inductor L2p and the capacitor C2p are connected to form an Lp-Cp series network. The capacitors C2r1 and C2r2 are connected to form a resonant capacitor. The capacitor C2r1 is connected to the drain of the MOS transistor Q21, the drain of the MOS transistor Q23, and the positive electrode of the battery cell V2. The capacitor C2r2 is connected to the source of the MOS transistor Q23, the drain of the MOS transistor Q24. The inductor L2r is connected to the source of the MOS transistor Q21, the drain of the MOS transistor Q22. The source of the MOS transistor Q22 is connected to the source of the MOS transistor Q24 and the negative electrode of the battery cell V2. The equivalent relationship expression of the resonant capacitor Cr is as follows: ， The equivalent exciting inductance Lmeq of the Lp-Cp series network, and its expression is as follows: 。 2. A battery management system, comprising the equalization circuit, battery pack, AFE chip, MCU chip and gate drive unit described in claim 1, characterized in that: The battery pack is connected to the AFE chip, the AFE chip is connected to the MCU chip, the MCU chip is connected to the gate driving unit, the gate driving unit is connected to the balancing circuit, and the balancing circuit is connected to the battery pack.

3. A battery management system according to claim 2, characterized in that: The model of the AFE chip used is ADBMS1818.

4. A battery management system according to claim 2, characterized in that: The model of the MCU chip used is GD32F307VET6.

5. A battery management system according to claim 2, characterized in that: The described gate driving unit includes a chip U1. The chip U1 is provided with an enable pin A, an enable pin B, an output pin A, an output pin B, an input pin A, and an input pin B. The enable pin A is connected to the drain of the MOS transistor Q2. The gate of the MOS transistor Q2 is connected to a resistor R3 and a resistor R4. The other end of the resistor R3 and the source of the MOS transistor Q2 are combined and grounded. The enable pin B is connected to the drain of the MOS transistor Q1. The gate of the MOS transistor Q1 is connected to a resistor R1 and a resistor R2. The other end of the resistor R2 and the source of the MOS transistor Q1 are combined and grounded. The input pin A and the input pin B are connected to the output end of the MCU chip. The control signals of the MCU chip are respectively transmitted to the resistor R1 and the resistor R4. The output pin A is connected to a transistor Q3 and a transistor Q4. One end of the transistor Q3 is connected to the supply voltage. One end of the transistor Q4 is grounded. The other ends of the transistor Q3 and the transistor Q4 are combined and connected to a resistor R5. The resistor R5 is connected to a capacitor C1. The capacitor C1 is connected to one end of the primary winding of the transformer TA. The other end of the primary winding of the transformer TA is grounded. One end of a secondary winding of the transformer TA is connected to a capacitor C2. The other end is connected to a diode D1, a capacitor C3, a resistor R6, and the source of the MOS transistor Q11. The diode D1, the capacitor C3, the resistor R6, and the gate of the MOS transistor Q11 are combined and connected to the capacitor C2. One end of the other secondary winding of the transformer TA is connected to a capacitor C4. The other end is connected to a diode D2, a capacitor C5, a resistor R7, and the source of the MOS transistor Q14. The diode D2, the capacitor C5, the resistor R7, and the gate of the MOS transistor Q14 are combined and connected to the capacitor C4. The output pin B is connected to a transistor Q5 and a transistor Q6. One end of the transistor Q5 is connected to the supply voltage. One end of the transistor Q6 is grounded. The other ends of the transistor Q5 and the transistor Q6 are combined and connected to a resistor R8. The resistor R8 is connected to a capacitor C6. The capacitor C6 is connected to one end of the primary winding of the transformer TB. The other end of the primary winding of the transformer TB is grounded. One end of a secondary winding of the transformer TB is connected to a capacitor C7. The other end is connected to a diode D3, a capacitor C8, a resistor R9, and the source of the MOS transistor Q12. The diode D3, the capacitor C8, the resistor R9, and the gate of the MOS transistor Q12 are combined and connected to the capacitor C7. One end of the other secondary winding of the transformer TB is connected to a capacitor C9. The other end is connected to a diode D4, a capacitor C10, a resistor R10, and the source of the MOS transistor Q13. The diode D4, the capacitor C10, the resistor R10, and the gate of the MOS transistor Q13 are combined and connected to the capacitor C9.

6. The control method of a battery management system according to any one of claims 2-5, characterized in that: When the AFE chip detects that the voltage of a single cell in the battery pack reaches the set threshold, the AFE chip sends information to the MCU chip. The MCU chip outputs control signals CON1 and CON2 to the gate drive unit and controls the gate drive unit to output pulse signals VgA or VgB to the equalization circuit through the control signals. The pulse signals control the four modes of the equalization circuit to alternate; when the control signals CON1 and CON2 are at high level, the gate drive unit has no output; when the control signals CON1 and CON2 are at low level, the gate drive unit outputs pulse signals VgA and VgB.

7. The control method of a battery management system according to claim 6, characterized in that: The four modes of the equalization circuit are controlled by the pulse signals to alternate, specifically including the following steps: Mode 1, in the dead zone stage before the MOS transistors Q11 and Q14 are turned on, the gate drive unit has no output. The resonant current charges the parallel junction capacitors of the MOS transistors Q12 and Q13, discharges the parallel junction capacitors of the MOS transistors Q11 and Q14 until the voltage reaches zero, and then the resonant current flows through the parallel body diodes of the MOS transistors Q11 and Q14. Mode 2, the gate drive unit outputs the VgA pulse signal. The VgA pulse signal controls the MOS transistors Q11 and Q14 to achieve zero-voltage-switching conduction. The resonant current of the parallel body diodes of the MOS transistors Q11 and Q14 flows into their channels. The high-voltage-side cell applies energy to the resonant network in the forward direction. The parallel body diodes of the low-voltage-side MOS transistors Q21 and Q24 conduct naturally, and the energy is transferred to the low-voltage-side cell through the transformer to achieve charge equalization between the cells. Mode 3, in the dead zone stage before the MOS transistors Q12 and Q13 are turned on, the gate drive unit has no output. The resonant current charges the parallel junction capacitors of the MOS transistors Q11 and Q14, discharges the parallel junction capacitors of the MOS transistors Q12 and Q13 until the voltage reaches zero, and then the resonant current flows through the parallel body diodes of the MOS transistors Q12 and Q13. Mode 4, the gate drive unit outputs the VgB pulse signal. The VgB pulse signal controls the MOS transistors Q12 and Q13 to achieve zero-voltage-switching conduction. The resonant current of the parallel body diodes of the MOS transistors Q12 and Q13 flows into their channels. The high-voltage-side cell applies energy to the resonant network in the reverse direction. The parallel body diodes of the low-voltage-side MOS transistors Q22 and Q23 conduct naturally, and the energy is transferred to the low-voltage-side battery through the transformer to achieve charge equalization between the cells.

8. The control method of a battery management system according to claim 7, wherein: When in Mode 2 and Mode 4, resonance occurs at the main resonance frequency fr; when in Mode 1 and Mode 3, resonance occurs at the secondary resonance frequency fr1. The expressions are as follows: 。

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