Charge modulation method and circuit applied to step-down conversion circuit, and electronic equipment

Abstract

The invention discloses a charge modulation method and circuit applied to a step-down conversion circuit, and electronic equipment. The charge modulation method comprises the following steps: acquiring a conduction current instantaneous value in an upper switch sub-circuit and / or a lower switch sub-circuit; carrying out integration processing on the conduction current instantaneous value to obtain a charge integration quantity; generating a driving control signal by using a charge error value between the charge integral quantity and the target charge quantity; detecting whether the step-down conversion circuit is in a first load state; if the step-down conversion circuit is in the first load state, the duty ratio of the driving control signal is adjusted to the previous set multiple; and the adjusted driving control signal is sent to one of the upper switch sub-circuit and the lower switch sub-circuit so as to trigger the upper switch sub-circuit and the lower switch sub-circuit to change the switch state. Through the above mode, the charge modulation method provided by the invention can quickly adjust the power supply output to a proper interval when the load is greatly changed, and can effectively suppress the ripple wave possibly occurring when the load is suddenly changed, and the dynamic response characteristic is good.

Description

Technical Field

[0001] This application relates to the field of circuit control technologies, and particularly to a charge modulation method and circuit, and an electronic device applied to a buck conversion circuit. Background Art

[0002] Currently, with the increasing richness of electronic devices, the performance requirements for the driving power supply of electronic devices are becoming increasingly stringent. Especially when the load device adopts a complex architecture such as multi-stage parallel operation or distributed connection, the demand for the power supply output of the driving power supply is a relatively wide voltage range, that is, there are application scenarios where the load varies within a large range, resulting in sudden changes in the load current and drastic fluctuations in the power supply output voltage. This trend poses higher challenges to the voltage withstand capacity, dynamic response characteristics, and power density of the driving power supply.

[0003] However, in related technologies, to obtain a wider range of output voltages, a linear power supply is usually adopted, that is, the power device operates in the linear region to control the output current. However, this solution is limited by the voltage stress limit of the power device, the single-tube voltage withstand is insufficient, and there are problems with voltage sharing in series devices, making it difficult to directly adapt to high-voltage scenarios. Moreover, parameters such as the larger parasitic capacitance and internal resistance of high-voltage devices will limit the current establishment speed, thereby affecting key indicators of the driving power supply such as the current rise time and dynamic response performance. Summary of the Invention

[0004] The main technical problem to be solved by this application is to provide a charge modulation method and circuit, and an electronic device applied to a buck conversion circuit, which can solve the problems in related technologies that linear power supplies are difficult to directly adapt to high-voltage scenarios and affect key indicators of the driving power supply such as the current rise time and dynamic response performance.

[0005] To solve the above technical problem, a technical solution adopted by this application is: to provide a charge modulation method applied to a buck conversion circuit, the buck conversion circuit includes an upper switch sub-circuit and a lower switch sub-circuit that are coupled to each other, and wherein, the charge modulation method includes: obtaining the instantaneous value of the conduction current in the upper switch sub-circuit and / or the lower switch sub-circuit; performing integral processing on the instantaneous value of the conduction current to obtain a charge integration amount; generating a drive control signal using the charge error value between the charge integration amount and the target charge amount; detecting whether the buck conversion circuit is in a first load state; if the buck conversion circuit is in the first load state, adjusting the duty cycle of the drive control signal to a previously set multiple; and sending the adjusted drive control signal to one of the upper switch sub-circuit and the lower switch sub-circuit to trigger it to change the switch state.

[0006] Among them, the steps of integrating the instantaneous value of the conduction current to obtain the charge integration amount include: obtaining the rising edge of the drive control signal; integrating the instantaneous value of the conduction current in response to the rising edge to obtain the charge integration amount; delaying a preset duration to reset the charge integration amount; where the preset duration is greater than or equal to the current high-level duration of the drive control signal and less than the current switching period of the drive control signal.

[0007] Among them, the steps of integrating the instantaneous value of the conduction current to obtain the charge integration amount include: obtaining the rising edge and falling edge of the drive control signal; integrating the instantaneous value of the conduction current in response to the rising edge to obtain the charge integration amount; resetting the charge integration amount in response to the falling edge.

[0008] Among them, the buck conversion circuit further includes an output regulation sub-circuit. The output regulation sub-circuit is coupled to the upper switching sub-circuit and the lower switching sub-circuit. The steps of generating a drive control signal using the charge error value between the charge integration amount and the target charge amount include: obtaining the output current of the output regulation sub-circuit; subtracting the target reference current from the output current to obtain a current error value; generating a drive control signal using the charge error value between the charge integration amount and the target charge amount and the current error value.

[0009] Among them, the steps of detecting whether the buck conversion circuit is in the first load state include: obtaining the target reference current sent by the host computer; determining whether the target reference current is less than the first mode switching threshold; if the buck conversion circuit is in the first load state, the steps of adjusting the duty cycle of the drive control signal to a previous set multiple include: if the target reference current is less than the first mode switching threshold, adjusting the duty cycle of the drive control signal to a previous set multiple.

[0010] Among them, the buck conversion circuit further includes an output regulation sub-circuit. The output regulation sub-circuit is coupled to the upper switching sub-circuit and the lower switching sub-circuit. The steps of detecting whether the buck conversion circuit is in the first load state include: obtaining the output current of the output regulation sub-circuit; integrating the output current to obtain a feedback charge integration amount; determining whether the feedback charge integration amount is less than the second mode switching threshold; if the buck conversion circuit is in the first load state, the steps of adjusting the duty cycle of the drive control signal to a previous set multiple include: if the feedback charge integration amount is less than the second mode switching threshold, adjusting the duty cycle of the drive control signal to a previous set multiple.

[0011] Among them, the steps of integrating the output current to obtain a feedback charge integration amount include: obtaining the rising edge and falling edge of the drive control signal; integrating the output current in response to the rising edge to obtain a feedback charge integration amount; resetting the feedback charge integration amount in response to the falling edge.

[0012] Among them, the drive control signal includes a first pulse width modulation signal and a second pulse width modulation signal. The charge modulation method further includes: if the buck conversion circuit is not in the first load state, sending the first pulse width modulation signal and the second pulse width modulation signal to the upper switch sub-circuit and the lower switch sub-circuit respectively to trigger the upper switch sub-circuit and the lower switch sub-circuit to change their switch states.

[0013] To solve the above technical problems, another technical solution adopted in this application is: to provide a charge modulation circuit, wherein the charge modulation circuit is coupled to the buck conversion circuit; wherein, the charge modulation circuit adjusts the current of the buck conversion circuit by using the charge modulation method described in any one of the above.

[0014] To solve the above technical problems, yet another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a housing and a charge modulation circuit connected to the housing; wherein, the charge modulation circuit is the charge modulation circuit described above.

[0015] The beneficial effect of this application is: different from the prior art, the charge modulation method provided in this application obtains the instantaneous value of the conduction current in the upper switch sub-circuit and / or the lower switch sub-circuit, integrates the instantaneous value of the conduction current to obtain the charge integration amount, and generates a drive control signal by using the charge error value between the charge integration amount and the target charge amount. When it is detected that the buck conversion circuit is in the first load state, the duty ratio of the drive control signal is adjusted to a previously set multiple, and the adjusted drive control signal is sent to one of the upper switch sub-circuit and the lower switch sub-circuit to trigger it to change its switch state. Therefore, when the load changes greatly, it can quickly adjust the output current and output voltage of the buck conversion circuit to a suitable range by reasonably adjusting the duty ratio of the drive control signal and blocking the wave of some switch sub-circuits, so as to adapt to the load's demand for a wide range of output voltages, effectively suppress the ripple that may occur during load mutation, and has good dynamic response characteristics, can effectively meet the demand for the power supply transient recovery ability, and does not require the configuration of high-voltage devices and complex compensation networks, and the hardware cost is also low. Description of the Drawings

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings, where: Figure 1 It is a schematic flowchart of the first embodiment of the charge modulation method of this application; Figure 2It is a schematic structural diagram of the first embodiment of the charge modulation circuit of the present application; Figure 3 is Figure 1 a schematic flowchart of an embodiment of S12 in Figure 4 is Figure 1 a schematic flowchart of another embodiment of S12 in Figure 5 is Figure 1 a schematic flowchart of an embodiment of S13 in Figure 6 It is a schematic structural diagram of the second embodiment of the charge modulation circuit of the present application; Figure 7 It is a schematic structural diagram of the third embodiment of the charge modulation circuit of the present application; Figure 8 It is a schematic flowchart of the second embodiment of the charge modulation method of the present application; Figure 9 It is a schematic flowchart of the third embodiment of the charge modulation method of the present application; Figure 10 is Figure 9 a schematic flowchart of an embodiment of S75 in Figure 11 It is a schematic structural diagram of an embodiment of the electronic device of the present application. Specific Embodiments

[0017] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0018] The terms "first", "second", and "third" in this application are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined. In all the directional indications (such as up, down, left, right, front, back...) in the embodiments of this application, they are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the drawings). If the specific posture changes, then the directional indications will also change accordingly. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0019] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0020] The following provides a detailed description of this application in conjunction with the drawings and embodiments.

[0021] Please refer to Figure 1 and Figure 2 , where Figure 1 is a schematic flowchart of the first embodiment of the charge modulation method of this application, Figure 2 and is a schematic structural diagram of the first embodiment of the charge modulation circuit of this application. Specifically, the following steps may be included:

[0022] It can be understood that the charge modulation method in this embodiment is specifically applied to the current regulation of the first buck conversion circuit 30 as shown in Figure 2 . The first buck conversion circuit 30 includes a first upper switch sub-circuit 31 and a first lower switch sub-circuit 32 that are coupled to each other; among them, the first charge modulation circuit 20 uses the charge modulation method described in any item herein to perform charge modulation on the first buck conversion circuit 30.

[0023] It should be noted that the first step-down conversion circuit 30 can specifically be a single-phase BUCK circuit (step-down conversion circuit), a multi-phase BUCK circuit, or a BOOST circuit (step-up conversion circuit), or any other reasonable form of circuit topology, and this embodiment does not limit this.

[0024] In some embodiments, the first charge modulation circuit 20 can specifically include a control chip, a DSP (Digital Signal Processing) chip, an MCU (Micro Controller Unit) circuit, a CPU (Central Processing Unit), a single-chip microcomputer, a field programmable gate array, a programmable logic device, discrete gates, or transistor logic devices, discrete hardware, or any other reasonable circuit unit with signal processing functions. This application does not limit this.

[0025] In addition, "coupled" in this article refers to including any direct and indirect connection means. Therefore, if it is described in the text that the first circuit is coupled to the second circuit, it means that the first circuit can be directly connected to the second circuit through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or can be indirectly electrically connected or signal-connected to the second circuit through other circuits or connection means.

[0026] Specifically, the first charge modulation circuit 20 monitors in real time the instantaneous value of the conduction current in the first upper switch sub-circuit 31 and / or the first lower switch sub-circuit 32, that is, the instantaneous current amplitude when the switching element inside the first upper switch sub-circuit 31 and / or the first lower switch sub-circuit 32 is triggered to conduct.

[0027] Among them, the instantaneous value of the conduction current can specifically be obtained through any reasonable sampling method such as a high-precision current sensor or circuit model estimation. This application does not limit this.

[0028] S12: Perform an integration process on the instantaneous value of the conduction current to obtain a charge integration quantity.

[0029] Perform an integration process on the instantaneous value of the conduction current to calculate and obtain a charge integration quantity.

[0030] S13: Generate a drive control signal using the charge error value between the charge integration quantity and the target charge quantity.

[0031] Set a target charge quantity, which is usually determined based on the desired output voltage and load requirements.

[0032] Subtract the target charge quantity from the charge integration quantity to calculate the charge error value.

[0033] The charge error value is processed by using a PID (Proportional Integral Derivative) controller, a PI controller, or any other reasonable feedback control algorithm to obtain a drive control signal, and the duty cycle of the drive control signal is dynamically adjusted. This application does not limit this.

[0034] Among them, the drive control signal is used to trigger the switching elements in each switching sub-circuit to control their on and off states.

[0035] In some embodiments, the drive control signal may specifically be one or more of any reasonable control signals such as a PWM (Pulse Width Modulation) signal or a PFM (Pulse Frequency Modulation) signal. This application does not limit this.

[0036] S14: Detect whether the buck conversion circuit is in the first load state.

[0037] Detect the current load rate of the first buck conversion circuit 30, that is, the ratio of the actual load power to the rated load power, to determine whether the current load rate is greater than the set proportional threshold, and further determine whether the first buck conversion circuit 30 is currently in the first load state.

[0038] It is worth noting that the load-carrying capacity of an electronic circuit usually includes no-load, light load, full load, and overload. Among them, no-load refers to the operating state where the device or system is not connected to any load; the load is significantly lower than the rated capacity, and the specific ratio varies in different fields. Usually, it refers to a load rate of less than 30% of the rated power (or defined as less than 50% in some scenarios); full load means that the load is close to or equal to the rated capacity, such as the output power of a generator being consistent with the nameplate nominal value; overload means that the load exceeds the rated capacity.

[0039] In addition, the load rate is a core parameter that measures the relationship between the actual operating load of a device or system and the rated capacity, and its definition and calculation method vary in different application fields.

[0040] ‌General definition: Load rate = actual load / rated load * 100%, which is applicable to scenarios such as transformers, motors, and power systems. For example: The load rate of a transformer is the ratio of the output apparent power to the rated capacity.

[0041] Among them, the load rate in the first load state is not greater than the set proportional threshold.

[0042] In some embodiments, the set ratio threshold may specifically correspond to the load rate under the light load state, such as 30% or 50%; or, the load rate corresponding to a large change in the load resulting in a large ripple risk; or, a critical load rate reasonably set to distinguish different working scenarios, such as powering different load devices or different numbers of load devices, such as any reasonable ratio thresholds like 20%, 40% or 60%, etc., and the present application does not limit this.

[0043] Wherein, if the first buck conversion circuit 30 is in the first load state, S15 is executed; if the first buck conversion circuit 30 is in the second load state, S17 is executed.

[0044] S15: Adjust the duty cycle of the drive control signal to a previously set multiple.

[0045] Wherein, if it is currently detected that the first buck conversion circuit 30 is in the first load state, the duty cycle of the drive control signal is adjusted to a previously set multiple, that is, multiplying the previously obtained duty cycle of the drive control signal by the set multiple.

[0046] In some embodiments, the set multiple is greater than 1, and specifically may be 1.5 - 2.5, such as any reasonable multiple like 1.9, 2 or 2.1, etc., and preferably 2, and the present application does not limit this.

[0047] S16: Send the adjusted drive control signal to one of the upper switch sub - circuit and the lower switch sub - circuit to trigger a change in its switching state.

[0048] When it is determined that the first buck conversion circuit 30 is in the first load state, according to the adjusted drive control signal, it is selectively sent to one of the first upper switch sub - circuit 31 and the first lower switch sub - circuit 32 to select only one of the switch sub - circuits to be driven.

[0049] Wherein, when the actual value currently obtained by the first charge modulation circuit 20 is the instantaneous conduction current value of the first upper switch sub - circuit 31, specifically, the adjusted drive control signal is sent to the first lower switch sub - circuit 32, and the first upper switch sub - circuit 31 is in the wave - blocking state; when the currently obtained value is the instantaneous conduction current value of the first lower switch sub - circuit 32, the adjusted drive control signal is sent to the first upper switch sub - circuit 31, and the first lower switch sub - circuit 32 is in the wave - blocking state; when the instantaneous conduction current values of the first upper switch sub - circuit 31 and the first lower switch sub - circuit 32 are currently obtained synchronously, the adjusted drive control signal is sent to any one of the first upper switch sub - circuit 31 and the first lower switch sub - circuit 32, and the present application does not limit this.

[0050] In a specific embodiment, the first load state may specifically correspond to a light load, the set ratio threshold is 30% or 50%, and the set multiple corresponds to 2 times. When blocking the wave of one of the first upper switching sub-circuit 31 and the first lower switching sub-circuit 32, the duty cycle of the drive control signal can be adjusted to 2 times the previous value, so as to adjust the output current and output voltage of the first buck conversion circuit 30 to an appropriate range, to meet the current power supply requirements while effectively suppressing the possible ripple when the load suddenly changes.

[0051] It should be noted that when the first buck conversion circuit 30 is in the first load state, adjusting the duty cycle of the drive control signal to the previously set multiple corresponds to sending the adjusted drive control signal to one of the first upper switching sub-circuit 31 and the first lower switching sub-circuit 32. For example, in the case of a light load, one of the first upper switching sub-circuit 31 and the first lower switching sub-circuit 32 will be in the wave-blocking state, and the other will be in the working state. To ensure that the output current and output voltage of the first buck conversion circuit 30 are adjusted to an appropriate range, that is, on the premise that only one switching sub-circuit is working, in order to meet the stable output power as much as possible, to adapt to the load's demand for a wide range of output voltages, and effectively suppress the possible ripple when the load suddenly changes, compared with the situation where both the first upper switching sub-circuit 31 and the first lower switching sub-circuit 32 are in the working state, the conduction time of the path between the input and the output corresponding to only the first upper switching sub-circuit 31 or the first lower switching sub-circuit 32 working is actually half of the previous value. To ensure that the output voltage does not change suddenly and is as close as possible to the output voltage when both the first upper switching sub-circuit 31 and the first lower switching sub-circuit 32 are in the working state, it is necessary to increase the duty cycle of the drive control signal at this time, that is, adjust the duty cycle to the previously set multiple, and the set multiple is greater than 1, and is preferably 2.

[0052] For ease of understanding, taking the output power of the first step-down conversion circuit 30 as 100 W (watts) as an example, if the first upper switch sub-circuit 31 and the first lower switch sub-circuit 32 work simultaneously, the single-channel output power of the first upper switch sub-circuit 31 or the first lower switch sub-circuit 32 is 50 W. When the duty cycle of each drive control signal is 70%, if the first step-down conversion circuit 30 switches to half load (load rate is 50%), that is, the output power is 50 W, then the single-channel output power of the first upper switch sub-circuit 31 or the first lower switch sub-circuit 32 is 25 W. At this time, the duty cycle of each drive control signal becomes 35%; and if while the first step-down conversion circuit 30 switches to half load, one drive is shut down, that is, the single-channel output power of the first upper switch sub-circuit 31 or the first lower switch sub-circuit 32 needs to meet 50 W. Then it is necessary to adjust the duty cycle of the drive control signal of the remaining working channel, that is, the first upper switch sub-circuit 31 or the first lower switch sub-circuit 32, which was 35% before, to 2 times the previous value, that is, adjust the duty cycle to 70%, to meet the requirements of the current output power, and on this premise, suppress the possible ripple when the load suddenly changes.

[0053] S17: Send the first pulse width modulation signal and the second pulse width modulation signal to the upper switch sub-circuit and the lower switch sub-circuit respectively, so as to trigger the upper switch sub-circuit and the lower switch sub-circuit to change their switch states respectively.

[0054] Among them, the drive control signal includes a first pulse width modulation signal and a second pulse width modulation signal. The first step-down conversion circuit 30 further includes a first regulated output sub-circuit 33, and the first regulated output sub-circuit 33 is coupled to the first upper switch sub-circuit 31 and the first lower switch sub-circuit 32.

[0055] When the first charge modulation circuit 20 determines that the first step-down conversion circuit 30 is in the second load state, it sends the first pulse width modulation signal and the second pulse width modulation signal to the first upper switch sub-circuit 31 and the first lower switch sub-circuit 32 respectively, so as to trigger the first upper switch sub-circuit 31 and the first lower switch sub-circuit 32 to change their switch states respectively, so as to adjust the output current of the first regulated output sub-circuit 33.

[0056] In addition, the load rate of the second load state is greater than the set proportional threshold, and specifically, it can be understood as heavy load, full load, or another load power supply scenario different from the load devices or the number of loaded devices corresponding to the first load state. The present application does not limit this.

[0057] In some embodiments, the first charge modulation circuit 20 may specifically synchronously control the first upper switch sub-circuit 31 and the first lower switch sub-circuit 32, that is, the first pulse width modulation signal and the second pulse width modulation signal have the same phase to ensure the optimal current change slope. It may also asynchronously control the first upper switch sub-circuit 31 and the first lower switch sub-circuit 32, that is, the first pulse width modulation signal and the second pulse width modulation signal are phase interleaved, and specifically may have an arbitrary reasonable phase deviation such as 180 degrees or 120 degrees to optimize the bus capacitor voltage sharing effect.

[0058] In the above solution, when the load changes greatly, by reasonably adjusting the duty cycle of the drive control signal and quickly blocking the wave of some switch sub-circuits, the output current and output voltage of the first buck conversion circuit 30 are adjusted to an appropriate range to adapt to the load's demand for a wide range of output voltages, effectively suppressing the possible ripple when the load suddenly changes, and having good dynamic response characteristics, which can effectively meet the demand for the power supply transient recovery ability. Moreover, there is no need to configure high-voltage devices and complex compensation networks, and the hardware cost is also low. In addition, this method not only improves the control accuracy, efficiency and response speed of the first buck conversion circuit 30 under different load conditions, but also enhances the flexibility and adaptability of the system, and is applicable to a variety of power electronics application fields.

[0059] Please continue to refer to Figure 3 , Figure 3 is Figure 1 a schematic flowchart of an embodiment of S12. In an embodiment, in addition to the above S11 - S17, the charge modulation method of the present application further includes some more specific steps. Specifically, the above S12 may further include the following steps: S1211: Obtain the rising edge of the drive control signal.

[0060] It can be understood that the drive control signal is actually a pulse signal, with a conversion from a low level to a high level, that is, a rising edge, and a conversion from a high level to a low level, that is, a falling edge.

[0061] Specifically, the first current regulation circuit identifies and detects the rising edge of the drive control signal. For example, this can be achieved by any reasonable means such as a hardware circuit (such as an edge trigger), a software algorithm (for example, writing corresponding code in an embedded system), or a controller counter. The present application does not limit this.

[0062] S1212: Integrate the instantaneous value of the conduction current in response to the rising edge to obtain a charge integration amount.

[0063] When the rising edge of the drive control signal is detected, the instantaneous value of the current conduction obtained currently is integrated to obtain a charge integration amount.

[0064] S1213: Reset the charge integration amount for a preset duration of delay.

[0065] Starting from the rising edge, after counting the preset duration of delay, reset the charge integration amount, that is, integrate the instantaneous value of the conduction current from the rising edge moment until the preset duration of delay, and then clear the charge integration amount to wait for the next rising edge to re-integrate the instantaneous value of the conduction current.

[0066] Among them, the preset duration is greater than or equal to the current high-level duration of the drive control signal and less than the current switching period of the drive control signal. Practically, it can be understood as the falling edge of the drive control signal or any moment between the falling edge and the rising edge to ensure the switching state change of the dynamic response first upper switch sub-circuit 31 and / or the first lower switch sub-circuit 32, and detect in real time whether the delay reaches the preset duration through any reasonable means such as a timer, a pulse counter, or a software algorithm.

[0067] Please continue to refer to Figure 4 , Figure 4 is Figure 1 a schematic flowchart of another embodiment of S12 in . In one embodiment, in addition to the above S11 - S17, the charge modulation method of the present application further includes some more specific steps. Specifically, the above S12 can further include the following steps: S1221: Obtain the rising edge and falling edge of the drive control signal.

[0068] Specifically, identify and detect the falling edge and rising edge of the drive control signal. For example, this goal can be achieved through any reasonable means such as a hardware circuit (such as an edge trigger), a software algorithm (for example, writing corresponding code in an embedded system), or a controller counter. The present application does not limit this.

[0069] S1222: Integrate the instantaneous value of the conduction current in response to the rising edge to obtain the charge integration amount.

[0070] When detecting the rising edge of the drive control signal, integrate the currently obtained instantaneous value of the conduction current to obtain the charge integration amount.

[0071] S1223: Reset the charge integration amount in response to the falling edge.

[0072] When detecting the falling edge of the drive control signal, reset and clear the charge integration amount to wait for the next rising edge to re-integrate the instantaneous value of the conduction current.

[0073] Please refer to Figure 5 , Figure 5 is Figure 1Flow schematic diagram of an embodiment of S13. In one embodiment, in addition to the above S11 - S17, the charge modulation method of the present application further includes some more specific steps. Specifically, the above S13 may further include the following steps: S131: Obtain the output current of the regulation output sub - circuit.

[0074] Please continue to refer to Figure 6 , Figure 6 is the structural schematic diagram of the second embodiment of the charge modulation circuit of the present application.

[0075] It can be understood that the charge modulation method in this embodiment may specifically be that the second charge modulation circuit 40 adjusts the current of the second buck - conversion circuit 50 as shown in Figure 6 . Among them, the second buck - conversion circuit 50 includes a second upper - side switch sub - circuit 51, a second lower - side switch sub - circuit 52, and a second regulation output sub - circuit 53; the second upper - side switch sub - circuit 51 includes a first upper - side switch transistor Q H 1, the second lower - side switch sub - circuit 52 includes a first lower - side switch transistor Q L 1, the second regulation output sub - circuit 53 includes a first capacitor C1, a second capacitor C2, a first upper - side diode D H 1, a first lower - side diode D L 1, a first inductor L1, and an output capacitor Co, corresponding to a single - phase BUCK circuit.

[0076] Among them, the first end of the first capacitor C1 is coupled to the first end of the first upper - side switch transistor Q H 1 and is used to be coupled to the first end of the DC power supply DC. The second end of the first capacitor C1 is coupled to the first end of the second capacitor C2, the first end of the first upper - side diode Q H 1, and the second end of the first lower - side diode Q L 1. The second end of the second capacitor C2 is coupled to the first end of the first lower - side switch transistor Q L 1 and is used to be coupled to the second end of the DC power supply DC and grounded. The second end of the first upper - side switch transistor Q H 1 is coupled to the second end of the first upper - side diode D H 1 and the first end of the first inductor L1. The second end of the first inductor L1 is coupled to the first end of the output capacitor Co and is used to be coupled to the first end of the equivalent series diode Do in the load circuit 101. The second end of the first lower - side switch transistor Q L 1 is coupled to the first end of the first upper - side diode D H 1 and the second end of the output capacitor Co and is used to be coupled to the second end of the equivalent series diode Do in the load circuit 101.

[0077] In other embodiments, the load circuit 101 may specifically further include one or more of any reasonable circuit elements such as an equivalent resistor, an equivalent capacitor, an equivalent series diode, etc., and the present application does not limit this.

[0078] Among them, the second charge modulation circuit 40 specifically further includes a charge sampling and integrating circuit 41 and a current sampling and regulating circuit 42. The charge sampling and integrating circuit 41 further includes a first sampling circuit 411, a charge integrating circuit 412, and a charge feedback control circuit 413. The current sampling and regulating circuit 42 includes a second sampling circuit 421 and an error processing circuit 422. Among them, the first sampling circuit 411 is coupled to the first end of the first upper switching transistor Q H 1 and / or the first end of the first lower switching transistor Q L 1, and is coupled to the charge integrating circuit 412. The second sampling circuit 421 is coupled to the first end of the output capacitor Co and the error processing circuit 422. The charge integrating circuit 412 is coupled to the charge feedback control circuit 413. The charge feedback control circuit 413 is coupled to the error processing circuit 422, the third end of the first upper diode D H 1, and the third end of the first lower diode D L 1.

[0079] In some embodiments, the first upper switching transistor Q H 1 and the first lower switching transistor Q L 1 may specifically be one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a triode, a thin film transistor, a field effect transistor, or any other reasonable switching transistor, and the present application does not limit this.

[0080] Please continue to refer to Figure 7 , Figure 7 , which is a schematic structural diagram of the third embodiment of the first charge modulation circuit 20 of the present application.

[0081] In other embodiments, the second buck conversion circuit 50 may specifically further be a multi-phase BUCK circuit, that is, the second upper switching sub-circuit 51 may specifically further include a first upper switching transistor Q H 1, a second upper switching transistor Q H 2,..., an nth upper switching transistor Q H n (n is an integer greater than 1). The second lower switching sub-circuit 52 includes a first lower switching transistor Q L 1, a second lower switching transistor Q L 2,..., an nth lower switching transistor Q L n; the second regulated output sub-circuit 53 includes a first capacitor C1, a second capacitor C2, a first upper diode DH 1. The second upper diode D H 2. ..., the nth upper diode D H n, the first lower diode D L 1. The second lower diode D L 2. ..., the nth lower diode D L n, the first inductor L1, the second inductor L2, ..., the nth inductor Ln, and the output capacitor Co.

[0082] Wherein, the first end of the first capacitor C1 is coupled to the first end of the first upper switching transistor Q H 1, the first end of the second upper switching transistor Q H 2, ..., the first end of the nth upper switching transistor Q H n, and is used to be coupled to the first end of the DC power supply DC. The second end of the first capacitor C1 is coupled to the first end of the second capacitor C2, the first end of the first upper diode D H 1, the first end of the second upper diode D H 2, ..., the first end of the nth upper diode D H n, and the second end of the first lower diode D L 1, the second end of the second lower diode D L 2, ..., the second end of the nth lower diode D L n. The second end of the second capacitor C2 is coupled to the first end of the first lower switching transistor Q L 1, the first end of the second lower switching transistor Q L 2, ..., the first end of the nth lower switching transistor Q L n, and is used to be coupled to the second end of the DC power supply DC and grounded. The second end of the first upper switching transistor Q H 1, the second end of the second upper switching transistor Q H 2, ..., the second end of the nth upper switching transistor Q H n are respectively coupled to the second end of the first upper diode D H 1, the second end of the second upper diode D H 2, ..., the second end of the nth upper diode D H n, and the first end of the first inductor L1, the first end of the second inductor L2, ..., the first end of the nth inductor Ln. The second end of the first inductor L1 is coupled to the second end of the second inductor L2, ..., the second end of the nth inductor Ln and the first end of the output capacitor Co, and is used to be coupled to the first end of the equivalent series diode Do in the load circuit 101. The second end of the first lower switching transistor Q L 1, the second end of the second lower switching transistor Q L 2, ..., the second end of the nth lower switching transistor Q LThe second terminal of n is respectively coupled to the first terminal of the first upper diode D H 1, the first terminal of the second upper diode D H 2, ..., the first terminal of the nth upper diode D H n and the second terminal of the output capacitor Co, and is used to be coupled to the second terminal of the equivalent series diode Do in the load circuit 101.

[0083] Specifically, for the convenience of understanding, taking the second buck conversion circuit 50 as a single-phase BUCK circuit as an example, the second sampling circuit 421 acquires the output current Io output to the equivalent series diode Do.

[0084] S132: Subtract the target reference current from the output current to obtain a current error value.

[0085] The error processing circuit 422 receives the output current Io sent by the second sampling circuit 421, and sets a target reference current Iref, or receives the target reference current Iref sent by the host computer, so as to subtract the target reference current Iref from the output current Io to obtain a current error value.

[0086] It is worth noting that the host computer usually refers to a computer system with powerful computing power and data processing capabilities. It is responsible for the monitoring, instruction issuing, data acquisition, processing and analysis, and user interaction of the entire control system. As the "brain" of the system, the host computer can process complex algorithms, perform long-term data storage, and provide a graphical interface for users to operate.

[0087] The slave computer refers to a device or controller directly connected to hardware such as sensors and actuators in the control system. It is responsible for executing specific control instructions sent by the host computer, such as the output of switch signals, the adjustment of analog quantities, and the acquisition of data. The slave computer usually performs simple logical judgment and real-time control tasks.

[0088] S133: Generate a drive control signal using the charge error value and current error value between the charge integration amount and the target charge amount.

[0089] The first sampling circuit 411 samples and acquires the instantaneous conduction current value Iphase of the first upper diode Q H 1 and / or the first lower diode Q L 1.

[0090] The charge integration circuit 412 receives the instantaneous conduction current value Iphase sent by the first sampling circuit 411, and performs integration processing on the instantaneous conduction current value Iphase to obtain a charge integration amount Qphase, that is, Qphase = ∫Iphase dt.

[0091] The charge feedback control circuit 413 subtracts the target charge quantity from the charge integration quantity Qphase to obtain a charge error value, and receives the current error value sent by the error processing circuit 422, so as to generate a drive control signal by using the currently obtained charge error value and current error value.

[0092] Further, in one embodiment, the above S16 may specifically further include: sending the adjusted drive control signal to one of the first upper diode Q H 1 and the first lower diode Q L 1.

[0093] And when the second buck conversion circuit 50 is a multi-phase BUCK circuit, the charge feedback control circuit may specifically further send the adjusted drive control signal to one of the first upper diode Q H 1 and the first lower diode Q L 1, one of the second upper diode Q H 2 and the second lower diode Q L 2,... and one of the nth upper diode Q H n and the nth lower diode Q L n.

[0094] In some embodiments, the second buck conversion circuit 50 may specifically be a drive power supply for a laser pump source. In order to improve the energy conversion efficiency and output power density, the laser system generally adopts a multi-stage pump or distributed pump architecture, resulting in the supply voltage level of the pump source being increased from the traditional hundreds of volts to above kilovolts. Correspondingly, the supply voltage of the pump source will also fluctuate violently when the load current changes suddenly. This trend poses higher challenges to the withstand voltage ability, dynamic response speed characteristics and power density of the power supply topology.

[0095] Since the output voltage of the laser power supply, that is, the second buck conversion circuit 50, will change under different load currents, for a high-voltage laser pump source with a large load change range, in order to solve the problem that when the load current, that is, the output current Io jumps from heavy load to light load, the output voltage drops, resulting in a decrease in the duty cycle of the buck circuit and thus deviating from the optimal working range, affecting the power supply dynamic response speed and the quality of the laser pump pulse waveform.

[0096] Therefore, by turning off the upper diode or the lower diode and increasing the small duty cycle in the second load state to a moderate duty cycle in the first load state, which is a set multiple of the previous small duty cycle, the voltage stress of the switching tube can be reduced to half of the input voltage, greatly reducing the withstand voltage requirement, facilitating the expansion of the high-voltage application range. At the same time, when selecting devices, a low-voltage switching tube with a smaller parasitic capacitance and a lower internal resistance can be chosen, which is beneficial to accelerating the power supply response speed and further promoting the high-frequency development of the laser power supply. Moreover, it is beneficial to meet the laser pumping requirements of high-voltage input, high pulse repetition frequency, and large load variation range.

[0097] Please refer to Figure 8 , Figure 8 which is a schematic flow chart of the second embodiment of the charge modulation method of this application. The charge modulation method of this embodiment is Figure 1 a schematic flow chart of a refined embodiment of the charge modulation method in S61: Obtain the instantaneous value of the conduction current in the upper switching sub-circuit and / or the lower switching sub-circuit.

[0098] S62: Perform integral processing on the instantaneous value of the conduction current to obtain the charge integration quantity.

[0099] S63: Generate a drive control signal using the charge error value between the charge integration quantity and the target charge quantity.

[0100] Among them, S61, S62, and S63 are the same as Figure 1 S11, S12, and S13 in

[0101] S64: Obtain the target reference current sent by the host computer.

[0102] It should be noted that the host computer can be specifically understood as a system processor that monitors and controls the working state and application scenario of the load circuit to determine the current power supply requirement of the load circuit, such as the output power requirement of the load circuit, and then sets the current target reference current.

[0103] Specifically, the first charge modulation circuit 20 is used to communicate with the host computer to receive the target reference current sent by the host computer.

[0104] S65: Determine whether the target reference current is less than the first mode switching threshold.

[0105] It can be understood that the first charge modulation circuit 20 can specifically also determine whether the first buck conversion circuit 30 is in the first load state by detecting whether the target reference current is less than the first mode switching threshold.

[0106] Among them, if the target reference current is less than the first mode switching threshold, S66 is executed; if the target reference current is not less than the first mode switching threshold, S68 is executed.

[0107] S66: Adjust the duty cycle of the drive control signal to a previously set multiple.

[0108] S67: Send the adjusted drive control signal to one of the upper switch sub-circuit and the lower switch sub-circuit to trigger a change in its switching state.

[0109] S68: Send the first pulse width modulation signal and the second pulse width modulation signal to the upper switch sub-circuit and the lower switch sub-circuit respectively to trigger the upper switch sub-circuit and the lower switch sub-circuit to change their switching states respectively.

[0110] Among them, S66, S67, and S68 are the same as S15, S16, and S17 in Figure 1 . For details, please refer to S15, S16, and S17 and their related text descriptions, which will not be elaborated here.

[0111] Please refer to Figure 9 , Figure 9 which is a schematic flowchart of the third implementation manner of the charge modulation method of this application. The charge modulation method of this implementation manner is Figure 1 a schematic flowchart of a refined implementation manner of the charge modulation method in and specifically includes the following steps:

[0112] S71: Obtain the instantaneous value of the conduction current in the upper switch sub-circuit and / or the lower switch sub-circuit.

[0113] S72: Perform an integration process on the instantaneous value of the conduction current to obtain the charge integration amount.

[0114] S73: Generate a drive control signal by using the charge error value between the charge integration amount and the target charge amount. Figure 1 Among them, S71, S72, and S73 are the same as S11, S12, and S13 in

[0115] For details, please refer to S11, S12, and S13 and their related text descriptions, which will not be elaborated here.

[0116] It can be understood that the first buck conversion circuit 30 further includes a first regulated output sub-circuit 33, and the first regulated output sub-circuit 33 is coupled to the first upper switch sub-circuit 31 and the first lower switch sub-circuit 32.

[0117] The first charge modulation circuit 20 is further configured to sample and obtain the output current from the first regulated output sub-circuit 33.

[0118] S75: Integrate the output current to obtain the feedback charge integration amount.

[0119] Integrate the currently obtained output current to calculate the feedback charge integration amount.

[0120] S76: Determine whether the feedback charge integration amount is less than the second mode switching threshold.

[0121] It can be understood that the first charge modulation circuit 20 can specifically determine whether the first buck conversion circuit 30 is in the first load state by detecting whether the feedback charge integration amount is less than the second mode switching threshold.

[0122] Among them, if the feedback charge integration amount is less than the second mode switching threshold, then execute S77; if the feedback charge integration amount is not less than the second mode switching threshold, then execute S79.

[0123] S77: Adjust the duty cycle of the drive control signal to a previously set multiple.

[0124] S78: Send the adjusted drive control signal to one of the upper switch sub-circuit and the lower switch sub-circuit to trigger it to change the switch state.

[0125] S79: Send the first pulse width modulation signal and the second pulse width modulation signal to the upper switch sub-circuit and the lower switch sub-circuit respectively to trigger the upper switch sub-circuit and the lower switch sub-circuit to change the switch state respectively.

[0126] Among them, S77, S78, and S79 are the same as Figure 1 S15, S16, and S17 in. For specific details, please refer to S15, S16, and S17 and their related text descriptions, which will not be elaborated here.

[0127] Please refer to Figure 10 , Figure 10 is Figure 9 The flowchart of an embodiment of S75 in. In an embodiment, the charge modulation method of the present application further includes some more specific steps in addition to the above S71 - S79. Specifically, the above S75 may further include the following steps: S751: Obtain the rising edge and falling edge of the drive control signal.

[0128] Specifically, identify and detect the falling edge and rising edge of the drive control signal. For example, this can be achieved through any reasonable means such as a hardware circuit (such as an edge trigger), a software algorithm (for example, writing corresponding code in an embedded system), or a controller counter. The present application does not limit this.

[0129] S752: Integrate the output current in response to the rising edge to obtain the feedback charge integration amount.

[0130] When the rising edge of the drive control signal is detected, integrate the currently obtained output current to obtain the feedback charge integration amount.

[0131] S753: Reset the feedback charge integration amount in response to the falling edge.

[0132] When the falling edge of the drive control signal is detected, reset the feedback charge integration amount to zero to wait for the next rising edge to re-integrate the output current.

[0133] This application also provides an electronic device. Please refer to Figure 11 , Figure 11 which is a schematic structural diagram of an embodiment of the electronic device of this application. In this embodiment, the electronic device 80 includes a housing 81 and a third charge modulation circuit 82 connected to the housing 81.

[0134] It should be noted that the third charge modulation circuit 82 described in this embodiment is the first charge modulation circuit 20 or the second charge modulation circuit 40 described in any one of the above embodiments. For details, please refer to Figures 1 - 10 and the relevant text content, which will not be elaborated here.

[0135] The beneficial effects of this application are as follows: Different from the prior art, the charge modulation method provided by this application obtains the instantaneous value of the conduction current in the upper switch sub-circuit and / or the lower switch sub-circuit, integrates the instantaneous value of the conduction current to obtain the charge integration amount, and generates a drive control signal using the charge error value between the charge integration amount and the target charge amount. When it is detected that the buck conversion circuit is in the first load state, the duty cycle of the drive control signal is adjusted to a previously set multiple, and the adjusted drive control signal is sent to one of the upper switch sub-circuit and the lower switch sub-circuit to trigger a change in its switch state. Therefore, when the load changes greatly, it is possible to reasonably adjust the duty cycle of the drive control signal and quickly block the wave of some switch sub-circuits to quickly adjust the output current and output voltage of the buck conversion circuit to an appropriate range to adapt to the load's demand for a wide range of output voltages, effectively suppress the ripple that may occur during load mutation, and have good dynamic response characteristics, effectively meeting the demand for the power supply transient recovery ability. There is no need to configure high-voltage devices and complex compensation networks, and the hardware cost is also low.

[0136] The above are only the embodiments of this application, and do not limit the patent scope of this application. Any equivalent structure or equivalent process transformation made using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be included in the patent protection scope of this application by the same token.

Claims

1. A charge modulation method applied to a buck conversion circuit, the buck conversion circuit comprising an upper switch sub-circuit and a lower switch sub-circuit that are coupled to each other, characterized in that, The charge modulation method includes: Obtaining the instantaneous value of the conduction current in the upper switch sub - circuit and / or the lower switch sub - circuit; Performing integral processing on the instantaneous value of the conduction current to obtain a charge integral; Generating a drive control signal using the charge error value between the charge integral and the target charge amount; Detecting whether the buck - conversion circuit is in a first load state; wherein, the load rate of the first load state is not greater than a set ratio threshold; If the buck - conversion circuit is in the first load state, adjusting the duty cycle of the drive control signal to a previously set multiple; wherein, the set multiple is greater than 1; Sending the adjusted drive control signal to one of the upper switch sub - circuit and the lower switch sub - circuit to trigger a change in its switch state.

2. The charge modulation method according to claim 1, wherein The step of performing integral processing on the instantaneous value of the conduction current to obtain a charge integral includes: Obtaining the rising edge of the drive control signal; Responsively performing integral processing on the instantaneous value of the conduction current in response to the rising edge to obtain the charge integral; Resetting the charge integral after a preset time delay; wherein, the preset time delay is greater than or equal to the current high - level duration of the drive control signal and less than the current switching period of the drive control signal.

3. The charge modulation method according to claim 1, characterized in that The step of performing integral processing on the instantaneous value of the conduction current to obtain a charge integral includes: Obtaining the rising edge and the falling edge of the drive control signal; Responsively performing integral processing on the instantaneous value of the conduction current in response to the rising edge to obtain the charge integral; Resetting the charge integral in response to the falling edge.

4. The charge modulation method according to claim 1, wherein The buck - conversion circuit further includes an adjustment output sub - circuit, the adjustment output sub - circuit is coupled to the upper switch sub - circuit and the lower switch sub - circuit, and the step of generating a drive control signal using the charge error value between the charge integral and the target charge amount includes: Obtaining the output current of the adjustment output sub - circuit; Subtracting the target reference current from the output current to obtain a current error value; Generating the drive control signal using the charge error value between the charge integral and the target charge amount and the current error value.

5. The charge modulation method according to claim 1, wherein The step of detecting whether the buck - conversion circuit is in a first load state includes: Obtaining the target reference current sent by the host computer; Judging whether the target reference current is less than a first mode - switching threshold; The step of, if the buck - conversion circuit is in the first load state, adjusting the duty cycle of the drive control signal to a previously set multiple includes: If the target reference current is less than the first mode - switching threshold, adjusting the duty cycle of the drive control signal to a previously set multiple.

6. The charge modulation method according to claim 1, characterized in that, The buck - conversion circuit further includes an adjustment output sub - circuit, the adjustment output sub - circuit is coupled to the upper switch sub - circuit and the lower switch sub - circuit, and the step of detecting whether the buck - conversion circuit is in a first load state includes: Obtaining the output current of the adjustment output sub - circuit; Performing integral processing on the output current to obtain a feedback charge integral; Judging whether the feedback charge integral is less than a second mode - switching threshold; The step of adjusting the duty cycle of the drive control signal to a previously set multiple if the buck conversion circuit is in the first load state includes: If the feedback charge integration amount is less than the second mode switching threshold, adjust the duty cycle of the drive control signal to a previously set multiple.

7. The charge modulation method according to claim 6, wherein The step of performing an integration process on the output current to obtain a feedback charge integration amount includes: Obtain the rising edge and falling edge of the drive control signal; In response to the rising edge, perform an integration process on the output current to obtain the feedback charge integration amount; In response to the falling edge, reset the feedback charge integration amount.

8. The charge modulation method according to any one of claims 1 to 7, characterized in that, The drive control signal includes a first pulse width modulation signal and a second pulse width modulation signal, and the charge modulation method further includes: If the buck conversion circuit is in the second load state, send the first pulse width modulation signal and the second pulse width modulation signal to the upper switch sub-circuit and the lower switch sub-circuit respectively to trigger the upper switch sub-circuit and the lower switch sub-circuit to change their switch states; wherein, the load rate in the second load state is greater than the set ratio threshold.

9. A charge modulation circuit, characterized in that, The charge modulation circuit is coupled to the buck conversion circuit; Wherein, the charge modulation circuit performs charge modulation on the buck conversion circuit by using the charge modulation method according to any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes a housing and a charge modulation circuit connected to the housing; Wherein, the charge modulation circuit is the charge modulation circuit according to claim 9.

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