Bit flipping decoding method, electronic equipment and computer readable storage medium
By using preset threshold values in bit flip decoding, the bit flip reliability is reduced, the decoding performance is improved, and the bit flip error problem is solved when the code length is long.
Patent Information
- Application Number
- CN202410097119.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-23
- Publication Date
- 2025-07-25
AI Technical Summary
When the existing bit flip decoding algorithms are long, they are prone to excessive bit error flips, affecting the decoding performance.
During the iteration of bit flip decoding, the reliability of the bits is judged by presetting the first and second threshold values, and only the bits whose historical reliability values meet the conditions are flipped to reduce the number of false flipped bits.
The number of false flip bits in bit flip decoding is reduced, and the accuracy and efficiency of decoding is improved.
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Figure CN120378043A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of coding, and particularly to a bit flipping decoding method, an electronic device, and a computer-readable storage medium. Background Art
[0002] The purpose of a communication system is to efficiently and reliably transmit information from a source to a destination. However, when a signal is transmitted through a channel, it is interfered by various random noises, resulting in bit errors in the transmitted information symbols and a decrease in the reliability of communication. Therefore, a key issue in the design of a digital communication system is how to reduce information transmission errors without reducing information transmission efficiency under the interference of random channel noises, that is, to transmit information effectively and reliably. Therefore, channel coding technology, as an effective method to improve the reliability of a communication system, plays an increasingly important role in data transmission of a communication system. The essence of channel coding technology is to add a certain amount of redundancy to the original information symbols to resist the influence of noise in the channel on the information and improve the anti-interference ability of the communication system.
[0003] After coding is completed, decoding is required to restore the original information symbols. Decoding methods can generally be divided into two types: hard decision algorithms and soft decision algorithms. Compared with each other, the soft decision has better performance, but its implementation is more complex; the hard decision operation has worse performance, but the operation is simple and easy to be implemented in hardware. Common hard decision algorithms include the Gradient Descent Bit Flipping (GDBF) algorithm. The currently used GDBF algorithm generally has the maximum value of the inversion function values of all bit positions in each iteration, and then flips the bit position corresponding to the maximum value, and uses the flipped result as the output of the decoder or the input of the next iteration. Summary of the Invention
[0004] The main purpose of this application is to provide a bit flipping decoding method, an electronic device, and a computer-readable storage medium, which can improve the decoding performance of the bit flipping decoding algorithm.
[0005] To solve the above technical problems, the first technical solution adopted in this application is: to provide a bit flipping decoding method. The method includes, in the flipping iteration process of bit flipping decoding, when in the current flipping, obtaining each first reliability value of all bit positions; in response to the maximum first reliability value being less than a preset first threshold, determining all bit positions corresponding to the maximum first reliability value as target bit positions; obtaining that each second reliability value in the historical flipping process of each target bit position is greater than a preset second threshold, and flipping the target bit positions corresponding to the second reliability values in the current flipping.
[0006] To solve the above technical problems, the second technical solution adopted in this application is as follows: obtain an initial decoding matrix; determine whether the result matrix obtained by multiplying the initial decoding matrix by the parity-check matrix is an all-zero matrix; if the result matrix is not an all-zero matrix, perform a flipping iteration process including at least one flip on the initial decoding until the result matrix obtained by multiplying the obtained target decoding matrix by the parity-check matrix is an all-zero matrix; obtain the final decoding based on the obtained target decoding matrix; wherein, during the flipping iteration process, the bit-flipping decoding method described in the first technical solution is executed.
[0007] To solve the above technical problems, the third technical solution adopted in this application is as follows: provide an electronic device. The electronic device includes a memory and a processor, and the memory is used to store program data, and the program data can be executed by the processor to implement the method described in the first technical solution.
[0008] To solve the above technical problems, the fourth technical solution adopted in this application is as follows: provide a computer-readable storage medium. The computer-readable storage medium stores program data, which can be executed by the processor to implement the method described in the first technical solution.
[0009] The beneficial effects of this application are as follows: This application uses a preset first threshold value to first determine whether the current flip belongs to the case where the maximum reliability value is small. When it is determined that the maximum reliability value of the current flip is small, obtain the reliability values that have appeared in the historical secondary flip times and the preset second threshold value to perform a secondary judgment to determine the bit positions that ultimately need to be flipped. When the maximum reliability value is small during the current flip process, the bit corresponding to the maximum reliability value is not directly flipped, but the reliability values in the historical secondary flip process are obtained for a secondary judgment to reduce the number of bits that need to be flipped, thereby reducing the number of erroneously flipped bit positions in the current bit flip. Correspondingly, the number of erroneously flipped bit positions input in the next iteration process is also reduced, thereby reducing the number of flip iterations required to obtain the correct decoding result and improving the performance of bit-flipping decoding. Description of the Drawings
[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0011] Figure 1 is a schematic flowchart of a conventional bit-flipping algorithm;
[0012] Figure 2It is a schematic flowchart of the first embodiment of the bit flipping decoding method of the present application;
[0013] Figure 3 It is a schematic flowchart of the second embodiment of the bit flipping decoding method of the present application;
[0014] Figure 4 It is a schematic flowchart of the third embodiment of the bit flipping decoding method of the present application;
[0015] Figure 5 It is a schematic flowchart of the fourth embodiment of the bit flipping decoding method of the present application;
[0016] Figure 6 It is a schematic flowchart of a specific embodiment of the bit flipping decoding of the present application;
[0017] Figure 7 It is a schematic structural diagram of an embodiment of an electronic device of the present application;
[0018] Figure 8 It is a schematic structural diagram of the first embodiment of the computer-readable storage medium of the present application. Detailed implementation manners
[0019] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0020] The terms "first", "second", etc. in the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.
[0021] Referring to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.
[0022] Before introducing the technical solutions of the present application, a brief description of the related technologies will be given first.
[0023] Reference Figure 1 , Figure 1 is a schematic diagram of a conventional bit - flipping algorithm process.
[0024] After receiving the symbol sequence y, perform a hard - decision decoding on it to obtain the decoding result Z(0). Then set the iteration number x = 0 and the maximum iteration number xmax. After obtaining the decoding result Z(0), check it to determine whether the result matrix S = Z(x)H T is an all - zero matrix, where H T is the parity - check matrix. If so, output Z(0) as the final decoding result. If the result matrix S is not an all - zero matrix, perform a flipping iteration on the decoding result Z(0). First, calculate the inversion function value q k ( x ), then find the maximum inversion function value max(q k ( x )) and flip the corresponding bit to obtain the flipped decoding result Z(x + 1), x = x + 1, that is, obtain Z(1). After obtaining Z(1), continue to judge the result matrix. The process is the same as the first judgment. If the result matrix is an all - zero matrix, output Z(1) as the final decoding result. If the result matrix is not an all - zero matrix, use Z(1) as the input for the next flip. Continue until the result matrix is an all - zero matrix to obtain the final decoding result or reach the maximum iteration number and report a decoding error.
[0025] The above - mentioned conventional bit - flipping decoding algorithm finds the bit corresponding to the maximum inversion function value in each iteration for flipping, and uses the flipped result as the decoding output or the input for the next flip.
[0026] This application has found through research that when the maximum value of the obtained inversion function is small, especially when the code length is long, there will be many bits whose inversion function values are the maximum. In this case, all the bits corresponding to the maximum value will be flipped. Since the number of flipped bits is too large, it is very easy to cause incorrect flipping of bits, and these incorrectly flipped bits will enter the next iteration and affect the subsequent decoding process.
[0027] Therefore, this application proposes the bit - flipping decoding method described in the following embodiments to improve the decoding performance of the bit - flipping decoding algorithm.
[0028] Reference Figure 2 , Figure 2 is a schematic diagram of the process of the first embodiment of the bit - flipping decoding method of this application. It includes the following steps:
[0029] S11: During the flipping iteration of bit - flipping decoding, when at the current flipping, obtain each first reliability value of all bit positions.
[0030] S12: In response to the largest first reliability value being less than a preset first threshold value, determine all bit positions corresponding to the largest first reliability value as target bit positions.
[0031] S13: Obtain each second reliability value during the historical flipping process of each target bit position.
[0032] S14: In response to the second reliability value being greater than a preset second threshold value, flip the target bit position corresponding to the second reliability value during the current flipping.
[0033] The first reliability value and the second reliability value are the result values for a single bit position obtained by using an inversion function during the bit - flipping decoding process. Before each bit position is flipped once, a reliability value is calculated through the inversion function.
[0034] During the process of performing the flipping iteration of the bit - flipping decoding algorithm, when at the current flipping process, before flipping, first obtain each first reliability value of all bit positions. Compare the largest first reliability value with the preset first threshold value. When the largest first reliability value is less than the preset first threshold value, do not flip all bit positions corresponding to the largest first reliability value, but take them as target bit positions, and obtain each second reliability value of each target bit position during a certain historical flipping process. Then compare each second reliability value with the preset second threshold value, and take the target bit positions corresponding to the second reliability values greater than the preset second threshold value as the final flipping objects.
[0035] The historical flipping process can be any flipping process before the current flipping process. For example, the reliability value calculated during the first flipping process can be used as the second reliability value required during subsequent flipping processes, or the reliability value calculated during the second flipping process can be used as the second reliability value required during subsequent flipping processes, and so on.
[0036] The magnitudes of the preset first threshold value and the preset second threshold value are not limited, and can be specifically changed according to the actual situation. The preset first threshold value can be equal to the preset second threshold value or not equal.
[0037] In this embodiment, by using a preset first threshold value, it is first determined whether the current flip belongs to the case where the maximum reliability value is small. When it is determined that the maximum reliability value of the current flip is small, the reliability values that have appeared in the historical secondary flip times and the preset second threshold value are obtained to perform a secondary determination to determine the bit positions that finally need to be flipped. When the maximum reliability value is small during the current flip process, the bit positions corresponding to the maximum reliability value are not directly flipped. Instead, the reliability values during the historical secondary flip process are obtained for secondary determination to reduce the number of bit positions that need to be flipped, thereby reducing the number of erroneously flipped bit positions in the current bit flip. Correspondingly, the number of erroneously flipped bit positions input in the next iteration process is also reduced, thereby reducing the number of flip iterations required to obtain the correct decoding result and improving the performance of bit flip decoding.
[0038] In one embodiment, during the flip iteration process of bit flip decoding, when at the current flip, after obtaining the first reliability value of each bit position, when it is determined that the largest first reliability value is greater than or equal to the preset first threshold value, the bit flip is performed according to the normal process. That is, in response to the largest first reliability value being greater than or equal to the preset first threshold value, all bit positions corresponding to the largest first reliability value are flipped.
[0039] In one embodiment, after obtaining each second reliability value in the historical secondary flips of the target bit positions, in response to all the second reliability values being less than or equal to the preset second threshold value and the number of target bit positions being at least two, part of the target bit positions are flipped.
[0040] When there is a second reliability value greater than the preset second threshold value, there are bit positions to be flipped. When all the second reliability values are less than or equal to the preset second threshold value, there are no bit positions that need to be flipped at this time. In order to ensure the normal operation of the decoding process, part of the target bit positions need to be flipped. Because when the result matrix is not an all-zero matrix, the obtained definite decoding result is incorrect. If the bit flip is not performed, the result matrix remains not an all-zero matrix, and the correct decoding result cannot be obtained through repeated cycles. Therefore, at least one bit position must be flipped in each flip process. In this application, when the number of target bit positions is at least two and all the second reliability values are less than or equal to the preset second threshold value, part of the target bit positions are flipped. When the number of target bit positions is one, the target bit position can be directly flipped.
[0041] When the number of target bit positions is at least two, the step of flipping part of the target bit positions can be implemented by the method described in the following embodiments.
[0042] In one embodiment, flipping part of the target bit positions may include randomly flipping part of the target bit positions. Using a random algorithm, part of the target bit positions are selected and their bit flips are performed.
[0043] The following is another embodiment for realizing the flipping of some target bit positions. Refer to Figure 3 , Figure 3 which is a schematic flowchart of the second embodiment of the bit flipping decoding method of the present application. It includes the following steps:
[0044] S21: Obtain a preset probability, where the preset probability is greater than zero and less than one.
[0045] S22: Flip all the target bit positions according to the preset probability.
[0046] S23: In response to the situation that no target bit position is flipped, randomly flip some of the target bit positions.
[0047] Set a preset probability in advance for flipping some of the target bit positions. The preset probability is greater than zero and less than one. Use the preset probability to judge whether to flip each target bit position to obtain the target bit positions that finally need to be flipped.
[0048] If it is judged that there is no target bit position to be flipped at the end, randomly flip some of the target bit positions.
[0049] The following is yet another embodiment for realizing the flipping of some target bit positions. Refer to Figure 4 , Figure 4 which is a schematic flowchart of the third embodiment of the bit flipping decoding method of the present application. It includes the following steps:
[0050] S31: Obtain a preset ratio, where the preset ratio is greater than zero and less than one.
[0051] S32: Flip some of the target bit positions from all the target bit positions according to the preset ratio.
[0052] Set a preset ratio in advance for flipping some of the target bit positions. Use the preset ratio to select the bit positions that need to be flipped from all the target bit positions. Multiply the number of all bit positions by the preset ratio to obtain the number of target bit positions that need to be flipped, and then select the corresponding number of target bit positions from all the target bit positions.
[0053] Refer to Figure 5 , Figure 5 which is a schematic flowchart of the fourth embodiment of the bit flipping decoding method of the present application. It includes the following steps:
[0054] S41: Obtain an initial decoding matrix.
[0055] S42: Judge whether the result matrix obtained by multiplying the initial decoding matrix and the check matrix is an all-zero matrix.
[0056] S43: If the result matrix is not an all-zero matrix, perform a flipping iteration process including at least one flip on the initial decoding until the result matrix obtained by multiplying the target decoding matrix with the parity-check matrix is an all-zero matrix.
[0057] S44: Obtain the final decoding based on the obtained target decoding matrix.
[0058] After the original code elements are received through the channel, a coded code element sequence can be obtained. First, perform a hard decision decoding on the code element sequence and convert it into a matrix form to obtain an initial decoding matrix.
[0059] By determining whether the result matrix obtained by multiplying the initial decoding matrix and the parity-check matrix is an all-zero matrix, it is determined whether the initial decoding matrix is the final correct decoding matrix. If it is not an all-zero matrix, perform a bit flipping process, and perform at least one bit flip on the code elements in the initial decoding matrix until the target decoding matrix can be multiplied by the parity-check matrix to obtain an all-zero matrix. Then, the target decoding matrix is the correct decoding matrix, and the correct decoded code element sequence can be obtained according to the target decoding matrix. Among them, in the process of flipping iteration, perform the bit flipping decoding method provided by any one of the above bit flipping decoding methods of the present application and possible combinations.
[0060] In an embodiment, when the result matrix is not an all-zero matrix, during the flipping iteration process including at least one flip on the initial decoding, in response to the number of flipping iterations being greater than the preset maximum number of iterations, abort the flipping iteration process and perform a decoding error prompt. In the process of bit flipping decoding, a maximum number of iterations can be set in advance for the decoding process. When the number of flipping iterations exceeds the maximum number of iterations, it means that the correct decoding cannot be obtained in time with the current process, so the flipping iteration process is aborted and the user is prompted.
[0061] The following gives specific embodiments to illustrate the process of the bit flipping decoding method of the present application in more detail. Refer to Figure 6 , Figure 6 which is a schematic flow chart of a specific embodiment of the bit flipping decoding of the present application.
[0062] First, obtain the coded code element sequence y via the channel, then perform a hard decision decoding on it and convert it into a matrix form to obtain the initial decoding matrix A(0). Then, set the number of iterations x = 0 and the maximum number of iterations xmax. After obtaining the initial decoding matrix A(0), perform a check on it to determine whether the result matrix S = A(x)H T is an all-zero matrix. If so, output A(0) as the final decoding result. If the result matrix S is not an all-zero matrix, perform a flipping iteration on the initial decoding matrix A(0). First, calculate the inversion function value q of each bit k (x ) and then find the maximum value of the inverse function max(q k ( x )) and flip the corresponding bit to obtain the flipped decoding matrix A(x + 1), where x = x + 1, that is, obtain A(1). After obtaining A(1), continue to judge the result matrix. The process is the same as the first judgment. If the result matrix is an all-zero matrix, Z(1) is output as the final decoding result. If the result matrix is not an all-zero matrix, Z(1) is used as the input for the next flip. This continues until the result matrix is an all-zero matrix to obtain the final decoding result or the maximum number of iterations is reached and a decoding error is reported.
[0063] During the bit flipping process, first obtain the first reliability values of all bits in the decoding matrix A, and determine the maximum first reliability value and the target bit corresponding to the maximum first reliability value. Then compare the maximum first reliability value with a preset first threshold. If the maximum first reliability value is greater than the preset first threshold, flip all the target bits corresponding to the maximum first reliability value. If the maximum first reliability value is less than or equal to the preset first threshold, obtain the second reliability value of the target bit during the previous flip process, and compare the second reliability value with a preset second threshold. If there is a second reliability value greater than the preset second threshold, flip the target bit corresponding to the second reliability value. If there is no second reliability value greater than the preset second threshold, perform a partial flip on the target bit, which can be a random partial flip or a partial flip according to a preset probability and a preset ratio.
[0064] As Figure 7 shown, Figure 7 is a schematic structural diagram of an embodiment of the electronic device of the present application.
[0065] The electronic device includes a processor 110 and a memory 120.
[0066] The processor 110 controls the operation of the electronic device. The processor 110 can also be referred to as a CPU (Central Processing Unit, central processing unit). The processor 110 may be an integrated circuit chip with the ability to process signal sequences. The processor 110 can also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
[0067] The memory 120 stores the instructions and program data required for the operation of the processor 110.
[0068] The processor 110 is configured to execute instructions to implement the method provided by any one of the foregoing bit - flipping decoding methods of the present application and possible combinations.
[0069] As Figure 8 shown, Figure 8 It is a schematic structural diagram of the first embodiment of the computer - readable storage medium of the present application.
[0070] One embodiment of the readable storage medium of the present application includes a memory 210, and the memory 210 stores program data. When the program data is executed, it implements the method provided by any one of the bit - flipping decoding methods of the present application and possible combinations.
[0071] The memory 210 may include media such as a USB flash drive, a mobile hard disk, a read - only memory (ROM), a random - access memory (RAM), a magnetic disk, or an optical disc that can store program instructions, or it may also be a server storing the program instructions. The server can send the stored program instructions to other devices for running, or it can also run the stored program instructions by itself.
[0072] In summary, the present application uses a preset first threshold value to first determine whether the current flip belongs to the case where the maximum reliability value is small. When it is determined that the maximum reliability value of the current flip is small, the reliability values that have appeared in the historical secondary flip times and a preset second threshold value are obtained to perform a secondary judgment to determine the bit positions that ultimately need to be flipped. When the maximum reliability value is small during the current flip process, the bit corresponding to the maximum reliability value is not directly flipped. Instead, the reliability values in the historical secondary flip process are obtained for secondary judgment to reduce the number of bits that need to be flipped, thereby reducing the number of erroneously flipped bit positions in the current bit - flipping. Correspondingly, the number of erroneously flipped bit positions input in the next iteration process is also reduced, thereby reducing the number of flip iterations required to obtain the correct decoding result and improving the performance of bit - flipping decoding.
[0073] In several embodiments provided by the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
[0074] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0075] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
[0076] If the integrated unit in the above-mentioned other embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.
[0077] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be similarly included in the patent protection scope of the present application.
Claims
1. A bit - flipping decoding method, characterized in that, The method includes: During the flipping iteration of bit - flipping decoding, when at the current flipping, obtain each first reliability value of all bit positions; In response to the largest of the first reliability values being less than a preset first threshold value, determine all bit positions corresponding to the largest of the first reliability values as target bit positions; Obtain each second reliability value during the historical flipping process of each of the target bit positions; In response to the second reliability value being greater than a preset second threshold value, flip the target bit positions corresponding to the second reliability value during the current flipping.
2. The method according to claim 1, wherein After obtaining each second reliability value during the historical flipping of the target bit positions, it includes: In response to all of the second reliability values being less than or equal to the preset second threshold value and the number of the target bit positions being at least two, flip some of the target bit positions.
3. The method according to claim 2, characterized in that, The flipping some of the target bit positions includes: Obtain a preset probability, where the preset probability is greater than zero and less than one; Flip all of the target bit positions according to the preset probability; In response to no target bit position being flipped, randomly flip some of the target bit positions.
4. The method according to claim 2, wherein The flipping some of the target bit positions includes: Obtain a preset ratio, where the preset ratio is greater than zero and less than one; Flip some of the target bit positions from all of the target bit positions according to the preset ratio.
5. The method according to claim 2, wherein The flipping some of the target bit positions includes: Randomly flip some of the target bit positions.
6. The method according to claim 1, wherein After obtaining each first reliability value of all bit positions during the flipping iteration of bit - flipping decoding when at the current flipping, it includes: In response to the largest of the first reliability values being greater than or equal to the preset first threshold value, flip all bit positions corresponding to the largest of the first reliability values.
7. A bit - flipping decoding method, characterized in that, The method includes: Obtain an initial decoding matrix; Judge whether the result matrix obtained by multiplying the initial decoding matrix and the parity - check matrix is an all - zero matrix; If the result matrix is not an all - zero matrix, perform a flipping iteration process including at least one flipping on the initial decoding until the result matrix obtained by multiplying the resulting target decoding matrix and the parity - check matrix is an all - zero matrix; Obtain the final decoding based on the resulting target decoding matrix; Wherein, during the flipping iteration process, execute the bit - flipping decoding method according to any one of claims 1 - 6.
8. The method according to claim 7, wherein The step of if the result matrix is not an all - zero matrix, perform a flipping iteration process including at least one flipping on the initial decoding until the result matrix obtained by multiplying the resulting target decoding matrix and the parity - check matrix is an all - zero matrix includes: During the process of performing the flipping iteration, in response to the number of flipping iterations being greater than a preset maximum number of iterations, abort the flipping iteration process and give a decoding error prompt.
9. An electronic device, characterized in that, It includes a memory and a processor, the memory is used to store program data, and the program data can be executed by the processor to implement the method according to any one of claims 1 - 8.
10. A computer-readable storage medium, characterized in that, Store program data that can be executed by a processor to implement the method according to any one of claims 1 - 8.