Decoding method and device

Abstract

The invention provides a decoding method and device, relates to the technical field of media, and can quickly and efficiently determine whether a knowledge image needs to be displayed or not. The method comprises the steps that a code stream is analyzed, a display knowledge coding image and display indication information are obtained, and the display indication information is used for indicating whether a display knowledge image obtained after the display knowledge coding image is decoded is displayed or not; decoding the display knowledge coding image to obtain a display knowledge image; and determining whether to display the display knowledge image according to the display indication information.

Description

[0001] This application claims the priority of a Chinese patent application with an application number of 202410103121.2 and an application title of "A Decoding Method and Device", which was filed with the National Intellectual Property Administration on January 24, 2024. The entire content of this application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of media technology, and in particular, to a decoding method and device. Background Art

[0003] During the video / image encoding and decoding process, after obtaining the bitstream and decoding to obtain the display knowledge image, the decoding end cannot directly distinguish whether the current display knowledge image needs to be displayed.

[0004] Currently, after the decoding end decodes the display knowledge image, it needs to continue decoding the next image and determine whether to display (or output) the display knowledge image by judging whether the display order of the display knowledge image and the next image is continuous. If the display order is not continuous, the display knowledge image does not need to be displayed; if the display order is continuous, the display knowledge image needs to be displayed.

[0005] The above method is time-consuming and inefficient when judging the display knowledge image as it needs to decode the next image. Summary of the Invention

[0006] This application provides a decoding method and device that can quickly and efficiently determine whether a display knowledge image needs to be displayed.

[0007] This application adopts the following technical solutions:

[0008] In a first aspect, this application provides a decoding method, including: parsing a bitstream to obtain a display knowledge encoded image and display indication information, where the display indication information is used to indicate whether to display the display knowledge image after decoding the display knowledge encoded image; decoding the display knowledge encoded image to obtain a display knowledge image; and determining whether to display the display knowledge image according to the display indication information.

[0009] For the decoding method provided by this application, since the display indication information indicating whether the display knowledge image needs to be displayed can be parsed from the bitstream, it is not necessary to determine whether the display knowledge image is displayed after decoding the next image. The decoding method provided by this application can quickly and efficiently determine whether the display knowledge image needs to be displayed.

[0010] In a possible implementation, the supplementary enhancement information in the bitstream includes display indication information. Specifically, the display indication information is carried in the payload where nal_unit_type is 6 (the NAL unit with nal_unit_type of 6 contains supplementary enhancement information) and PayloadType is equal to 26.

[0011] In a possible implementation, the authentication flag of the NAL unit containing the display indication information is a first value, and the first value is used to indicate that the NAL unit containing the display indication information is not authenticated.

[0012] In a possible implementation, the first value is specifically used to indicate to the decoding end that the NAL unit containing the display indication information is not authenticated. In this way, the decoding end does not need to authenticate the NAL unit containing the display indication information.

[0013] In a possible implementation, the encryption flag of the NAL unit containing the display indication information is a second value, and the second value is used to indicate that the NAL unit containing the display indication information is not encrypted.

[0014] In a possible implementation, the second value is specifically used to indicate to the decoding end that the encoding end has not encrypted the NAL unit containing the display indication information. In this way, the decoding end does not need to decrypt the NAL unit containing the display indication information.

[0015] In a possible implementation, the NAL unit containing the display indication information is carried in the bitstream of the first layer of the display knowledge image. When the nal_unit_type of a NAL unit is 6 and it contains a payload with PayloadType equal to 26, layer_id should be 0 (that is, the Layer_id corresponding to the NAL unit where the display indication information is located is 0).

[0016] In a second aspect, the present application provides a decoding device, which includes various modules for implementing the method described in the first aspect and any of its possible implementation manners. The decoding device has the function of implementing the behaviors in the method examples of any one of the above-mentioned first aspect and its possible implementation manners. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0017] In a third aspect, the present application provides a decoding device, including at least one processor and a memory. The at least one processor executes the program or instructions stored in the memory so that the decoding device implements the method described in any one of the above-mentioned first aspect or any of its possible implementation manners.

[0018] Fourthly, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, where the computer program includes a method for implementing the method described in the first aspect or any possible implementation manner thereof above.

[0019] Fifthly, an embodiment of the present application further provides a computer program product containing instructions, which, when running on a computer, enables the computer to implement the method described in the first aspect or any possible implementation manner thereof above.

[0020] Sixthly, an embodiment of the present application further provides a chip, including: an input interface, an output interface, and at least one processor. Optionally, the chip further includes a memory. The at least one processor is configured to execute the code in the memory, and when the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation manner thereof above.

[0021] Optionally, the above chip may also be an integrated circuit.

[0022] The decoding device, computer storage medium, computer program product, and chip provided by the present application are all used to execute the decoding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the decoding method provided above, and will not be elaborated here. Description of the Drawings

[0023] Figure 1a It is an exemplary block diagram of a decoding system provided by an embodiment of the present application;

[0024] Figure 1b It is an exemplary block diagram of a video decoding system provided by an embodiment of the present application;

[0025] Figure 2 It is an exemplary block diagram of a video encoder provided by an embodiment of the present application;

[0026] Figure 3 It is an exemplary block diagram of a video decoder provided by an embodiment of the present application;

[0027] Figure 4 It is an exemplary schematic diagram of a candidate image block provided by an embodiment of the present application;

[0028] Figure 5 It is an exemplary block diagram of a video decoding device provided by an embodiment of the present application;

[0029] Figure 6 It is an exemplary block diagram of a device provided by an embodiment of the present application;

[0030] Figure 7 It is a schematic flowchart of a decoding method provided by an embodiment of the present application;

[0031] Figure 8 Schematic diagram of a decoding device provided by an embodiment of the present application;

[0032] Figure 9 Schematic structural diagram of a chip provided by an embodiment of the present application;

[0033] Figure 10 Schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0034] Figure 11 Schematic structural diagram of a decoding device provided by an embodiment of the present application. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the embodiments of the present application.

[0036] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0037] The terms "first" and "second" in the description and drawings of the embodiments of the present application are used to distinguish different objects or different processes for the same object, rather than to describe a specific order of the objects.

[0038] In addition, the terms "including" and "having" and any variations thereof mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include other steps or units not listed, or may optionally further include other steps or units inherent to these processes, methods, products, or devices.

[0039] It should be noted that in the description of the embodiments of the present application, words such as "exemplarily" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplarily" or "for example" is intended to present relevant concepts in a specific manner.

[0040] Data encoding and decoding includes two parts: data encoding and data decoding. Data encoding is performed on the source side (or commonly referred to as the encoder side), and typically includes processing (e.g., compressing) the original data to reduce the amount of data required to represent the original data (thereby enabling more efficient storage and / or transmission). Data decoding is performed on the destination side (or commonly referred to as the decoder side), and typically includes performing inverse processing relative to the encoder side to reconstruct the original data. The "encoding and decoding" of data involved in the embodiments of this application should be understood as "encoding" or "decoding" of data. The encoding part and the decoding part are also collectively referred to as encoding and decoding (encoding and decoding, CODEC).

[0041] In the case of lossless data encoding, the original data can be reconstructed, that is, the reconstructed original data has the same quality as the original data (assuming no transmission loss or other data loss during storage or transmission). In the case of lossy data encoding, further compression is performed through quantization, etc., to reduce the amount of data required to represent the original data, and the decoder side cannot fully reconstruct the original data, that is, the quality of the reconstructed original data is lower or worse than the quality of the original data.

[0042] The embodiments of this application can be applied to video data and other data with compression / decompression requirements, etc. The following takes the encoding of video data (abbreviated as video encoding) as an example to illustrate the embodiments of this application. Other types of data (such as image data, audio data, integer data, and other data with compression / decompression requirements) can refer to the following description, and the embodiments of this application will not elaborate further. It should be noted that compared with video encoding, during the encoding process of data such as audio data and integer data, there is no need to divide the data into blocks, but the data can be directly encoded.

[0043] Video encoding generally refers to processing an image sequence that forms a video or a video sequence. In the field of video encoding, the terms "picture", "frame", or "image" can be used as synonyms.

[0044] Several video coding standards belong to "lossy hybrid video coding and decoding" (i.e., combining spatial and temporal prediction in the pixel domain with 2D transform coding for quantization application in the transform domain). Each image in a video sequence is typically segmented into a set of non-overlapping blocks and is usually coded at the block level. In other words, the encoder typically processes, i.e., codes the video at the block (video block) level. For example, by spatial (intra-frame) prediction and temporal (inter-frame) prediction to generate a predicted block; subtracting the predicted block from the current block (the currently processed / to-be-processed block) to obtain a residual block; transforming and quantizing the residual block in the transform domain to reduce the amount of data to be transmitted (compressed), while the decoder side applies the inverse processing part relative to the encoder to the coded or compressed block to reconstruct the current block for representation. Additionally, the encoder needs to repeat the processing steps of the decoder so that the encoder and the decoder generate the same predictions (e.g., intra-frame prediction and inter-frame prediction) and / or reconstructed pixels for processing, i.e., coding subsequent blocks.

[0045] In the following embodiments of the decoding system 10, the encoder 20 and the decoder 30 are described according to Figures 1a to 3 as follows.

[0046] Figure 1a FIG. is an exemplary block diagram of a decoding system 10 provided in an embodiment of the present application. For example, a video decoding system 10 (or simply referred to as the decoding system 10) that can utilize the technology of the embodiments of the present application. The video encoder 20 (or simply referred to as the encoder 20) and the video decoder 30 (or simply referred to as the decoder 30) in the video decoding system 10 represent devices and the like that can be used to execute various techniques according to the various examples described in the embodiments of the present application.

[0047] As Figure 1a shown, the decoding system 10 includes a source device 12, and the source device 12 is configured to provide encoded image data 21 such as encoded images to a destination device 14 for decoding the encoded image data 21.

[0048] The source device 12 includes an encoder 20, and additionally, optionally, may include an image source 16, a pre-processor (or pre-processing unit) 18 such as an image pre-processor, and a communication interface (or communication unit) 22.

[0049] The image source 16 may include or may be any type of image capture device for capturing real-world images, etc., and / or any type of image generation device, such as a computer graphics processor for generating computer animated images or any type of device for acquiring and / or providing real-world images, computer-generated images (e.g., screen content, virtual reality (VR) images, and / or any combination thereof (e.g., augmented reality (AR) images). The above image source may be any type of memory or storage device for storing any of the above images.

[0050] To distinguish the processing performed by the preprocessor (or preprocessing unit) 18, the image (or image data) 17 may also be referred to as the raw image (or raw image data) 17.

[0051] The preprocessor 18 is used to receive the raw image data 17 and preprocess the raw image data 17 to obtain the preprocessed image (or preprocessed image data) 19. For example, the preprocessing performed by the preprocessor 18 may include trimming, color format conversion (e.g., from RGB to YCbCr), color correction, or denoising. It can be understood that the preprocessing unit 18 may be an optional component.

[0052] The video encoder (or encoder) 20 is used to receive the preprocessed image data 19 and provide the encoded image data 21 (which will be further described below according to Figure 2 etc.).

[0053] The communication interface 22 in the source device 12 can be used to: receive the encoded image data 21 and send the encoded image data 21 (or any other processed version) to another device such as the destination device 14 or any other device through the communication channel 13 for storage or direct reconstruction.

[0054] The destination device 14 includes a decoder 30, and additionally, optionally, may include a communication interface (or communication unit) 28, a postprocessor (or postprocessing unit) 32, and a display device 34.

[0055] The communication interface 28 in the destination device 14 is used to directly receive the encoded image data 21 (or any other processed version) from the source device 12 or from any other source device such as a storage device. For example, the storage device is an encoded image data storage device, and provide the encoded image data 21 to the decoder 30.

[0056] The communication interfaces 22 and 28 can be used to send or receive encoded image data (or encoded data) 21 via a direct communication link between the source device 12 and the destination device 14, such as a direct wired or wireless connection, etc., or via any type of network, such as a wired network, a wireless network, or any combination thereof, any type of private network and public network, or any combination of any type thereof.

[0057] For example, the communication interface 22 can be used to encapsulate the encoded image data 21 into a suitable format such as a packet, and / or use any type of transmission encoding or processing to process the encoded image data above for transmission over the communication link or communication network.

[0058] The communication interface 28 corresponds to the communication interface 22. For example, it can be used to receive the transmitted data and process the transmitted data using any type of corresponding transmission decoding or processing and / or de-encapsulation to obtain the encoded image data 21.

[0059] Both the communication interface 22 and the communication interface 28 can be configured as Figure 1a a unidirectional communication interface as indicated by the arrow of the corresponding communication channel 13 pointing from the source device 12 to the destination device 14 in

[0060] or a bidirectional communication interface, and can be used to send and receive messages, etc., to establish a connection, confirm and exchange any other information related to the communication link and / or data transmission such as the transmission of encoded image data, etc. Figure 3 etc. will be further described below.

[0061] The video decoder (or decoder) 30 is used to receive the encoded image data 21 and provide decoded image data (or decoded image data) 31 (which will be further described below according to

[0062] The display device 34 is configured to receive the post - processed image data 33 to display an image to a user, viewer, etc. The display device 34 may be or include any type of display for presenting the reconstructed image. For example, an integrated or external display screen or monitor. For example, the display screen may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro - LED display, a liquid crystal on silicon (LCoS), a digital light processor (DLP), or any other type of display screen.

[0063] The decoding system 10 further includes a training engine 25. The training engine 25 is configured to train the encoder 20 (especially the entropy encoding unit 270 in the encoder 20) or the decoder 30 (especially the entropy decoding unit 304 in the decoder 30) to perform entropy encoding on the image blocks to be encoded according to the estimated probability distribution. For a detailed description of the training engine 25, please refer to the method test examples described below.

[0064] Although Figure 1a The source device 12 and the destination device 14 are shown as separate devices, but device embodiments may also include both the source device 12 and the destination device 14 or the functions of both the source device 12 and the destination device 14 simultaneously, that is, including both the source device 12 or its corresponding function and the destination device 14 or its corresponding function. In these embodiments, the source device 12 or its corresponding function and the destination device 14 or its corresponding function may be implemented using the same hardware and / or software, or by separate hardware and / or software, or any combination thereof.

[0065] According to the description, Figure 1a The presence and (exact) division of different units or functions in the shown source device 12 and / or destination device 14 may vary according to the actual device and application, which is obvious to those skilled in the art.

[0066] Please refer to Figure 1b , Figure 1b FIG. is an exemplary block diagram of a video decoding system 40 provided by an embodiment of the present application. The encoder 20 (such as a video encoder 20) or the decoder 30 (such as a video decoder 30), or both, may be implemented by, for example, Figure 1bThe processing circuitry in the illustrated video decoding system 40 is implemented by, for example, one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, video encoding-specific processors, or any combination thereof. Refer to Figure 2 and Figure 3 , Figure 2 which is an exemplary block diagram of a video encoder provided by an embodiment of the present application, Figure 3 and Figure 2 which is an exemplary block diagram of a video decoder provided by an embodiment of the present application. The encoder 20 may be implemented by the processing circuitry 46 to include various modules discussed with reference to Figure 3 the encoder 20 and / or any other encoder system or subsystem described herein. The decoder 30 may be implemented by the processing circuitry 46 to include various modules discussed with reference to Figure 5 the decoder 30 and / or any other decoder system or subsystem described herein. The above-mentioned processing circuitry 46 may be used to perform various operations discussed below. As Figure 1b shown, if part of the technology is implemented in software, the device may store the instructions of the software in a suitable non-transitory computer-readable storage medium and execute the instructions in hardware using one or more processors, thereby implementing the technology of the embodiments of the present application. One of the video encoder 20 and the video decoder 30 may be integrated as part of a combined encoder / decoder (CODEC) in a single device, as

[0067] shown. The source device 12 and the destination device 14 may include any of a variety of devices, including any type of handheld or fixed device, such as, for example, a laptop or notebook computer, a cell phone, a smartphone, a tablet or tablet computer, a camera, a desktop computer, a set-top box, a television, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiving device, a broadcast transmitting device, and a monitoring device, etc., and may or may not use any type of operating system. The source device 12 and the destination device 14 may also be devices in a cloud computing scenario, such as virtual machines in a cloud computing scenario. In some cases, the source device 12 and the destination device 14 may be equipped with components for wireless communication. Therefore, the source device 12 and the destination device 14 may be wireless communication devices.

[0068] ​The source device 12 and the destination device 14 can install virtual scene application programs (applications, APPs) such as virtual reality (VR) applications, augmented reality (AR) applications, or mixed reality (MR) applications, and can run VR applications, AR applications, or MR applications based on user operations (such as clicking, touching, swiping, shaking, voice control, etc.). The source device 12 and the destination device 14 can collect images / videos of any object in the environment through a camera and / or a sensor, and then display virtual objects on the display device according to the collected images / videos. The virtual objects can be virtual objects in a VR scene, an AR scene, or an MR scene (i.e., objects in a virtual environment).

[0069] It should be noted that in the embodiments of the present application, the virtual scene application programs in the source device 12 and the destination device 14 can be application programs built into the source device 12 and the destination device 14 themselves, or can be application programs provided by third-party service providers installed by users, and no specific limitation is made thereto.

[0070] In addition, the source device 12 and the destination device 14 can install real-time video transmission applications, such as live broadcast applications. The source device 12 and the destination device 14 can collect images / videos through a camera, and then display the collected images / videos on the display device.

[0071] In some cases, Figure 1a the illustrated video decoding system 10 is merely exemplary, and the technology provided by the embodiments of the present application is applicable to video coding settings (e.g., video encoding or video decoding), and these settings do not necessarily include any data communication between the encoding device and the decoding device. In other examples, data is retrieved from a local memory, sent over a network, etc. The video encoding device can encode data and store the data in a memory, and / or the video decoding device can retrieve data from the memory and decode the data. In some examples, encoding and decoding are performed by devices that do not communicate with each other but only encode data into a memory and / or retrieve and decode data from the memory.

[0072] Please refer to Figure 1b , Figure 1b which is an exemplary block diagram of the video decoding system 40 provided by the embodiments of the present application. As Figure 1b shown, the video decoding system 40 can include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video codec implemented by a processing circuit 46), an antenna 42, one or more processors 43, one or more memory memories 44, and / or a display device 45.

[0073] AsFigure 1b As shown, the imaging device 41, antenna 42, processing circuit 46, video encoder 20, video decoder 30, processor 43, memory 44, and / or display device 45 can communicate with each other. In different instances, the video decoding system 40 may include only the video encoder 20 or only the video decoder 30.

[0074] In some instances, the antenna 42 can be used to transmit or receive an encoded bitstream of video data. Additionally, in some instances, the display device 45 can be used to present video data. The processing circuit 46 can include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, etc. The video decoding system 40 can also include an optional processor 43, which can similarly include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, etc. Additionally, the memory 44 can be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.). In non-limiting instances, the memory 44 can be implemented by cache memory. In other instances, the processing circuit 46 can include a memory (e.g., a cache, etc.) for implementing an image buffer, etc.

[0075] In some instances, the video encoder 20 implemented by logic circuits can include an image buffer (e.g., implemented by the processing circuit 46 or the memory 44) and a graphics processing unit (e.g., implemented by the processing circuit 46). The graphics processing unit can be communicatively coupled to the image buffer. The graphics processing unit can include the video encoder 20 implemented by the processing circuit 46 to implement various modules discussed with reference to Figure 2 and / or any other encoder system or subsystem described herein. The logic circuits can be used to perform the various operations discussed herein.

[0076] In some instances, the video decoder 30 can be implemented in a similar manner by the processing circuit 46 to implement with reference to Figure 3The video decoder 30 and / or the various modules discussed for any other decoder system or subsystem described herein. In some examples, the video decoder 30 implemented by logic circuitry may include an image buffer (implemented by the processing circuitry 46 or the memory 44) and a graphics processing unit (e.g., implemented by the processing circuitry 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include the video decoder 30 implemented by the processing circuitry 46 to implement with reference to Figure 3 and / or the various modules discussed for any other decoder system or subsystem described herein.

[0077] In some examples, the antenna 42 may be used to receive an encoded bitstream of video data. As discussed, the encoded bitstream may include data, indicators, index values, mode selection data, etc. discussed herein related to the coded video frames, e.g., data related to coded partitions (e.g., transform coefficients or quantized transform coefficients, optional indicators as discussed, and / or data defining the coded partitions). The video decoding system 40 may also include a video decoder 30 coupled to the antenna 42 and configured to decode the encoded bitstream. A display device 45 is used to present the video frames.

[0078] It should be understood that for the examples described with reference to the video encoder 20 in the embodiments of the present application, the video decoder 30 may be used to perform the reverse process. Regarding signaling syntax elements, the video decoder 30 may be used to receive and parse such syntax elements and accordingly decode the relevant video data. In some examples, the video encoder 20 may entropy code the syntax elements into an encoded video bitstream. In such examples, the video decoder 30 may parse such syntax elements and accordingly decode the relevant video data.

[0079] For ease of description, the embodiments of the present application are described with reference to the Versatile Video Coding (VVC) reference software or the High-Efficiency Video Coding (HEVC) developed by the Video Coding Experts Group (VCEG) of the ITU-T and the Joint Collaborative Team on Video Coding (JCT-VC) of the ISO / IEC Moving Picture Experts Group (MPEG). Those of ordinary skill in the art understand that the embodiments of the present application are not limited to HEVC or VVC.

[0080] Encoder and encoding method

[0081] As Figure 2As shown, the video encoder 20 includes an input end (or input interface) 201, a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy encoding unit 270, and an output end (or output interface) 272. The mode selection unit 260 may include an inter prediction unit 244, an intra prediction unit 254, and a segmentation unit 262. The inter prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). Figure 2 The illustrated video encoder 20 may also be referred to as a hybrid video encoder or a video encoder based on a hybrid video codec.

[0082] See Figure 2 , the inter prediction unit is a trained target model (also referred to as a neural network), and this neural network is used to process an input image or an image region or an image block to generate a predicted value of the input image block. For example, the neural network for inter prediction is used to receive an input image or an image region or an image block and generate a predicted value of the input image or an image region or an image block.

[0083] The residual calculation unit 204, the transform processing unit 206, the quantization unit 208, and the mode selection unit 260 form the forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, the inter prediction unit 244, and the intra prediction unit 254 form the backward signal path of the encoder, where the backward signal path of the encoder 20 corresponds to the signal path of the decoder (see Figure 3 the decoder 30 in). The inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer 230, the inter prediction unit 244, and the intra prediction unit 254 also form the "built-in decoder" of the video encoder 20.

[0084] Images and image segmentation (images and blocks)

[0085] The encoder 20 can be used to receive an image (or image data) 17 through an input terminal 201, etc., for example, an image in an image sequence forming a video or a video sequence. The received image or image data can also be a preprocessed image (or preprocessed image data) 19. For simplicity, the following description uses the image 17. The image 17 can also be referred to as the current image or the image to be encoded (especially when distinguishing the current image from other images in video coding, such as the previously encoded and / or decoded images in the same video sequence, i.e., the video sequence that also includes the current image).

[0086] (Digital) An image is or can be regarded as a two-dimensional array or matrix composed of pixel points with intensity values. The pixel points in the array can also be called pixels (pixel or pel for short, short for picture element). The number of pixel points in the horizontal and vertical directions (or axes) of the array or image determines the size and / or resolution of the image. To represent colors, usually three color components are used, that is, the image can be represented as or include three pixel point arrays. In the RBG format or color space, the image includes corresponding red, green, and blue pixel point arrays. However, in video coding, each pixel is usually represented in a luminance / chrominance format or color space, such as YCbCr, including a luminance component indicated by Y (sometimes also represented by L) and two chrominance components represented by Cb and Cr. The luminance component Y represents the luminance or gray-level intensity (for example, they are the same in a grayscale image), while the two chrominance components Cb and Cr represent the chrominance or color information components. Accordingly, an image in the YCbCr format includes a luminance pixel point array of luminance pixel point values (Y) and two chrominance pixel point arrays of chrominance values (Cb and Cr). An image in the RGB format can be converted or transformed into the YCbCr format, and vice versa, and this process is also called color transformation or conversion. If the image is black and white, the image can only include a luminance pixel point array. Accordingly, the image can be, for example, a luminance pixel point array in a monochrome format or a luminance pixel point array and two corresponding chrominance pixel point arrays in 4:2:0, 4:2:2, and 4:4:4 color formats.

[0087] In one embodiment, an embodiment of the video encoder 20 may include an image segmentation unit ( Figure 2(not shown in the figure) for dividing the image 17 into multiple (usually non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macro blocks (H.264 / AVC), or coding tree blocks (CTB), or coding tree units (CTU) in the H.265 / HEVC and VVC standards. The segmentation unit can be used to use the same block size for all images in the video sequence and the corresponding grid defining the block size, or to change the block size between images or subsets or groups of images, and divide each image into corresponding blocks.

[0088] In other embodiments, the video encoder can be used to directly receive the blocks 203 of the image 17, for example, one, several, or all of the blocks that make up the above-mentioned image 17. The image block 203 can also be referred to as the current image block or the image block to be encoded.

[0089] Similar to the image 17, the image block 203 is also or can be considered as a two-dimensional array or matrix composed of pixel points with intensity values (pixel point values), but the image block 203 is smaller than the image 17. In other words, the block 203 can include an array of pixel points (for example, the luminance array in the case of a monochromatic image 17 or the luminance array or chrominance array in the case of a color image) or three arrays of pixel points (for example, one luminance array and two chrominance arrays in the case of a color image 17) or any other number and / or type of arrays according to the color format adopted. The number of pixel points in the horizontal and vertical directions (or axes) of the block 203 defines the size of the block 203. Accordingly, the block can be an array of M×N (M columns × N rows) pixel points, or an array of M×N transform coefficients, etc.

[0090] In one embodiment, Figure 2 The illustrated video encoder 20 is used to encode the image 17 block by block, for example, performing encoding and prediction on each block 203.

[0091] In one embodiment, Figure 2 The illustrated video encoder 20 can also be used to segment and / or encode the image using slices (also called video slices), where the image can be segmented or encoded using one or more slices (usually non-overlapping). Each slice can include one or more blocks (for example, coding tree units CTU) or one or more block groups (for example, coding blocks (tile) in the H.265 / HEVC / VVC standards and bricks in the VVC standard).

[0092] In one embodiment, Figure 2The video encoder 20 shown can also be used to segment and / or encode an image using slices / coding block groups (also known as video coding block groups) and / or coding blocks (also known as video coding blocks), where the image can be segmented or encoded using one or more slices / coding block groups (usually non-overlapping), and each slice / coding block group can include one or more blocks (e.g., CTUs) or one or more coding blocks, etc., where each coding block can be in a shape such as a rectangle and can include one or more whole or partial blocks (e.g., CTUs).

[0093] Residual calculation

[0094] The residual calculation unit 204 is used to calculate the residual block 205 based on the image block (or original block) 203 and the prediction block 265 (the prediction block 265 is introduced in detail later) in the following way: for example, subtract the pixel values of the prediction block 265 from the pixel values of the image block 203 pixel by pixel (pixel by pixel) to obtain the residual block 205 in the pixel domain.

[0095] Transformation

[0096] The transformation processing unit 206 is used to perform a discrete cosine transform (DCT) or a discrete sine transform (DST), etc. on the pixel values of the residual block 205 to obtain the transform coefficients 207 in the transform domain. The transform coefficients 207 can also be referred to as transform residual coefficients, representing the residual block 205 in the transform domain.

[0097] The transformation processing unit 206 can be used to apply an integer approximation of DCT / DST, such as the transformation specified for H.265 / HEVC. Compared with the orthogonal DCT transform, this integer approximation is usually scaled by a certain factor. In order to maintain the norm of the residual block after the forward and inverse transform processes, other scaling factors are used as part of the transform process. The scaling factors are usually selected according to certain constraints, such as the scaling factor being a power of 2 for shift operations, the bit depth of the transform coefficients, the trade-off between accuracy and implementation cost, etc. For example, a specific scaling factor is specified for the inverse transform by the inverse transform processing unit 212 on the encoder 20 side (and for the corresponding inverse transform by, for example, the inverse transform processing unit 312 on the decoder 30 side), and correspondingly, a corresponding scaling factor can be specified for the forward transform by the transformation processing unit 206 on the encoder 20 side.

[0098] In one embodiment, the video encoder 20 (correspondingly, the transform processing unit 206) can be used to output transform parameters such as the type of one or more transforms. For example, it can be directly output or output after being encoded or compressed by the entropy encoding unit 270, such that the video decoder 30 can receive and use the transform parameters for decoding.

[0099] Quantization

[0100] The quantization unit 208 is used to quantize the transform coefficients 207 through, for example, scalar quantization or vector quantization to obtain quantized transform coefficients 209. The quantized transform coefficients 209 can also be referred to as quantized residual coefficients 209.

[0101] The quantization process can reduce the bit depth associated with some or all of the transform coefficients 207. For example, an n-bit transform coefficient can be rounded down to an m-bit transform coefficient during quantization, where n is greater than m. The degree of quantization can be modified by adjusting the quantization parameter (QP). For example, for scalar quantization, different degrees of scaling can be applied to achieve finer or coarser quantization. A smaller quantization step corresponds to finer quantization, while a larger quantization step corresponds to coarser quantization. The appropriate quantization step can be indicated by the quantization parameter (QP). For example, the quantization parameter can be an index of a predefined set of appropriate quantization steps. For example, a smaller quantization parameter can correspond to fine quantization (smaller quantization step), and a larger quantization parameter can correspond to coarse quantization (larger quantization step), and vice versa. Quantization can include dividing by the quantization step, and the corresponding or inverse dequantization performed by the dequantization unit 210 and the like can include multiplying by the quantization step. Embodiments according to some standards such as HEVC can be used to determine the quantization step using the quantization parameter. Generally, the quantization step can be calculated using a fixed-point approximation of an equation involving division based on the quantization parameter. Other scaling factors can be introduced for quantization and dequantization to restore the norm of the residual block that may be modified due to the scaling used in the fixed-point approximation of the equations for the quantization step and the quantization parameter. In one exemplary implementation, the scaling of the inverse transform and dequantization can be combined. Alternatively, a custom quantization table can be used and indicated from the encoder to the decoder in the bitstream. Quantization is a lossy operation, and the larger the quantization step, the greater the loss.

[0102] In one embodiment, the video encoder 20 (correspondingly, the quantization unit 208) can be used to output the quantization parameter (QP), for example, directly output or output after being encoded or compressed by the entropy encoding unit 270, such that the video decoder 30 can receive and use the quantization parameter for decoding.

[0103] Dequantization

[0104] The inverse quantization unit 210 is used to perform inverse quantization on the quantization coefficients by the quantization unit 208 to obtain the dequantized coefficients 211. For example, the inverse quantization scheme of the quantization scheme performed by the quantization unit 208 is performed according to or using the same quantization step as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211, corresponding to the transform coefficients 207. However, due to the loss caused by quantization, the dequantized coefficients 211 are usually not exactly the same as the transform coefficients.

[0105] Inverse transform

[0106] The inverse transform processing unit 212 is used to perform the inverse transform of the transform performed by the transform processing unit 206, such as inverse discrete cosine transform (DCT) or inverse discrete sine transform (DST), to obtain a reconstructed residual block 213 (or corresponding dequantized coefficients 213) in the pixel domain. The reconstructed residual block 213 may also be referred to as a transform block 213.

[0107] Reconstruction

[0108] The reconstruction unit 214 (e.g., adder 214) is used to add the transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain a reconstructed block 215 in the pixel domain. For example, the pixel point values of the reconstructed residual block 213 and the pixel point values of the prediction block 265 are added.

[0109] Filtering

[0110] The loop filter unit 220 (or simply referred to as "loop filter" 220) is used to filter the reconstructed block 215 to obtain the filtered block 221, or is generally used to filter the reconstructed pixel points to obtain the filtered pixel point values. For example, the loop filter unit is used to smoothly perform pixel transitions or improve video quality. The loop filter unit 220 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process may be the deblocking filter, the SAO filter, and the ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., an adaptive in-loop shaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process may also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 220 is shown as a loop filter in Figure 2 it can be implemented as a post-loop filter in other configurations. The filtered block 221 may also be referred to as the filtered reconstructed block 221.

[0111] In one embodiment, the video encoder 20 (correspondingly, the loop filter unit 220) may be used to output loop filter parameters (such as SAO filtering parameters, ALF filtering parameters, or LMCS parameters), for example, directly output or output after entropy coding by the entropy coding unit 270, such that the decoder 30 can receive and use the same or different loop filter parameters for decoding.

[0112] Decoded picture buffer

[0113] The decoded picture buffer (DPB) 230 can be a reference picture memory that stores reference picture data for use by the video encoder 20 when encoding video data. The DPB 230 can be formed of any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of storage devices. The decoded picture buffer 230 can be used to store one or more filtered blocks 221. The decoded picture buffer 230 can also be used to store other previously filtered blocks, such as previously reconstructed and filtered blocks 221, of the same current picture or a different picture such as a previous reconstructed picture, and can provide a full previously reconstructed i.e., decoded picture (and corresponding reference blocks and pixels) and / or a partially reconstructed current picture (and corresponding reference blocks and pixels), e.g., for inter prediction. The decoded picture buffer 230 can also be used to store one or more unfiltered reconstructed blocks 215, or generally unfiltered reconstructed pixels, e.g., reconstructed blocks 215 that have not been filtered by the loop filter unit 220, or reconstructed blocks or reconstructed pixels that have not undergone any other processing.

[0114] Mode Selection (Partitioning and Prediction)

[0115] The mode selection unit 260 includes a partitioning unit 262, an inter prediction unit 244, and an intra prediction unit 254, and is configured to receive or obtain original picture data such as original blocks 203 (current blocks 203 of the current picture 17) and reconstructed picture data from the decoded picture buffer 230 or other buffers (e.g., a column buffer, Figure 2 not shown), e.g., filtered and / or unfiltered reconstructed pixels or reconstructed blocks of the same (current) picture and / or one or more previous decoded pictures. The reconstructed picture data is used as reference picture data required for prediction such as inter prediction or intra prediction to obtain a predicted block 265 or a predicted value 265.

[0116] The mode selection unit 260 can be used to determine or select a partitioning for a current block (including no partitioning) and a prediction mode (e.g., an intra or inter prediction mode), and generate a corresponding predicted block 265 for calculating the residual block 205 and reconstructing the reconstructed block 215.

[0117] In one embodiment, the mode selection unit 260 may be used to select a splitting and prediction mode (e.g., from the prediction modes supported or available to the mode selection unit 260), where the prediction mode provides the best match or the smallest residual (the smallest residual means better compression in transmission or storage), or provides the smallest signaling overhead (the smallest signaling overhead means better compression in transmission or storage), or considers or balances both of the above. The mode selection unit 260 may be used to determine the splitting and prediction mode according to rate distortion Optimization (RDO), that is, to select the prediction mode that provides the smallest rate distortion optimization. Terms such as "best", "lowest", "optimal", etc. in this article do not necessarily refer to "the best", "the lowest", "the optimal" overall, but may also refer to situations that meet the termination or selection criteria. For example, values that exceed or are below a threshold or other limitations may result in a "sub-optimal choice", but will reduce complexity and processing time.

[0118] In other words, the splitting unit 262 may be used to split the images in the video sequence into a sequence of coding tree units (CTUs). The CTU 203 may be further split into smaller block parts or sub-blocks (again forming blocks), for example, by iteratively using quad-tree partitioning (QT), binary-tree partitioning (BT), triple-tree partitioning (TT), or any combination thereof, and is used to perform prediction on, for example, each of the block parts or sub-blocks, where mode selection includes selecting the tree structure for splitting the block 203 and selecting the prediction mode applied to each of the block parts or sub-blocks.

[0119] The splitting (e.g., performed by the splitting unit 262) and prediction processing (e.g., performed by the inter-frame prediction unit 244 and the intra-frame prediction unit 254) performed by the video encoder 20 will be described in detail below.

[0120] Splitting

[0121] The splitting unit 262 can split (or divide) an image block (or CTU) 203 into smaller parts, such as small blocks in the shape of a square or a rectangle. For an image with an array of three pixel points, a CTU consists of an N×N block of luminance pixel points and two corresponding chrominance pixel point blocks. The maximum allowed size of the luminance block in the versatile video coding (VVC) standard under development is specified as 128×128, but it may be specified as a value different from 128×128 in the future, such as 256×256. The CTUs of an image can be grouped / concentrated into slices / coding tree units, coding blocks, or tiles. A coding block covers a rectangular area of an image, and a coding block can be divided into one or more tiles. A tile consists of multiple CTU rows within a coding block. A coding block that is not divided into multiple tiles can be called a tile. However, a tile is a true subset of a coding block and is thus not called a coding block. VVC supports two coding tree unit modes, namely the raster scan slice / coding tree unit mode and the rectangular slice mode. In the raster scan coding tree unit mode, a slice / coding tree unit contains a sequence of coding blocks in the raster scan of the coding blocks of an image. In the rectangular slice mode, a slice contains multiple tiles of an image, and these tiles together form a rectangular area of the image. The tiles within a rectangular slice are arranged in the tile raster scan order of the slice. These smaller blocks (which can also be called sub-blocks) can be further divided into even smaller parts. This is also called tree splitting or hierarchical tree splitting, where a root block at the root tree level 0 (hierarchical level 0, depth 0), etc., can be recursively split into two or more blocks at the next lower tree level, such as nodes at tree level 1 (hierarchical level 1, depth 1). These blocks can in turn be split into two or more blocks at the next lower level, such as tree level 2 (hierarchical level 2, depth 2), etc., until the splitting ends (because an end criterion is met, such as reaching the maximum tree depth or the minimum block size). Blocks that are not further split are also called leaf blocks or leaf nodes of the tree. A tree split into two parts is called a binary-tree (BT), a tree split into three parts is called a ternary-tree (TT), and a tree split into four parts is called a quad-tree (QT).

[0122] For example, a coding tree unit (CTU) may be or include a CTB of luminance pixel points, two corresponding CTBs of chrominance pixel points of an image having three pixel point arrays, or a CTB of pixel points of a monochrome image or a CTB of pixel points of an image encoded using three independent color planes and a syntax structure (for encoding pixel points). Accordingly, a coding tree block (CTB) may be a block of N×N pixel points, where N may be set to a certain value such that components are divided into CTBs, which is segmentation. A coding unit (CU) may be or include a coding block of luminance pixel points, two corresponding coding blocks of chrominance pixel points of an image having three pixel point arrays, or a coding block of pixel points of a monochrome image or a coding block of pixel points of an image encoded using three independent color planes and a syntax structure (for encoding pixel points). Accordingly, a coding block (CB) may be a block of M×N pixel points, where M and N may be set to a certain value such that the CTB is divided into coding blocks, which is segmentation.

[0123] For example, in an embodiment, according to HEVC, a coding tree unit (CTU) may be divided into multiple CUs by using a quadtree structure represented as a coding tree. A decision on whether to use inter (temporal) prediction or intra (spatial) prediction to encode an image region is made at the leaf CU level. Each leaf CU may be further divided into one, two, or four PUs according to the PU partition type. The same prediction process is used within one PU, and relevant information is transmitted to the decoder in units of PUs. After obtaining a residual block by applying the prediction process according to the PU partition type, the leaf CU may be segmented into transform units (TUs) according to another quadtree structure similar to the coding tree used for the CU.

[0124] For example, in an embodiment, according to the latest video coding standard currently under development (referred to as Versatile Video Coding (VVC)), a combined quadtree using nested multi-type trees (such as binary trees and ternary trees) is used to divide the segmentation structure for splitting coding tree units. In the coding tree structure within a coding tree unit, a CU can be square or rectangular. For example, a coding tree unit (CTU) is first segmented by a quadtree structure. The quadtree leaf nodes are further segmented by a multi-type tree structure. The multi-type tree structure has four partitioning types: vertical binary tree partitioning (SPLIT_BT_VER), horizontal binary tree partitioning (SPLIT_BT_HOR), vertical ternary tree partitioning (SPLIT_TT_VER), and horizontal ternary tree partitioning (SPLIT_TT_HOR). The multi-type tree leaf nodes are called coding units (CUs), unless the CU is too large for the maximum transform length. Such segments are used for prediction and transform processing without any further splitting. In most cases, this means that the CU, PU, and TU have the same block size in the coding block structure of the quadtree nested multi-type tree. This exception occurs when the maximum supported transform length is less than the width or height of the color component of the CU. VVC has developed a unique signaling mechanism for the segmentation partitioning information in the coding structure with a quadtree nested multi-type tree. In the signaling mechanism, a coding tree unit (CTU), as the root of the quadtree, is first segmented by the quadtree structure. Then each quadtree leaf node (when large enough to be) is further segmented into a multi-type tree structure. In the multi-type tree structure, it is indicated by a first identifier (mtt_split_cu_flag) whether the node is further segmented. When the node is further segmented, the partitioning direction is first indicated by a second identifier (mtt_split_cu_vertical_flag), and then it is indicated by a third identifier (mtt_split_cu_binary_flag) whether the partitioning is a binary tree partitioning or a ternary tree partitioning. According to the values of mtt_split_cu_vertical_flag and mtt_split_cu_binary_flag, the decoder can derive the multi-type tree partitioning mode (MttSplitMode) of the CU based on predefined rules or tables. It should be noted that for a certain design, such as the 64×64 luma block and 32×32 chroma pipeline design in a VVC hardware decoder, when the width or height of the luma coding block is greater than 64, TT partitioning is not allowed. When the width or height of the chroma coding block is greater than 32, TT partitioning is also not allowed. The pipeline design divides the image into multiple virtual pipeline data units (VPDUs), and each VPDU is defined as non-overlapping units in the image. In a hardware decoder, consecutive VPDUs are processed simultaneously in multiple pipeline stages. In most pipeline stages, the VPDU size is roughly proportional to the buffer size, so it is necessary to keep the VPDU small.In most hardware decoders, the VPDU size can be set to the maximum transform block (TB) size. However, in VVC, the splitting of the ternary tree (TT) and binary tree (BT) may increase the VPDU size.

[0125] In addition, it should be noted that when a part of the tree node block extends beyond the bottom or the right image boundary, the tree node block is forced to be divided until all pixel points of each coded CU are within the image boundary.

[0126] For example, the above intra sub - partitions (ISP) tool can vertically or horizontally divide the luma intra - prediction block into two or four sub - parts according to the block size.

[0127] In one example, the mode selection unit 260 of the video encoder 20 can be used to perform any combination of the segmentation techniques described above.

[0128] As described above, the video encoder 20 is used to determine or select the best or optimal prediction mode from a (predetermined) set of prediction modes. The set of prediction modes may include, for example, intra - prediction modes and / or inter - prediction modes.

[0129] Intra - prediction

[0130] The set of intra - prediction modes may include 35 different intra - prediction modes. For example, non - directional modes such as DC (or mean) mode and planar mode, or directional modes defined as in HEVC, or may include 67 different intra - prediction modes. For example, non - square - block wide - angle intra - prediction modes defined in VVC adaptively replace several traditional angular intra - prediction modes. Also, for example, to avoid the division operation of DC prediction, only the longer side is used to calculate the average value of the non - square block. And, the intra - prediction result of the planar mode can also be modified using the position - dependent intra - prediction combination (PDPC) method.

[0131] The intra - prediction unit 254 is used to generate an intra - prediction block 265 by reconstructing pixel points using adjacent blocks of the same current image according to the intra - prediction mode in the set of intra - prediction modes.

[0132] The intra-frame prediction unit 254 (or generally the mode selection unit 260) is also used to output intra-frame prediction parameters (or generally information indicating the selected intra-frame prediction mode of the block) in the form of syntax elements 266 to the entropy coding unit 270 for inclusion in the encoded image data 21, so that the video decoder 30 can perform operations, such as receiving and using the prediction parameters for decoding.

[0133] The intra prediction modes in HEVC include DC prediction mode, plane prediction mode and 33 angle prediction modes, with a total of 35 candidate prediction modes. The current block can use the pixels of the reconstructed image blocks on the left and above as references for intra prediction. The image blocks in the surrounding area of the current block used for intra prediction of the current block become reference blocks, and the pixels in the reference blocks are called reference pixels. Among the 35 candidate prediction modes, the DC prediction mode is applicable to the area with flat texture in the current block, and all pixels in this area use the average value of the reference pixels in the reference block as prediction; the plane prediction mode is applicable to image blocks with smoothly changing textures. The current block that meets this condition uses the reference pixels in the reference block for bilinear interpolation as the prediction of all pixels in the current block; the angle prediction mode uses the characteristics that the texture of the current block is highly correlated with the texture of the adjacent reconstructed image blocks, and copies the values of the reference pixels in the corresponding reference block along a certain angle as the prediction of all pixels in the current block.

[0134] The HEVC encoder selects an optimal intra-frame prediction mode for the current block from 35 candidate prediction modes and writes the optimal intra-frame prediction mode into the video bitstream. To improve the coding efficiency of intra-frame prediction, the encoder / decoder derives three most likely modes from the optimal intra-frame prediction modes of the reconstructed image blocks in the surrounding area using intra-frame prediction. If the optimal intra-frame prediction mode selected for the current block is one of the three most likely modes, a first index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the three most likely modes; if the selected optimal intra-frame prediction mode is not one of the three most likely modes, a second index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the other 32 modes (other modes among the 35 candidate prediction modes except the aforementioned three most likely modes). The HEVC standard uses a 5-bit fixed-length code as the aforementioned second index.

[0135] The methods for the HEVC encoder to derive the three most probable modes include: selecting the optimal intra prediction modes of the left adjacent picture block and the upper adjacent picture block of the current block and putting them into a set. If these two optimal intra prediction modes are the same, only one of them needs to be retained in the set. If these two optimal intra prediction modes are the same and both are angular prediction modes, then select two angular prediction modes adjacent to this angular direction and add them to the set; otherwise, sequentially select the planar prediction mode, the DC mode, and the vertical prediction mode and add them to the set until the number of modes in the set reaches 3.

[0136] After the HEVC decoder performs entropy decoding on the bitstream, it obtains the mode information of the current block. This mode information includes an indication flag indicating whether the optimal intra prediction mode of the current block is among the three most probable modes, and the index of the optimal intra prediction mode of the current block among the three most probable modes or the index of the optimal intra prediction mode of the current block among the other 32 modes.

[0137] Inter-frame prediction

[0138] In a possible implementation, the inter-frame prediction mode set depends on the available reference images (i.e., for example, at least some of the previously decoded images stored in the DBP 230 as described above) and other inter-frame prediction parameters. For example, it depends on whether to use the entire reference image or only a part of the reference image, such as the search window area near the region of the current block, to search for the best-matching reference block, and / or for example, it depends on whether to perform pixel interpolation such as half-pixel, quarter-pixel, and / or sixteenth-pixel interpolation.

[0139] In addition to the above prediction modes, a skip mode and / or a direct mode can also be adopted.

[0140] For example, for extended merge prediction, the merge candidate list for this mode consists of the following five candidate types in order: spatial MVP from spatially adjacent CUs, temporal MVP from collocated CUs, history-based MVP from the FIFO table, pairwise average MVP, and zero MV. Decoder side motion vector refinement (DMVR) based on bilateral matching can be used to increase the accuracy of the MVs of the merge mode. The merge mode with MVD (MMVD) comes from the merge mode with motion vector differences. The MMVD flag is sent immediately after the skip flag and the merge flag to specify whether the CU uses the MMVD mode. An adaptive motion vector resolution (AMVR) scheme for the CU level can be used. AMVR supports encoding the MVD of the CU with different precisions. The MVD of the current CU is adaptively selected according to the prediction mode of the current CU. When the CU is encoded in the merge mode, the combined inter / intra prediction (CIIP) mode can be applied to the current CU. The inter and intra prediction signals are weighted and averaged to obtain the CIIP prediction. For affine motion compensation prediction, the affine motion field of the block is described by the motion information of the motion vectors of 2 control points (4 parameters) or 3 control points (6 parameters). Subblock-based temporal motion vector prediction (SbTMVP), similar to the temporal motion vector prediction (TMVP) in HEVC, predicts the motion vectors of the sub-CUs within the current CU. Bi-directional optical flow (BDOF), formerly known as BIO, is a simplified version that reduces calculations, especially in terms of the number of multiplications and the size of the multipliers. In the triangle partitioning mode, the CU is evenly divided into two triangular parts in two partitioning ways: diagonal partitioning and anti-diagonal partitioning. In addition, the bi-directional prediction mode is extended on the basis of simple averaging to support the weighted average of two prediction signals.

[0141] The inter prediction unit 244 may include a motion estimation (ME) unit and a motion compensation (MC) unit (both in Figure 2(not shown in the figure). The motion estimation unit can be used to receive or obtain the image block 203 (the current image block 203 of the current image 17) and the decoded image 231, or at least one or more previously reconstructed blocks, for example, the reconstructed blocks of one or more other / different previously decoded images 231, to perform motion estimation. For example, the video sequence may include the current image and the previously decoded image 231, or in other words, the current image and the previously decoded image 231 may be part of the image sequence forming the video sequence or form the image sequence.

[0142] For example, the encoder 20 can be used to select a reference block from multiple reference blocks of the same or different images in multiple other images, and provide the reference image (or reference image index) and / or the offset (spatial offset) between the position (x, y coordinates) of the reference block and the position of the current block as an inter-frame prediction parameter to the motion estimation unit. This offset is also called a motion vector (MV).

[0143] The motion compensation unit is used to obtain, for example, receive, the inter-frame prediction parameter, and perform inter-frame prediction according to or using the inter-frame prediction parameter to obtain the inter-frame prediction block 246. The motion compensation performed by the motion compensation unit may include extracting or generating a prediction block according to the motion / block vector determined by motion estimation, and may also include performing interpolation at sub-pixel accuracy. The interpolation filter can generate pixel points of other pixels from the pixel points of known pixels, thereby potentially increasing the number of candidate prediction blocks available for encoding the image block. Once the motion vector corresponding to the PU of the current image block is received, the motion compensation unit can locate the prediction block pointed to by the motion vector in one of the reference image lists.

[0144] The motion compensation unit can also generate syntax elements related to the block and the video slice for the video decoder 30 to use when decoding the image blocks of the video slice. Additionally, or as an alternative to the slice and the corresponding syntax elements, coded block groups and / or coded blocks and the corresponding syntax elements can be generated or used.

[0145] During the process of obtaining the candidate motion vector list in the advanced motion vector prediction (AMVP) mode, the motion vectors (MVs) that can be added to the candidate motion vector list as an alternative include the MVs of the spatially adjacent and temporally adjacent image blocks of the current block, where the MVs of the spatially adjacent image blocks can further include the MVs of the left candidate image block located on the left side of the current block and the MVs of the upper candidate image block located above the current block. Exemplarily, please refer to Figure 4 , Figure 4 which is an exemplary schematic diagram of the candidate image block provided by the embodiment of the present application, such as Figure 4As shown, the set of left candidate image blocks includes {A0, A1}, the set of upper candidate image blocks includes {B0, B1, B2}, and the set of temporally adjacent candidate image blocks includes {C, T}. All three sets can be added as alternatives to the candidate motion vector list. However, according to the existing coding standard, the maximum length of the candidate motion vector list of AMVP is 2. Therefore, it is necessary to determine at most two MVs of image blocks to be added to the candidate motion vector list from the three sets according to the specified order. This order can be to give priority to the set of left candidate image blocks {A0, A1} of the current block (first consider A0, and if A0 is not available, then consider A1), followed by the set of upper candidate image blocks {B0, B1, B2} of the current block (first consider B0, if B0 is not available, then consider B1, and if B1 is not available, then consider B2), and finally consider the set of temporally adjacent candidate image blocks {C, T} of the current block (first consider T, if T is not available, then consider C).

[0146] After obtaining the above candidate motion vector list, the optimal MV is determined from the candidate motion vector list through the rate distortion cost (RDcost), and the candidate motion vector with the minimum RD cost is used as the motion vector predictor (MVP) of the current block. The rate distortion cost is calculated by the following formula:

[0147] J = SAD + λR

[0148] Where J represents the RD cost, SAD is the sum of absolute differences (SAD) between the pixel values of the predicted block obtained by motion estimation using the candidate motion vector and the pixel values of the current block, R represents the bit rate, and λ represents the Lagrange multiplier.

[0149] The encoder transmits the index of the determined MVP in the candidate motion vector list to the decoder. Further, a motion search can be performed within the neighborhood centered on the MVP to obtain the actual motion vector of the current block. The encoder calculates the motion vector difference (MVD) between the MVP and the actual motion vector and also transmits the MVD to the decoder. The decoder parses the index, finds the corresponding MVP in the candidate motion vector list according to the index, parses the MVD, and adds the MVD to the MVP to obtain the actual motion vector of the current block.

[0150] In the process of obtaining the candidate motion information list in the Merge mode, the motion information that can be added to the candidate motion information list as an alternative includes the motion information of spatially or temporally adjacent image blocks of the current block, where the spatially adjacent image blocks and the temporally adjacent image blocks can be referred to Figure 4 , the candidate motion information corresponding to the spatial domain in the candidate motion information list comes from 5 spatially adjacent blocks (A0, A1, B0, B1, and B2). If the spatially adjacent blocks are not available or are intra-frame predicted, their motion information is not added to the candidate motion information list. The candidate motion information in the temporal domain of the current block is obtained by scaling the MV of the corresponding position block in the reference frame according to the picture order count (POC) of the reference frame and the current frame. First, it is judged whether the block at position T in the reference frame is available. If not, the block at position C is selected. After obtaining the above candidate motion information list, the optimal motion information is determined from the candidate motion information list through the RD cost as the motion information of the current block. The encoding end transmits the index value of the position of the optimal motion information in the candidate motion information list (denoted as mergeindex) to the decoding end.

[0151] Entropy coding

[0152] The entropy coding unit 270 is used to apply an entropy coding algorithm or scheme (for example, variable length coding (VLC) scheme, context adaptive VLC (CALVC), arithmetic coding scheme, binarization algorithm, context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or other entropy coding methods or techniques) to the quantized residual coefficients 209, inter-frame prediction parameters, intra-frame prediction parameters, loop filter parameters, and / or other syntax elements, to obtain encoded image data 21 that can be output in the form of an encoded bitstream 21, etc. through the output end 272, so that a video decoder 30, etc. can receive and use the parameters for decoding. The encoded bitstream 21 can be transmitted to the video decoder 30, or stored in a memory for later transmission or retrieval by the video decoder 30.

[0153] Other structural variants of the video encoder 20 can be used to encode a video stream. For example, a non-transform-based encoder 20 can directly quantize the residual signal in the case where some blocks or frames do not have a transform processing unit 206. In another implementation, the encoder 20 can have a quantization unit 208 and an inverse quantization unit 210 combined into a single unit.

[0154] Decoder and decoding method

[0155] As Figure 3 shown, the video decoder 30 is used to receive encoded image data 21 (e.g., an encoded bitstream 21) encoded by, for example, the encoder 20 to obtain a decoded image 331. The encoded image data or bitstream includes information for decoding the above-mentioned encoded image data, such as data representing image blocks of an encoded video slice (and / or an encoded group of blocks or an encoded block) and related syntax elements.

[0156] In Figure 3 the example of, the decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., an adder 314), a loop filter 320, a decoded image buffer (DBP) 330, a mode application unit 360, an inter prediction unit 344, and an intra prediction unit 354. The inter prediction unit 344 can be or include a motion compensation unit. In some examples, the video decoder 30 can perform a decoding process that is generally opposite to the encoding process described with reference to Figure 2 the video encoder 100.

[0157] As in the encoder 20 above, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded image buffer DPB 230, the inter prediction unit 344, and the intra prediction unit 354 also form the "built-in decoder" of the video encoder 20. Accordingly, the inverse quantization unit 310 can be functionally the same as the inverse quantization unit 110, the inverse transform processing unit 312 can be functionally the same as the inverse transform processing unit 122, the reconstruction unit 314 can be functionally the same as the reconstruction unit 214, the loop filter 320 can be functionally the same as the loop filter 220, and the decoded image buffer 330 can be functionally the same as the decoded image buffer 230. Therefore, the explanations of the corresponding units and functions of the video encoder 20 correspondingly apply to the corresponding units and functions of the video decoder 30.

[0158] Entropy decoding

[0159] The entropy decoding unit 304 is used to parse the bitstream 21 (or generally the encoded image data 21) and perform entropy decoding on the encoded image data 21 to obtain quantization coefficients 309 and / or decoded encoding parameters ( Figure 3etc. (not shown in the figure), such as any one or all of inter-frame prediction parameters (such as reference image index and motion vector), intra-frame prediction parameters (such as intra-frame prediction mode or index), transform parameters, quantization parameters, loop filter parameters, and / or other syntax elements. The entropy decoding unit 304 can be used to apply a decoding algorithm or scheme corresponding to the encoding scheme of the entropy encoding unit 270 of the encoder 20. The entropy decoding unit 304 can also be used to provide inter-frame prediction parameters, intra-frame prediction parameters, and / or other syntax elements to the mode application unit 360, and provide other parameters to other units of the decoder 30. The video decoder 30 can receive video slice and / or video block-level syntax elements. Additionally, or as an alternative to slices and corresponding syntax elements, coded block groups and / or coded blocks and corresponding syntax elements can be received or used.

[0160] In some implementations, the video decoder 30 can include multiple entropy decoding units 304. For example, in a privacy protection scenario, the bitstream obtained by encoding video images includes a privacy bitstream and a non-privacy bitstream. Therefore, the video decoder 30 can include two entropy decoding units 304, where one entropy decoding unit 304 is used to parse the privacy bitstream in the bitstream, and the other entropy decoding unit 304 is used to parse the non-privacy bitstream in the bitstream.

[0161] Inverse quantization

[0162] The inverse quantization unit 310 can be used to receive a quantization parameter (quantization parameter, QP) (or generally information related to inverse quantization) and quantization coefficients from the encoded image data 21 (such as parsed and / or decoded by the entropy decoding unit 304), and perform inverse quantization on the decoded quantization coefficients 309 based on the above quantization parameter to obtain inverse quantization coefficients 311. The inverse quantization coefficients 311 can also be referred to as transform coefficients 311. The inverse quantization process can include using the quantization parameter calculated by the video encoder 20 for each video block in the video slice to determine the quantization degree, and also determine the degree of inverse quantization that needs to be performed.

[0163] Inverse transformation

[0164] The inverse transformation processing unit 312 can be used to receive the dequantized coefficients 311, also referred to as transform coefficients 311, and apply a transformation to the dequantized coefficients 311 to obtain a reconstructed residual block 213 in the pixel domain. The reconstructed residual block 213 can also be referred to as a transform block 313. The transformation can be an inverse transformation, such as inverse DCT, inverse DST, inverse integer transformation, or a conceptually similar inverse transformation process. The inverse transformation processing unit 312 can also be used to receive transform parameters or corresponding information from the encoded image data 21 (such as parsed and / or decoded by the entropy decoding unit 304) to determine the transformation applied to the dequantized coefficients 311.

[0165] Reconstruction

[0166] The reconstruction unit 314 (e.g., the adder 314) is used to add the reconstruction residual block 313 to the prediction block 365 to obtain the reconstruction block 315 in the pixel domain. For example, the pixel values of the reconstruction residual block 313 and the pixel values of the prediction block 365 are added together.

[0167] Filtering

[0168] The loop filter unit 320 (in or after the encoding loop) is used to filter the reconstruction block 315 to obtain the filtered block 321, so as to smoothly perform pixel transformation or improve video quality, etc. The loop filter unit 320 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process may be the deblocking filter, the SAO filter, and the ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., an adaptive in-loop shaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process may also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 320 is Figure 3 shown as a loop filter, in other configurations, the loop filter unit 320 may be implemented as a post-loop filter.

[0169] Decoded picture buffer

[0170] Subsequently, the decoded video block 321 in an image is stored in the decoded picture buffer 330. The decoded picture buffer 330 stores the decoded picture 331 as a reference picture, and the reference picture is used for subsequent motion compensation of other pictures and / or output for display respectively.

[0171] The decoder 30 is used to output the decoded picture 311 through the output terminal 312, etc., for the user to display or view.

[0172] Prediction

[0173] The inter-frame prediction unit 344 can be functionally the same as the inter-frame prediction unit 244 (especially the motion compensation unit), and the intra-frame prediction unit 354 can be functionally the same as the inter-frame prediction unit 254, and determines the division or segmentation and performs prediction based on the segmentation and / or prediction parameters or corresponding information received from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304). The mode application unit 360 can be used to perform prediction (intra-frame or inter-frame prediction) for each block according to the reconstructed image, block or corresponding pixel points (filtered or unfiltered), to obtain the predicted block 365.

[0174] When encoding a video slice as an intra-coded (I) slice, the intra-frame prediction unit 354 in the mode application unit 360 is used to generate a predicted block 365 for the image block of the current video slice according to the indicated intra-frame prediction mode and the data of the previously decoded blocks from the current image. When the video image is encoded as an inter-coded (i.e., B or P) slice, the inter-frame prediction unit 344 (e.g., the motion compensation unit) in the mode application unit 360 is used to generate a predicted block 365 for the video block of the current video slice according to the motion vector and other syntax elements received from the entropy decoding unit 304. For inter-frame prediction, these predicted blocks can be generated from one of the reference images in one of the reference image lists. The video decoder 30 can use the default construction technique to construct reference frame list 0 and list 1 according to the reference images stored in the DPB 330. In addition to slices (e.g., video slices) or as an alternative to slices, the same or similar process can be applied to embodiments of coded block groups (e.g., video coded block groups) and / or coded blocks (e.g., video coded blocks), for example, video can be encoded using I, P or B coded block groups and / or coded blocks.

[0175] The mode application unit 360 is used to determine the prediction information for the video block of the current video slice by parsing the motion vector and other syntax elements, and use the prediction information to generate a predicted block for the current video block being decoded. For example, the mode application unit 360 uses some received syntax elements to determine the prediction mode (e.g., intra-frame prediction or inter-frame prediction) for the video block of the encoded video slice, the inter-frame prediction slice type (e.g., B slice, P slice or GPB slice), the construction information for one or more reference image lists for the slice, the motion vector for each inter-frame coded video block of the slice, the inter-frame prediction state for each inter-frame coded video block of the slice, and other information to decode the video blocks within the current video slice. In addition to slices (e.g., video slices) or as an alternative to slices, the same or similar process can be applied to embodiments of coded block groups (e.g., video coded block groups) and / or coded blocks (e.g., video coded blocks), for example, video can be encoded using I, P or B coded block groups and / or coded blocks.

[0176] In one embodiment, Figure 3The video decoder 30 can also be used to segment and / or decode an image using slices (also referred to as video slices), where the image can be segmented or decoded using one or more slices (usually non-overlapping). Each slice can include one or more blocks (e.g., CTUs) or one or more block groups (e.g., coding tree units in the H.265 / HEVC / VVC standards and tiles in the VVC standard).

[0177] In one embodiment, Figure 3 the illustrated video decoder 30 can also be used to segment and / or decode an image using slice / coding tree unit groups (also referred to as video coding tree unit groups) and / or coding tree units (also referred to as video coding tree units), where the image can be segmented or decoded using one or more slice / coding tree unit groups (usually non-overlapping), each slice / coding tree unit group can include one or more blocks (e.g., CTUs) or one or more coding tree units, etc., where each coding tree unit can be in a shape such as a rectangle and can include one or more whole or partial blocks (e.g., CTUs).

[0178] Other variants of the video decoder 30 can be used to decode the encoded image data 21. For example, the decoder 30 can produce an output video stream without the loop filter unit 320. For example, a non-transform-based decoder 30 can directly dequantize the residual signal without the inverse transform processing unit 312 for some blocks or frames. In another implementation, the video decoder 30 can have the dequantization unit 310 and the inverse transform processing unit 312 combined into a single unit.

[0179] It should be understood that in the encoder 20 and the decoder 30, the processing result of the current step can be further processed and then output to the next step. For example, after interpolation filtering, motion vector derivation, or loop filtering, further operations such as clip or shift operations can be performed on the processing result of interpolation filtering, motion vector derivation, or loop filtering.

[0180] It should be noted that further operations can be performed on the derived motion vectors of the current block (including but not limited to the control point motion vectors in affine mode, the sub-block motion vectors in affine, planar, ATMVP mode, the temporal motion vectors, etc.). For example, the value of the motion vector can be restricted within a predefined range according to the representation bits of the motion vector. If the representation bits of the motion vector are bitDepth, the range is from -2^(bitDepth - 1) to 2^(bitDepth - 1) - 1, where "^" represents exponentiation. For example, if bitDepth is set to 16, the range is from -32768 to 32767; if bitDepth is set to 18, the range is from -131072 to 131071. For example, the values of the derived motion vectors (such as the MVs of 4 4×4 sub-blocks in an 8×8 block) are restricted such that the maximum difference between the integer parts of the above 4 4×4 sub-block MVs does not exceed N pixels, for example, does not exceed 1 pixel. Two methods for restricting the motion vector according to bitDepth are provided here.

[0181] Although the above embodiments mainly describe video coding and decoding, it should be noted that the embodiments of the decoding system 10, the encoder 20, and the decoder 30, as well as other embodiments described herein, can also be used for still image processing or coding / decoding, that is, the processing or coding / decoding of a single image independent of any previous or consecutive images in video coding and decoding. Generally, if the image processing is limited to a single image 17, the inter-frame prediction units 244 (encoder) and 344 (decoder) may not be available. All other functions (also referred to as tools or techniques) of the video encoder 20 and the video decoder 30 can equally be used for static image processing, such as residual calculation 204 / 304, transformation 206, quantization 208, inverse quantization 210 / 310, (inverse) transformation 212 / 312, segmentation 262 / 362, intra-frame prediction 254 / 354, and / or loop filtering 220 / 320, entropy coding 270, and entropy decoding 304.

[0182] Please refer to Figure 5 , Figure 5 which is an exemplary block diagram of the video decoding device 500 provided by the embodiments of the present application. The video decoding device 500 is suitable for implementing the disclosed embodiments described herein. In one embodiment, the video decoding device 500 can be a decoder, such as Figure 1a the video decoder 30 in Figure 1a , or it can be an encoder, such as

[0183] Video decoding device 500 includes: an input port 510 (or input port 510) for receiving data and a receiver unit (Rx) 520; a processor, logic unit or central processing unit (CPU) 530 for processing data; for example, the processor 530 here can be a neural network processor 530; a transmitter unit (Tx) 540 and an output port 550 (or output port 550) for transmitting data; and a memory 560 for storing data. The video decoding device 500 may further include optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to the input port 510, the receiving unit 520, the transmitting unit 540, and the output port 550 for the exit or entry of optical or electrical signals.

[0184] The processor 530 is implemented by hardware and software. The processor 530 can be implemented as one or more processor chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs. The processor 530 communicates with the input port 510, the receiving unit 520, the transmitting unit 540, the output port 550, and the memory 560. The processor 530 includes a decoding module 570 (e.g., a neural network-based decoding module 570). The decoding module 570 implements the embodiments disclosed above. For example, the decoding module 570 performs, processes, prepares, or provides various encoding operations. Therefore, the decoding module 570 provides a substantial improvement to the functions of the video decoding device 500 and affects the switching of the video decoding device 500 to different states. Alternatively, the decoding module 570 is implemented by instructions stored in the memory 560 and executed by the processor 530.

[0185] The memory 560 includes one or more disks, tape drives, and solid-state drives and can be used as an overflow data storage device for storing such programs when a selected program is to be executed and for storing instructions and data read during program execution. The memory 560 can be volatile and / or non-volatile and can be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and / or static random-access memory (SRAM).

[0186] Please refer to Figure 6 , Figure 6An exemplary block diagram of apparatus 600 provided by an embodiment of the present application. Apparatus 600 can be used as Figure 1a either or both of source device 12 and destination device 14 in

[0187] The processor 602 in apparatus 600 can be a central processing unit. Alternatively, processor 602 can be any other type of device or multiple devices that can manipulate or process information, existing or to be developed in the future. Although a single processor such as Figure 6 processor 602 as shown can be used to implement the disclosed implementations, using more than one processor is faster and more efficient.

[0188] In one implementation, the memory 604 in apparatus 600 can be a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device can be used as memory 604. Memory 604 can include code and data 606 that the processor 602 accesses via bus 612. Memory 604 can also include an operating system 608 and application programs 610, and the application programs 610 include at least one program that allows the processor 602 to execute the methods described above in this document. For example, the application programs 610 can include applications 1 to N, and also include a video decoding application that executes the methods described above in this document.

[0189] Apparatus 600 can also include one or more output devices, such as a display 618. In one example, the display 618 can be a touch-sensitive display that combines a display with a touch-sensitive element that can be used to sense touch inputs. The display 618 can be coupled to the processor 602 via bus 612.

[0190] Although the bus 612 in apparatus 600 is described herein as a single bus, the bus 612 can include multiple buses. In addition, the secondary storage can be directly coupled to other components of apparatus 600 or accessed via a network, and can include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Therefore, apparatus 600 can have various configurations.

[0191] It can be understood that after encoding a video and / or an image, a bitstream is obtained. The bitstream (or referred to as a code stream) includes one or more consecutive access units (AUs). Generally, one AU includes encoded data of one or more images. An access unit AU includes a set of network abstract layer units (NAL units), that is, NAL units, which are associated with each other according to specified rules.

[0192] The NAL unit includes different types of NAL units. The bitstream includes a NAL unit type flag (nal_unit_type), which is a 5-bit unsigned integer. The nal_unit_type indicates the type of the RBSP data structure in the NAL unit. Referring to Table 1 below, the NAL unit type flag and the type of the raw byte sequence payload (RBSP) data structure in the NAL unit are shown.

[0193] Table 1. NAL Unit Type Table

[0194]

[0195]

[0196] Combined with Table 1, some technical terms related to the embodiments of the present application are introduced first.

[0197] 1. Knowledge Image (library picture)

[0198] Each frame of image corresponds to a sequence parameter set, and the image whose knowledge bitstream flag in the corresponding sequence set parameter is 1. Referring to Table 1, the video coding layer NAL unit type of the knowledge image is 12, 17 or 18.

[0199] The knowledge bitstream flag (library_stream_flag) is a binary variable. The value of '1' indicates that the current sequence parameter set is the sequence parameter set corresponding to the knowledge image; the value of '0' indicates that the current sequence parameter set is the sequence parameter set corresponding to the display image. The value of LibraryStreamFlag is equal to the value of library_stream_flag.

[0200] Among them, the knowledge image mode index (library_picture_mode_index) is a 2-bit unsigned integer, and the value range is 0 to 3. It indicates the knowledge image mode. The value of '0' represents the knowledge image single-stream mode, the value of '1' represents the long-term reference image mode, the value of '2' represents the knowledge image dual-stream mode, and the value of '3' is reserved.

[0201] 2. Display Knowledge Image (output library picture)

[0202] Each frame of image corresponds to a sequence parameter set, and the image whose knowledge bitstream flag is 1 and the knowledge image mode index is 1 in the corresponding sequence set parameter. Referring to Table 1, the video coding layer NAL unit type of the display knowledge image is 17. The display knowledge image is a random access point image.

[0203] 3. Non-display knowledge image (non output library picture)

[0204] Each frame of image corresponds to a sequence parameter set, and the images whose knowledge bitstream flag is 1 and knowledge picture mode index is 0 or 2 in the corresponding sequence set parameters. Referring to Table 1, the NAL unit type of the video coding layer of the non-display knowledge image is 12 or 18.

[0205] 4. RL image (reference library picture, efrence library picture)

[0206] A P picture or a B picture that only uses knowledge pictures as reference pictures for inter-frame prediction decoding. An RL picture is a random access point picture. If the first decoded picture after the NAL unit of the sequence parameter set corresponding to the current displayed picture is an RL picture, and the display order of the current displayed picture is after this RL picture, then the reference pictures of the current displayed picture should be within the following range: this RL picture, the displayed pictures whose display order is after this RL picture, and the knowledge pictures referred to by this RL picture.

[0207] Among them, a P picture is a picture that can use knowledge pictures and pictures in the past in the display order as reference pictures for decoding in inter-frame prediction. A B picture is a picture that can use knowledge pictures, pictures in the past and future in the display order as reference pictures for decoding in inter-frame prediction.

[0208] 5. Leading library picture of an RL picture

[0209] A non-display knowledge picture before an RL picture in the bitstream order. All knowledge bitstream slices of this non-display knowledge picture are consecutive in the bitstream order, and there is no access unit of other pictures between the first knowledge bitstream slice and the access unit of the RL picture.

[0210] Some syntax elements included in the bitstream include but are not limited to the following:

[0211] 1. Library_stream_flag

[0212] A binary variable. A value of '1' indicates that the current sequence parameter set is the sequence parameter set corresponding to a knowledge picture; a value of '0' indicates that the current sequence parameter set is the sequence parameter set corresponding to a displayed picture. The value of LibraryStreamFlag is equal to the value of library_stream_flag

[0213] 2. Library_picture_mode_index

[0214] Unsigned 2-bit integer, with a value range of 0 to 3. It indicates the knowledge image mode. A value of '0' represents the knowledge image single-stream mode, a value of '1' represents the long-term reference image mode, a value of '2' represents the knowledge image dual-stream mode, and the value '3' is reserved. The value of LibraryPictureModeIndex is equal to the value of library_picture_mode_index. If library_picture_mode_index does not exist in the bitstream, the value of LibraryPictureModeIndex is equal to 0.

[0215] It should be noted that in the knowledge image single-stream mode, only non-display knowledge images are allowed to exist in the encoded video sequence, and display knowledge images are not allowed. The NAL units of the non-display knowledge image coded slices and the NAL units of the display image coded slices are interleaved to form an encoded video sequence. In the long-term reference mode, only display knowledge images are allowed to exist in the encoded video sequence, and non-display knowledge images are not allowed. All the NAL units of the display knowledge images are consecutive in ascending order of the slice index and should not be interleaved with the access units of the display images. In the knowledge image dual-stream mode, only the display image coded NAL units are allowed to exist in the main bitstream encoded video sequence, and only the knowledge image coded slice NAL units are allowed to exist in the knowledge bitstream encoded image sequence. It is determined whether the current encoded video sequence is in the main bitstream or the knowledge bitstream according to LibraryStreamFlag.

[0216] 3. Encryption flag (encryption_idc)

[0217] Binary variable. Indicates whether the NAL unit is encrypted. A value of '0' means that the RBSP in this NAL unit is not encrypted, and a value of '1' means that the RBSP in this NAL unit is encrypted according to the encryption method specified in the security parameter set with the RBSP as the basic data unit. The last byte of the RBSP is not encrypted.

[0218] 4. Authentication flag (authentication_idc)

[0219] Binary variable. Indicates whether the NAL unit is authenticated. A value of '0' means that this NAL unit is not authenticated, and a value of '1' means that this NAL unit is authenticated according to the authentication method specified in the security parameter set, and the absolute time extension information must be carried in the encoded bitstream to identify the authentication time.

[0220] Combining the above content, during the video / image encoding and decoding process, the bitstream received at the decoding end may be the bitstream that has not been processed (or edited) by the encoding end after encoding the video / image (which can be understood as the original bitstream), or the bitstream may also be the bitstream processed by the encoding end from the original bitstream, or the bitstream processed by other devices. For the display knowledge image in the bitstream, the decoding end may not be able to determine whether the display knowledge image needs to be displayed. For example, in one case, after bitstream editing of the display knowledge image, it can be used as the RL pre-knowledge image, and at this time, the display knowledge image does not need to be displayed.

[0221] To facilitate the decoding side to efficiently determine whether a display knowledge image needs to be displayed, an embodiment of the present application provides a decoding method, which can add indication information in the bitstream to indicate whether the display knowledge image needs to be displayed (whether the display knowledge image within the same access unit is displayed).

[0222] Combining the above content, the following is a detailed description of the decoding method provided by the embodiment of the present application with the decoding end as the execution subject.

[0223] As Figure 7 shown, an embodiment of the present application provides a decoding method, which can be applied to the decoder 30 (or the video decoder 30) in the above Figure 1a 、 Figure 1b or Figure 3 . The method includes S701 - S703.

[0224] S701. Parse the bitstream to obtain the display knowledge encoded image and the display indication information, where the display indication information is used to indicate whether to display the display knowledge image after decoding the display knowledge encoded image.

[0225] In the embodiment of the present application, the bitstream obtained by the decoding end can be the bitstream obtained from the encoding end or the bitstream obtained from other devices, and the bitstream can be the original bitstream or the edited bitstream. The decoding end can parse the encoded image and some syntax elements from the received bitstream.

[0226] For the display knowledge image in the video sequence, after encoding the display knowledge image, the display knowledge encoded image is obtained. In the embodiment of the present application, when the bitstream contains the display knowledge encoded image, the bitstream also carries the display indication information of the display knowledge image. After the decoding end parses the display indication information from the bitstream, it can determine whether to display the decoded display knowledge image according to the display indication information.

[0227] In one implementation, the supplementary enhancement information in the bitstream includes the above-mentioned display indication information (i.e., the display indication information is carried in the supplementary enhancement information). Specifically, refer to Table 2 and Table 3 below. Table 2 is the definition of the supplementary enhancement payload syntax, and Table 3 is the definition of the display knowledge image display information payload syntax.

[0228] Table 2

[0229]

[0230] Table 3

[0231]

[0232] According to Table 2, in the payload of the supplementary enhancement information, the payload with a payload type (i.e., PayloadType) of 26 contains the display information of the display knowledge image (such as library_display_info). According to Table 3, the library_display_info includes the display information of the display knowledge image, specifically the display knowledge image display flag (library_display_flag) in Table 3. The library_display_flag is a binary variable. When the value of the library_display_flag is '1', it indicates that the display knowledge image of the current access unit needs to be displayed. When the value of the library_display_flag is '0', it indicates that the display knowledge image of the current access unit does not need to be displayed. The value of LibraryDisplayFlag is equal to the value of the library_display_flag. If the library_display_flag does not exist in the bitstream, the value of LibraryDisplayFlag is equal to 1.

[0233] S702. Decode the display knowledge encoded image to obtain the display knowledge image.

[0234] In the embodiments of the present application, after parsing the display knowledge encoded image and some syntax information from the bitstream, and performing operations such as decoding, inverse quantization, inverse transformation, and filtering on the display knowledge encoded image in combination with the syntax information, the display knowledge image is obtained. For a detailed description of the decoding process of the display knowledge encoded image, reference can be made to the prior art materials, and the present application will not elaborate.

[0235] S703. Determine whether to display the display knowledge image according to the display indication information.

[0236] When the value of LibraryDisplayFlag for displaying the knowledge image is 1, the decoding end displays the knowledge image; when the value of LibraryDisplayFlag for displaying the knowledge image is 0, the decoding end does not display the knowledge image.

[0237] The following describes the detailed process of the output image (i.e., the display image) at the decoding end. Specifically, the following steps are executed to output the decoded image (the decoded image in the embodiments of the present application is the knowledge image).

[0238] 1. If the value of LibraryStreamFlag for the current sequence is equal to 1 (indicating that the current sequence parameter set is the sequence parameter set corresponding to the knowledge image), and the value of LibraryPictureModeIndex is equal to 2 (indicating the knowledge image dual-stream mode), then output the current decoded image and the corresponding LibraryPictureIndex (knowledge image index) to the external knowledge image buffer.

[0239] 2. Otherwise (that is, the value of LibraryStreamFlag is equal to 1 (indicating that the current sequence parameter set is the sequence parameter set corresponding to the knowledge image), and the value of LibraryPictureModeIndex is equal to 0 or 1 (indicating the knowledge image single-stream mode or the long-term reference image mode); or, the value of LibraryStreamFlag is equal to 0 (indicating that the current sequence parameter set is the sequence parameter set corresponding to the display image), and the value of LibraryPictureModeIndex is equal to 0 or 1 or 2), execute the following steps 1)-2).

[0240] Step 1) Mark the "outputable" image:

[0241] Search for a display image in the decoded image buffer that is marked as "not output" and the sum of the decoding order index (decode order index, DOI) and the image output delay is less than or equal to the decoding order index DOI of the current image. If it exists, mark this image as "outputable". It can be understood that the sum of the decoding order index and the image output delay is the display order index of this display image. The image output delay represents the time to wait from the completion of image decoding to output.

[0242] Search for a display knowledge image in the decoded image buffer that is marked as "not output" and the sum of the decoding order index and the image output delay is less than or equal to DOI. If it exists and the value of LibraryDisplayFlag is equal to 1, mark this image as "outputable".

[0243] Search for non-display knowledge images in the decoded image buffer. If any exist, mark the current decoded image as "not outputtable".

[0244] Search for display knowledge images in the decoded image buffer. If any exist and the value of LibraryDisplayFlag is equal to 0, mark the current decoded image as "not outputtable".

[0245] If the value of the image output delay PictureOutputDelay is 0, mark the current decoded image as "outputtable".

[0246] Step 2) If there are "outputtable" images, output the image with the smallest display order index among the "outputtable" images, and mark this image as "output".

[0247] It should be noted that if the RL pre-knowledge image is a display knowledge image, the display knowledge image does not need to be output at this time. It can be identified through the display information SEI payload of the display knowledge image (library_display_flag should be '0'), that is, the display indication information library_display_flag is carried in the SEI (Supplemental Enhancement Information) to indicate that there is no need to display.

[0248] In one implementation, the above display indication information is carried in the supplemental enhancement information. Correspondingly, the constraints between the access unit and the NAL unit are as follows:

[0249] 1) If there is a NAL unit with nal_unit_type equal to 15 (indicating the coding picture boundary), it must be the starting NAL unit of the access unit, and there is at most one NAL unit with nal_unit_type equal to 15 in one access unit.

[0250] 2) If there is a NAL unit with nal_unit_type equal to 16 (indicating the end of the coded video sequence) and there is no NAL unit with nal_unit_type equal to 11 after this NAL unit, then this NAL unit should be the last NAL unit of the access unit.

[0251] 3) If there is a NAL unit with nal_unit_type equal to 11 (indicating the end of the stream), then this NAL unit should be the last NAL unit of the access unit.

[0252] 4) If there is a NAL unit with nal_unit_type equal to 19 (indicating an encoded slice of a privacy image), the access order of this NAL unit shall be after the access units with nal_unit_type equal to 0, 1, 2, 12, 14, 17.

[0253] 5) If there is a NAL unit with nal_unit_type equal to 6 (indicating supplementary enhancement information) and PayloadType equal to 127, it shall be transmitted in each access unit where the first picture in a sequence and random access point pictures are located, and before the first coded slice NAL unit (FirstCrrCpNalUnit) of this access unit.

[0254] 6) If there is a NAL unit with nal_unit_type equal to 6 (indicating supplementary enhancement information) and PayloadType equal to 26 (indicating that this NAL unit carries display indication information for a display knowledge picture), then this NAL unit shall only appear in the access unit of the display knowledge picture.

[0255] In one implementation, the above display indication information is carried in the supplementary enhancement information, and the encryption method of this display indication information can be indicated by an encryption flag (encryption_idc).

[0256] When the nal_unit_type of a NAL unit is 11 (indicating end of stream), 15 (indicating coded picture boundary), 16 (indicating end of coded video sequence), the encryption_idc shall be 0 (indicating that the RBSP in this NAL unit is not encrypted).

[0257] When the nal_unit_type of a NAL unit is 6 and it contains a payload with PayloadType equal to 26 (carrying display indication information), the encryption_idc shall be 0. That is to say, the encryption flag of the NAL unit containing display indication information is the second value (i.e., 0), and the second value is used to indicate that the NAL unit containing display indication information is not encrypted. Specifically, the second value is used to indicate to the decoding end that the encoding end has not encrypted the NAL unit containing display indication information. In this way, the decoding end does not need to decrypt the NAL unit containing display indication information.

[0258] In one implementation, the above display indication information is carried in the supplementary enhancement information, and the authentication method of this display indication information can be indicated by an authentication flag (authentication_idc).

[0259] When the nal_unit_type of a NAL unit is 11, 15 or 16, the authentication_idc shall be 0 (indicating that the RSRP in this NAL unit is not authenticated).

[0260] When the nal_unit_type of a NAL unit is 6 and it contains a payload with PayloadType equal to 26 (carrying display indication information), the authentication_idc shall be 0. That is to say, the authentication flag of the NAL unit containing display indication information is the first value (i.e., 0), and the first value is used to indicate that the NAL unit containing display indication information is not authenticated. Specifically, the first value is used to indicate to the decoding end that the NAL unit containing display indication information is not authenticated. In this way, the decoding end does not need to authenticate the NAL unit containing display indication information.

[0261] In one implementation, the above display indication information is carried in the supplementary enhancement information, and the layer where the display indication information is located can be restricted by the layer identifier.

[0262] Layer identifier layer_id: A 2-bit unsigned integer. It indicates the layer identifier of the current image. The value range of the layer identifier is 0 to MAX_LAYERS - 1. The layer_id of the sequence parameter set and the picture parameter set NALU (NALU represents NAL unit) is 0. The layer_id of the picture header NAL unit and all coded slice NAL units of a coded picture should be the same. The value of LayerId is equal to the value of layer_id. Note: MAX_LAYERS is specified by the profile.

[0263] When the nal_unit_type of a NAL unit is 6 and it contains a payload with PayloadType equal to 26, the layer_id shall be 0 (that is, the Layer_id corresponding to the NAL unit where the display indication information is located is 0).

[0264] In summary, in the decoding method provided by the embodiments of the present application, since the display indication information indicating whether the display knowledge image needs to be displayed can be parsed from the bitstream, it is not necessary to determine whether the display knowledge image is to be displayed after decoding the next image. This method can quickly and efficiently determine whether the display knowledge image needs to be displayed.

[0265] It can be understood that, in order to implement the above functions, the decoding device includes corresponding hardware and / or software modules for executing each function. Combining the algorithm steps of each example described in the embodiments disclosed in this article, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0266] The embodiments of the present application can divide the functional modules of the decoding device according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is illustrative, only a logical function division, and there can be other division methods in actual implementation.

[0267] In the case of dividing each functional module corresponding to each function, Figure 8 shows a possible composition schematic diagram of the decoding device involved in the above embodiment, as Figure 8 shown, the decoding device 800 may include: a parsing module 801, a decoding module 802, and a determination module 803.

[0268] The parsing module 801, the decoding module 802, and the determination module 803 cooperate to execute the steps of S701 - S703 in the above method embodiment.

[0269] The embodiments of the present application also provide a chip. Figure 9 shows a structural schematic diagram of a chip 900. The chip 900 includes one or more processors 901 and an interface circuit 902. Optionally, the above chip 900 may further include a bus 903.

[0270] The processor 901 may be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above decoding method can be completed through the integrated logic circuit in the processor 901 or instructions in software form.

[0271] Optionally, the above-mentioned processor 901 may be a general-purpose processor, a digital signal processing (DSP) processor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, and can implement or execute the various methods and steps disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor, etc.

[0272] The interface circuit 902 may be used for sending or receiving data, instructions, or information. The processor 901 may process the data, instructions, or other information received by using the interface circuit 902, and may send the processed information out through the interface circuit 902.

[0273] Optionally, the chip further includes a memory, which may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A part of the memory may also include a non-volatile random access memory (NVRAM).

[0274] Optionally, the memory stores an executable software module or a data structure, and the processor may execute corresponding operations by calling the operation instructions stored in the memory (the operation instructions may be stored in the operating system).

[0275] Optionally, the chip may be used in the encoding device involved in the embodiments of the present application. Optionally, the interface circuit 902 may be used to output the execution result of the processor 901. For the decoding method provided by one or more embodiments of the present application, reference may be made to the foregoing respective embodiments, and details are not described herein again.

[0276] It should be noted that the respective functions corresponding to the processor 901 and the interface circuit 902 may be implemented through hardware design, may also be implemented through software design, or may be implemented through a combination of software and hardware, and no limitation is made herein.

[0277] Figure 10 This is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 1000 may be a processor, a chip, or a functional module in the processor. As Figure 10 shown, the electronic device 1000 includes a processor 1001, a transceiver 1002, and a communication line 1003.

[0278] Among them, the processor 1001 is used to execute any step in the decoding method provided by the embodiments of the present application. During the execution of any step in the decoding method provided by the embodiments of the present application, the transceiver 1002 and the communication line 1003 can be selectively called to complete the corresponding operations.

[0279] Further, the electronic device 1000 may further include a memory 1004. Among them, the processor 1001, the memory 1004, and the transceiver 1002 can be connected through the communication line 1003.

[0280] Among them, the processor 1001 is a processor, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 1001 can also be other devices with processing functions, such as circuits, devices, or software modules, without limitation.

[0281] The transceiver 1002 is used to communicate with other devices or other communication networks. The other communication networks can be Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc. The transceiver 1002 can be a module, a circuit, a transceiver, or any device capable of implementing communication.

[0282] The transceiver 1002 is mainly used for the transmission and reception of commands and information, etc. It can include a transmitter and a receiver, which are used for the transmission and reception of commands and information, etc. respectively; operations other than the transmission and reception of commands and information, etc. are implemented by the processor.

[0283] The communication line 1003 is used to transmit information between the components included in the electronic device 1000.

[0284] In one design, the processor can be regarded as a logic circuit, and the transceiver can be regarded as an interface circuit.

[0285] The memory 1004 is used to store instructions. Among them, the instructions can be computer programs.

[0286] Among them, the memory 1004 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM). The memory 1004 can also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, etc. It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0287] It should be noted that the memory 1004 can exist independently of the processor 1001 or can be integrated with the processor 1001. The memory 1004 can be used to store instructions, program codes, or some data, etc. The memory 1004 can be located inside the electronic device 1000 or outside the electronic device 1000, without limitation. The processor 1001 is used to execute the instructions stored in the memory 1004 to implement the method provided in the foregoing embodiments of the present application.

[0288] In one example, the processor 1001 can include one or more processors, such as Figure 10 processor 0 (CPU0) and processor 1 (CPU1) in

[0289] As an alternative implementation, the electronic device 1000 includes multiple processors. For example, in addition to the processor 1001 in Figure 10 , the processor 1007 may also be included.

[0290] As an alternative implementation, the electronic device 1000 further includes an output device 1005 and an input device 1006. Exemplarily, the input device 1006 is a device such as a keyboard, a mouse, a microphone, or a joystick, and the output device 1005 is a device such as a display screen or a speaker.

[0291] It should be noted that the electronic device 1000 may be a chip system or a device with a Figure 10 similar structure. Among them, the chip system may be composed of chips or may include chips and other discrete devices. Actions, terms, etc. involved between the embodiments of the present application may be referred to each other without limitation. The message names or parameter names in the messages exchanged between the devices in the embodiments of the present application are only examples, and other names may also be adopted in specific implementations without limitation. In addition, Figure 10 the shown component structure does not constitute a limitation on the electronic device 1000. Except for Figure 10 the shown components, the electronic device 1000 may include more or fewer components than Figure 10 shown, or combine some components, or have different component arrangements.

[0292] The processors and transceivers described in the present application may be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processors and transceivers may also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (PMOS), bipolar junction transistor (BJT), BiCMOS, silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0293] Figure 11The figure is a schematic structural diagram of a decoding device provided by an embodiment of the present application. The decoding device can be applied to the scenarios shown in the above method embodiments. For ease of description, Figure 11 only the main components of the decoding device are shown, including a processor 1101, a memory 1102, a control circuit 1103, and an input / output device 1104. The processor 1101 is mainly used for processing communication protocols and communication data, executing software programs, and processing data of software programs. The memory 1102 is mainly used for storing software programs and data. The control circuit 1103 is mainly used for power supply and transmission of various electrical signals. The input / output device 1104 is mainly used for receiving data input by users and outputting data to users.

[0294] When the decoding device is the processor 1101, the control circuit 1103 can be a main board, the memory 1102 includes storage media with storage functions such as a hard disk, RAM, and ROM, the processor 1101 can include a baseband processor 1101 and a central processor. The baseband processor is mainly used for processing communication protocols and communication data, and the central processor is mainly used for controlling the entire decoding device, executing software programs, and processing data of software programs. The input / output device 1104 includes a display screen, a keyboard, a mouse, etc.; the control circuit 1103 can further include or be connected to a transceiver circuit or a transceiver, for example: a network interface, etc., for sending or receiving data or signals, for example, for data transmission and communication with other devices. Further, an antenna can also be included for wireless signal transmission and reception, for data / signal transmission with other devices.

[0295] An embodiment of the present application also provides a decoding device, which includes: at least one processor, when the at least one processor executes program code or instructions, the above-mentioned related method steps are implemented to realize the decoding method in the above embodiment.

[0296] Optionally, the device can further include at least one memory, and the at least one memory is used for storing the program code or instructions.

[0297] An embodiment of the present application also provides a computer storage medium, in which computer instructions are stored. When the computer instructions run on the decoding device, the decoding device is enabled to execute the above-mentioned related method steps to realize the decoding method in the above embodiment.

[0298] An embodiment of the present application also provides a computer program product. When the computer program product runs on a computer, the computer is enabled to execute the above-mentioned related steps to realize the decoding method in the above embodiment.

[0299] The embodiments of the present application further provide a decoding device, which may specifically be a chip, an integrated circuit, a component or a module. Specifically, the device may include a processor connected to a memory for storing instructions, or the device includes at least one processor for obtaining instructions from an external memory. When the device runs, the processor may execute the instructions to cause the chip to execute the decoding method in each of the above method embodiments.

[0300] In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that the computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (such as a floppy disk, a magnetic disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state drive (SSD)), etc.

[0301] Through the description of the above embodiments, those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional module is used as an example. In actual applications, the above functions may be allocated to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working processes of the systems, devices and units described above may refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0302] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0303] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0304] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0305] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes such as flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk, or optical disc.

[0306] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A decoding method, characterized in that, Including: Analyze the bitstream to obtain the display knowledge encoded image and display indication information; The display indication information is used to indicate whether to display the display knowledge image obtained after decoding the display knowledge encoded image; Decode the display knowledge encoded image to obtain a display knowledge image; Determine whether to display the display knowledge image according to the display indication information.

2. The method according to claim 1, wherein: The display indication information is included in the supplementary enhancement information in the bitstream.

3. The method according to claim 1 or 2, wherein: The authentication flag of the network abstraction layer (NAL) unit including the display indication information is a first value, and the first value is used to indicate that the NAL unit including the display indication information is not authenticated.

4. The method according to any one of claims 1 to 3, wherein: The encryption flag of the NAL unit including the display indication information is a second value, and the second value is used to indicate that the NAL unit including the display indication information is not encrypted.

5. The method according to any one of claims 1 to 4, wherein: The NAL unit of the network abstraction layer including the display indication information is carried in the bitstream of the first layer of the display knowledge image.

6. The method according to claim 3, wherein: The first value is specifically used to indicate to the decoding end that the NAL unit including the display indication information is not authenticated.

7. The method according to claim 4, wherein: The second value is specifically used to indicate to the decoding end that the encoding end has not encrypted the NAL unit including the display indication information.

8. A decoding device, comprising at least one processor and a memory, characterized in that, The at least one processor executes the program or instruction stored in the memory so that the device implements the method according to any one of claims 1 to 7 above.

9. A computer-readable storage medium for storing a computer program, characterized in that, When the computer program runs on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 7 above.

10. A computer program product comprising instructions, characterized in that, When the instruction runs on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 7 above.

11. A chip, comprising at least one processor and a memory, characterized in that, The at least one processor executes the program or instruction stored in the memory so that the chip implements the method according to any one of claims 1 to 7 above.

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