Semiconductor device and preparation method thereof, memory system and signal generation method

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, a memory system and a signal generation method for the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a differential interconnect structure. The first semiconductor structure includes a first circuit. The second semiconductor structure is located on one side of the first semiconductor structure and comprises a plurality of sub-semiconductor structures stacked in the first direction. The plurality of differential interconnection structures are arranged corresponding to the plurality of sub-semiconductor structures, extend along a first direction, and comprise first conductive structures and second conductive structures which are adjacently arranged in a direction intersected with the first direction; the first conductive structure and the second conductive structure are respectively connected with the first circuit and the corresponding sub-semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and fabrication, and more particularly, to semiconductor devices, methods for fabricating semiconductor devices, memory systems, and signal generation methods for semiconductor devices. Background Art

[0002] Memory is one of the important components in an electronic system. Taking memory as an example, a semiconductor device may include memory cells composed of capacitors and transistors, and multiple memory cells may be arranged in the form of a two-dimensional array. To further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor (VGT). In this structure, the source and drain of the transistor are respectively located at both ends of the extension direction of the channel of the transistor, and the gate structure of the transistor is at least located on one side of the channel.

[0003] With the rapid development of semiconductor technology, how to improve the storage density of semiconductor devices such as memory, optimize their comprehensive performance, and reduce their process costs is one of the important research directions in the industry. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above problems or other problems in this field.

[0005] On the one hand, this application provides a semiconductor device, which includes: a first semiconductor structure including a first circuit; a second semiconductor structure located on one side of the first semiconductor structure and including a plurality of sub-semiconductor structures stacked along a first direction; and a differential interconnect structure, where a plurality of the differential interconnect structures are correspondingly arranged with the plurality of sub-semiconductor structures. Among them, the differential interconnect structure extends along the first direction and includes a first conductive structure and a second conductive structure that are adjacent to each other in a direction intersecting the first direction. Both the first conductive structure and the second conductive structure are respectively connected to the first circuit and the corresponding sub-semiconductor structure.

[0006] In an embodiment of this application, in the direction intersecting the first direction, the sizes of the first conductive structure and the second conductive structure are the same; and the first conductive structure and the second conductive structure include the same conductive material.

[0007] In one embodiment of the present application, in a direction intersecting the first direction, the distance between the first conductive structure and the second conductive structure of the same differential interconnect structure is less than the distance between adjacent differential interconnect structures, where the distance between adjacent differential interconnect structures includes: the distance between first conductive structures that belong to different differential interconnect structures and are adjacent to each other; the distance between second conductive structures that belong to different differential interconnect structures and are adjacent to each other; and the distance between a first conductive structure and a second conductive structure that belong to different differential interconnect structures and are adjacent to each other.

[0008] In one embodiment of the present application, at least one of the plurality of sub-semiconductor structures includes a second circuit and a memory array connected to the second circuit, where the differential interconnect structure connects at least one of the second circuit and the memory array of the corresponding sub-semiconductor structure to the first circuit.

[0009] In one embodiment of the present application, a first connection layer is provided between the first semiconductor structure and the second semiconductor structure, and the first connection layer includes a bonding layer. Wherein, the semiconductor structure further includes a second interconnect structure that passes through the first connection layer along the first direction, and the second interconnect structure connects the first circuit and the differential interconnect structure.

[0010] In one embodiment of the present application, the plurality of sub-semiconductor structures of the second semiconductor structure include a first sub-semiconductor structure and the remaining sub-semiconductor structures located between the first semiconductor structure and the first sub-semiconductor structure along the first direction. Wherein, the differential interconnect structure corresponding to the first sub-semiconductor structure extends along the first direction and passes through the remaining sub-semiconductor structures, and is connected to the first circuit.

[0011] In one embodiment of the present application, the first sub-semiconductor structure includes a first region and a second region that are adjacent and distributed in a direction intersecting the first direction. Wherein, the second circuit and the memory array of the first sub-semiconductor structure are located in the first region; and the differential interconnect structure corresponding to the first sub-semiconductor structure is located in the second region and extends along the first direction through the remaining sub-semiconductor structures.

[0012] In an embodiment of the present application, the remaining sub-semiconductor structures include a second sub-semiconductor structure closest to the first semiconductor structure in the first direction. Wherein, the second sub-semiconductor structure includes a first portion and a second portion arranged along the first direction, the first portion is closer to the first semiconductor structure than the second portion, a differential interconnect structure corresponding to the second sub-semiconductor structure is located in the first portion, extends along the first direction, and is connected to the first circuit; and one of the first portion and the second portion includes a second circuit, and the other of the first portion and the second portion includes a memory array connected to the second circuit.

[0013] In an embodiment of the present application, the first semiconductor structure further includes a first substrate, the first circuit is disposed on one side of the first substrate, and the first substrate is away from the second semiconductor structure relative to the first circuit; and / or at least one of the plurality of sub-semiconductor structures further includes a second substrate, a second circuit, and a memory array, the second circuit and the memory array are disposed on one side of the second substrate, and the second substrate is away from the first semiconductor structure relative to at least one of the second circuit and the memory array.

[0014] In an embodiment of the present application, adjacent sub-semiconductor structures are directly bonded; and / or a second connection layer is provided between adjacent sub-semiconductor structures, wherein the second connection layer includes a bonding layer.

[0015] In an embodiment of the present application, the memory array includes at least one of a non-volatile memory cell and a volatile memory cell.

[0016] In an embodiment of the present application, the volatile memory cell includes a vertical transistor and a memory cell connected to the vertical transistor. Wherein, along the first direction, the vertical transistor is closer to the second circuit than the memory cell.

[0017] In an embodiment of the present application, the differential interconnect structure further includes an isolation layer and a dielectric filling layer. Wherein, the isolation layer is disposed around the first conductive structure and the second conductive structure; and the dielectric filling layer is located between the isolation layer and the first conductive structure or between the isolation layer and the second conductive structure.

[0018] In one embodiment of the present application, the first circuit includes a first differential pair circuit and a second differential pair circuit connected in reverse, wherein the first differential pair circuit includes a first switch unit, and a first input port and a fourth input port belonging to the first switch unit are connected to the first conductive structure; and the second differential pair circuit includes a second switch unit, and a second input port and a third input port belonging to the second switch unit are connected to the second conductive structure.

[0019] In one embodiment of the present application, the first circuit further includes a common constant current source, a first current negative feedback circuit, and a second current negative feedback circuit, wherein the first current negative feedback circuit is connected to the first switch unit and the common constant current source, and the second current negative feedback circuit is connected to the second switch unit and the common constant current source.

[0020] On the other hand, the present application provides a method for manufacturing a semiconductor device, the method including: stacking a plurality of sub-semiconductor structures along a first direction to form a second semiconductor structure; forming a plurality of differential interconnect structures corresponding to the plurality of sub-semiconductor structures, wherein the differential interconnect structures extend along the first direction and include a first conductive structure and a second conductive structure adjacent to each other in a direction intersecting the first direction, and one end of the first conductive structure and one end of the second conductive structure are respectively connected to the sub-semiconductor structure corresponding to the differential interconnect structure; and disposing a first semiconductor structure on one side of the second semiconductor structure, wherein the first semiconductor structure includes a first circuit, and the other end of the first conductive structure and the other end of the second conductive structure are connected to the first circuit.

[0021] In one embodiment of the present application, disposing a first semiconductor structure on one side of the second semiconductor structure includes: forming a first connection layer on one side of the second semiconductor structure, wherein the first connection layer includes a bonding layer; forming a second interconnect structure passing through the first connection layer along the first direction, one end of the second interconnect structure being connected to the differential interconnect structure; and disposing the first semiconductor structure on one side of the first connection layer, wherein the other end of the second interconnect structure is connected to the first circuit.

[0022] In one embodiment of the present application, forming a plurality of differential interconnect structures corresponding to the plurality of sub-semiconductor structures includes: using an etching process to form openings for accommodating the differential interconnect structures, the plurality of openings respectively extending from a surface of the second semiconductor structure along the first direction to different sub-semiconductor structures, wherein the etching time for the openings extending to different sub-semiconductor structures is different.

[0023] In one embodiment of the present application, forming a plurality of differential interconnect structures corresponding to the plurality of sub-semiconductor structures further includes: filling the opening with a dielectric filling layer; forming a first sub-opening and a second sub-opening in the dielectric filling layer, which respectively extend along the first direction and have the same extension length; and filling the first sub-opening and the second sub-opening with a conductive material to form the first conductive structure and the second conductive structure, wherein, in a direction intersecting the first direction, the sizes of the first sub-opening and the second sub-opening are the same.

[0024] In another aspect of the present application, a memory system is provided. The memory system includes the second semiconductor structure provided in one aspect of the present application and a controller. The controller includes a first circuit and controls the second semiconductor structure to store data through the first circuit.

[0025] In another aspect of the present application, a method for generating a signal of a semiconductor device is provided. The semiconductor device includes a first circuit and a differential interconnect structure. The differential interconnect structure includes a first conductive structure and a second conductive structure. The first circuit includes a first differential pair circuit and a second differential pair circuit connected in reverse. The first differential pair circuit includes a first switch unit connected to the first conductive structure, and the second differential pair circuit includes a second switch unit connected to the second conductive structure. The signal generation method includes: generating a pair of differential signals from the signals from the first conductive structure and the second conductive structure by switching the switch states of the first switch unit and the second switch unit.

[0026] According to the semiconductor device and manufacturing method, memory system, and signal generation method for a semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure having a first circuit and a second semiconductor structure serving as a memory. The plurality of sub-semiconductor structures of the second semiconductor structure can be interconnected with the first circuit of the first semiconductor structure by using a differential interconnect structure. Since the differential interconnect structure has characteristics such as a small pitch and anti-interference, using the differential interconnect structure for signal input and output can reduce crosstalk between transmitted signals and increase the signal transmission frequency of the semiconductor device. Description of the Drawings

[0027] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings. Among them:

[0028] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present application;

[0029] Figure 2is a cross-sectional view of a semiconductor device according to an embodiment of the present application;

[0030] Figure 3 is Figure 1 a top view schematic diagram of the semiconductor device shown taken along line A-A';

[0031] Figure 4 is a structural block diagram of an electronic device according to an embodiment of the present application;

[0032] Figure 5 is a cross-sectional view of a differential interconnect structure according to an embodiment of the present application;

[0033] Figure 6 is a schematic diagram of a differential circuit according to an embodiment of the present application;

[0034] Figure 7 is a schematic diagram of a differential signal according to an embodiment of the present application;

[0035] Figure 8 is a schematic diagram of a single-ended signal of an embodiment;

[0036] Figure 9 is a flowchart of a signal generation method for a semiconductor device according to an exemplary embodiment of the present application;

[0037] Figure 10 is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of the present application;

[0038] Figures 11 - 24 are process schematic diagrams of a method for fabricating a semiconductor device according to an embodiment of the present application, respectively; and

[0039] Figure 25 is a schematic diagram of a memory system structure according to an embodiment of the present application. Detailed Embodiments

[0040] For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features, especially do not represent any order. Therefore, without departing from the teachings of the present application, the second semiconductor structure discussed in the present application can also be referred to as the first semiconductor structure, and vice versa.

[0042] In the drawings, for ease of illustration, the thickness, dimensions and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to strict scale. As used herein, terms such as "substantially", "about" and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0043] It should also be understood that expressions such as "comprising", "including", "having", "containing" and / or "including having" are open-ended rather than closed-ended expressions in this specification, which means that the stated features, elements and / or components exist, but do not exclude the existence of one or more other features, elements, components and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just individual elements in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0044] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0045] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in this application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel.

[0046] In addition, when using "connected" or "coupled" in the present application, it may mean direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0047] The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0048] Some embodiments of the present application provide a semiconductor device. Figure 1 It is a cross-sectional view of a semiconductor device 1000 according to an embodiment of the present application. Figure 2 It is a cross-sectional view of a semiconductor device 1000 according to an embodiment of the present application. Figure 3 is Figure 1 A top view schematic diagram of the illustrated semiconductor device taken along line A-A'.

[0049] As Figures 1 - 3 As shown, the semiconductor device 1000 includes a first semiconductor structure 100, a second semiconductor structure 200, and a differential interconnect structure 230. The first semiconductor structure 100 includes a first circuit 110. The second semiconductor structure 200 is located on one side of the first semiconductor structure 100 and includes a plurality of sub-semiconductor structures stacked along a first direction (z direction). For example, the plurality of sub-semiconductor structures may include a first sub-semiconductor structure 201, a second sub-semiconductor structure 202, a third sub-semiconductor structure 203, a fourth sub-semiconductor structure 204, and so on. A plurality of differential interconnect structures 230 are correspondingly arranged with the plurality of sub-semiconductor structures. For example, the plurality of differential interconnect structures 230 may include a first differential interconnect structure 231, a second differential interconnect structure 232, a third differential interconnect structure 233, a fourth differential interconnect structure 234, and so on. Among them, the first differential interconnect structure 231 is correspondingly arranged with the first sub-semiconductor structure 201, the second differential interconnect structure 232 is with the second sub-semiconductor structure 202, the third differential interconnect structure 233 is correspondingly arranged with the third sub-semiconductor structure 203, and the fourth differential interconnect structure 234 is correspondingly arranged with the fourth sub-semiconductor structure 204, and so on. The differential interconnect structure 230 extends along the z direction and includes a first conductive structure 230-1 and a second conductive structure 230-2 that are adjacent to each other in a direction intersecting the first direction z (for example, the x direction or the y direction). Both the first conductive structure 230-1 and the second conductive structure 230-2 are respectively connected to the first circuit 110 and the corresponding sub-semiconductor structure.

[0050] Figure 4 It is a structural block diagram of an electronic device 9000 according to an embodiment of the present application. The electronic device 9000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (such as a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device with a memory.

[0051] As Figure 4As shown, the electronic device 9000 may include a memory system 910 and a host 920. Among them, the memory system 910 may be integrated into various types of storage devices, such as memory cards. Among them, memory cards include any one of PC cards (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC), Secure Digital Memory Cards (SD), and Universal Flash Storage (UFS). That is to say, the memory system 910 can be applied and encapsulated into different types of electronic products.

[0052] In some embodiments, the memory system 910 may include a controller 912 and a memory 911. The host 920 may include a processor of the electronic device 9000, such as a Central Processing Unit (CPU), or a System-on-Chip (SoC), such as an Application Processor (AP). The host 920 may be configured to send data to or receive data from the memory 911.

[0053] Optionally, the controller 912 may be configured to operate in a low-duty-cycle environment, such as SD cards, CF cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. Or, in some other examples, the controller 912 may be configured to operate in a high-duty-cycle environment such as SSDs or eMMCs, which are used as data storage for mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays. Or, in some examples, the controller 912 may be coupled to the memory 911 and the host 920 and be configured to control the data in the memory 911 and communicate with external devices (such as the host 920).

[0054] The number of memories 911 in the memory system 910 may be one or more. Figure 4The following uses three memories 911 as an example for illustration. The controller 912 can manage the data stored in each memory 911 and communicate with the host 920. The controller 912 can be configured to control the operations of each memory 911, such as read, write, and refresh operations. The controller 912 can also be configured to manage various functions regarding the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity that the computer system can use, the number of memory banks, the memory type and speed, the memory die data depth and data width, and other important parameters. Any other suitable functions can also be performed by the controller 912. The controller 912 can communicate with external devices (e.g., the host 920) according to a specific communication protocol. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnection (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer Small Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, etc.

[0055] Optionally, the memory system 910 can be the same as the semiconductor device 1000 described in any embodiment of the present application; or, the memory system 910 can include the semiconductor device 1000 described in any embodiment of the present application.

[0056] Optionally, the memory 911 can be the same as the sub-semiconductor structure of the second semiconductor structure 200 described in any embodiment of the present application; or, the memory 911 can include the sub-semiconductor structure of the second semiconductor structure 200 described in any embodiment of the present application.

[0057] Optionally, the controller 912 may be the same as the first semiconductor structure 100 described in any embodiment of the present application; or, the controller 912 may include the first semiconductor structure 100 described in any embodiment of the present application. As an option, the first circuit 110 of the first semiconductor structure 100 may include circuits related to operations such as reading, writing, and refreshing, as well as refresh control, timing control, command / request translation, buffering, scheduling, power management, etc.

[0058] As electronic technology continues to develop towards high frequency, high speed, and miniaturization, the interconnection structure between the memory and the controller has become one of the bottlenecks restricting the overall performance of the memory system. In at least one embodiment of the present application, a semiconductor device may include a first semiconductor structure having a first circuit and a second semiconductor structure serving as a memory. A plurality of sub-semiconductor structures of the second semiconductor structure are interconnected with the first circuit of the first semiconductor structure by using a differential interconnection structure. Since the differential interconnection structure has the characteristics of small pitch and anti-interference, using the differential interconnection structure for signal input and output can reduce crosstalk between signals, increase the signal transmission frequency of the semiconductor device, and optimize the comprehensive performance of the memory system.

[0059] Figure 5 is a cross-sectional view of a differential interconnection structure 230 according to an embodiment of the present application.

[0060] Specifically, as Figure 1 , Figure 3 and Figure 5 shown, in some embodiments of the present application, in a direction intersecting the z direction (for example, the x direction or the y direction), the size D1 of the first conductive structure 230-1 and the size D2 of the second conductive structure 230-2 may be the same. In addition, the first conductive structure 230-1 and the second conductive structure 230-2 may include the same conductive material. For example, both the first conductive structure 230-1 and the second conductive structure 230-2 may include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), polysilicon, silicide, or any combination thereof. The first conductive structure 230-1 and the second conductive structure 230-2 are respectively connected to the first circuit 110 and the corresponding sub-semiconductor structure. Therefore, reducing the differences in physical characteristics such as the size and material of the first conductive structure and the second conductive structure can effectively reduce signal loss or interference between signals caused by such differences.

[0061] Optionally, the differential interconnect structure 230 may further include an isolation layer 230-3 and a dielectric filling layer 230-6. The isolation layer 230-3 is disposed around the first conductive structure 230-1 and the second conductive structure 230-2. The dielectric filling layer 230-6 is located between the isolation layer 230-3 and the first conductive structure 230-1 or between the isolation layer 230-3 and the second conductive structure 230-2 to space the first conductive structure 230-1 and the second conductive structure 230-2 apart from each other.

[0062] In some embodiments of the present application, the isolation layer 230-3 may include any suitable dielectric material, such as, for example, an oxide, a nitride, a nitroxide, or a high dielectric constant (k) dielectric. For example, the isolation layer 230-3 may include a high-k dielectric. The dielectric filling layer 230-6 may include any suitable dielectric material, such as, for example, an oxide, a nitride, a nitroxide, or a high-k dielectric. For example, the dielectric filling layer 230-6 may include silicon oxide.

[0063] In addition, the differential interconnect structure 230 may further include a first adhesion layer 230-4 and a second adhesion layer 230-5. The first adhesion layer 230-4 is disposed around the first conductive structure 230-1, and the second adhesion layer 230-5 is disposed around the second conductive structure 230-2. In this case, the dielectric filling layer 230-6 fills the remaining space surrounded by the isolation layer 230-3. For example, a part of the dielectric filling layer 230-6 may be located between the first adhesion layer 230-4 and the second adhesion layer 230-5, a part of the dielectric filling layer 230-6 may be located between the first adhesion layer 230-4 and the isolation layer 230-3, and a part of the dielectric filling layer 230-6 may be located between the second adhesion layer 230-5 and the isolation layer 230-3.

[0064] In some embodiments of the present application, the first adhesion layer 230-4 and the second adhesion layer 230-5 may be made of the same material. For example, both the first adhesion layer 230-4 and the second adhesion layer 230-5 may include at least one of titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0065] In addition, referring again to Figure 3, in a direction intersecting the z - direction (e.g., the x - direction or the y - direction), the distance between the first conductive structure and the second conductive structure of the same differential interconnect structure is less than the distance between adjacent differential interconnect structures, where the distance between adjacent differential interconnect structures may include: the distance between first conductive structures that belong to different differential interconnect structures and are adjacent to each other; the distance between second conductive structures that belong to different differential interconnect structures and are adjacent to each other; and the distance between a first conductive structure and a second conductive structure that belong to different differential interconnect structures and are adjacent to each other. The fact that the distance between the first conductive structure and the second conductive structure of the same differential interconnect structure is less than the distance between adjacent differential interconnect structures can effectively reduce interference from adjacent differential interconnect structures.

[0066] Taking the first differential interconnect structure 231 and the second differential interconnect structure 232 as an example, in a direction intersecting the z - direction (e.g., the x - direction or the y - direction), the distance h1 between the first conductive structure 230 - 1 and the second conductive structure 230 - 2 of the first differential interconnect structure 231 is less than the distance h2 between the first conductive structure 230 - 1 of the first differential interconnect structure 231 and the first conductive structure 230 - 1 of the second differential interconnect structure 232; the distance h1 between the first conductive structure 230 - 1 and the second conductive structure 230 - 2 of the first differential interconnect structure 231 is less than the distance h3 between the second conductive structure 230 - 2 of the first differential interconnect structure 231 and the second conductive structure 230 - 2 of the second differential interconnect structure 232; the distance h1 between the first conductive structure 230 - 1 and the second conductive structure 230 - 2 of the first differential interconnect structure 231 is less than the distance h4 between the first conductive structure 230 - 1 of the first differential interconnect structure 231 and the second conductive structure 230 - 2 of the second differential interconnect structure 232.

[0067] Refer again to Figure 1 and Figure 2 , in some embodiments, at least one of the plurality of sub - semiconductor structures may include a second circuit 220 and a memory array 210 connected to the second circuit 220, where the differential interconnect structure 230 connects at least one of the second circuit 220 and the memory array 210 of the corresponding sub - semiconductor structure to the first circuit 110.

[0068] For example, taking the fourth sub - semiconductor structure 204 as an example, the fourth sub - semiconductor structure 204 includes a second circuit 220 and a memory array 210 connected to the second circuit 220, where the fourth differential interconnect structure 234 connects at least one of the second circuit 220 and the memory array 210 of the fourth sub - semiconductor structure 204 to the first circuit 110.

[0069] Optionally, in some embodiments, the storage array 210 may include a plurality of memory cells, such as at least one of non-volatile memory cells and volatile memory cells.

[0070] Taking the example that the storage array 210 includes a plurality of volatile memory cells, the volatile memory cells may include a transistor 211 and a storage cell 212 coupled to the transistor 211. For example, in some embodiments, the storage cell 212 may include a capacitor for storing charge as binary information stored by a corresponding DRAM (Dynamic Random Access Memory) cell. Additionally, in some embodiments, the storage cell 212 may include a PCM element (e.g., including a chalcogenide alloy) for storing binary information of a corresponding PCM cell based on different resistivities of the PCM (Phase Change Memory) element in the amorphous phase and the crystalline phase. Further, in some embodiments, the storage cell 212 may include a ferroelectric capacitor for storing binary information of a corresponding FRAM (Ferroelectric Random Access Memory) cell based on the switching between two polarization states of a ferroelectric material under an external electric field.

[0071] Optionally, the plurality of memory cells may be arranged in the form of a two-dimensional array to form the storage array 210. In some embodiments, in order to further reduce the size of the two-dimensional array, the transistor 211 may include a vertical gate transistor (VerticalGate Transistor, VGT, also simply referred to as a vertical transistor). In this structure, the source (not shown) and the drain (not shown) of the transistor are respectively located at both ends of the extension direction (e.g., the z direction) of the channel (not shown) of the transistor 211, and the gate structure (not shown) of the transistor 211 is at least on one side of the channel. For example, the transistor 211 may include a semiconductor body extending along the z direction and a gate structure located on at least one sidewall of the semiconductor body. In other words, in some embodiments of the present application, the transistor 211 may include at least one of a fully depleted surround gate transistor, a multi-gate transistor, and a single-gate transistor.

[0072] As an option, the vertical transistor 211 may be closer to the second circuit 220 along the z direction relative to the storage cell 212, so as to reduce the complexity of the interconnection wiring between the storage array and the second circuit, reduce the length of the interconnection wiring, and reduce the parasitic capacitance of the interconnection wiring.

[0073] In addition, optionally, the memory array 210 of the sub-semiconductor structure and the second circuit 220 connected to the memory array 210 may be formed on two different wafers (e.g., a memory array wafer and a peripheral circuit wafer) respectively, and then the peripheral circuit wafer and the memory array wafer are bonded together through a process such as wafer bonding, and the circuits of the second circuit 220 and the memory array 210 are connected together through interconnection wirings (interconnection paths or connection lines, etc.). In this case, the memory array wafer and the peripheral circuit wafer included in the sub-semiconductor structure may be connected through, for example, hybrid bonding, and the sub-semiconductor structure further includes a hybrid bonding layer (not shown) connecting the memory array wafer and the peripheral circuit wafer, and the hybrid bonding layer may be located between the memory array 210 and the second circuit 220.

[0074] Optionally, the memory array 210 of the sub-semiconductor structure and the second circuit 220 connected to the memory array 210 may also be formed on the same wafer. For example, at least one of the sub-semiconductor structures further includes a second substrate 240, the second circuit 220 is located on one side of the second substrate 240, and the memory array 210 is located on one side of the second circuit 220 and is in direct contact with the second circuit 220.

[0075] In addition, the first semiconductor structure 100 further includes a first substrate 120, and the first circuit 110 is located on one side of the first substrate 120. As an option, the first substrate 120 is farther from the second semiconductor structure 200 relative to the first circuit 110; as another option, the second substrate 240 is farther from the first semiconductor structure 100 relative to at least one of the second circuit 220 and the memory array 210; as still another option, the first substrate 120 is farther from the second semiconductor structure 200 relative to the first circuit 110, and the second substrate 240 is farther from the first semiconductor structure 100 relative to at least one of the second circuit 220 and the memory array 210. By disposing the first circuit close to the second semiconductor structure, or disposing the second circuit and the memory array of the sub-semiconductor structure close to the first semiconductor structure, the length of the differential interconnection structure can be shortened, the sensing tolerance of the differential interconnection structure can be improved, and the overall size of the semiconductor device can be reduced accordingly.

[0076] In addition, in some embodiments of the present application, a first connection layer 300 may be disposed between the first semiconductor structure 100 and the second semiconductor structure 200, the first connection layer 300 includes a bonding layer, and the semiconductor structure 1000 further includes a second interconnection structure 310 passing through the first connection layer 300 in the z direction, and the second interconnection structure 310 connects the first circuit 100 and the differential interconnection structure 230.

[0077] Optionally, the first semiconductor structure 100 and the second semiconductor structure 200 can be electrically and mechanically connected by, for example, hybrid bonding, and the first connection layer 300 can include a hybrid bonding layer (not shown). Optionally, the second interconnect structure 310 can include a conductive material layer, which includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof. For example, the second interconnect structure 310 can include a vertical interconnect access (VIA).

[0078] By connecting the first semiconductor structure and the second semiconductor structure through hybrid bonding, and arranging the second interconnect structure connecting the first circuit and the differential interconnect structure to pass through the first connection layer in the z direction, the length of the second interconnect structure between the first circuit and the differential interconnect structure can be shortened, and the sensing tolerance of components such as the differential interconnect structure and the second interconnect structure can be improved, thereby correspondingly reducing the overall size of the semiconductor device.

[0079] In some embodiments of the present application, as an option, adjacent sub-semiconductor structures can be connected by direct bonding; as another option, a second connection layer can be provided between adjacent sub-semiconductor structures, where the second connection layer includes a bonding layer; in addition, as yet another option, some adjacent sub-semiconductor structures can be connected by direct bonding, and a second connection layer can be provided between some adjacent sub-semiconductor structures to connect adjacent sub-semiconductor structures through the second connection layer.

[0080] For example, the second sub-semiconductor structure 202 and the third sub-semiconductor structure 203 are adjacent in the z direction, and a second connection layer 400, such as a first sub-connection layer 401, is provided between the second sub-semiconductor structure 202 and the third sub-semiconductor structure 203 to connect the second sub-semiconductor structure 202 and the third sub-semiconductor structure 203 through the first sub-connection layer 401. The first sub-semiconductor structure 201 and the second sub-semiconductor structure 202 are adjacent in the z direction, and a second connection layer 400, such as a second sub-connection layer 402, is provided between the first sub-semiconductor structure 201 and the second sub-semiconductor structure 202 to connect the first sub-semiconductor structure 201 and the second sub-semiconductor structure 202 through the second sub-connection layer 402. The third sub-semiconductor structure 203 and the fourth sub-semiconductor structure 204 are adjacent in the z direction, and the third sub-semiconductor structure 203 and the fourth sub-semiconductor structure 204 can be directly bonded and connected.

[0081] In addition, referring back to Figures 1 - 3 、 Figure 5, in some embodiments of the present application, the multiple sub-semiconductor structures of the second semiconductor structure 200 include a first sub-semiconductor structure 201 and the remaining sub-semiconductor structures located between the first sub-semiconductor structure 201 and the first semiconductor structure 100 along the z direction, such as a second sub-semiconductor structure 202, a third sub-semiconductor structure 203, a fourth sub-semiconductor structure 204, and so on. The first differential interconnect structure 231 corresponding to the first sub-semiconductor structure 201 extends along the z direction and passes through the above-mentioned remaining sub-semiconductor structures, and is connected to the first circuit 110.

[0082] Similarly, the multiple sub-semiconductor structures of the second semiconductor structure 200 include a second sub-semiconductor structure 202 and the remaining sub-semiconductor structures located between the second sub-semiconductor structure 202 and the first semiconductor structure 100 along the z direction, such as a third sub-semiconductor structure 203, a fourth sub-semiconductor structure 204, and so on. The second differential interconnect structure 232 corresponding to the second sub-semiconductor structure 202 extends along the z direction and passes through the above-mentioned remaining sub-semiconductor structures, and is connected to the first circuit 110.

[0083] The multiple sub-semiconductor structures of the second semiconductor structure 200 include a third sub-semiconductor structure 203 and the remaining sub-semiconductor structures located between the third sub-semiconductor structure 203 and the first semiconductor structure 100 along the z direction, such as a fourth sub-semiconductor structure 204, and so on. The third differential interconnect structure 233 corresponding to the third sub-semiconductor structure 203 extends along the z direction and passes through the above-mentioned remaining sub-semiconductor structures, and is connected to the first circuit 110.

[0084] As Figure 1 shown, optionally, the sub-semiconductor structure may include a first region 01 and a second region 02 that are adjacent to each other in a direction intersecting the z direction (for example, the x direction or the y direction). For example, the first sub-semiconductor structure 201 includes a first region 01 and a second region 02 that are adjacent to each other in a direction intersecting the z direction (for example, the x direction or the y direction), where both the second circuit 220 and the memory array 210 of the first sub-semiconductor structure 201 are located in the first region 01, and the first differential interconnect structure 231 corresponding to the first sub-semiconductor structure 201 is located in the second region 02. The first differential interconnect structure 231 extends along the z direction in the second region 02 of the first sub-semiconductor structure 201, and sequentially passes through the second region 02 of the second sub-semiconductor structure 202, the second region 02 of the third sub-semiconductor structure 203, and the second region 02 of the fourth sub-semiconductor structure 204, and is connected to the first circuit 110. Therefore, as an option, the second regions of the multiple sub-semiconductor structures can be sequentially arranged along the z direction, so that the differential interconnect structure can sequentially pass through the second regions of the multiple sub-semiconductor structures along the z direction and be connected to the first circuit 110.

[0085] Optionally, the first sub-semiconductor structure 201 may include a plurality of first regions 01, such as a first sub-region 011 and a second sub-region 012. The second region 02 may be disposed at the edge of the first region 01, for example, between the first sub-region 011 and the second sub-region 012. The first differential interconnect structure 231 located in the second region 02 may be connected to at least one of the second circuit 220 and the memory array 210 located in the first region 01 through the third interconnect structure 250. As an option, the third interconnect structure 250 may extend in a direction perpendicular to the z-direction, thereby shortening the length of the third interconnect structure and correspondingly reducing the overall size of the semiconductor device.

[0086] In addition, as Figure 1 shown, a plurality of sub-semiconductor structures of the second semiconductor structure 200 include a sub-semiconductor structure closest to the first semiconductor structure 100 in the z-direction, such as a fourth sub-semiconductor structure 204. Optionally, the fourth sub-semiconductor structure 204 includes a first portion 204-1 and a second portion 204-2 arranged in the z-direction. The first portion 204-1 is closer to the first semiconductor structure 100 than the second portion 204-2. The fourth differential interconnect structure 234 corresponding to the fourth sub-semiconductor structure 204 may be located in the first portion 204-1. In other words, the fourth differential interconnect structure 234 is located in the first portion 204-1 and extends in the z-direction to connect to the first circuit 100. Arranging the fourth differential interconnect structure 234 close to the first semiconductor structure 100 can effectively shorten the length of the fourth differential interconnect structure, reduce the parasitic capacitance of the differential interconnect structure, and improve the sensing tolerance and storage density of the semiconductor device.

[0087] Furthermore, as an option, one of the first portion 204-1 and the second portion 204-2 may include the second circuit 220, and the other of the first portion 204-1 and the second portion 204-2 may include a memory array 210 connected to the second circuit 220. For example, the first portion 204-1 includes the memory array 210, and the second portion 204-2 includes the second circuit 220.

[0088] Figure 6 is a schematic diagram of a differential circuit 111 according to an embodiment of the present application. Figure 7 is a schematic diagram of a differential signal according to an embodiment of the present application. Figure 8 is a schematic diagram of a single-ended signal of an embodiment.

[0089] As Figure 1 、 Figure 3 、 Figure 6 and Figure 7 shown, in some embodiments of the present application, the first circuit 110 includes a differential circuit 111, and the differential circuit 111 includes a first differential pair circuit connected in reverse (such as Figure 6The gray circuit shown) and the second differential pair circuit (such as Figure 6 The black circuit shown). The first differential pair circuit includes a first switch unit, and a first input port N1 and a fourth input port N4 belonging to the first switch unit are connected to the first conductive structure 230-1. The second differential pair circuit includes a second switch unit, and a second input port N2 and a third input port N3 belonging to the second switch unit are respectively connected to the second conductive structure 230-2. By switching the switch states of the first switch unit and the second switch unit, a pair of differential signals DATA+ and DATA- can be generated from the signals from the first conductive structure 230-1 and the second conductive structure 230-2.

[0090] In other words, in some embodiments of the present application, the present application provides a signal generation method 2000 for a semiconductor device. Figure 9 It is a schematic diagram of a signal generation method 2000 for a semiconductor device according to an exemplary embodiment of the present application.

[0091] Such as Figure 1 , Figure 3 , Figure 6 And Figure 9 As shown, in some embodiments of the present application, the semiconductor device 1000 includes a first circuit 110 and a differential interconnect structure 230. The differential interconnect structure 230 includes a first conductive structure 230-1 and a second conductive structure 230-2. The first circuit 110 includes a differential circuit 111. The differential circuit 111 includes a first differential pair circuit and a second differential pair circuit connected in reverse. The first differential pair circuit includes a first switch unit connected to the first conductive structure 230-1, and the second differential pair circuit includes a second switch unit connected to the second conductive structure 230-2. The signal generation method 2000 includes: by switching the switch states of the first switch unit and the second switch unit, generating a pair of differential signals DATA+ and DATA- from the signals from the first conductive structure 230-1 and the second conductive structure 230-2.

[0092] Therefore, according to the semiconductor device and the signal generation method for the semiconductor device provided by at least one embodiment of the present application, the semiconductor device may include a first semiconductor structure having a first circuit and a second semiconductor structure serving as a memory. A plurality of sub-semiconductor structures of the second semiconductor structure can be interconnected with the first circuit of the first semiconductor structure by using a differential interconnect structure. Since the differential interconnect structure has the characteristics of small pitch and anti-interference, using the differential interconnect structure for signal input and output can reduce crosstalk between transmitted signals and improve the signal transmission frequency of the semiconductor device.

[0093] Specifically, such as Figure 7 And Figure 8As shown, a single-ended interconnect structure can be understood as an interconnect structure different from a differential interconnect structure. It has only one conductive structure inside, and this single conductive structure is used to realize the interconnection between the sub-semiconductor structure of the second semiconductor structure and the first circuit of the first semiconductor structure. When using a single-ended interconnect structure for signal input and output, the value of the input or output signal can be determined by referring to the reference high level (High) and the reference low level (Low). For example, if the value of the input or output signal is less than the reference low level, it is determined that the value of the input or output signal is "0"; if the value of the input or output signal is greater than the reference high level, it is determined that the value of the input or output signal is "1". In this case, the input or output signal is easily interfered by the interference signal (Noise) and misjudged. For example, Figure 8 As shown, when the "Noise" signal is superimposed on the input or output signal, it will cause the original value at this position to change from less than the reference low level to greater than the reference low level, resulting in misjudgment. Therefore, when using a single-ended interconnect structure for signal input and output, the crosstalk between transmission signals is serious, reducing the signal transmission frequency of semiconductor devices.

[0094] When using a differential interconnect structure for signal input and output, the value of the input or output signal can be determined by the phase difference between the differential signals DATA+ and DATA-. Specifically, the differential signals DATA+ and DATA- can be understood as a pair of signals with the same value and a phase difference of 180°. In other words, the values of the differential signals DATA+ and DATA- are equal in magnitude and opposite in direction. Therefore, when the values of the differential signals DATA+ and DATA- are subtracted, the result is equal to twice the value of the input or output signal. For example, in Figure 7 As shown at the position of the "Noise" signal, the value of DATA+ includes the sum of the value of the positive input or output signal and the value of the "Noise" signal; the value of DATA- includes the sum of the value of the negative input or output signal and the value of the "Noise" signal. By obtaining the phase difference between the differential signals DATA+ and DATA-, the value of the input or output signal at the position of the "Noise" signal in the figure can be obtained. During the obtaining process, the "Noise" signal included in DATA+ and DATA- is cancelled out. Therefore, determining the value of the input or output signal through the phase difference between the differential signals DATA+ and DATA- is not interfered by the interference signal (Noise). Using a differential interconnect structure for signal input and output can reduce the crosstalk between transmission signals and increase the signal transmission frequency of semiconductor devices.

[0095] Optionally, referring again to Figure 1 、 Figure 3 and Figure 6, the first circuit 110 further includes a common constant current source, a first current negative feedback circuit, and a second current negative feedback circuit. For example, the first circuit 110 includes a first common constant current source Idd and a second common constant current source Igd. The first differential pair circuit includes a first current negative feedback circuit, and the first current negative feedback circuit is connected to the first switch unit and the common constant current source; the second differential pair circuit includes a second current negative feedback circuit, and the second current negative feedback circuit is connected to the second switch unit and the common constant current source. By setting the common constant current source and the current negative feedback circuit, the gains of the first differential pair circuit and the second differential pair circuit for the differential signals DATA+ and DATA- can be controlled, thereby improving the comprehensive performance of the differential circuit.

[0096] For example, in a state where the first switch unit is turned on and the second switch unit is turned off, the first input port N1 and the fourth input port N4 belonging to the first switch unit are connected to the first conductive structure 230-1. The current Id1 of the first differential pair circuit can flow from the first common constant current source Idd to the first input port N1, then flow through the first differential pair circuit to the receiver, flow back to the fourth input port N4 via the resistor (Rterm) of the receiver, and reach the ground terminal via the second common constant current source Igd.

[0097] In a state where the second switch unit is turned on and the first switch unit is turned off, the second input port N2 and the third input port N3 belonging to the second switch unit are connected to the second conductive structure 230-2. The current Id2 of the second differential pair circuit can flow from the first common constant current source Idd to the second input port N2, then flow through the second differential pair circuit to the receiver, flow back to the third input port N3 via the resistor of the receiver, and reach the ground terminal via the second common constant current source Igd.

[0098] Some other embodiments of the present application provide a method for manufacturing a semiconductor device. Figure 10 It is a flowchart of a method 3000 for manufacturing a semiconductor device according to an exemplary embodiment of the present application. Figures 11 - 24 They are process schematic diagrams of a method 3000 for manufacturing a semiconductor device according to an embodiment of the present application, respectively.

[0099] As Figure 10 shown, a method 3000 for manufacturing a semiconductor device provided by the present application includes:

[0100] S1, stacking a plurality of sub-semiconductor structures along a first direction to form a second semiconductor structure.

[0101] S2. Form a plurality of differential interconnect structures respectively corresponding to a plurality of sub-semiconductor structures, where the differential interconnect structures extend along a first direction and include a first conductive structure and a second conductive structure that are adjacently arranged in a direction intersecting the first direction. One end of the first conductive structure and one end of the second conductive structure are respectively connected to the sub-semiconductor structure corresponding to the differential interconnect structure.

[0102] S3. Arrange a first semiconductor structure on one side of the second semiconductor structure, where the first semiconductor structure includes a first circuit, and the other end of the first conductive structure and the other end of the second conductive structure are connected to the first circuit.

[0103] The following will combine Figures 11 - 24 to elaborate in detail the specific processes of each step of the above preparation method 3000.

[0104] Step S1

[0105] Figure 11 FIG. is a cross-sectional schematic view of the structure formed after forming the fourth initial sub-semiconductor structure 204' according to a preparation method of an embodiment of the present application. Figure 12 FIG. is a cross-sectional schematic view of the structure formed after forming the support layer 500 according to a preparation method of an embodiment of the present application. Figure 13 FIG. is a cross-sectional schematic view of the structure formed after forming the fourth sub-semiconductor structure 204 according to a preparation method of an embodiment of the present application. Figure 14 FIG. is a cross-sectional schematic view of the structure formed after forming the third initial sub-semiconductor structure 203' according to a preparation method of an embodiment of the present application. Figure 15 FIG. is a cross-sectional schematic view of the structure formed after forming the third sub-semiconductor structure 203 according to a preparation method of an embodiment of the present application. Figure 16 FIG. is a cross-sectional schematic view of the structure formed after forming the first initial sub-semiconductor structure 201' according to a preparation method of an embodiment of the present application. Figure 17 FIG. is a cross-sectional schematic view of the structure formed after removing the support layer 500 (as Figure 16 shown) according to a preparation method of an embodiment of the present application.

[0106] As Figures 10 - 17 shown, in some embodiments of the present application, step S1 of stacking a plurality of sub-semiconductor structures along a first direction to form a second semiconductor structure may include, for example: forming a sub-semiconductor structure; combining one sub-semiconductor structure with another sub-semiconductor structure along the z direction; and repeating the above steps to form a second semiconductor structure including a plurality of sub-semiconductor structures.

[0107] Specifically, as Figures 11 - 13As shown, in one embodiment of the present application, taking the formation of the fourth sub-semiconductor structure 204 as an example, forming a sub-semiconductor structure may include, for example: forming a fourth initial sub-semiconductor structure 204'; and thinning the initial substrate 244' of the fourth initial sub-semiconductor structure 204' to form the fourth sub-semiconductor structure 204.

[0108] It should be noted that, in order to correspond to the cross-sectional view showing the semiconductor device 1000, in the manufacturing method 3000 of the semiconductor device, taking the formation of the fourth sub-semiconductor structure 204 first as an example, a detailed description will be given. However, the expressions such as first, second, third, fourth, etc. are only used to distinguish one sub-semiconductor structure from another, and do not represent any limitation on the sub-semiconductor structure. Therefore, without departing from the teachings of the present application, the fourth sub-semiconductor structure described herein in the present application may also be referred to as the first sub-semiconductor structure, and vice versa. In addition, in the manufacturing method 3000 of the semiconductor device, taking the second semiconductor structure including four sub-semiconductor structures as an example, a detailed description will be given. However, the second semiconductor structure is not limited to a structure including only four sub-semiconductor structures, and it may include more than one sub-semiconductor structure. The present application does not limit the number of sub-semiconductor structures included in the second semiconductor structure. Figure 1 or Figure 2 As shown, the material of the initial substrate 244' for preparing the fourth initial sub-semiconductor structure 204' can be selected from any suitable semiconductor material, for example, it can be single-crystalline silicon (Si), single-crystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or group III-V compounds such as gallium arsenide.

[0109] As Figure 11 shown, the initial substrate 240' of each sub-semiconductor structure can be selected from the same material or structure as the initial substrate 244' of the fourth initial sub-semiconductor structure 204'. Therefore, the initial substrate 240' including the initial substrate 244' will be described in detail below. It should be noted that those skilled in the art can design a suitable initial substrate of the sub-semiconductor structure according to the specific structural requirements of different semiconductor devices, and the present application does not limit this.

[0110] In addition, the initial substrate 240' of each sub-semiconductor structure can be the same as the initial substrate 244' of the fourth initial sub-semiconductor structure 204' in terms of material or structure. Therefore, the initial substrate 240' including the initial substrate 244' will be described in detail below. It should be noted that those skilled in the art can design a suitable initial substrate of the sub-semiconductor structure according to the specific structural requirements of different semiconductor devices, and the present application does not limit this.

[0111] In one embodiment of the present application, the initial substrate 240' can be, for example, a composite substrate for supporting the device structure thereon. Multiple layers made of different materials can be sequentially deposited to form the initial substrate 240' through thin film deposition processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof.

[0112] In some embodiments of the present application, the initial substrate 240' may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer can include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer can include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer can be a high-k dielectric layer. As another option, the substrate sacrificial layer can include a dielectric layer, a sacrificial layer, and a dielectric layer arranged in sequence, where the dielectric layer can be a silicon nitride layer and the sacrificial layer can be a silicon oxide layer. As yet another option, the substrate sacrificial layer can include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer can be single-crystalline silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer can be polycrystalline silicon.

[0113] In addition, well regions (not shown) doped with N-type or P-type dopants can be formed in some regions of the initial substrate 240' through ion implantation or diffusion processes. The dopants can include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or combination of boron (B), gallium (Ga), or indium (In). In some embodiments of the present application, the well regions can be prepared with the same dopant or different dopants. Further, the doping concentrations of the well regions can be the same or different, and the present application does not limit this.

[0114] The initial substrate 240' includes two opposite sides in the first direction (z direction), a first side 240'-1 and a second side 240'-2'. After forming the initial substrate 240', a peripheral circuit layer can be formed on the first side 240'-1 of the initial substrate 240'. The peripheral circuit layer includes a second circuit 220. Optionally, a part of the second circuit 220 can extend from the first side 240'-1 into the initial substrate 240' along the z direction. In other words, the second circuit 220 can be formed in or on the initial substrate 240'. Optionally, the second circuit 220 can include a driving structure, a sensing structure, and so on.

[0115] According to some embodiments of the present application, the second circuit 220 may be implemented using, for example, complementary metal-oxide-semiconductor (CMOS) technology. The fabrication process and structural design of the second circuit 220 may adopt existing conventional processes and be designed according to actual needs, which will not be elaborated here.

[0116] In some embodiments of the present application, multiple memory cells (e.g., a memory array) of the sub-semiconductor structure and the peripheral circuit (e.g., the second circuit) connected to the multiple memory cells may be formed on two different wafers (e.g., a memory array wafer and a peripheral circuit wafer) respectively, and then the peripheral circuit wafer is combined with the memory array wafer through processes such as wafer bonding, and the peripheral circuit and the memory array circuit are connected together through interconnection wiring. In addition, in some embodiments, multiple memory cells of the semiconductor structure and the peripheral circuit connected to the multiple memory cells may also be formed on the same wafer.

[0117] In this embodiment, taking the formation of multiple memory cells and the second circuit on the same wafer as an example, the formation process of the sub-semiconductor structure will be described. However, it should be noted that the specific process can be selected according to actual production. The formation process of the sub-semiconductor structure described in this embodiment is only an exemplary illustration and is not a limitation on the second semiconductor structure or its sub-semiconductor structure. Those skilled in the art can design a suitable second semiconductor structure or its sub-semiconductor structure according to the specific structural requirements of different semiconductor devices, and the present application does not limit this.

[0118] In at least one embodiment of the present application, after forming the second circuit 220, a first dielectric covering layer 260 may be formed through one or more thin film deposition processes, and the thin film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes or any combination thereof. The first dielectric covering layer 260 covers at least the second circuit 220. The first dielectric covering layer 260 may include any suitable dielectric material, for example, an oxide, a nitride, a nitroxide, or a high-k dielectric. For example, the first dielectric covering layer 260 may include silicon oxide.

[0119] In addition, after the first dielectric covering layer 260 is formed, the surface of the first dielectric covering layer 260 can be processed by any suitable planarization process, such as grinding and / or chemical mechanical polishing process, so that the processed first dielectric covering layer 260 has a relatively flat surface, facilitating the formation of the memory array 210 on the flat surface. The memory array 210 includes a plurality of memory cells 210-1. The structure and fabrication process of the memory cells 210-1 can adopt existing conventional processes and be fabricated according to actual needs, which are not elaborated in this application.

[0120] Optionally, the memory array 210 can include at least one of non-volatile memory cells and volatile memory cells. For example, in some embodiments of the present application, taking DRAM as an example, the memory cell 210-1 can include a capacitor, and a plurality of memory cells 210-1 can be arranged in the form of a two-dimensional array. Optionally, in some embodiments of the present application, taking PCM elements as an example, the memory cell 210-1 can include units with different resistivities in the amorphous phase and the crystalline phase to store the corresponding PCM. For example, it includes chalcogenide alloys. Optionally, in some embodiments of the present application, taking FRAM as an example, the memory cell 210-1 can include a ferroelectric capacitor, which is not limited in this application.

[0121] After the memory cells 210-1 are formed, a second dielectric covering layer that at least covers the memory cells 210-1 can be formed. The second dielectric covering layer can include any suitable dielectric material, such as oxides, nitrides, oxynitrides, or high-k dielectrics. Additionally, the second dielectric covering layer and the first dielectric covering layer 260 can be fabricated using the same material. In the case of using the same material for fabrication, there is no obvious boundary between the two.

[0122] In addition, after the memory cells 210-1 are formed, a third interconnect structure 250 can also be formed. The third interconnect structure 250 can extend in a direction perpendicular to the z direction, from the first region 01 of the fourth initial sub-semiconductor structure 204' to the second region 02 of the fourth initial sub-semiconductor structure 204'. In other words, as an option, the memory array 210 and the second circuit 220 can be formed in the first region 01 of the fourth initial sub-semiconductor structure 204', and the subsequent formed differential interconnect structure can be formed in the second region 02 of the fourth initial sub-semiconductor structure 204', where the first region 01 and the second region 02 are adjacent to each other in a direction intersecting the z direction.

[0123] The third interconnect structure 250 includes a head end and a tail end opposite to each other in the extending direction. The head end can be connected to at least one of the memory array 210 and the second circuit 220, and the tail end can be connected to a subsequently formed differential interconnect structure. Specifically, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, to form a slot (not shown) for accommodating the third interconnect structure 250, and then the third interconnect structure 250 is formed in the slot through one or more thin film deposition processes. The third interconnect structure 250 can include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof.

[0124] It should be noted that Figure 11 Only the number and positions of the memory cells, interconnect structures, and the second circuit are shown exemplarily. However, it can be understood that the situations of the memory cells, interconnect structures, and the second circuit shown in the figures and related content herein are only shown for convenience of illustration, and the present application is not limited thereto. Those skilled in the art can adjust the situations of the memory cells, interconnect structures, and the second circuit according to the idea of the present invention to achieve the same technical effects.

[0125] As Figures 11 - 12 shown, after forming the fourth initial sub-semiconductor structure 204', a support layer 500 can be formed on the side of the fourth initial sub-semiconductor structure 204' away from its initial substrate 244'. For example, a temporary attachment layer 510 can be formed on the side of the fourth initial sub-semiconductor structure 204' away from its initial substrate 244'. The temporary attachment layer 510 can be a temporary bonding film for debonding in subsequent steps by methods such as laser irradiation. The temporary attachment layer 510 temporarily binds the fourth initial sub-semiconductor structure 204' and the support layer 500 together. Optionally, after forming the support layer 500, it can be flipped 180° to form an intermediate as Figure 12 shown.

[0126] As Figures 12 - 13 shown, the initial substrate 244' can be thinned to form the fourth sub-semiconductor structure 204. Optionally, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. In addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, to remove part of the initial substrate 244' of the fourth initial sub-semiconductor structure 204' to form the second four-substrate 244. As an option, the thickness of the second four-substrate 244 obtained by the thinning process can be 1 - 10 micrometers. After forming the second four-substrate 244, the fourth initial sub-semiconductor structure 204' is formed into the fourth sub-semiconductor structure 204.

[0127] As Figures 13 - 14 shown, as an option, the above steps can be repeated to form a third initial sub-semiconductor structure 203', and the third initial sub-semiconductor structure 203' and the fourth sub-semiconductor structure 204 can be bonded together through processes such as bonding. Optionally, the surface of the third initial sub-semiconductor structure 203' away from its second three-substrate 243 is bonded to the surface of the second four-substrate 244 of the fourth sub-semiconductor structure 204 facing away from the memory array 210.

[0128] In some embodiments of the present application, as an option, the sub-semiconductor structures adjacent in the z direction can be connected by direct bonding; as another option, a second connection layer can also be provided between the sub-semiconductor structures adjacent in the z direction, and the adjacent sub-semiconductor structures are connected through the second connection layer, where the second connection layer includes a bonding layer; in addition, as yet another option, some adjacent sub-semiconductor structures can be connected by direct bonding, and a second connection layer can be provided between some adjacent sub-semiconductor structures, and the adjacent sub-semiconductor structures are connected through the second connection layer.

[0129] For example, as Figures 14 - 15 shown, the third initial sub-semiconductor structure 203' and the fourth sub-semiconductor structure 204 are adjacent in the z direction, and the third initial sub-semiconductor structure 203' and the fourth sub-semiconductor structure 204 can be directly bonded and connected. In addition, after the direct bonding connection, by thinning the initial substrate 243' of the third initial sub-semiconductor structure 203', the second three-substrate 243 can be formed, thereby forming the third sub-semiconductor structure 203 and the fourth sub-semiconductor structure 204 connected by direct bonding.

[0130] As Figures 15 - 16 shown, the second initial sub-semiconductor structure (not shown) and the third sub-semiconductor structure 204 are adjacent in the z direction, and a second connection layer 400, such as a first sub-connection layer 401, can be provided between the second initial sub-semiconductor structure and the third sub-semiconductor structure 204, and the second initial sub-semiconductor structure and the third sub-semiconductor structure 203 are connected through the first sub-connection layer 401. In addition, after the connection is formed, by thinning the initial substrate of the second initial sub-semiconductor structure, the second sub-semiconductor structure 202 is formed.

[0131] After the second sub-semiconductor structure 202 is formed, the first initial sub-semiconductor structure 201' can be bonded to one side of the second sub-semiconductor structure 202. Optionally, a second connection layer 400, such as a second sub-connection layer 402, can be provided between the first initial sub-semiconductor structure 201' and the second sub-semiconductor structure 202, and the first initial sub-semiconductor structure 201' and the second sub-semiconductor structure 202 are connected through the second sub-connection layer 402.

[0132] By repeating the above steps, multiple sub-semiconductor structures of the second semiconductor structure 200 can be formed. As Figures 16 - 17 shown, after the second semiconductor structure 200 is formed, a debonding process can be performed by methods such as laser irradiation to remove the support layer 500. After the support layer 500 is removed, the second semiconductor structure 200 can be rotated 180°, so that the surface of the fourth sub-semiconductor structure 204 away from its second substrate 244 is exposed.

[0133] In addition, optionally, for the Figure 17 sub-semiconductor structure located at the bottom of the second semiconductor structure 200 as shown, the process of removing its initial substrate may not be performed. For example, the first sub-semiconductor structure 201 may not be processed to remove its initial substrate. In other words, the second substrate 240 of the sub-semiconductor structure at the bottom of the second semiconductor structure 200 can be used to support the devices thereon, so it is relatively thicker than the second substrates of other sub-semiconductor structures.

[0134] Step S2

[0135] Figure 18 It is a cross-sectional schematic view of the structure formed after forming the patterned hard mask 600 according to the preparation method of an embodiment of the present application. Figure 19 It is a cross-sectional schematic view of the structure formed after forming the opening 620 according to the preparation method of an embodiment of the present application. Figure 20 It is a cross-sectional schematic view of the structure formed after forming the differential interconnect structure 230 according to the preparation method of an embodiment of the present application. Figure 21 It is a top view schematic view of the structure formed after forming the first sub-opening 620-1 and the second sub-opening 620-2 according to the preparation method of an embodiment of the present application.

[0136] As Figures 17 - 21 shown, in some embodiments of the present application, step S2 of forming a plurality of differential interconnect structures corresponding to the plurality of sub-semiconductor structures may include, for example: forming an opening 620 for accommodating the differential interconnect structure; and filling the opening 620 to form the differential interconnect structure 230.

[0137] As Figures 17 - 19 shown, in an embodiment of the present application, an etching process can be used to form the opening 620, where a plurality of openings such as the first opening 621, the second opening 622, the third opening 623, and the fourth opening 624 can extend from a surface 2041 of the second semiconductor structure 200 in the z direction to different sub-semiconductor structures respectively, and the etching times of the plurality of openings 620 are different. By controlling the etching time, the plurality of openings have different extension lengths in the z direction.

[0138] Specifically, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to form a plurality of openings 620, where the first opening 621 extends in the z direction into the first sub-semiconductor structure 201, the second opening 622 extends in the z direction into the second sub-semiconductor structure 202, the third opening 623 extends in the z direction into the third sub-semiconductor structure 203, and the fourth opening 624 extends in the z direction into the fourth sub-semiconductor structure 204. Optionally, the plurality of openings 620 can extend to the third interconnect structure 250 of different sub-semiconductor structures, so as to facilitate the subsequent formation of a differential interconnect structure in the openings 620 to form a connection with the third interconnect structure 250.

[0139] As Figures 17 - 18 shown, a patterned hard mask 600 can be formed on the surface 2041 of the uppermost sub-semiconductor structure of the second semiconductor structure 200. Optionally, the hard mask layer 600 can include a silicon oxide layer, a silicon nitride layer, a polysilicon layer, etc., and the present application does not limit the material of the hard mask 600. Through, for example, lithography, a patterned hard mask layer 600 can be formed, where the pattern of the hard mask layer 600 includes the pattern 610 of the subsequent formed openings.

[0140] As Figures 18 - 19 shown, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., based on the patterned hard mask layer 600, a plurality of openings 620 extending in the z direction can be formed.

[0141] Optionally, in combination with Figure 5 、 Figures 19 - 21 shown, after forming the plurality of openings 620, forming the differential interconnect structure 230 can, for example, include: filling the openings 620 with a dielectric filling layer 230-6; forming a first sub-opening 620-1 and a second sub-opening 620-2 that respectively extend in the z direction and have the same extension length in the dielectric filling layer 230-6; and filling the first sub-opening 620-1 and the second sub-opening 620-2 with a conductive material to form a first conductive structure 230-1 and a second conductive structure 230-2. As an option, in a direction intersecting the z direction (for example, the X direction or the y direction), the size D3 of the first sub-opening 620-1 and the size D4 of the second sub-opening 620-2 are the same.

[0142] In addition, before filling the opening 620 with the dielectric filling layer 230-6, an isolation layer 230-3 may be formed on the inner wall of the opening 620 through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of these thin film deposition processes or any combination thereof.

[0143] In some embodiments of the present application, the isolation layer 230-3 may include any suitable dielectric material, such as oxides, nitrides, oxynitrides, or high dielectric constant (k) dielectrics. For example, the isolation layer 230-3 may include a high-k dielectric. The dielectric filling layer 230-6 may include any suitable dielectric material, such as oxides, nitrides, oxynitrides, or high-k dielectrics. For example, the dielectric filling layer 230-6 may include silicon oxide.

[0144] It is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc. By removing a part of the dielectric filling layer 230-6, a first sub-opening 620-1 and a second sub-opening 620-2 that extend in the z direction and have the same extension length can be formed.

[0145] After forming the first sub-opening 620-1 and the second sub-opening 620-2, a conductive material may be filled in the first sub-opening 620-1 and the second sub-opening 620-2 respectively through one or more thin film deposition processes to form a first conductive structure 230-1 and a second conductive structure 230-2. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of these thin film deposition processes or any combination thereof. The conductive material may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), polysilicon, silicide, or any combination thereof.

[0146] In addition, before filling the first sub-opening 620-1 and the second sub-opening 620-2 with the conductive material, a first adhesion layer 230-4 and a second adhesion layer 230-5 may be formed on the inner walls of the first sub-opening 620-1 and the second sub-opening 620-2 respectively through one or more thin film deposition processes. Then, a first conductive structure 230-1 and a second conductive structure 230-2 are formed in the remaining spaces of the first sub-opening 620-1 and the second sub-opening 620-2 respectively. In some embodiments of the present application, the first adhesion layer 230-4 and the second adhesion layer 230-5 may be prepared from the same material. For example, both the first adhesion layer 230-4 and the second adhesion layer 230-5 may include at least one of titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0147] Optionally, the first conductive structure 230-1 includes a first end and a second end opposite to each other in the z direction, and the second conductive structure 230-2 includes a third end and a fourth end opposite to each other in the z direction. Taking the first differential interconnect structure 231 as an example, the first conductive structure 230-1 of the first differential interconnect structure 231 includes a first end 231-1 and a second end 231-3 opposite to each other in the z direction, and the second conductive structure 230-2 of the first differential interconnect structure 231 includes a third end 231-2 and a fourth end 231-4 opposite to each other in the z direction. In addition, the second end of the first conductive structure of the differential interconnect structure and the fourth end of the second conductive structure are respectively connected to the sub-semiconductor structure corresponding to the differential interconnect structure. For example, the second end 231-3 of the first conductive structure 230-1 of the first differential interconnect structure 231 and the fourth end 231-4 of the second conductive structure 230-2 of the first differential interconnect structure 231 are respectively connected to the first sub-semiconductor structure 201.

[0148] Step S3

[0149] Figure 22 It is a cross-sectional schematic view of the structure formed after forming the first part 301 of the first connection layer 300 according to the preparation method of an embodiment of the present application. Figure 23 It is a cross-sectional schematic view of the structure formed after forming the initial first semiconductor 100' according to the preparation method of an embodiment of the present application. Figure 24 It is a cross-sectional schematic view of the structure formed after forming the first connection layer 300 according to the preparation method of an embodiment of the present application.

[0150] Combined with Figures 1 - 2 and Figures 22 - 24 , in some embodiments of the present application, in step S3, a first semiconductor structure is disposed on one side of the second semiconductor structure, where the first semiconductor structure includes a first circuit, and the other ends of the first conductive structure and the second conductive structure are connected to the first circuit, which may include, for example: forming a first connection layer 300 on one side 200-1 of the second semiconductor structure 200, where the first connection layer 300 includes a bonding layer; forming a second interconnect structure 310 passing through the first connection layer 300 in the z direction, one end of the second interconnect structure 310 is connected to the differential interconnect structure 230; and disposing a first semiconductor structure 100 on one side of the first connection layer 300, where the other end of the second interconnect structure 310 is connected to the first circuit 110.

[0151] Specifically, as Figure 23As shown, the initial first semiconductor 100' may include an initial first substrate 120' and a first circuit 110 located on one side of the initial first substrate 120'. The material for preparing the initial first substrate 120' can be any suitable semiconductor material, such as single-crystalline silicon (Si), single-crystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or group III-V compounds such as gallium arsenide.

[0152] In one embodiment of the present application, the initial first substrate 120' may be, for example, a composite substrate for supporting the device structure thereon. The initial first substrate 120' can be formed by sequentially setting multiple layers made of different materials through one or more thin-film deposition processes. The thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0153] In some embodiments of the present application, the initial first substrate 120' may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer can be a high-k dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer arranged in sequence, where the dielectric layer can be a silicon nitride layer and the sacrificial layer can be a silicon oxide layer. As yet another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer can be single-crystalline silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer can be polycrystalline silicon.

[0154] In addition, well regions (not shown) doped with N-type or P-type dopants may be formed in some regions of the initial first substrate 120' through ion implantation or diffusion processes. The dopants may include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or combination of boron (B), gallium (Ga), or indium (In). In some embodiments of the present application, the well regions may be prepared with the same dopant or different dopants. Further, the doping concentrations of the well regions may be the same or different, and the present application does not limit this.

[0155] After forming the initial first substrate 120', a first circuit 110 may be formed on one side of the initial first substrate 120'. The first circuit 110 can be used to manage data stored in the second semiconductor structure, and thus can be configured to control the operation of sub-semiconductor structures in the second semiconductor structure, such as read, write, and refresh operations. In addition, it can also be configured to manage various functions regarding data stored or to be stored in the sub-semiconductor structures, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. Optionally, the first circuit 110 may include circuits related to operations such as the above-mentioned read, write, and refresh, as well as refresh control, timing control, command / request translation, buffering, scheduling, power management, etc.

[0156] According to some embodiments of the present application, the first circuit 110 can be implemented using, for example, complementary metal-oxide-semiconductor technology. The manufacturing process and structural design of the first circuit 110 can adopt existing conventional processes and be designed according to actual needs, which will not be elaborated here.

[0157] As Figure 20 and Figure 22 shown, in some embodiments of the present application, the second semiconductor structure 200 includes two opposite sides in the z direction, one side 200-1 and the other side 200-2. Among them, the surface 2041 exposing one end of the differential interconnect structure 230 is located on one side 200-1.

[0158] Optionally, referring to Figure 20 、 Figures 22 - 24 , a first layer 301 of the first connection layer 300 is formed on one side 200-1 of the second semiconductor structure 200, and a second layer (not shown) of the first connection layer 300 is formed on the side of the initial first semiconductor 100' away from the initial first substrate 120'. As an option, the first connection layer 300 may include a bonding layer. In this case, both the first layer 301 and the second layer include bonding interface layers, and the initial first semiconductor 100' and the second semiconductor structure 200 can be connected through, for example, hybrid bonding.

[0159] In addition, in some embodiments of the present application, a second interconnect structure 310 may also be formed passing through the first connection layer 300 in the z direction. One end of the second interconnect structure 310 is connected to the differential interconnect structure 230, and the other end of the second interconnect structure 310 is connected to the first circuit 110.

[0160] For example, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to form a first through hole (not shown) that penetrates the first layer 301 along the z direction. After that, the first through hole is filled with a conductive material to form the first part 310-1 of the second interconnect structure 310. The conductive material layer can include tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), polysilicon, silicide, or any combination thereof.

[0161] In addition, the same process as described above can be used to form a second through hole (not shown) that penetrates the second layer along the z direction, and the second through hole is filled with a conductive material to form the second part of the second interconnect structure 310.

[0162] As Figures 1 - 2 and Figures 23 - 24 As shown, after the initial first semiconductor 100' is disposed on one side 200-1 of the second semiconductor structure 200, the initial first substrate 120' of the initial first semiconductor 100' can be thinned. It can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove part of the initial first substrate 120' to form the first substrate 120. As an option, the thickness of the first substrate 120 obtained by the thinning process can be 1-10 microns. After the first substrate 120 is formed, the initial first semiconductor 100' is formed into the first semiconductor 100.

[0163] According to the method for preparing a semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure having a first circuit and a second semiconductor structure serving as a memory. Multiple sub-semiconductor structures of the second semiconductor structure can be interconnected with the first circuit of the first semiconductor structure by using a differential interconnect structure. Since the differential interconnect structure has the characteristics of small pitch and anti-interference, the use of the differential interconnect structure for signal input and output can reduce crosstalk between transmitted signals and improve the signal transmission frequency of the semiconductor device.

[0164] In addition, Figure 25 is a schematic structural diagram of a memory system 30000 according to an embodiment of the present application.

[0165] As Figure 25As shown, at least one embodiment of another aspect of the present application also provides a memory system 30000. The memory system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and the present application will not elaborate on this. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. Hereinafter, a three-dimensional semiconductor device will be taken as an example for illustration.

[0166] As an option, the three-dimensional semiconductor device may include at least one of non-volatile memory cells and volatile memory cells.

[0167] The memory system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and the present application will not elaborate on this. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to requests from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform internal operations corresponding to the command on the region selected by the address.

[0168] In some embodiments, the three-dimensional memory system may be implemented as a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick, etc. Since the semiconductor device provided in the present application is provided in the memory system provided in the present application, it has the same beneficial effects as the semiconductor device, and will not be elaborated here.

[0169] Although exemplary preparation methods and structures of the semiconductor device are described herein, it can be understood that one or more features may be omitted, substituted, or added to the structure of the semiconductor device. In addition, the materials of the exemplified layers are merely exemplary.

[0170] The above description is only a preferred embodiment of the present application and an explanation of the technical principles applied. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solutions formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with technical features (but not limited to) having similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A first semiconductor structure including a first circuit; A second semiconductor structure located on one side of the first semiconductor structure and including a plurality of sub-semiconductor structures stacked along a first direction; And A differential interconnect structure, with a plurality of the differential interconnect structures corresponding to the plurality of sub-semiconductor structures, wherein the differential interconnect structure extends along the first direction and includes a first conductive structure and a second conductive structure adjacent to each other in a direction intersecting the first direction, and both the first conductive structure and the second conductive structure are respectively connected to the first circuit and the corresponding sub-semiconductor structure.

2. The semiconductor device according to claim 1, wherein In a direction intersecting the first direction, the first conductive structure and the second conductive structure have the same size; and The first conductive structure and the second conductive structure include the same conductive material.

3. The semiconductor device according to claim 1, wherein In a direction intersecting the first direction, the distance between the first conductive structure and the second conductive structure of the same differential interconnect structure is less than the distance between adjacent differential interconnect structures, wherein the distance between the adjacent differential interconnect structures includes: The distance between first conductive structures belonging to different differential interconnect structures and adjacent to each other; The distance between second conductive structures belonging to different differential interconnect structures and adjacent to each other; and The distance between a first conductive structure and a second conductive structure belonging to different differential interconnect structures and adjacent to each other.

4. The semiconductor device according to claim 1, wherein At least one of the plurality of sub-semiconductor structures includes a second circuit and a storage array connected to the second circuit, wherein the differential interconnect structure connects at least one of the second circuit and the storage array of the corresponding sub-semiconductor structure to the first circuit.

5. The semiconductor device according to claim 1, wherein A first connection layer is provided between the first semiconductor structure and the second semiconductor structure, and the first connection layer includes a bonding layer, wherein the semiconductor device further includes a second interconnect structure passing through the first connection layer along the first direction, and the second interconnect structure connects the first circuit and the differential interconnect structure.

6. The semiconductor device according to claim 1, wherein The plurality of sub-semiconductor structures of the second semiconductor structure include a first sub-semiconductor structure and the remaining sub-semiconductor structures located between the first semiconductor structure and the first sub-semiconductor structure along the first direction, wherein the differential interconnect structure corresponding to the first sub-semiconductor structure extends along the first direction and passes through the remaining sub-semiconductor structures and is connected to the first circuit.

7. The semiconductor device according to claim 6, wherein The first sub-semiconductor structure includes a first region and a second region adjacent to each other in a direction intersecting the first direction, wherein the second circuit and the storage array of the first sub-semiconductor structure are located in the first region; and A differential interconnection structure corresponding to the first sub-semiconductor structure is located in the second region and extends in the first direction through the remaining sub-semiconductor structures.

8. The semiconductor device according to claim 6, wherein, the remaining sub-semiconductor structures include a second sub-semiconductor structure closest to the first semiconductor structure in the first direction, wherein the second sub-semiconductor structure includes a first portion and a second portion arranged in the first direction, the first portion is closer to the first semiconductor structure than the second portion, a differential interconnection structure corresponding to the second sub-semiconductor structure is located in the first portion, extends in the first direction, and is connected to the first circuit; and one of the first portion and the second portion includes a second circuit, and the other of the first portion and the second portion includes a memory array connected to the second circuit.

9. The semiconductor device according to claim 1, wherein, the first semiconductor structure further includes a first substrate, the first circuit is disposed on one side of the first substrate, and the first substrate is farther from the second semiconductor structure than the first circuit; and / or at least one of the plurality of sub-semiconductor structures further includes a second substrate, a second circuit, and a memory array, the second circuit and the memory array are disposed on one side of the second substrate, and the second substrate is farther from the first semiconductor structure than at least one of the second circuit and the memory array.

10. The semiconductor device according to claim 1, wherein, adjacent sub-semiconductor structures are directly bonded; and / or a second connection layer is disposed between adjacent sub-semiconductor structures, and the second connection layer includes a bonding layer.

11. The semiconductor device according to claim 1, wherein, the memory array includes at least one of non-volatile memory cells and volatile memory cells.

12. The semiconductor device according to claim 11, wherein, the volatile memory cells include vertical transistors and memory cells connected to the vertical transistors, wherein, along the first direction, the vertical transistors are closer to the second circuit than the memory cells.

13. The semiconductor device according to any one of claims 1-12, wherein, the differential interconnection structure further includes an isolation layer and a dielectric filling layer, wherein the isolation layer is disposed around the first conductive structure and the second conductive structure; and the dielectric filling layer is located between the isolation layer and the first conductive structure or between the isolation layer and the second conductive structure.

14. The semiconductor device according to any one of claims 1 to 12, wherein, The first circuit includes a first differential pair circuit and a second differential pair circuit connected in reverse, wherein the first differential pair circuit includes a first switch unit, and a first input port and a fourth input port belonging to the first switch unit are respectively connected to the first conductive structure; and the second differential pair circuit includes a second switch unit, and a second input port and a third input port belonging to the second switch unit are respectively connected to the second conductive structure.

15. The semiconductor device according to claim 14, wherein, The first circuit further includes a common constant current source, a first current negative feedback circuit, and a second current negative feedback circuit. Wherein, the first current negative feedback circuit is connected to the first switch unit and the common constant current source, and the second current negative feedback circuit is connected to the second switch unit and the common constant current source.

16. A method for manufacturing a semiconductor device, characterized in that, The preparation method includes: Stacking a plurality of sub-semiconductor structures along a first direction to form a second semiconductor structure; Forming a plurality of differential interconnect structures corresponding to the plurality of sub-semiconductor structures, wherein the differential interconnect structures extend along the first direction and include a first conductive structure and a second conductive structure that are adjacent to each other in a direction intersecting the first direction, and one end of the first conductive structure and one end of the second conductive structure are respectively connected to the sub-semiconductor structure corresponding to the differential interconnect structure; and Providing a first semiconductor structure on one side of the second semiconductor structure, wherein the first semiconductor structure includes a first circuit, and the other end of the first conductive structure and the other end of the second conductive structure are connected to the first circuit.

17. The preparation method according to claim 16, wherein, Providing a first semiconductor structure on one side of the second semiconductor structure includes: Forming a first connection layer on one side of the second semiconductor structure, wherein the first connection layer includes a bonding layer; Forming a second interconnect structure that passes through the first connection layer along the first direction, and one end of the second interconnect structure is connected to the differential interconnect structure; and Providing the first semiconductor structure on one side of the first connection layer, wherein the other end of the second interconnect structure is connected to the first circuit.

18. The preparation method according to claim 16 or 17, wherein, Forming a plurality of differential interconnect structures corresponding to the plurality of sub-semiconductor structures includes: Using an etching process to form openings for accommodating the differential interconnect structures, and the plurality of openings respectively extend from a surface of the second semiconductor structure along the first direction to different sub-semiconductor structures, Wherein, the etching time for the openings extending to different sub-semiconductor structures is different.

19. The preparation method according to claim 18, wherein, Forming a plurality of differential interconnect structures corresponding to the plurality of sub-semiconductor structures further includes: Filling the openings with a dielectric filling layer; Forming a first sub-opening and a second sub-opening that respectively extend along the first direction and have the same extension length in the dielectric filling layer; and Filling the first sub-opening and the second sub-opening with a conductive material to form the first conductive structure and the second conductive structure, Wherein, in a direction intersecting the first direction, the sizes of the first sub-opening and the second sub-opening are the same.

20. A memory system, characterized in that, Comprising: At least one second semiconductor structure according to any one of claims 1-15; And A controller, including the first circuit, and controlling the second semiconductor structure to store data through the first circuit.

21. A signal generation method for a semiconductor device, characterized in that, The semiconductor device includes a first circuit and a differential interconnect structure. The differential interconnect structure includes a first conductive structure and a second conductive structure. The first circuit includes a first differential pair circuit and a second differential pair circuit connected in reverse. Wherein the first differential pair circuit includes a first switching unit connected to the first conductive structure, and the second differential pair circuit includes a second switching unit connected to the second conductive structure. Wherein, the signal generation method includes: By switching the switching states of the first switching unit and the second switching unit, a pair of differential signals are generated from the signals from the first conductive structure and the second conductive structure.

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