Semiconductor device and integrated circuit memory device

Abstract

A semiconductor device and an integrated circuit memory device are provided. The integrated circuit memory device includes a bit line extending longitudinally in a first direction across an underlying substrate and having a trench therein, the trench having opposing first and second sidewalls. Providing a first word line and a second word line spaced apart, the first word line and the second word line longitudinally extending in parallel across the underlying substrate in a second direction perpendicular to the first direction; the first word line has a first portion extending opposite a first sidewall of the trench and a second portion extending outside the trench, and the second word line has a first portion extending opposite a second sidewall of the trench and a second portion extending outside the trench. A semiconductor channel pattern is provided that extends between the first portion of the first word line and the first sidewall of the trench, along the bottom of the trench, and between the first portion of the second word line and the second sidewall of the trench.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0011772, filed on January 25, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to an integrated circuit device, and more particularly, to an integrated circuit memory device and a method of manufacturing an integrated circuit memory device. Background Art

[0003] There is a need to increase the integration degree of integrated circuit memory devices in order to meet the excellent performance and low price required by consumers. In the case of semiconductor-type integrated circuit memory devices, since the integration degree is an important factor determining the price of products, an increased integration degree is generally required.

[0004] In the case of two-dimensional (2D) semiconductor memory devices or planar semiconductor memory devices, since the integration degree is mainly determined by the area occupied by a unit memory cell, it is greatly affected by the level of fine pattern formation technology. However, since ultra-expensive equipment is required to refine the patterns, the integration degree of 2D semiconductor memory devices is increasing, but is still actually limited. Accordingly, semiconductor memory devices including vertical channel transistors whose channels extend in a vertical direction have been proposed. Summary of the Invention

[0005] The present disclosure provides an integrated circuit device including a semiconductor device that can reduce contact resistance and improve on-current I due to a wide contact area between a bit line and a channel pattern on and can increase V o (output voltage) not only due to a wide contact area between the channel pattern and a contact pattern, but also can prevent a decrease in V th (threshold voltage) by first passivating the contact pattern before sufficiently passivating the channel pattern during subsequent oxygen O2 passivation.

[0006] According to one embodiment, a semiconductor device includes: a substrate; a bit line located on the substrate and extending in a first direction; a word line located above the bit line and extending in a second direction different from the first direction; a channel pattern spaced apart from the word line in the first direction and including an oxide semiconductor material; and a gate insulating pattern located between the channel pattern and the word line. In some embodiments, the bit line includes a recess having an opening, the channel pattern includes a first portion located in the recess and a second portion located above the bit line, and a width of the recess in the first direction is greater than a width of the opening in the first direction.

[0007] According to another embodiment, a semiconductor device includes: a substrate; bit lines located on the substrate and extending in a first direction; word lines located above the bit lines and extending in a second direction different from the first direction; a channel pattern spaced apart from the word lines in the first direction and including an oxide semiconductor material; and a gate insulating pattern extending between the channel pattern and the word lines. In some embodiments, the channel pattern includes a first portion inserted into the bit line and a second portion located above the bit line, and the thickness of the first portion of the channel pattern in the first direction is greater than the thickness of the second portion of the channel pattern in the first direction.

[0008] According to another embodiment, a semiconductor device includes: a substrate; bit lines located on the substrate and extending in a first direction; word lines located above the bit lines and extending in a second direction different from the first direction; a channel pattern spaced apart from the word lines in the first direction and including an oxide semiconductor material; and a gate insulating pattern located between the channel pattern and the word lines. In some embodiments, the bit line has a recess with an upward opening, and the channel pattern includes a first portion located in the recess and a second portion located above the bit line; the first portion of the channel pattern may have a surface that contacts the bit line in a concave shape facing the bit line in the first direction.

[0009] According to one embodiment, the semiconductor device can reduce the contact resistance and improve the on-current (I on ) due to the wide contact area between the bit line and the channel pattern, and not only increase V o due to the wide contact area between the channel pattern and the contact pattern, but also prevent V th from decreasing by passivating the contact pattern first before fully passivating the channel pattern during subsequent oxygen O2 passivation.

[0010] According to yet another embodiment, a semiconductor device includes: bit lines extending in a first direction across a underlying substrate, and the bit lines having an opening at its first surface and a recess within the opening; the recess having a greater lateral width relative to the width of the opening, the width of the opening being measured in the first direction and the lateral width being measured in the first direction. A channel pattern is provided that extends through the opening and at least partially fills the recess; the channel pattern extends in a second direction orthogonal to the first direction. A first word line is provided that extends through the opening and into the recess and extends longitudinally in the second direction. A gate insulating pattern is provided that extends between the channel pattern and the first word line. In some of these embodiments, the recess includes opposing sidewalls that are concave when viewed from a cross-sectional perspective, the channel pattern contacts the opposing concave sidewalls of the recess, and the channel pattern forms a non-rectifying junction with the bit line along the opposing concave sidewalls of the recess.

[0011] In another embodiment of the invention, there is provided an integrated circuit memory device including: bit lines longitudinally extending in a first direction across a underlying substrate; the bit lines having trenches with opposite first and second sidewalls. Spaced-apart first and second word lines are provided, the first and second word lines longitudinally extending parallel to each other in a second direction perpendicular to the first direction across the underlying substrate; the first word line having a first portion extending opposite to the first sidewall of the trench and a second portion extending outside the trench, and the second word line having a first portion extending opposite to the second sidewall of the trench and a second portion extending outside the trench. A channel pattern is provided, the channel pattern extending between the first portion of the first word line and the first sidewall of the trench, along the bottom of the trench, and between the first portion of the second word line and the second sidewall of the trench. In some embodiments, each of the opposite first and second sidewalls is concave or convex when viewed from a cross-sectional perspective. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a layout diagram for explaining a semiconductor device according to an embodiment.

[0013] Figure 2 is taken along lines A-A' and B-B' Figure 1 of the semiconductor device.

[0014] Figure 3 is Figure 2 an enlarged cross-sectional view of P1.

[0015] Figure 4 is a diagram for explaining a semiconductor device according to some embodiments and is a cross-sectional view corresponding to Figure 3 thereof.

[0016] Figure 5 is a diagram for explaining a semiconductor device according to some embodiments and is a cross-sectional view corresponding to Figure 3 thereof.

[0017] Figure 6 is a diagram for explaining a semiconductor device according to some embodiments and is a cross-sectional view corresponding to Figure 3 thereof.

[0018] Figures 7 to 21 is a cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to an embodiment.

[0019] Figures 22 to 24 is a diagram for explaining a method of manufacturing a semiconductor memory device according to some embodiments and is a cross-sectional view corresponding to Figure 9 and Figure 10 thereof. DETAILED DESCRIPTION

[0020] In the following, with reference to the accompanying drawings, various embodiments of the present disclosure will be described in detail so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in many different forms and is not limited to the embodiments set forth herein. To clearly explain the present disclosure in the drawings, components irrelevant to the description are omitted, and throughout the specification, the same reference numerals are used for the same or similar elements. In addition, since the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown for ease of description, the present disclosure is not necessarily limited to those shown. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, in the drawings, for ease of explanation, the thicknesses of some layers and regions are exaggerated. It will also be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, the element can be directly on the other element or there can also be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, "above" or "on" a reference component means above or below the reference component and does not necessarily mean "above" or "on" in the opposite direction of gravity.

[0021] Throughout the specification, unless explicitly stated to the contrary, the word "comprising" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements. In addition, two directions parallel to the upper surface of the substrate and intersecting each other are respectively defined as a first direction (Y direction) and a second direction (X direction), and the direction perpendicular to the upper surface of the substrate is interpreted as a third direction (Z direction). For example, the first direction (Y direction) and the second direction (X direction) can be perpendicular to each other.

[0022] In the following, reference will be made to Figures 1 to 3 describe in detail a semiconductor device according to an embodiment, where Figure 1 is a layout diagram for explaining the layout of a semiconductor device according to an embodiment, Figure 2 is a cross-sectional view of the semiconductor device taken along lines A-A' and B-B', and Figure 1 and Figure 3 is Figure 2 an enlarged cross-sectional view of P1 of

[0023] Refer to Figures 1 to 3, A semiconductor device according to an embodiment may include a peripheral circuit structure PS and a cell array structure CS located on the peripheral circuit structure PS. The peripheral circuit structure PS may include a substrate 100, a core integrated on the upper surface of the substrate 100, and a peripheral circuit SA. The substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but is not limited thereto. For example, the substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor-on-insulator (SOI) substrate. Hereinafter, it is described that the substrate 100 is a silicon substrate. The core and the peripheral circuit SA may include NMOS transistors and PMOS transistors integrated on the substrate 100. The core and the peripheral circuit SA may be electrically connected to the bit lines BL through peripheral circuit wirings and peripheral circuit contact plugs. That is, the sense amplifiers may be electrically connected to the bit lines BL, and each sense amplifier may amplify and output the difference in voltage levels detected by a pair of bit lines BL.

[0024] The cell array structure CS may include memory cells including vertical channel transistors (VCTs). The VCT may refer to a structure in which the channel length extends in a direction perpendicular to the upper surface of the substrate 100 (e.g., the third direction Z). In one embodiment, the cell array structure CS may include a lower insulating layer 110, bit lines BL, a first insulating pattern 120, a channel pattern CP, word lines WL1 and WL2, a gate insulating pattern Gox, a second insulating pattern 130, a third insulating pattern 140, a contact pattern BC, an interlayer insulating layer 150, and a data storage pattern DSP.

[0025] The lower insulating layer 110 may cover the core and the peripheral circuit SA, the peripheral circuit wirings, and the peripheral circuit contact plugs on the substrate 100. The lower insulating layer 110 may include insulating films stacked in multiple layers. For example, the lower insulating layer 110 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a low-k dielectric film, or a combination thereof.

[0026] The bit lines BL may be located on the substrate 100. For example, the lower insulating layer 110 may be located on the substrate 100, and the bit lines BL may be located on the lower insulating layer 110. The bit lines BL extend in a first direction (Y direction) and may be arranged to be spaced apart in a second direction (X direction). The lower insulating layer 110 may be provided to fill the space between the bit lines BL. For example, the upper surface of the lower insulating layer 110 and the upper surface of the bit lines BL may be at substantially the same height.

[0027] The bit line BL may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line BL may be made of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x 、or a combination thereof, but is not limited thereto. The bit line BL may include a single layer or multiple layers of the above materials. Moreover, in some embodiments, the bit line BL may include two-dimensional (2D) semiconductor materials (e.g., graphene, carbon nanotubes, or a combination thereof).

[0028] The bit line BL has an opening therein, and the opening has a first recess RC1 that opens in the third direction (Z direction). As will be described below with reference to Figure 9 and Figure 10 , after forming the first insulating pattern 120 that defines the first trench TRC1, the first recess RC1 may be formed by etching the bit line BL. At this time, the first recess RC1 may have an enlarged structure by over-etching the bit line BL laterally. In other words, the width W_RC of the first recess RC1 in the bit line BL in the first direction (Y direction) may be greater than the distance between the first insulating patterns 120 in the first direction (Y direction) (i.e., the width of the first trench TRC1 in the first direction (Y direction)). Here, the width W_RC of the first recess RC1 in the first direction (Y direction) may be the maximum width among the widths of the first recess RC1 in the first direction (Y direction).

[0029] Therefore, the width W_RC of the first recess RC1 in the first direction (Y direction) may be greater than the width W_OP of the opening of the first recess RC1 in the first direction (Y direction). Here, the width W_OP of the opening of the first recess RC1 in the first direction (Y direction) may be the width of the first recess RC1 in the first direction (Y direction) "at the uppermost end of the first recess RC1 along the third direction (Z direction)". In addition, the width W_RC of the first recess RC1 in the first direction (Y direction) may be greater than the distance between the first insulating patterns 120 in the first direction (Y direction), which will be described below. In addition, the width W_RC of the first recess RC1 in the first direction (Y direction) may be greater than the width of the first trench TRC1 (in Figure 10 ), which will be described below, in the first direction (Y direction).

[0030] In addition, the width W_RC of the first recess RC1 in the bit line BL in the first direction (Y direction) may have a maximum value at the middle region of the first recess RC1, and the width W_RC of the first recess RC1 in the bit line BL in the first direction (Y direction) may have a minimum value at the uppermost or lowermost end of the first recess RC1 along the third direction (Z direction). For example, the width W_RC of the first recess RC1 in the bit line BL in the first direction (Y direction) may have the characteristic of "gradually increasing towards the inside of the bit line BL (i.e., downward along the third direction (Z direction)), reaching the maximum value, and then gradually decreasing".

[0031] Therefore, the first recess RC1 may have an extension EL_RC1 protruding towards the bit line BL in the first direction (Y direction). Here, the extension EL_RC1 of the first recess RC1 refers to the part where the width W_RC of the first recess RC1 in the first direction (Y direction) is greater than the distance between the first insulating patterns 120 in the first direction (Y direction). At this time, the extension EL_RC1 of the first recess RC1 may have a surface that "contacts the bit line BL in a convex shape towards the bit line BL in the first direction (Y direction)" (i.e., the extension EL_RC1 of the first recess RC1 may have a shape protruding towards the bit line BL).

[0032] The first insulating pattern 120 is located above the bit line BL and may extend in the second direction (X direction). The first insulating pattern 120 may be arranged to intersect the bit line BL. The first insulating patterns 120 may be spaced apart in the first direction (Y direction). Since the first insulating patterns 120 are spaced apart in the first direction (Y direction), a channel trench TRC may be formed between the first insulating patterns 120. The channel trench TRC may extend in the second direction (X direction) like the first insulating pattern 120 and may be arranged to be spaced apart in the first direction (Y direction).

[0033] The first insulating pattern 120 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, a low-k material having a dielectric constant smaller than that of silicon oxide, or a combination thereof, but is not limited thereto.

[0034] The low-k material may include, for example, FOX (flowable oxide), TOSZ (Torene SilaZene), USG (undoped silicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PTEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluoride silicate glass), CDO (carbon-doped silicon oxide), dry gel, aerogel, amorphous fluorocarbon, OSG (organic silicate glass), parylene, BCB (benzocyclobutene), SiLK, polyimide, a porous polymer material, or a combination thereof, but is not limited thereto.

[0035] The channel pattern CP includes a first portion CP1 inserted into a bit line BL (e.g., an opening of the bit line BL) and a second portion CP2 located above the bit line BL. In other words, the first portion CP1 of the channel pattern CP is located in the first recess RC1, and the second portion CP2 is located above the bit line BL. The first portion CP1 of the channel pattern CP may include a first sidewall portion SW1_CP1, a second sidewall portion SW2_CP1, and a lower end portion LP_CP1. The first sidewall portion SW1_CP1 and the second sidewall portion SW2_CP1 are located within the first recess RC1 and are arranged to be adjacent to the sidewalls of the first recess RC1 that face each other in the first direction (Y direction). The lower end portion LP_CP1 is disposed on the bottom surface of the first recess RC1 and is connected between the first sidewall portion SW1_CP1 and the second sidewall portion SW2_CP1.

[0036] The second portion CP2 of the channel pattern CP may be arranged to be adjacent to the sidewall of the first insulating pattern 120. The second portion CP2 of the channel pattern CP may be located within the channel trench TRC. In other words, the second portion CP2 of the channel pattern CP may be located above the bit line BL and may be located on each of the first sidewall portion SW1_CP1 and the second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP. Thus, the channel pattern CP may have an overall "U" shape in a cross-section cut along the first direction (Y direction) and the third direction (Z direction). In addition, the channel pattern CP may extend in the second direction (X direction).

[0037] The first portion CP1 of the channel pattern CP may fill the extension EL_RC1 of the first recess RC1. Accordingly, the thickness T_CP1 of the first sidewall portion SW1_CP1 or the second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP in the first direction (Y direction) may be greater than the thickness T_CP2 of the second portion CP2 of the channel pattern CP in the first direction (Y direction). Here, the thickness T_CP1 of the first sidewall portion SW1_CP1 or the second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP in the first direction (Y direction) may be the maximum thickness of the first sidewall portion SW1_CP1 or the second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP in the first direction (Y direction), and the thickness T_CP2 of the second portion CP2 of the channel pattern CP in the first direction (Y direction) may be the maximum thickness of the second portion CP2 of the channel pattern CP in the first direction (Y direction).

[0038] For example, when the thickness T_CP2 of the second part CP2 of the channel pattern CP in the first direction (Y direction) is 1, the thickness T_CP1 of the first sidewall part SW1_CP1 or the second sidewall part SW2_CP1 of the first part CP1 of the channel pattern CP in the first direction (Y direction) can be 1.1 or greater (e.g., 1.2 or greater, 1.3 or greater, 1.4 or greater, 1.5 or greater, or 2 or greater), and can be 2 or less, 1.5 or less, 1.4 or less, 1.3 or less, or 1.2 or less.

[0039] In addition, the thickness T_CP1 of the first sidewall part SW1_CP1 or the second sidewall part SW2_CP1 of the first part CP1 of the channel pattern CP in the first direction (Y direction) can be greater than the thickness T_LP_CP1 of the lower end part LP_CP1 of the first part CP1 of the channel pattern CP in the third direction (Z direction). Here, the thickness T_LP_CP1 of the lower end part LP_CP1 of the first part CP1 of the channel pattern CP in the third direction (Z direction) can be the maximum thickness of the lower end part LP_CP1 of the first part CP1 of the channel pattern CP in the third direction (Z direction).

[0040] For example, when the thickness T_LP_CP1 of the lower end part LP_CP1 of the first part CP1 of the channel pattern CP in the third direction (Z direction) is 1, the thickness T_CP1 of the first sidewall part SW1_CP1 or the second sidewall part SW2_CP1 of the first part CP1 of the channel pattern CP in the first direction (Y direction) can be 1.1 or greater, 1.2 or greater, 1.3 or greater, 1.4 or greater, 1.5 or greater, or 2 or greater, and can be 2 or less, 1.5 or less, 1.4 or less, 1.3 or less, or 1.2 or less.

[0041] In addition, the thickness T_CP1 of the first sidewall part SW1_CP1 or the second sidewall part SW2_CP1 of the first part CP1 of the channel pattern CP in the first direction (Y direction) can have a maximum value at the middle region of the first recess RC1, and the thickness T_CP1 of the first sidewall part SW1_CP1 or the second sidewall part SW2_CP1 of the first part CP1 of the channel pattern CP in the first direction (Y direction) can have a minimum value at the uppermost or lowermost end of the first recess RC1 in the third direction (Z direction). For example, the thickness T_CP1 of the first sidewall part SW1_CP1 or the second sidewall part SW2_CP1 of the first part CP1 of the channel pattern CP in the first direction (Y direction) can have the characteristic of "gradually increasing towards the inside of the bit line BL (i.e., downward in the third direction (Z direction)), reaching the maximum value, and then gradually decreasing".

[0042] Accordingly, the first portion CP1 of the channel pattern CP may have a surface S_CP1 that "contacts the bit line BL in a convex shape toward the bit line BL in a first direction (Y direction)" (i.e., the first sidewall portion SW1_CP1 or the second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP may have a shape protruding toward the bit line BL). As described above, the contact area between the bit line BL and the channel pattern CP is increased, and thus, the contact resistance of the semiconductor device can be reduced, and the on-current I can be improved. on .

[0043] For example, the channel pattern CP may have an overall conformal shape. That is, the channel pattern CP may cover the bottom surface of the first recess RC1 of the bit line BL, the sidewall of the first recess RC1 of the bit line BL, and the sidewall of the first insulating pattern 120 by a specific thickness, and the thickness T_CP2 of the second portion CP2 of the channel pattern CP in the first direction (Y direction) and the thickness T_LP_CP1 of the lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP in the third direction (Z direction) may be similar to each other.

[0044] However, as the first portion CP1 of the channel pattern CP fills the extension portion EL_RC1 of the first recess RC1, the thickness T_CP1 of the first sidewall portion SW1_CP1 or the second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP in the first direction (Y direction) may be greater than each of the thickness T_CP2 of the second portion CP2 of the channel pattern CP in the first direction (Y direction) and the thickness T_LP_CP1 of the lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP in the third direction (Z direction).

[0045] Meanwhile, the upper surface of the second portion CP2 of the channel pattern CP adjacent to the sidewall of the first insulating pattern 120 may be located at a height lower than the upper surface of the first insulating pattern 120. The upper surface of the second portion CP2 of the channel pattern CP adjacent to the sidewall of the first insulating pattern 120 may contact the contact pattern BC, which will be described below.

[0046] The channel pattern CP may be arranged to be spaced apart in a second direction (X direction) within the channel trench TRC. In other words, the first sidewall portion SW1_CP1 of the first part CP1 of the channel pattern CP and the second part CP2 on the first sidewall portion SW1_CP1 may be located on one side surface of the channel trench TRC in a first direction (Y direction), and the second sidewall portion SW2_CP1 of the first part CP1 of the channel pattern CP and the second part CP2 on the second sidewall portion SW2_CP1 may be located on the other side surface of the channel trench TRC in the first direction (Y direction). However, the first sidewall portion SW1_CP1 and the second sidewall portion SW2_CP1 of the first part CP1 of the channel pattern CP may be connected to each other through a lower end portion LP_CP1 on the bottom surface of the first recess RC1. In addition, the second insulating pattern 130 and the third insulating pattern 140, which will be described below, may be located between the channel patterns CP adjacent in the first direction (Y direction).

[0047] The channel pattern CP may include a first source / drain region and a second source / drain region. For example, the first part CP1 of the channel pattern CP may be connected to the bit line BL and serve as the first source / drain region, a part of the second part CP2 of the channel pattern CP may be connected to the contact pattern BC and serve as the second source / drain region, and the remaining portion of the second part CP2 of the channel pattern CP between the first source / drain region and the second source / drain region may serve as the channel region.

[0048] The channel pattern CP may include an oxide semiconductor material. The oxide semiconductor material may be an oxide of a material including In, Ga, Zn, Al, Sn, Hf, or a combination thereof, but is not limited thereto. The oxide semiconductor material may also include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn into the above components. For example, the channel pattern CP may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZZTO), tin oxide (SnO), hafnium indium zinc oxide (HIZO), gallium zinc tin oxide (GZTO), aluminum zinc tin oxide (AZTO), ytterbium gallium zinc oxide (YGZO), IGO (indium gallium oxide), or a combination thereof. However, the channel pattern CP is not limited thereto, and the oxide semiconductor material included in the channel pattern CP may be changed in various ways.

[0049] According to some embodiments, the first part CP1 and the second part CP2 of the channel pattern CP may include different oxide semiconductor materials. For example, the second part CP2 of the channel pattern CP may include IGZO, and the first part CP1 of the channel pattern CP may exclude indium oxide, zinc oxide, gallium oxide, or a combination thereof and further include other oxides. Optionally, the oxide semiconductor materials of the first part CP1 of the channel pattern CP and the second part CP2 of the channel pattern CP may have the same components but different component ratios. For example, when the first part CP1 of the channel pattern CP and the second part CP2 of the channel pattern CP include IGZO, the component ratios of indium, gallium, zinc, and oxygen of the first part CP1 of the channel pattern CP may be different from the component ratios of indium, gallium, zinc, and oxygen of the second part CP2 of the channel pattern CP.

[0050] For example, the first part CP1 of the channel pattern CP may include an oxide semiconductor material having a higher component ratio of indium than the material of the second part CP2 of the channel pattern CP. As the component ratio of indium increases, the contact resistance can be improved (reduced). The second part CP2 of the channel pattern CP may include an oxide semiconductor material having a higher component ratio of gallium than the material of the first part CP1. The higher the component ratio of gallium, the more the reliability can be improved. Here, improving the reliability may mean reducing the change in film quality that occurs as the semiconductor device operates.

[0051] The word lines WL1 and WL2 may extend across the bit line BL in the second direction (X direction) and may be arranged to be spaced apart in the first direction (Y direction). The word lines WL1 and WL2 may be spaced apart from the bit line BL in the third direction (Z direction). A pair of word lines WL1 and WL2 may be located between the channel patterns CP within the channel trench TRC. A pair of word lines WL1 and WL2 may be located between the second parts CP2 of the channel patterns CP covering the two sidewalls of the channel trench TRC. In addition, a pair of word lines WL1 and WL2 may extend through the opening of the bit line BL and extend into the first recess RC1. Each of the word lines WL1 and WL2 may have one side and the other side facing each other in the first direction (Y direction), and the pair of word lines WL1 and WL2 located in the channel trench TRC may be arranged such that one side of them faces each other.

[0052] The word lines WL1 and WL2 can be spaced apart from the channel pattern CP. The word lines WL1 and WL2 can be spaced apart from the channel pattern CP by a gate insulating pattern Gox, which will be described below. That is, the gate insulating pattern Gox is located between the word lines WL1 and WL2 and the channel pattern CP. The word lines WL1 and WL2 can include upper and lower surfaces facing each other in a third direction (Z direction). The lower surfaces of the word lines WL1 and WL2 can face the bit line BL, where the gate insulating pattern Gox and the channel pattern CP are disposed between the lower surfaces of the word lines WL1 and WL2 and the bit line BL. The upper surfaces of the word lines WL1 and WL2 can face the contact pattern BC, where a second insulating pattern 130 and a third insulating pattern 140, which will be described below, are disposed between the upper surfaces of the word lines WL1 and WL2 and the contact pattern BC.

[0053] It is shown that the upper surfaces of the word lines WL1 and WL2 are located at a higher height than the upper surfaces of the second part CP2 of the adjacent channel pattern CP, but the upper surfaces of the word lines WL1 and WL2 are not limited thereto, and the upper surfaces of the word lines WL1 and WL2 can be located at substantially the same height as the upper surfaces of the second part CP2 of the adjacent channel pattern CP or at a lower height than the upper surfaces of the second part CP2 of the adjacent channel pattern CP. The word lines WL1 and WL2 can include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The word lines WL1 and WL2 can include, for example, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x 、or a combination thereof, but is not limited thereto. The word lines WL1 and WL2 can include a single layer or multiple layers of the above materials. In some embodiments, the word lines WL1 and WL2 can include 2D semiconductor materials (e.g., graphene, carbon nanotubes, or a combination thereof).

[0054] The gate insulating pattern Gox may be located between the channel pattern CP and the word lines WL1 and WL2. The gate insulating pattern Gox may conformally cover the channel pattern CP. That is, the gate insulating pattern Gox may be disposed adjacent to the following components: a pair of second portions CP2 of the channel pattern CP that face each other in the channel trench TRC, a first sidewall portion SW1_CP1 and a second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP, and a lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP. In one embodiment, the gate insulating pattern Gox may include a first portion Gox1 inserted into the bit line BL and a second portion Gox2 located above the bit line BL. In other words, the first portion Gox1 of the gate insulating pattern Gox may be located in the first recess RC1, and the second portion Gox2 of the gate insulating pattern Gox may be located above the bit line BL.

[0055] The gate insulating pattern Gox covering the sidewalls of the second portion CP2 of the channel pattern CP may further extend in the third direction (Z direction). However, it is shown that the gate insulating pattern Gox extends to a height substantially the same as the upper surface of the first insulating pattern 120, but is not limited thereto. For example, the uppermost surface of the gate insulating pattern Gox may be located at a height lower than the upper surface of the first insulating pattern 120. In addition, the uppermost surface of the gate insulating pattern Gox may be located at a height substantially the same as the upper surfaces of the word lines WL1 and WL2 or at a height higher than the upper surfaces of the word lines WL1 and WL2.

[0056] The gate insulating pattern Gox may overlap with the first sidewall portion SW1_CP1 and the second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP and the second portion CP2 of the channel pattern CP in the first direction (Y direction). A portion of the gate insulating pattern Gox that does not overlap with the second portion CP2 of the channel pattern CP may contact the contact pattern BC described below and be located between the contact pattern BC and the second insulating pattern 130. The gate insulating pattern Gox may overlap with the lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP in the third direction (Z direction). At this time, one side of the gate insulating pattern Gox may be adjacent to the lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP, and the other side of the gate insulating pattern Gox may be adjacent to the lower surfaces of the word lines WL1 and WL2 and the lower surface of the second insulating pattern 130.

[0057] However, Figure 3It is shown that the gate insulating pattern Gox is seamlessly connected to the lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP in the first direction (Y direction) to have an overall "U" shape, but is not limited thereto. In one embodiment, a central portion of the gate insulating pattern Gox adjacent to the lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP may be disconnected such that the gate insulating pattern Gox has an overall "└ ┘" shape, and the second insulating pattern 130 may be located between the disconnected central portions of the gate insulating pattern Gox.

[0058] The gate insulating pattern Gox may include silicon oxide, silicon oxynitride, a high-k material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k material may include a metal oxide or a metal oxynitride. The high-k material may include, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof. However, the gate insulating pattern Gox is not limited thereto, and the materials included in the gate insulating pattern Gox may be changed in various ways.

[0059] The second insulating pattern 130 and the third insulating pattern 140 may be located in the channel trench TRC. The second insulating pattern 130 and the third insulating pattern 140 may be located above the word lines WL1 and WL2 and the gate insulating pattern Gox. The second insulating pattern 130 may be in contact with the word lines WL1 and WL2 and the gate insulating pattern Gox. The second insulating pattern 130 may conformally cover the word lines WL1 and WL2 and the gate insulating pattern Gox. The second insulating pattern 130 may cover the upper surfaces and the side walls facing each other of the word lines WL1 and WL2 located in the channel trench TRC. The second insulating pattern 130 may cover the portion of the gate insulating pattern Gox in the channel trench TRC that is not covered by the word lines WL1 and WL2. The second insulating pattern 130 may cover the upper surface of the gate insulating pattern Gox located between the word lines WL1 and WL2. The second insulating pattern 130 may cover the side walls of the gate insulating pattern Gox protruding in the third direction (Z direction) from the upper surfaces of the word lines WL1 and WL2.

[0060] The third insulating pattern 140 may be located on the second insulating pattern 130. The third insulating pattern 140 may be spaced apart from the word lines WL1 and WL2 and the gate insulating pattern Gox by the second insulating pattern 130. That is, the second insulating pattern 130 may be located between the word lines WL1 and WL2 and the third insulating pattern 140, and between the gate insulating pattern Gox and the third insulating pattern 140. The third insulating pattern 140 may fill the remaining channel trench TRC after the channel pattern CP, the gate insulating pattern Gox, the word lines WL1 and WL2, and the second insulating pattern 130 are formed.

[0061] The third insulating pattern 140 may include a vertical portion between the word lines WL1 and WL2 and a horizontal portion above the upper surfaces of the word lines WL1 and WL2. Accordingly, the third insulating pattern 140 may have a "T" shape in a cross-section cut along the first direction (Y direction) and the third direction (Z direction). The vertical portion of the third insulating pattern 140 may extend from the horizontal portion of the third insulating pattern 140 toward the bit line BL in the third direction (Z direction). The horizontal portion of the third insulating pattern 140 may be farther from the bit line BL than the vertical portion of the third insulating pattern 140. In a cross-section cut along the first direction (Y direction) and the third direction (Z direction), the width (in the Y direction) of the horizontal portion of the third insulating pattern 140 may be greater than the width (in the Y direction) of the vertical portion of the third insulating pattern 140.

[0062] The second insulating pattern 130 and the third insulating pattern 140 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, a low-k material having a dielectric constant smaller than that of silicon oxide, or a combination thereof, but is not limited thereto. For example, the second insulating pattern 130 and the third insulating pattern 140 may include different materials. For example, the second insulating pattern 130 may include silicon nitride, and the third insulating pattern 140 may include silicon oxide. When the second insulating pattern 130 and the third insulating pattern 140 include different materials, the second insulating pattern 130 and the third insulating pattern 140 may be formed sequentially, but when the second insulating pattern 130 and the third insulating pattern 140 include the same material, the second insulating pattern 130 and the third insulating pattern 140 may be formed integrally.

[0063] The contact pattern BC may be arranged to overlap at least a part of the channel pattern CP in the third direction (Z direction). The contact patterns BC may be arranged to be spaced apart from each other in the first direction (Y direction) and the second direction (X direction). The contact patterns BC may be arranged in a matrix form, but this is only an example and is not limited thereto. The contact patterns BC may be arranged in various shapes (such as a honeycomb shape). In addition, the contact pattern BC may have a circular shape, an oval shape, a rectangular shape, a square shape, a rhombus shape, or a hexagonal shape on a plane, but the planar shape of the contact pattern BC is not limited thereto.

[0064] The contact pattern BC may be electrically connected to the channel pattern CP. The contact pattern BC may contact at least a portion of the channel pattern CP. In some embodiments, the contact pattern BC may be located between the first insulating pattern 120 and the gate insulating pattern Gox. The contact pattern BC may include a first portion extending in a first direction (Y direction) and a second portion extending from the first portion in a third direction (Z direction). The first portion of the contact pattern BC may be located on the upper surface of the gate insulating pattern Gox, the upper surface of the second insulating pattern 130, and the upper surface of the third insulating pattern 140. The lower surface of the first portion of the contact pattern BC is shown to be at substantially the same height as each of the upper surface of the first insulating pattern 120 and the upper surface of the third insulating pattern 140, but is not limited thereto. For example, the lower surface of the first portion of the contact pattern BC may be at a height lower than each of the upper surface of the first insulating pattern 120 and the upper surface of the third insulating pattern 140.

[0065] The second portion of the contact pattern BC may extend from the first portion toward the bit line BL in the third direction (Z direction) and contact the upper surface of the second portion CP2 of the channel pattern CP. Accordingly, the contact pattern BC may be electrically connected to the second portion CP2 of the channel pattern CP and may be electrically connected to the first portion CP1 of the channel pattern CP through the second portion CP2 of the channel pattern CP.

[0066] One side of the second portion of the contact pattern BC in the first direction (Y direction) may contact the first insulating pattern 120, and the other side in the first direction (Y direction) may contact the gate insulating pattern Gox. The lower surface of the second portion of the contact pattern BC may be at a height lower than the upper surface of the word lines WL1 and WL2, but is not limited thereto. For example, the lower surface of the second portion of the contact pattern BC may be at substantially the same height as the upper surface of the word lines WL1 and WL2 or at a height higher than the upper surface of the word lines WL1 and WL2. The contact pattern BC may include doped polysilicon, metal, conductive metal nitride, conductive metal oxide, or a combination thereof. For example, the contact pattern BC may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x 、or a combination thereof, but is not limited thereto.

[0067] In some embodiments, a landing pad may be disposed on the contact pattern BC. The landing pads may be arranged to overlap at least a portion of the contact pattern BC in a third direction (Z direction). The landing pads may be arranged to be spaced apart from each other in a first direction (Y direction) and a second direction (X direction). The landing pads may be arranged in a matrix form, but this is only an example and is not limited thereto. The landing pads may be arranged in various shapes (such as a honeycomb shape). In addition, the landing pads may have a circular shape, an oval shape, a rectangular shape, a square shape, a rhombus shape, or a hexagonal shape in a plane, but the planar shape of the landing pads is not limited thereto.

[0068] The landing pads may include doped polysilicon, metal, conductive metal nitride, conductive metal oxide, or a combination thereof. For example, the landing pads may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x 、or a combination thereof, but is not limited thereto.

[0069] The interlayer insulating layer 150 may fill the space between the contact patterns BC, and the contact patterns BC are arranged to be spaced apart in a first direction (Y direction) on the first insulating pattern 120 and the third insulating pattern 140. For example, the lower surface of the interlayer insulating layer 150 may be located at substantially the same height as the lower surface of the first portion of the contact pattern BC, but is not limited thereto.

[0070] The data storage patterns may be respectively disposed on the landing pads LP. The data storage patterns DSP may be electrically connected to the channel patterns CP through the landing pads LP respectively. As Figure 1 shown, the data storage patterns DSP may be arranged in a matrix form in a first direction (Y direction) and a second direction (X direction). In one embodiment, the data storage pattern DSP may be a capacitor and may include a lower electrode, an upper electrode, and a capacitor dielectric film disposed therebetween. When the data storage pattern DSP is a capacitor, the lower electrode may contact the landing pad LP, and the lower electrode may have various shapes (such as a circular shape, an oval shape, a rectangular shape, a square shape, a rhombus shape, or a hexagonal shape) in a plane.

[0071] In contrast, the data storage pattern DSP may be a variable resistance pattern, and the variable resistance pattern can be switched between two resistance states by applying an electrical pulse to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystalline state changes according to the amount of current.

[0072] In the following, reference is made to Figure 4 to describe some embodiments of a semiconductor device. In the following embodiments, components that are the same as those in the above embodiments are denoted by the same reference numerals, redundant descriptions thereof are omitted or simplified, and differences are mainly explained.

[0073] Figure 4 is a diagram for explaining a semiconductor device according to some embodiments and is a cross-sectional view corresponding to Figure 3 the corresponding cross-sectional view. Figure 3 It is shown that a first portion CP1 of a channel pattern CP fills an extension EL_RC1 of a first recess RC1, and a thickness T_CP1 of a first sidewall portion SW1_CP1 or a second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP in a first direction (Y direction) is greater than a thickness T_CP2 of a second portion CP2 of the channel pattern CP in the first direction (Y direction). On the other hand, it is shown that a gate insulating pattern Gox conformally covers the channel pattern CP.

[0074] Referring to Figure 4 , a first portion CP1 of a channel pattern CP fills an extension EL_RC1 of a first recess RC1, but a thickness T_CP1 of a first sidewall portion SW1_CP1 or a second sidewall portion SW2_CP1 of the first portion CP1 of the channel pattern CP in a first direction (Y direction) may not be greater than (e.g., may not be significantly greater than) a thickness T_CP2 of a second portion CP2 of the channel pattern CP in the first direction (Y direction) and may be substantially the same as the thickness T_CP2.

[0075] In other words, the channel pattern CP may have an overall conformal shape. That is to say, the channel pattern CP may cover a specific thickness on the bottom surface of the first recess RC1 of the bit line BL, the sidewall of the first recess RC1 of the bit line BL, and the sidewall of the first insulating pattern 120. Therefore, an inner surface of the first portion CP1 of the channel pattern CP may have a second recess RC2 that opens in a third direction (Z direction). A width of the second recess RC2 in the first direction (Y direction) may be greater than a width of an opening of the second recess RC2 in the first direction (Y direction). Here, the width of the opening of the second recess RC2 in the first direction (Y direction) may be the width of the second recess RC2 in the first direction (Y direction) starting from the uppermost end of the second recess RC2 in the third direction (Z direction). In addition, the width of the second recess RC2 in the first direction (Y direction) may be greater than a minimum distance between a pair of second portions CP2 of the channel pattern CP in the first direction (Y direction).

[0076] In addition, the width of the second recess RC2 in the channel pattern CP in the first direction (Y direction) may have a maximum value at the middle region of the second recess RC2, and the width of the second recess RC2 in the channel pattern CP in the first direction (Y direction) may have a minimum value at the uppermost or lowermost end of the second recess RC2 in the third direction (Z direction). For example, the width W_RC of the second recess RC2 in the channel pattern CP in the first direction (Y direction) may have the characteristic of "gradually increasing towards the inside of the first part CP1 of the channel pattern CP (i.e., downward along the third direction (Z direction)), reaching the maximum value, and then gradually decreasing".

[0077] Therefore, the second recess RC2 of the channel pattern CP may have an extension portion EL_RC2 that protrudes towards the first sidewall portion SW1_CP1 and the second sidewall portion SW2_CP1 of the first part CP1 of the channel pattern CP in the first direction (Y direction). Here, the extension portion EL_RC2 of the second recess RC2 refers to the portion where the width W_RC of the second recess RC2 in the first direction (Y direction) is greater than the minimum distance between the pair of second parts CP2 of the channel pattern CP in the first direction (Y direction).

[0078] At this time, the gate insulating pattern Gox includes a first part Gox1 inserted into the bit line BL and a second part Gox2 located above the bit line BL. In other words, the first part Gox1 of the gate insulating pattern Gox is located in the first recess RC1, and the second part Gox2 is located above the bit line BL. In addition, the first part Gox1 of the gate insulating pattern Gox may include a first sidewall portion SW1_Gox1, a second sidewall portion SW2_Gox1, and a lower end portion LP_Gox1. The first sidewall portion SW1_Gox1 and the second sidewall portion SW2_Gox1 are respectively located inside the second recess RC2 of the channel pattern CP and are arranged adjacent to the sidewalls of the second recess RC2 of the channel pattern CP that face each other in the first direction (Y direction). The lower end portion LP_Gox1 is provided on the bottom surface of the second recess RC2 and is connected between the first sidewall portion SW1_Gox1 and the second sidewall portion SW2_Gox1.

[0079] The second part Gox2 of the gate insulating pattern Gox may be arranged adjacent to the sidewalls of the second part CP2 of the channel pattern CP. In addition, the second part Gox2 of the gate insulating pattern Gox may be located above the bit line BL and may be located on each of the first sidewall portion SW1_Gox1 and the second sidewall portion SW2_Gox1 of the first part Gox1 of the gate insulating pattern Gox. Therefore, the gate insulating pattern Gox may have an overall "U" shape in the cross-section cut along the first direction (Y direction) and the third direction (Z direction).

[0080] The first portion Gox1 of the gate insulating pattern Gox may fill the extension EL_RC2 of the second recess RC2. Accordingly, the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may be greater than the thickness T_Gox2 of the second portion Gox2 of the gate insulating pattern Gox in the first direction (Y direction). Here, the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may be the maximum thickness of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction), and the thickness T_Gox2 of the second portion Gox2 of the gate insulating pattern Gox in the first direction (Y direction) may be the maximum thickness of the second portion Gox2 of the gate insulating pattern Gox in the first direction (Y direction).

[0081] In addition, the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may be greater than the thickness T_LP_Gox1 of the lower end portion LP_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the third direction (Z direction). Here, the thickness T_LP_Gox1 of the lower end portion LP_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the third direction (Z direction) may be the maximum thickness of the lower end portion LP_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the third direction (Z direction).

[0082] In addition, the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may have a maximum value at an intermediate region inside the second recess RC2, and the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may have a minimum value at the uppermost or lowermost end of the second recess RC2 in the third direction (Z direction). For example, the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may have the characteristic of "gradually increasing towards the inside of the second recess RC2 (i.e., downward in the third direction (Z direction)), reaching a maximum value, and then gradually decreasing".

[0083] Thus, the first portion Gox1 of the gate insulating pattern Gox may have a surface S_Gox1 that "contacts the channel pattern CP in a convex shape toward the channel pattern CP in the first direction (Y direction)" (i.e., the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox may have a shape that protrudes toward the channel pattern CP). For example, the gate insulating pattern Gox may have an overall conformal shape. That is, the gate insulating pattern Gox may cover the inner surface of the second recess RC2 and the sidewalls of the second portion CP2 of the channel pattern CP by a specific thickness, and the thickness T_LP_Gox1 of the lower end portion LP_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the third direction (Z direction) may be greater than the thickness T_Gox2 of the second portion Gox2 of the gate insulating pattern Gox in the first direction (Y direction). In some embodiments, the thickness T_Gox2 of the second portion Gox2 of the gate insulating pattern Gox in the first direction (Y direction) and the thickness T_LP_Gox1 of the lower end portion LP_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the third direction (Z direction) may be similar to each other (e.g., equal).

[0084] However, as the first portion Gox1 of the gate insulating pattern Gox fills the extension EL_RC2 of the second recess RC2, the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may be greater than each of the thickness T_Gox2 of the second portion Gox2 of the gate insulating pattern Gox in the first direction (Y direction) and the thickness T_LP_Gox1 of the lower end portion LP_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the third direction (Z direction).

[0085] Hereinafter, refer to Figure 5 Some embodiments of the semiconductor device are described. In the following embodiments, the same components as those in the above embodiments are denoted by the same reference numerals, and their redundant descriptions are omitted or simplified, and the differences are mainly explained.

[0086] Figure 5 is a diagram for explaining a semiconductor device according to some embodiments and is a cross-sectional view corresponding to Figure 3 corresponding. Figure 3 It is shown that the extension EL_RC1 of the first recess RC1 of the bit line BL has a surface S_CP1 that "contacts the bit line BL in a convex shape toward the bit line BL in the first direction (Y direction)" (i.e., the extension EL_RC1 of the first recess RC1 has a shape that protrudes toward the bit line BL).

[0087] Figure 5 The first recess RC1 showing the bit line BL has a surface S_CP1 that is concave in the first direction (Y direction) and contacts the bit line BL (i.e., the bit line BL has a shape that protrudes toward the first recess RC1). Thus, the width W_RC of the first recess RC1 in the bit line BL in the first direction (Y direction) can be smaller than the distance between the first insulating patterns 120 in the first direction (Y direction) (i.e., the width of the first trench TRC1 in the first direction (Y direction) in Figure 10 ). Here, the width W_RC of the first recess RC1 in the first direction (Y direction) can be the minimum width among the widths of the first recess RC1 in the first direction (Y direction).

[0088] In addition, the width W_RC of the first recess RC1 in the first direction (Y direction) can be smaller than the width W_OP of the opening of the first recess RC1 in the first direction (Y direction). In addition, the width W_RC of the first recess RC1 in the first direction (Y direction) can be smaller than the distance between the first insulating patterns 120 in the first direction (Y direction). In addition, the width W_RC of the first recess RC1 in the first direction (Y direction) can be smaller than the width of the first trench TRC1 in the first direction (Y direction) in Figure 10 ), which will be described below.

[0089] In addition, the width W_RC of the first recess RC1 in the bit line BL in the first direction (Y direction) can have a minimum value at the lowermost end of the first recess RC1 in the third direction (Z direction), and the width W_RC of the first recess RC1 in the bit line BL in the first direction (Y direction) can have a maximum value at the uppermost end of the first recess RC1 in the third direction (Z direction). As described above, the contact area between the bit line BL and the channel pattern CP increases, and thus, the contact resistance of the semiconductor device can be reduced, and the on-current I on .

[0090] At this time, the channel pattern CP can have a conformal shape. That is, the channel pattern CP can have an overall conformal shape. That is, the channel pattern CP can cover the bottom surface of the first recess RC1 of the bit line BL, the side walls of the first recess RC1 of the bit line BL, and the side walls of the first insulating pattern 120 by a specific thickness, and the thickness T_CP1 of the first side wall portion SW1_CP1 or the second side wall portion SW2_CP1 of the first portion CP1 of the channel pattern CP in the first direction (Y direction) can be similar to each of the thickness T_CP2 of the second portion CP2 of the channel pattern CP in the first direction (Y direction) and the thickness T_LP_CP1 of the lower end portion LP_CP1 of the first portion CP1 of the channel pattern CP in the third direction (Z direction).

[0091] The gate insulating pattern Gox includes a first portion Gox1 inserted into the bit line BL and a second portion Gox2 located above the bit line BL. In other words, the first portion Gox1 of the gate insulating pattern Gox is located in the first recess RC1, and the second portion Gox2 is located above the bit line BL. The gate insulating pattern Gox may have a conformal shape. That is, the gate insulating pattern Gox may cover the inner surface of the second recess RC2 and the sidewalls of the second portion CP2 of the channel pattern CP with a specific thickness, and the thickness T_Gox1 of the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the first direction (Y direction) may be similar to each of the thickness T_Gox2 of the second portion Gox2 of the gate insulating pattern Gox in the first direction (Y direction) and the thickness T_LP_Gox1 of the lower end portion LP_Gox1 of the first portion Gox1 of the gate insulating pattern Gox in the third direction (Z direction).

[0092] The first portion Gox1 of the gate insulating pattern Gox may have a surface S_Gox1 that "contacts the channel pattern CP in the first direction (Y direction) in a concave shape facing the first portion CP1 of the channel pattern CP" (i.e., the first portion CP1 of the channel pattern CP may have a shape protruding toward the first sidewall portion SW1_Gox1 or the second sidewall portion SW2_Gox1 of the first portion Gox1 of the gate insulating pattern Gox).

[0093] In addition, the word lines WL1 and WL2 include first portions WL1_P1 and WL2_P1 inserted into the bit line BL and second portions WL1_P2 and WL2_P2 located above the bit line BL. In other words, the first portions WL1_P1 and WL2_P1 of the word lines WL1 and WL2 are located in the first recess RC1, and the second portions WL1_P2 and WL2_P2 are located above the bit line BL.

[0094] The first portions WL1_P1 and WL2_P1 of the word lines WL1 and WL2 may have a surface S_WL that "contacts the gate insulating pattern Gox in the first direction (Y direction) in a concave shape facing the first portion Gox1 of the gate insulating pattern Gox" (i.e., the first portion Gox1 of the gate insulating pattern Gox may have a shape protruding toward the first portions WL1_P1 and WL2_P1 of the word lines WL1 and WL2).

[0095] Hereinafter, refer to Figure 6 Describe some embodiments of the semiconductor device. In the following embodiments, the same components as those in the above embodiments are denoted by the same reference numerals, and their redundant descriptions are omitted or simplified, and the differences are mainly explained.

[0096] Figure 6 is a view for explaining a semiconductor device according to some embodiments and is a cross-sectional view corresponding to Figure 3 . Figure 3 It is shown that a second part of the contact pattern BC contacts a first insulating pattern 120 on one side in a first direction (Y direction), and the other side thereof in the first direction (Y direction) is flat and contacts a gate insulating pattern Gox. Figure 6 It is shown that the contact pattern BC further includes an extension part ET_BC extending from the second part in a third direction (Z direction). The extension part ET_BC of the contact pattern BC may extend from the second part toward a bit line BL in the third direction (Z direction) and is located between a channel pattern CP and a gate insulating pattern Gox.

[0097] In other words, the extension part ET_BC of the contact pattern BC is adjacent to the gate insulating pattern Gox on one side in the first direction (Y direction), and the extension part ET_BC is adjacent to the channel pattern CP on the other side in the first direction (Y direction). The extension part ET_BC of the contact pattern BC is adjacent to the second part of the contact pattern BC on one side in the third direction (Z direction), and the extension part ET_BC is adjacent to the channel pattern CP on the other side in the third direction (Z direction). Therefore, the contact area between the channel pattern CP and the contact pattern BC is increased, which can not only increase V o but also prevent V from decreasing by passivating the contact pattern BC first before sufficiently passivating the channel pattern CP when passivating with oxygen O2 in a subsequent process. th decrease.

[0098] Hereinafter, with reference to Figures 7 to 21 , a method of manufacturing a semiconductor device according to an embodiment shown in Figures 1 to 3 will be described. In Figures 7 to 21 , for convenience, a peripheral circuit structure PS is omitted, and a lower insulating layer 110 formed on the peripheral circuit structure PS is shown. Figure 2 is a cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to an embodiment. Figures 7 to 21

[0099] Figure 7 With reference to Figure 7 , a bit line BL may be formed on the lower insulating layer 110. The lower insulating layer 110 may include insulating films stacked in multiple layers. For example, the lower insulating layer 110 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a low-k dielectric film, or a combination thereof. The bit line BL may extend in a first direction (Y direction) and may be arranged to be spaced apart in a second direction (X direction) intersecting the first direction (Y direction). The bit line BL may be formed by depositing a conductive layer on the lower insulating layer 110 and then patterning the conductive layer.

[0100] Although not shown, an insulating material may be filled in the space between the bit lines BL. The insulating material may include the same insulating material as the lower insulating layer 110, but is not limited thereto. When the insulating material includes the same insulating material as the lower insulating layer 110, the insulating material may be integrated with the lower insulating layer 110. For example, the upper surface of the lower insulating layer 110 and the upper surface of the bit line BL may be located at substantially the same height.

[0101] Referring to Figure 8 , a first insulating pattern material layer 120_L may be formed on the bit line BL and the lower insulating layer 110. For example, the first insulating pattern material layer 120_L may be deposited by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process, but is not limited thereto. The first insulating pattern material layer 120_L may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0102] Referring to Figure 9 , the first insulating pattern 120 may be formed by patterning the first insulating pattern material layer 120_L. The first insulating pattern 120 may extend in the second direction (X direction), and the first insulating pattern 120 that defines first trenches TRC1 spaced apart from each other in the first direction (Y direction) may be formed. The first trenches TRC1 may intersect the bit line BL, and the first trenches TRC1 may expose the upper surface of the bit line BL.

[0103] Referring to Figure 10 , a first recess RC1 is formed by etching the bit line BL. At this time, the first recess RC1 may be formed in an enlarged structure by over-etching the bit line BL using the first insulating pattern 120 as a mask. In other words, the width of the first recess RC1 in the bit line BL in the first direction (Y direction) may be greater than the distance between the first insulating patterns 120 in the first direction (Y direction) (i.e., the width of the first trenches TRC1 in the first direction (Y direction)). Here, the width of the first recess RC1 in the first direction (Y direction) may be the maximum width among the widths of the first recess RC1 in the first direction (Y direction).

[0104] Referring to Figure 11, a channel pattern material layer CP_L can be formed inside the first recess RC1, on the sidewalls of the first insulating pattern 120, and on the upper surface of the first insulating pattern 120. For example, the channel pattern material layer CP_L can be formed by an atomic layer deposition (ALD) process. Therefore, the channel pattern material layer CP_L can be conformally deposited inside the first recess RC1, on the sidewalls of the first insulating pattern 120, and on the upper surface of the first insulating pattern 120. At this time, the channel pattern material layer CP_L can also fill the extension of the first recess RC1. For example, the channel pattern material layer CP_L can include an oxide semiconductor material. For example, the channel pattern material layer CP_L can include IGZO, but is not limited thereto.

[0105] Although not shown, a spin-on hard mask (SOH) layer can be formed on the channel pattern material layer CP_L. The SOH layer can be formed by a spin-coating process. For example, the SOH layer can include carbon, but is not limited thereto. Next, the channel pattern material layer CP_L can be etched by patterning the SOH layer, forming an SOH pattern, and using the SOH pattern as an etching mask. Therefore, the channel pattern material layer CP_L can be patterned and extend in the first direction (Y direction) on the bit line BL and be spaced apart in the second direction (X direction). The channel pattern material layer CP_L can cover the upper surface of the bit line BL, as well as the sidewalls and the upper surface of the first insulating pattern 120, in the first direction (Y direction). Next, the SOH pattern can be removed. For example, the SOH pattern can be removed by an ashing process or a strip process.

[0106] Referring to Figure 12 , a gate insulating pattern material layer Gox_L can be formed to conformally cover the channel pattern material layer CP_L. For example, the gate insulating pattern material layer Gox_L can be deposited by a CVD process, a PVD process, or an ALD process, but is not limited thereto. The gate insulating pattern material layer Gox_L can include silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material can include a metal oxide or a metal oxynitride.

[0107] Referring to Figure 13 , a word line material layer WL_L can be formed to conformally cover the gate insulating pattern material layer Gox_L. For example, the word line material layer WL_L can be deposited by a CVD process, a PVD process, or an ALD process, but is not limited thereto. The word line material layer WL_L can include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof.

[0108] Referring to Figure 14, a pair of word lines WL1 and WL2 spaced apart from each other in a first direction (Y direction) in the first trench TRC1 can be formed by performing an anisotropic etching process on the word line material layer WL_L. During the anisotropic etching process of the word line material layer WL_L, the upper surfaces of the word lines WL1 and WL2 can be lower than the upper surface of the channel pattern material layer CP_L, the upper surface of the gate insulating pattern material layer Gox_L, and the upper surface of the first insulating pattern 120. In some embodiments, an etching process for recessing the upper surfaces of the word lines WL1 and WL2 can be additionally performed.

[0109] Referring to Figure 15 , a second insulating pattern material layer 130_L conformally covering the gate insulating pattern material layer Gox_L and the word lines WL1 and WL2 can be formed. For example, the second insulating pattern material layer 130_L can be deposited by a CVD process, a PVD process, or an ALD process, but is not limited thereto. The second insulating pattern material layer 130_L can include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0110] Referring to Figure 16 , a third insulating pattern material layer 140_L filling "the first trench TRC1 remaining after the formation of the second insulating pattern material layer 130_L" can be formed. The third insulating pattern material layer 140_L can cover the upper surface of the first trench TRC1 and the upper surface of the second insulating pattern material layer 130_L. For example, the third insulating pattern material layer 140_L can be deposited by a CVD process, a PVD process, or an ALD process, but is not limited thereto. The third insulating pattern material layer 140_L can include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto. The third insulating pattern material layer 140_L can include a material different from that of the second insulating pattern material layer 130_L, but is not limited thereto. When the second insulating pattern material layer 130_L and the third insulating pattern material layer 140_L include the same material, the second insulating pattern material layer 130_L and the third insulating pattern material layer 140_L can be integrally formed.

[0111] Referring to Figure 17, a channel pattern CP, a gate insulating pattern Gox, a second insulating pattern 130, and a third insulating pattern 140 can be formed through a planarization process. Through the planarization process, the upper surfaces of the first insulating pattern 120, the channel pattern CP, the gate insulating pattern Gox, the second insulating pattern 130, and the third insulating pattern 140 can be exposed. That is, a part of the channel pattern material layer CP_L, a part of the gate insulating pattern material layer Gox_L, a part of the second insulating pattern material layer 130_L, and a part of the third insulating pattern material layer 140_L "located at a height higher than the upper surface of the first insulating pattern 120" can be removed through the planarization process.

[0112] Referring to Figure 18 , a second trench TRC2 can be formed through an etching process for recessing a part of the channel pattern CP. Specifically, the second trench TRC2 extending in the third direction (Z direction) can be formed by etching the channel pattern CP from the upper surface to the lower surface. For example, a wet etching can be performed on a part of the channel pattern CP using an etchant that selectively etches the channel pattern CP. However, the etching process for recessing the channel pattern CP is not limited to this, and can be changed in various ways.

[0113] Referring to Figure 19 , a contact pattern material layer BC_L can be formed, and the contact pattern material layer BC_L covers the upper surfaces of the first insulating pattern to the third insulating patterns 120, 130, and 140 and the upper surface of the gate insulating pattern Gox, and fills the second trench TRC2. The contact pattern material layer BC_L can fill the second trench TRC2 and can contact the upper surface of the channel pattern CP (for example, the second part CP2 of the channel pattern CP).

[0114] Referring to Figure 20 , a planarization process can be performed by patterning the contact pattern material layer BC_L to form holes exposing the upper surfaces of the first insulating pattern 120 and the third insulating pattern 140, and then burying the interlayer insulating layer 150 in the holes. Thus, a contact pattern BC can be formed. However, the order of forming the contact pattern BC and the interlayer insulating layer 150 is not limited to this. In some embodiments, a bonding pad can be further formed on the contact pattern BC.

[0115] Referring to Figure 21 , a data storage pattern DSP can be formed on the contact pattern BC, respectively. In one embodiment, the data storage pattern DSP can be a capacitor including a lower electrode, a capacitor dielectric layer, and an upper electrode. In this case, the lower electrode can contact the contact pattern BC.

[0116] Hereinafter, referring to Figures 22 to 24 , the manufacturing according toFigure 5 A method of a semiconductor device of the embodiment shown in. In Figures 22 to 24 , for convenience, the peripheral circuit structure PS is omitted Figure 2 , and the lower insulating layer 110 formed on the peripheral circuit structure PS is shown. Figures 22 to 24 is a diagram for explaining a method of manufacturing a semiconductor memory device according to some embodiments, and is a cross-sectional view corresponding to Figure 9 and Figure 10 .

[0117] Referring to Figure 22 , the first insulating pattern 120 is formed by patterning the first insulating pattern material layer 120_L, but different from Figure 9 , the width of the preliminary first trench TRC1_P1 in the first direction (Y direction) is narrower than the width of the first trench TRC1.

[0118] Referring to Figure 23 , the preliminary first recess RC1_P1 is formed by etching the bit line BL using the preliminary first trench TRC1_P1 as a mask. At this time, different from Figure 10 , the bit line BL is not over-etched.

[0119] Referring to Figure 24 , the first trench TRC1 is formed by etching the sidewalls of the first insulating pattern 120 using a mask. That is, the width of the first trench TRC1 in the first direction (Y direction) is greater than the width of the preliminary first trench TRC1_P1 in the first direction (Y direction). At this time, the bit line BL in the preliminary first recess RC1_P1 is also partially etched, and the first recess RC1 is formed. Therefore, the first recess RC1 of the bit line BL may have a surface S_CP1 that "contacts the bit line BL in a concave shape facing the bit line BL in the first direction (Y direction)" (i.e., the bit line BL may have a shape protruding toward the first recess RC1).

[0120] In addition, the width of the first recess RC1 in the first direction (Y direction) may be smaller than the distance between the first insulating patterns 120 in the first direction (Y direction) (i.e., the width of the first trench TRC1 in the first direction (Y direction)). Here, the width of the first recess RC1 in the first direction (Y direction) may be the minimum width among the widths of the first recess RC1 in the first direction (Y direction).

[0121] Although the embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by those of ordinary skill in the art to which the present disclosure pertains also belong to the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A bit line extending in a first direction across a underlying substrate, the bit line having an opening at its first surface and a recess within the opening, the recess having a greater lateral width relative to the width of the opening, the width of the opening being measured in the first direction, the lateral width being measured in the first direction; A channel pattern extending through the opening and at least partially filling the recess, the channel pattern extending in a second direction orthogonal to the first direction; A first word line extending through the opening and into the recess, and longitudinally extending in the second direction; And A gate insulating pattern extending between the channel pattern and the first word line.

2. The semiconductor device according to claim 1, wherein, The recess includes opposite sidewalls which are concave when viewed from a cross-sectional perspective.

3. The semiconductor device according to claim 2, wherein, The channel pattern contacts the opposite concave sidewalls of the recess.

4. The semiconductor device according to claim 1, wherein, The channel pattern extends along the bottom and the opposite sidewalls of the recess; and wherein, the gate insulating pattern extends between the first word line and a first portion of the channel pattern, the first portion of the channel pattern being on the bottom of the recess.

5. The semiconductor device according to claim 4 further comprises: A second word line extending through the opening and into the recess, and longitudinally extending in the second direction; and wherein, the gate insulating pattern further extends between the second word line and a second portion of the channel pattern, the second portion of the channel pattern being on the bottom of the recess.

6. The semiconductor device according to claim 5, wherein, The thickness of the channel pattern measured in a third direction between the gate insulating pattern and the bottom of the recess is less than the thickness of the channel pattern measured in the first direction between the gate insulating pattern and the sidewall of the recess, wherein the third direction is orthogonal to the first direction and the second direction.

7. The semiconductor device according to claim 6, wherein, The channel pattern includes a semiconductor material.

8. The semiconductor device according to claim 4, wherein, The thickness of the gate insulating pattern extending between the bottom of the first word line and the first portion of the channel pattern in the third direction is greater than the thickness of the gate insulating pattern extending between the first word line and a third portion of the channel pattern in the first direction, the third portion of the channel pattern extending above the opening in the bit line in the third direction, wherein the third direction is orthogonal to the first direction and the second direction.

9. The semiconductor device according to claim 4, wherein, The thickness of the gate insulating pattern extending between the first word line and a portion of the channel pattern located above the bit line in the first direction is less than the maximum thickness of the gate insulating pattern measured in the first direction between the first word line and a portion of the channel pattern located within the recess.

10. The semiconductor device according to claim 5, further comprising: A first contact pattern electrically connected to the channel pattern; And A second contact pattern electrically connected to the channel pattern; And Wherein, a first portion of the gate insulating pattern extends between the first word line and the first contact pattern, and a second portion of the gate insulating pattern extends between the second word line and the second contact pattern.

11. A semiconductor device, comprising: A substrate; A bit line located on the substrate and extending in a first direction; A word line located above the bit line and extending in a second direction different from the first direction; A channel pattern spaced apart from the word line in the first direction and including an oxide semiconductor material; And A gate insulating pattern extending between the channel pattern and the word line; Among them, the channel pattern includes a first portion inserted into the bit line and a second portion located above the bit line; and Among them, the thickness of the first portion of the channel pattern in the first direction is greater than the thickness of the second portion of the channel pattern in the first direction.

12. The semiconductor device according to claim 11, wherein, The first portion of the channel pattern has a surface that contacts the bit line in the first direction with a convex shape facing the bit line.

13. An integrated circuit memory device, comprising: A bit line that extends longitudinally in a first direction across a underlying substrate, the bit line having a recess therein, the recess having opposing first and second sidewalls; Spaced-apart first and second word lines that extend longitudinally in parallel in a second direction perpendicular to the first direction across the underlying substrate, the first word line having a first portion that extends opposite to the first sidewall of the recess and a second portion that extends outside the recess, and the second word line having a first portion that extends opposite to the second sidewall of the recess and a second portion that extends outside the recess; And A channel pattern that extends between the first portion of the first word line and the first sidewall of the recess, along the bottom of the recess, and between the first portion of the second word line and the second sidewall of the recess.

14. The integrated circuit memory device according to claim 13, wherein, When viewed from a cross-sectional perspective, each of the opposing first and second sidewalls is concave or convex.

15. The integrated circuit memory device according to claim 13, further comprising: A gate insulating pattern that extends between the first and second portions of the first word line and the channel pattern and between the first and second portions of the second word line and the channel pattern.

16. The integrated circuit memory device according to claim 15, wherein, The gate insulating pattern also extends between the first portion of the first word line and the bottom of the recess and between the first portion of the second word line and the bottom of the recess.

17. A semiconductor device, comprising: A substrate; A bit line located on the substrate and extending in a first direction; A word line located above the bit line and extending in a second direction different from the first direction; A channel pattern spaced apart from the word line in the first direction and including an oxide semiconductor material; And A gate insulating pattern located between the channel pattern and the word line, Among them, the bit line has an upwardly open recess, The channel pattern includes a first portion located in the recess and a second portion located above the bit line, and The first portion of the channel pattern has a surface that contacts the bit line in the first direction with a concave shape facing the bit line.

18. The semiconductor device according to claim 17, wherein, At least one of the channel pattern and the gate insulating pattern has a conformal shape.

19. The semiconductor device according to claim 17, Among them, The gate insulating pattern includes a first portion located in the recess and a second portion located above the bit line; and Among them, the first portion of the gate insulating pattern has a surface that contacts the first portion of the channel pattern in the first direction with a concave shape facing the first portion of the channel pattern.

20. The semiconductor device according to claim 19, Among them, The word line includes a first portion located in the recess and a second portion located above the bit line; And Among them, the first portion of the word line has a surface that contacts the first portion of the gate insulating pattern in the first direction with a concave shape facing the first portion of the gate insulating pattern.

Images