Semiconductor device and data storage system including the same

Abstract

The invention provides a semiconductor device and a data storage system including the same. A semiconductor device includes: a plate layer; a plurality of gate electrodes including a lower gate electrode, a memory gate electrode, and an upper gate electrode; a channel structure in a channel hole penetrating through the plurality of gate electrodes; a cell region insulating layer on the channel structure; a plurality of pillars penetrating the cell region insulating layer and connected to the channel structures, respectively; a first separation region penetrating the plurality of gate electrodes; and a second separation region penetrating the cell region insulating layer and the upper gate electrode between the plurality of pillars, in which a side surface of the second separation region includes a rounded portion and a straight portion between the rounded portions, each gate electrode including a first conductive layer and a second conductive layer, the second separation region is in contact with the first conductive layer and the second conductive layer of the upper gate electrode.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0002] In a data storage system that needs to store data, a semiconductor device capable of storing high-capacity data is required. Therefore, ways to increase the data storage capacity of semiconductor devices are being studied. For example, as a way to increase the data storage capacity of semiconductor devices, semiconductor devices including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0003] Some example embodiments of the present disclosure provide semiconductor devices with improved reliability and large-scale productivity.

[0004] Some example embodiments of the present disclosure provide a data storage system including a semiconductor device having improved reliability and large-scale productivity.

[0005] According to an example embodiment of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure on the first semiconductor structure. The first semiconductor structure includes a substrate, circuit elements on the substrate, and circuit interconnections on the circuit elements. The second semiconductor structure includes: a plate layer; a plurality of gate electrodes stacked on the plate layer and spaced apart from each other in a first direction perpendicular to the upper surface of the plate layer. The plurality of gate electrodes includes a lower gate electrode, a storage gate electrode, and an upper gate electrode stacked in sequence on the plate layer; an interlayer insulating layer; stacked alternately with the plurality of gate electrodes; a channel structure in a channel hole penetrating the stacked structure of the plurality of gate electrodes and the interlayer insulating layer; a cell region insulating layer on the channel structure; a plurality of pillars penetrating the cell region insulating layer and respectively connected to the channel structure. The plurality of pillars are arranged in multiple rows in a second direction perpendicular to the first direction; a first separation region penetrating the stacked structure and extending in the second direction; and a second separation region penetrating the cell region insulating layer and the upper gate electrode. The second separation region extends in the second direction and is between adjacent rows of the plurality of pillars. The second separation region may overlap the pillars of the adjacent rows in the second direction, and an upper surface of the second separation region may be coplanar with upper surfaces of the plurality of pillars.

[0006] According to an exemplary embodiment of the present disclosure, a semiconductor device includes: a board layer; a plurality of gate electrodes stacked on the board layer and spaced apart from each other in a first direction perpendicular to the upper surface of the board layer, and including a lower gate electrode, a storage gate electrode, and an upper gate electrode sequentially stacked from the board layer; a channel structure in a channel hole penetrating the plurality of gate electrodes; a cell region insulating layer on the channel structure; a plurality of pillars penetrating the cell region insulating layer and respectively connected to the channel structure; a first separation region penetrating the plurality of gate electrodes and extending in a second direction perpendicular to the first direction; and a second separation region penetrating the cell region insulating layer and the upper gate electrode, extending in the second direction and between the plurality of pillars, wherein a side surface of the second separation region includes a circular portion surrounding the pillars and a straight portion extending in the second direction between the circular portions, wherein each gate electrode includes a first conductive layer and a second conductive layer covering upper and lower surfaces of the first conductive layer, and wherein the second separation region is in contact with the first and second conductive layers of the upper gate electrode.

[0007] According to an exemplary embodiment of the present disclosure, a data storage system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first semiconductor structure including circuit elements, a second semiconductor structure on a surface of the first semiconductor structure, and input / output pads electrically connected to the circuit elements. The controller is electrically connected to the semiconductor memory device through the input / output pads and configured to control the semiconductor memory device. The second semiconductor structure includes: a board layer; a plurality of gate electrodes stacked on the board layer and spaced apart from each other in a first direction perpendicular to the upper surface of the board layer. The plurality of gate electrodes include a lower gate electrode, a storage gate electrode, and an upper gate electrode sequentially stacked from the board layer; a channel structure in a channel hole penetrating the plurality of gate electrodes; a cell region insulating layer on the channel structure; a plurality of pillars penetrating the cell region insulating layer and respectively connected to the channel structure; a first separation region penetrating the plurality of gate electrodes and extending in a second direction perpendicular to the first direction; and a second separation region penetrating the cell region insulating layer and the upper gate electrode. The second separation region extends in the second direction and is between the plurality of pillars, and wherein the second separation region may not overlap with the channel structure in the first direction and may overlap with some of the plurality of pillars in the second direction.

[0008] The second separation region to be aligned can be provided between the pillars, thereby providing a semiconductor device and a data storage system including the semiconductor device with improved reliability and mass productivity.

[0009] Advantages and effects of the present disclosure are not limited to the foregoing and can be more easily understood in the process of understanding the disclosed specific exemplary embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment;

[0012] Figure 2A and Figure 2B is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0013] Figure 3A and Figure 3B is a schematic partial enlarged view of a semiconductor device according to an exemplary embodiment;

[0014] Figure 4 is a schematic plan view of a semiconductor device according to an exemplary embodiment;

[0015] Figure 5A and Figure 5B is a schematic plan view and cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0016] Figure 6 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0017] Figure 7 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0018] Figure 8 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0019] Figures 9A to 9I is a schematic cross-sectional view for describing a method of manufacturing a semiconductor device according to an exemplary embodiment;

[0020] Figure 10 is a view schematically showing a data storage system including a semiconductor device according to an exemplary embodiment;

[0021] Figure 11 is a perspective view schematically showing a data storage system including a semiconductor device according to an exemplary embodiment; and

[0022] Figure 12 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0024] Although the terms "same", "equal", or "equivalent" are used in the description of the exemplary embodiments, it should be understood that there may be some imprecision. Thus, when an element is referred to as being the same as another element, it should be understood that within the desired manufacturing or operating tolerances (e.g., ±10%), one element or value is the same as another element.

[0025] When the terms "about", "substantially", or "approximately" are used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operating tolerances (e.g., ±10%) near the recited numerical value. Further, when the words "about", "substantially", or "approximately" are used in connection with a geometric shape, it is intended that the precision of the geometric shape is not required, but rather the latitude of the shape is within the scope of the present disclosure. Further, whether the numerical value or shape is modified by "about" or "substantially", it will be understood that these values and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) near the recited numerical value or shape.

[0026] A statement such as "at least one of..." when following a list of elements modifies the entire list of elements, rather than individual elements in the list. For example, a statement such as "at least one of A, B, and C" or "at least one selected from the group consisting of A, B, and C" can be interpreted to mean only A, only B, only C, or any combination of two or more of A, B, and C, such as A, B, and C, A and B, B and C, and A and C.

[0027] Figure 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment.

[0028] Figure 2A and Figure 2B is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment. Figure 2A is a cross-sectional view taken along the Figure 1 cutting line I-I' of Figure 2B is a cross-sectional view taken along the Figure 1 cutting line II-II′ of Figure 2A In

[0029] Figure 3A and Figure 3B are schematic partial enlarged views of a semiconductor device according to an exemplary embodiment. Figure 3A is Figure 2A an enlarged view of region "A" of Figure 3B is Figure 2A an enlarged view of region "B" of

[0030] Figure 4is a schematic plan view of a semiconductor device according to an exemplary embodiment. Figure 4 is a plan view taken along Figure 2A cutting line III-III'.

[0031] Referring to Figures 1 to 4 , the semiconductor device 100 may include a peripheral circuit region PERI and a memory cell region CELL. The peripheral circuit region PERI is a first semiconductor structure including a substrate 201, and the memory cell region CELL is a second semiconductor structure including a plate layer 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. Conversely, in some exemplary embodiments, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

[0032] The peripheral circuit region PERI may include a substrate 201, an impurity region 205 in the substrate 201, a device isolation layer 210, circuit elements 220 disposed on the substrate 201, a peripheral region insulating layer 290, circuit contact plugs 270, and circuit interconnections 280.

[0033] The substrate 201 may have an upper surface extending in the X direction and the Y direction. Active regions may be defined in the substrate 201 by the device isolation layer 210. The impurity region 205 including impurities may be disposed in a part of the active regions. The substrate 201 may include a semiconductor material such as a group-IV semiconductor, a group-III-V compound semiconductor, or a group-II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0034] The circuit elements 220 may include planar transistors. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The impurity region 205 may be provided as source / drain regions in the substrate 201 and on both sides of the circuit gate electrode 225.

[0035] The peripheral region insulating layer 290 may be disposed on the circuit elements 220 on the substrate 201. The peripheral region insulating layer 290 may include a plurality of insulating layers formed in different process operations. The peripheral region insulating layer 290 may be formed of an insulating material.

[0036] The circuit contact plug 270 and the circuit interconnect 280 can form a circuit interconnect structure that is electrically connected to the circuit element 220 and the impurity region 205. The circuit contact plug 270 can have a cylindrical shape, and the circuit interconnect 280 can have a linear shape. An electrical signal can be applied to the circuit element 220 through the circuit contact plug 270 and the circuit interconnect 280. In a region not shown, the circuit contact plug 270 can also be connected to the circuit gate electrode 225. The circuit interconnect 280 can be connected to the circuit contact plug 270 and can be arranged in multiple layers. The circuit contact plug 270 and the circuit interconnect 280 can include a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and can also include a diffusion barrier. In some example embodiments, the number of layers of the circuit contact plug 270 and the circuit interconnect 280 can vary.

[0037] The memory cell region CELL can include a source structure SS, a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 120 stacked alternately with the gate electrode 130 to form a stacked structure GS, a channel structure CH provided to penetrate the gate electrode 130, a first separation region MS extending through the gate electrode 130, a cell region insulating layer 190 on the channel structure CH, pillars 170 respectively connected to the channel structure CH, a second separation region US penetrating the upper gate electrode 130U in the gate electrode 130 between the pillars 170, and a bit line 180 on the pillars 170.

[0038] The source structure SS can include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 stacked in sequence. However, in an example embodiment, the number of conductive layers forming the source structure SS can vary.

[0039] The plate layer 101 has the shape of a plate and can be used as at least a part of a common source line of the semiconductor device 100. The plate layer 101 can have an upper surface extending in the X direction and the Y direction. The plate layer 101 can include a conductive material. For example, the plate layer 101 can include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, or silicon germanium. The plate layer 101 can also include impurities. The plate layer 101 can be provided as a polycrystalline semiconductor layer (such as a polysilicon layer) or an epitaxial layer.

[0040] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be stacked in sequence and disposed on the upper surface of the plate layer 101. The first horizontal conductive layer 102 can be used as a part of the common source line of the semiconductor device 100, for example, can be used as the common source line together with the plate layer 101. As Figure 3B shown, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 around the channel layer 140.

[0041] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material, such as polysilicon. In this case, at least the first horizontal conductive layer 102 may be a layer doped with impurities of the same conductive type as the layer 101, and the second horizontal conductive layer 104 may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102.

[0042] The gate electrodes 130 may be spaced apart from each other perpendicularly and stacked on the layer 101 to form a stacked structure GS together with the interlayer insulating layer 120. The stacked structure GS may include a lower stacked structure and an upper stacked structure stacked vertically. However, according to some example embodiments, the stacked structure GS may be formed of a single stacked structure.

[0043] The gate electrodes 130 may include a lower gate electrode 130L forming the gate of the ground selection transistor, a storage gate electrode 130M forming the storage gates of a plurality of storage units, and an upper gate electrode 130U forming the gate of the string selection transistor. The number of the storage gate electrodes 130M forming the storage units may be determined depending on the capacity of the semiconductor device 100. The upper gate electrode 130U and the lower gate electrode 130L may also be referred to as an upper selection gate electrode and a lower selection gate electrode, respectively. According to some example embodiments, one to four or more upper gate electrodes 130U and lower gate electrodes 130L may be present respectively, and the upper gate electrode 130U and the lower gate electrode 130L may have the same or different structures from the storage gate electrode 130M. In some example embodiments, the gate electrodes 130 may further include a gate electrode of an erase transistor disposed on one side of the upper gate electrode 130U and / or the lower gate electrode 130L and formed to be used in an erase operation utilizing the gate induced drain leakage (GIDL) phenomenon. In addition, some of the gate electrodes 130 (for example, the storage gate electrodes 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) may be dummy gate electrodes.

[0044] All of the gate electrodes 130 may include the same material. The gate electrodes 130 may include a first conductive layer 132 and a second conductive layer 135, as Figure 3A and Figure 3B shown. The second conductive layer 135 may surround the upper surface, the lower surface, and the side surface of the first conductive layer 132. The channel structure CH may be in contact with the second conductive layer 135, and the second separation region US may be in contact with the first conductive layer 132 and the second conductive layer 135. The first separation region MS may also be in contact with the first conductive layer 132 and the second conductive layer 135. In the gate electrode 130, the second conductive layer 135 may cover the side surface of the first conductive layer 132 in the region in contact with the channel structure CH, and the side surface of the first conductive layer 132 may be exposed from the second conductive layer 135 in the region in contact with the first separation region MS and the second separation region US.

[0045] The first conductive layer 132 may include a metallic material such as tungsten (W) or molybdenum (Mo). According to an exemplary embodiment, the first conductive layer 132 may include polysilicon or a metal silicide material. The second conductive layer 135 may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0046] The interlayer insulating layer 120 may be alternately disposed with the gate electrode 130. Similar to the gate electrode 130, the interlayer insulating layers 120 may also be spaced apart from each other in a direction perpendicular to the upper surface of the plate layer 101. Some of the interlayer insulating layers 120 may have different thicknesses. For example, the interlayer insulating layer 120 adjacent to the region where the first channel structure CH1 and the second channel structure CH2 are connected and the interlayer insulating layer 120 on the uppermost upper gate electrode 130U may have a relatively large thickness.

[0047] The interlayer insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride. In an exemplary embodiment, the thickness of each interlayer insulating layer 120 may vary variously.

[0048] The channel structure CH may extend in the Z direction by penetrating the stacked structure GS and may be connected to the plate layer 101. Each channel structure CH may form a memory cell string and may be arranged in rows and columns on the plate layer 101 to be spaced apart from each other. As Figure 1 shown, the channel structures CH may be arranged to form a grid pattern in the X-Y plane, or may be arranged in a zigzag shape in one direction. The channel structure CH may have a column shape and may have inclined side surfaces that become narrower as they approach the plate layer 101. The channel structure CH may be spaced apart from the second separation region US, and each channel structure CH may have a complete shape in which the channel layer 140 is not cut.

[0049] The channel structure CH may include a first channel structure CH1 and a second channel structure CH2 stacked vertically. The channel structure CH may also have a shape in which the first channel structure CH1 and the second channel structure CH2 are connected, and may have a bent portion due to a width difference in the connection region. However, according to an exemplary embodiment, the number of channel structures stacked in the Z direction may vary variously.

[0050] Each channel structure CH may include a channel layer 140 disposed in a channel hole, a gate dielectric layer 145, a channel buried insulating layer 147, and a channel pad 149, as Figure 3A and Figure 3BAs shown. The channel layer 140 may be formed in an annular shape surrounding the internal channel buried insulating layer 147. However, according to an exemplary embodiment, the channel layer 140 may have a columnar shape without the channel buried insulating layer 147, such as a cylinder or a prism. The channel layer 140 may be connected to the first horizontal conductive layer 102 at its lower end. The channel layer 140 may include a semiconductor material, such as polysilicon or single crystal silicon.

[0051] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer stacked in sequence from the channel layer 140. The tunneling layer may allow charges to tunnel into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-κ dielectric material, or a combination thereof. In some exemplary embodiments, at least a portion of the gate dielectric layer 145 may extend in the horizontal direction along the gate electrode 130.

[0052] The channel pad 149 may be disposed only on the upper end of the upper channel structure CH2. The channel pad 149 may be disposed to fill the inside of the channel layer 140 at the upper end of the channel layer 140. The lower surface of the channel pad 149 may be disposed at a level higher than the uppermost surface of the gate electrode 130. The channel pad 149 may include, for example, doped polysilicon.

[0053] The channel layer 140, the gate dielectric layer 145, and the channel buried insulating layer 147 may be continuous between the first channel structure CH1 and the second channel structure CH2.

[0054] The first separation region MS may be disposed to extend in the X direction by penetrating the stacked structure GS. As Figure 1 shown, the first separation regions MS may be disposed parallel to each other. As Figure 2B shown, the first separation region MS may penetrate the stacked structure GS, further penetrate the underlying first horizontal conductive layer 102 and second horizontal conductive layer 104, and be connected to the plate layer 101. The first separation region MS may have a shape in which its width decreases toward the plate layer 101 due to a high aspect ratio.

[0055] The upper surface of the first separation region MS may be set at a level lower than the upper surface of the pillar 170 and may be set at a level substantially the same as the upper surface of the channel structure CH. The upper surface of the first separation region MS may be coplanar with the upper surface of the channel structure CH. However, in some exemplary embodiments, the upper surface of the first separation region MS may be set at a level lower than the upper surface of the pillar 170 and may be set at a level higher than the upper surface of the channel structure CH. The first separation region MS may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0056] The cell region insulating layer 190 may be disposed on the stacked structure GS. The cell region insulating layer 190 may cover the upper surface of the channel structure CH and the upper surface of the first separation region MS. The cell region insulating layer 190 may be formed of an insulating material and each may be formed of a plurality of insulating layers.

[0057] The pillars 170 may be physically and electrically connected to the channel structure CH on the channel structure CH, respectively. The pillars 170 may penetrate the cell region insulating layer 190 and may be connected to the channel pads 149 of the channel structure CH, respectively. The pillars 170 may electrically connect the channel structure CH and the bit line 180. In some exemplary embodiments, the pillars 170 may be arranged such that the channel pads 149 are partially recessed.

[0058] The pillars 170 may have a cylindrical shape and may have inclined side surfaces such that their width decreases toward the channel structure CH. In each pillar 170, the diameter of its upper surface may be greater than the diameter of its lower surface. The first diameter L1 of the upper surface of the pillar 170 may be greater than the second diameter L2 of the upper surface of the channel structure CH. However, in some exemplary embodiments, the first diameter L1 may be the same as the second diameter L2.

[0059] In an exemplary embodiment, the pillars 170 may be aligned such that their central axes coincide with the central axis of the channel structure CH. For example, the central axis of the pillar 170 in the vertical direction may substantially coincide with the central axis of the channel structure CH in the vertical direction. As Figure 1 shown, the center of the pillar 170 and the center of the channel structure CH may coincide in a plan view.

[0060] The pillars 170 may include a conductive material such as tungsten (W), aluminum (Al), ruthenium (Ru), molybdenum (Mo), copper (Cu), etc. According to an exemplary embodiment, the pillars 170 may include the same material as the gate electrode 130 or a different material from the gate electrode 130. When the pillars 170 include the same material as the gate electrode 130, the pillars 170 may be formed by forming a sacrificial layer and then replacing the sacrificial layer.

[0061] As Figure 1As shown, the second separation region US can extend in the X direction between adjacent first separation regions MS and can penetrate the upper gate electrode 130U among the gate electrodes 130. The second separation region US can be disposed between the pillars 170. For example, the second separation region US can extend in the X direction along two adjacent rows among multiple rows of the pillars 170 in the Y direction. The second separation region US can overlap the two rows of pillars 170 in the X direction. The second separation region US can surround a part of each pillar 170 of the two rows. For example, the second separation region US can surround each pillar 170 of the two rows in a semi-circular or similar shape in a plan view. In an exemplary embodiment, the ratio of the part surrounded by the second separation region US on the outer peripheral surface of each pillar 170 can be variously changed.

[0062] In a plan view, the side surface of the second separation region US can include a straight portion US_SL extending linearly in the X direction and a circular portion US_SR surrounding the pillar 170 and the channel structure CH. On each side surface of the second separation region US, the straight portion US_SL and the circular portion US_SR can be alternately arranged in the X direction.

[0063] The upper surface of the second separation region US can be disposed at substantially the same level as the upper surface of the pillar 170 and can be substantially coplanar with the upper surface of the pillar 170. The second separation region US can contact at least one of the two rows of pillars 170 on its upper surface or at the edge of its upper end. The second separation region US can have an inclined side surface to narrow its width toward the laminate 101. However, the degree of inclination of the side surface can vary in exemplary embodiments, and in some exemplary embodiments, the side surface can be perpendicular to the upper surface of the laminate 101.

[0064] The second separation region US can be horizontally spaced apart from the pillar 170 in at least a part of the region below the upper surface. The second separation region US can be horizontally spaced apart from the adjacent channel structure CH. The second separation region US can not overlap the channel structure CH in the Z direction. A part of each upper gate electrode 130U can be disposed between the second separation region US and the channel structure CH. The lower surface of the second separation region US can be disposed at a lower level than the lower surface of the lowermost upper gate electrode 130U. The lower surface of the second separation region US can be disposed between the lowermost upper gate electrode 130U and the uppermost storage gate electrode 130M. The second separation region US can have a first width W1 on its upper surface. The first width W1 can be, for example, 80 nm or less, for example, in the range from about 30 nm to about 50 nm. The second separation region US can have a second width W2 equal to or less than the first width W1 at the level corresponding to the upper surface of the channel structure CH.

[0065] As Figure 4 shown, the second separation region US can divide each upper gate electrode 130U into a first sub-gate electrode 130U1 and a second sub-gate electrode 130U2. The first sub-gate electrode 130U1 and the second sub-gate electrode 130U2 can be spaced apart from each other in the Y direction by the second separation region US. The second separation region US can be spaced apart from the channel structure CH by the upper gate electrode 130U. In some example embodiments, a plurality of second separation regions US can be provided between a pair of first separation regions MS.

[0066] The second separation region US can include an insulating material, such as a low dielectric constant material having a lower dielectric constant than silicon dioxide (SiO2). The second separation region US can include, for example, silicon oxide, silicon nitride, or silicon oxynitride. The second separation region US can have an air gap AG therein, in which case the dielectric constant can be further reduced. However, in some example embodiments, the second separation region US can be without the air gap AG.

[0067] In the semiconductor device 100, the second separation region US can be arranged to overlap the channel structure CH in the horizontal direction and can be self-aligned between the pillars 170, thereby simplifying the manufacturing process. The second separation region US can be spaced apart from the channel structure CH in the horizontal direction without partially penetrating the channel structure CH, thereby improving the reliability of the semiconductor device 100.

[0068] The bit line 180 can form a cell interconnect structure electrically connected to the memory cells in the memory cell region CELL. The bit line 180 can be electrically connected to the channel structure CH through the pillar 170. The bit line 180 can be arranged to extend, for example, in the Y direction. The bit line 180 can include a conductive material, such as a metal (e.g., tungsten (W), copper (Cu), or aluminum (Al)).

[0069] Figure 5A and Figure 5B are a schematic plan view and a cross-sectional view of a semiconductor device according to an example embodiment. Figure 5A and Figure 5B respectively show regions corresponding to Figure 1 and Figure 2A of.

[0070] Referring to Figure 5A and Figure 5B , in the semiconductor device 100a, the arrangement of the pillars 170a can be different from Figures 1 to 4Those of the example embodiments. For example, the pillars 170a in two rows (i.e., the first row RS1 and the second row RS2) overlapping with the second separation region US in the X direction may be offset to face each other. The pillars 170a in the first row RS1 and the second row RS2 may be offset toward the second separation region US in the Y direction. The central axis of each of the pillars 170a in the first row RS1 and the second row RS2 may not coincide with the central axis of the corresponding one in the connected channel structure CH. According to this example embodiment, since the second separation region US can be spaced farther from the channel structure CH in the horizontal direction, the channel structure CH can be more reliably protected during the manufacture of the semiconductor device 100a.

[0071] Figure 6 is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 6 shows corresponding to Figure 2A region.

[0072] Referring to Figure 6 , in the semiconductor device 100b, at least one of the pillars 170b adjacent to the second separation region USb may have a recessed region at an end in contact with the second separation region USb. The pillar 170b may have a shape in which an end in contact with the second separation region USb is partially removed from its upper surface and edge region. The second separation region USb may extend and be disposed on the recessed region. In the example embodiment, the recessed depth and width of the recessed region may be variously changed.

[0073] Figure 7 is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 7 shows corresponding to Figure 2A region.

[0074] Referring to Figure 7 , in the semiconductor device 100c, the upper surface of the second separation region US may be horizontally spaced from the upper surface of the adjacent pillar 170c. In this example embodiment, the second separation region US may not be in contact with the pillar 170c. For example, when the pillar 170c has a relatively small height, the pillar 170c may be spaced from the second separation region US. In the example embodiment, the separation distance between the second separation region US and the pillar 170c may be variously changed.

[0075] Figure 8 is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 8 shows corresponding to Figure 2A region.

[0076] Referring to Figure 8, the semiconductor device 100d may include a first semiconductor structure S1 and a second semiconductor structure S2 joined by a wafer bonding method.

[0077] The description of the peripheral circuit region PERI referred to above Figures 1 to 2B may be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may further include a first bonding via 295, a first bonding metal layer 298, and a first bonding insulating layer 299 that form a bonding structure. The first bonding via 295 may be disposed on top of the uppermost circuit interconnect 280 and may be connected to the circuit interconnect 280. At least a portion of the first bonding metal layer 298 may be connected to the first bonding via 295 on the first bonding via 295. The first bonding metal layer 298 may be connected to a second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 and the second bonding metal layer 198 together may provide an electrical connection path for bonding the first semiconductor structure S1 and the second semiconductor structure S2. Some of the first bonding metal layer 298 may not be connected to the lower circuit interconnect 280 and may be provided only for bonding. The first bonding via 295 and the first bonding metal layer 298 may include a conductive material, such as copper (Cu). The first bonding insulating layer 299 may be disposed around the first bonding metal layer 298. The first bonding insulating layer 299 may also serve as a diffusion prevention layer for the first bonding metal layer 298 and may include at least one of, for example, SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0078] For the second semiconductor structure S2, unless otherwise stated, the description of the memory cell region CELL referred to above Figures 1 to 4 may be applied. The second semiconductor structure S2 may further include a lower contact plug 182 and a cell interconnect 184 that form a cell interconnect structure, and may further include a second bonding via 195, a second bonding metal layer 198, and a second bonding insulating layer 199 that form a bonding structure. The second semiconductor structure S2 may further include a passivation layer 106 that covers the upper surface of the cover plate layer 101.

[0079] The lower contact plug 182 may be connected to the bit line 180, and the cell interconnect 184 may be connected to the lower contact plug 182. However, in an exemplary embodiment, the number of layers and the arrangement form of the contact plugs and interconnects that form the cell interconnect structure may be variously changed. The lower contact plug 182 and the cell interconnect 184 may be formed of a conductive material and may include at least one of, for example, tungsten (W), aluminum (Al), and copper (Cu).

[0080] The second bonding via 195 and the second bonding metal layer 198 may be disposed under the bottommost cell interconnect 184. The second bonding via 195 may connect the cell interconnect 184 and the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 may be bonded and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 195 and the second bonding metal layer 198 may include a conductive material such as copper (Cu). The second bonding insulating layer 199 may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0081] The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded by bonding the first bonding metal layer 298 and the second bonding metal layer 198 and bonding the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding of the first bonding metal layer 298 and the second bonding metal layer 198 may be, for example, copper (Cu) to copper (Cu) bonding, and the bonding of the first bonding insulating layer 299 and the second bonding insulating layer 199 may be, for example, dielectric to dielectric bonding such as SiCN to SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded by a hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0082] The passivation layer 106 may be disposed on the upper surface of the plate layer 101 and may protect the semiconductor device 100d. According to some example embodiments, the passivation layer 106 may include an insulating material such as at least one of silicon oxide, silicon nitride, and silicon carbide, and may be formed of a plurality of insulating layers.

[0083] In this example embodiment, the second semiconductor structure S2 may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see Figure 2A ). The channel structure CH may be directly connected to the plate layer 101, where the channel layer 140 (see Figure 3B ) is exposed through its upper end. However, in the example embodiment, the form of the electrical connection between the channel structure CH and the common source line may be variously changed, and the channel structure CH and the source structure SS may also have the same structure as that of the Figure 2A example embodiment.

[0084] Figures 9A to 9I is a schematic cross-sectional view for describing a method of manufacturing a semiconductor device according to an example embodiment. Figures 9A to 9I Each of the Figure 2A shows a region corresponding to

[0085] Referring to Figure 9A, circuit elements 220, circuit interconnect structures, and a peripheral region insulating layer 290 forming a peripheral circuit region PERI may be formed on a substrate 201.

[0086] First, a device isolation layer 210 may be formed in the substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The device isolation layer 210 may be formed in, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polysilicon and a metal silicide layer, but the exemplary embodiments of the present disclosure are not limited thereto. Next, a spacer layer 224 and an impurity region 205 may be formed on or near two sidewalls of the circuit gate dielectric layer 222 and two sidewalls of the circuit gate electrode 225. According to an exemplary embodiment, the spacer layer 224 may be formed of multiple layers. The impurity region 205 may be formed when an ion implantation process is performed.

[0087] Among the circuit interconnect structures, a circuit contact plug 270 may be formed by forming a part of the peripheral region insulating layer 290, etching and removing a part thereof, and then burying a conductive material therein. The circuit interconnect 280 may be formed, for example, by depositing a conductive material and then patterning the conductive material.

[0088] The peripheral region insulating layer 290 may be formed of multiple insulating layers. Each insulating layer in the peripheral region insulating layer 290 may be a part of each operation of forming the circuit interconnect structure. Thus, the peripheral circuit region PERI may be formed.

[0089] Referring to Figure 9B , a memory cell region CELL provided with a plate layer 101, a horizontal sacrificial layer 110, and a second horizontal conductive layer 104 may be formed on the peripheral circuit region PERI, a sacrificial insulating layer 118 and an interlayer insulating layer 120 may be alternately stacked to form a lower molding structure, and after forming a lower channel sacrificial layer 119, an upper molding structure may be formed.

[0090] The plate layer 101 may be formed on the peripheral region insulating layer 290. The plate layer 101 may be formed of, for example, polysilicon and may be formed in a CVD process. The polysilicon forming the plate layer 101 may include impurities.

[0091] A first horizontal insulating layer 111 and a second horizontal insulating layer 112 forming the horizontal sacrificial layer 110 may be alternately stacked on the plate layer 101. The horizontal sacrificial layer 110 may be removed in a subsequent process using Figure 2AThe layer replaced by the first horizontal conductive layer 102. The first horizontal insulating layer 111 may include a material different from that of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the sacrificial insulating layer 118. The second horizontal conductive layer 104 may be formed on the horizontal sacrificial layer 110.

[0092] The lower molding structure may be formed on the second horizontal conductive layer 104 at the height of the first channel structure CH1 (see Figure 2A ) where the channel structure CH (see Figure 2A ) is provided.

[0093] The sacrificial insulating layer 118 may be a layer that is replaced by a subsequent process with a part of the gate electrode 130 (see Figure 2A ). The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120 and may be formed of a material having an etching selectivity with respect to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some exemplary embodiments, the thickness of the interlayer insulating layer 120 may not be the same. The thickness and the number of constituent films of the interlayer insulating layer 120 and the sacrificial insulating layer 118 may be changed differently from those shown.

[0094] The lower channel sacrificial layer 119 may be formed at a position corresponding to the first channel structure CH1. The lower channel sacrificial layer 119 may be formed by forming a hole penetrating the lower molding structure, depositing a material for forming the lower channel sacrificial layer 119 in the hole, and performing a planarization process. The lower channel sacrificial layer 119 may include, for example, polysilicon.

[0095] The upper molding structure may be formed on the lower molding structure at the height of the second channel structure CH2 (see Figure 2A ) where the channel structure CH is provided. The upper molding structure may be formed by alternately stacking the sacrificial insulating layer 118 and the interlayer insulating layer 120 in the same manner as the lower molding structure.

[0096] Referring to Figure 9C , a channel structure CH penetrating the lower molding structure and the upper molding structure may be formed.

[0097] An upper channel sacrificial layer penetrating the upper molding structure may be formed. The upper channel sacrificial layer may be formed at a position corresponding to the upper channel structure CH2. The upper channel sacrificial layer may be formed to be connected to the lower channel sacrificial layer 119, respectively.

[0098] The channel structure CH can be formed by removing the lower channel sacrificial layer 119 and the upper channel sacrificial layer to form a hole-shaped channel hole, sequentially depositing at least a part of the gate dielectric layer 145, the channel layer 140, and the channel buried insulating layer 147 in the channel hole, and forming the channel pad 149.

[0099] The gate dielectric layer 145 can be formed to have a uniform thickness using an ALD or CVD process. In this operation, the gate dielectric layer 145 can be formed in whole or in part, and a part extending perpendicular to the plate layer 101 along the channel structure CH can be formed in this operation. The channel layer 140 can be formed on the gate dielectric layer 145 in the channel hole. The channel buried insulating layer 147 can be formed to fill the channel hole and can be formed of an insulating material. The channel pad 149 can be formed after partially removing the channel buried insulating layer 147. The channel pad 149 can be formed of a conductive material, such as polysilicon.

[0100] Referring to Figure 9D , the first horizontal conductive layer 102 can be formed and the sacrificial insulating layer 118 can be removed.

[0101] An opening can be formed at the position of the first separation region MS (see Figure 1 ). The opening can be formed to extend through the sacrificial insulating layer 118 and the interlayer insulating layer 120 to the plate layer 101. The horizontal sacrificial layer 110 can be selectively removed through the opening, and a part of the exposed gate dielectric layer 145 can also be removed. The first horizontal conductive layer 102 can be formed by depositing a conductive material in the region where the horizontal sacrificial layer 110 has been removed.

[0102] The sacrificial insulating layer 118 can be selectively removed with respect to the interlayer insulating layer 120, the second horizontal conductive layer 104, and the channel structure CH, for example, using wet etching. The tunnel portion TL can be formed in the region where the sacrificial insulating layer 118 has been removed.

[0103] Referring to Figure 9E , the gate electrode 130 can be formed.

[0104] The gate electrode 130 can be formed by depositing a conductive material on the tunnel portion TL. As shown in Figure 3A and Figure 3B , the second conductive layer 135 can be formed first, and then the first conductive layer 132 can be formed to fill the tunnel portion TL. In some exemplary embodiments, a part of the gate dielectric layer 145 can be formed first before forming the second conductive layer 135. After forming the gate electrode 130, the first separation region MS (see Figure 2B ) can be formed by depositing an insulating material in the opening.

[0105] Referring to Figure 9F, the unit region insulating layer 190 and the pillar 170 can be formed.

[0106] The unit region insulating layer 190 can be formed to cover the upper surface of the stacked structure GS and the upper surface of the channel structure CH.

[0107] The pillar 170 can be formed to penetrate the unit region insulating layer 190 and connect to the channel structure CH. The pillar 170 can include a conductive material different from that of the gate electrode 130 so as to have an etching selectivity with respect to the gate electrode 130 in subsequent processes.

[0108] In some example embodiments, a sacrificial layer can be formed instead of the pillar 170 in this operation, and the sacrificial layer can be replaced with the pillar 170 in a subsequent process. In this case, the sacrificial layer can include, for example, aluminum oxide or silicon nitride.

[0109] Referring to Figure 9G , an upper opening UH can be formed to form a second separation region US (see Figure 2A ).

[0110] A mask layer ML can be formed to expose the region corresponding to the second separation region US. Next, the unit region insulating layer 190 and the stacked structure GS exposed between the pillars 170 can be partially removed in an etching process. The etching process can be, for example, a dry etching process, and can selectively etch the gate electrode 130 and the interlayer insulating layer 120 while reducing or minimizing the etching of the pillar 170.

[0111] The upper opening UH can be formed in the form of a trench spanning two rows of pillars 170, similar to Figure 1 the second separation region US. When the upper opening UH is formed, the two rows of pillars 170 serve as a mask, such that the upper opening UH can be formed by self-alignment between the pillars 170. In this operation, the upper ends of the pillars 170 adjacent to the upper opening UH can be partially recessed. However, in some example embodiments, the upper ends of the pillars 170 may not be recessed in this operation.

[0112] Referring to Figure 9H , the upper opening UH can be filled with an insulating material to form an initial second separation region USp.

[0113] The initial second separation region USp can include an air gap AG therein. In some example embodiments, the insulating material can be a low dielectric constant material. The initial second separation region USp can have a shape in which its width decreases toward the plate layer 101. However, in some example embodiments, the side surface of the initial second separation region USp can be perpendicular to the upper surface of the plate layer 101.

[0114] Referring to Figure 9I , a planarization process can be performed to form the second separation region US.

[0115] A planarization process such as chemical mechanical polishing (CMP) can be performed to partially remove the pillar 170, the cell region insulating layer 190, and the initial second partition region USp, and a second partition region US can be formed. In this operation, the region where the upper end of the pillar 170 is recessed can also be removed.

[0116] In some example embodiments, when a sacrificial layer is formed instead of the pillar 170 in the operations described above with reference to Figure 9F In this operation, after the planarization process, the sacrificial layer can be replaced with a conductive material to form the pillar 170.

[0117] For Figure 6 example embodiments, by reducing the amount removed by the planarization process in this operation, the upper end of the pillar 170 can be formed to include a recessed region. For Figure 7 example embodiments, by increasing the amount removed by the planarization process in this operation, the upper end of the pillar 170 can be formed to be spaced apart from the second partition region US.

[0118] Next, with reference to Figure 2A , the semiconductor device 100 can be fabricated by forming a bit line 180 on the pillar 170.

[0119] Figure 10 is a view schematically showing a data storage system including a semiconductor device according to an example embodiment.

[0120] Referring to Figure 10 , the data storage system 1000 can include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 can be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 can be a solid state drive (SSD) device including one or more semiconductor devices 1100, a universal serial bus (USB) device, a computing system, a medical device, or a communication device.

[0121] The semiconductor device 1100 can be a non-volatile storage device, such as the one described above with reference to Figures 1 to 8The described NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed beside the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including bit lines BL, a common source line CSL, word lines WL, upper gate lines UL1 and UL2, lower gate lines LL1 and LL2, and a memory cell string CSTR between the bit lines BL and the common source line CSL.

[0122] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit lines BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. According to an exemplary embodiment, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously modified.

[0123] In some exemplary embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The first lower gate line LL1 and the second lower gate line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistors MCT, and the first upper gate line UL1 and the second upper gate line UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0124] In some exemplary embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used for an erase operation to erase data stored in the memory cell transistors MCT by using the GIDL phenomenon.

[0125] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 through the first interconnect 1115 that extends from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 through the second interconnect 1125 that extends from the first structure 1100F to the second structure 1100S.

[0126] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through the input / output interconnect 1135 that extends from the first structure 1100F to the second structure 1100S.

[0127] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. According to some example embodiments, the data storage system 1000 can include a plurality of semiconductor devices 1100, and in this case, the controller 1200 can control the plurality of semiconductor devices 1100.

[0128] The processor 1210 can control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 can operate according to a predetermined firmware and can control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 can include a controller interface 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors (MCTs) of the semiconductor device 1100, and data to be read from the memory cell transistors (MCTs) of the semiconductor device 1100, etc. can be sent. The host interface 1230 can provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0129] Figure 11 is a perspective view schematically showing a data storage system including a semiconductor device according to an example embodiment.

[0130] Referring to Figure 11, according to an example embodiment of the present disclosure, a data storage system 2000 may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 through an interconnect pattern 2005 formed on the motherboard 2001.

[0131] The motherboard 2001 may include a connector 2006, and the connector 2006 includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. In some example embodiments, the data storage system 2000 may communicate with an external host according to any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In some example embodiments, the data storage system 2000 may be operated using power supplied from an external host through the connector 2006. The data storage system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes the power supplied from the external host to the controller 2002 and the semiconductor packages 2003.

[0132] The controller 2002 may record data in the semiconductor package 2003 or read data from the semiconductor package 2003, and may improve the operation speed of the data storage system 2000.

[0133] The DRAM 2004 may be a buffer memory to mitigate the speed difference between the semiconductor package 2003 as a data storage space and the external host. The DRAM 2004 included in the data storage system 2000 may operate as a cache memory and may provide a space for temporarily storing data during the control operation of the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004.

[0134] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 on the package substrate 2100 covering the semiconductor chips 2200 and the connection structure 2400.

[0135] The package substrate 2100 may be a printed circuit board including package upper pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to Figure 10 the input / output pads 1101. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the semiconductor device described above with reference to Figures 1 to 8 description.

[0136] In some example embodiments, the connection structure 2400 may be a bonding lead electrically connecting the input / output pads 2210 and the package upper pads 2130. Thus, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using the bonding lead method and may be electrically connected to the package upper pads 2130 of the package substrate 2100. According to some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including through-silicon vias (TSVs) instead of the bonding lead type connection structure 2400.

[0137] In some example embodiments, the controller 2002 and the semiconductor chips 2200 may be included in one package. In an example embodiment, the controller 2002 and the semiconductor chips 2200 may be mounted on a separate interposer substrate different from the main board 2001, and the controller 2002 and the semiconductor chips 2200 may be connected to each other through the interconnections formed on the interposer substrate.

[0138] Figure 12 is a cross-sectional view schematically showing a semiconductor package according to an example embodiment. Figure 12 shows Figure 11An exemplary embodiment of semiconductor package 2003, and conceptually shows cutting along cutting line IV-IV' Figure 11 the area of semiconductor package 2003.

[0139] Referring to Figure 12 , in semiconductor package 2003, package substrate 2100 may be a printed circuit board. Package substrate 2100 may include a package substrate main body portion 2120, package upper pads 2130 disposed on an upper surface of the package substrate main body portion 2120, lower pads 2125 disposed on a lower surface of the package substrate main body portion 2120 or exposed through its lower surface, and internal interconnections 2135 in the package substrate main body portion 2120 that electrically connect the package upper pads 2130 and the lower pads 2125. The lower pads 2125 may be connected to an interconnection pattern 2005 of motherboard 2001 of data storage system 2000 as shown in Figure 11 .

[0140] Each semiconductor chip 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 stacked in sequence on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region that includes peripheral interconnections 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210, an isolation structure 3230, and bit lines 3240 electrically connected to the channel structure 3220. As referred to above with reference to Figures 1 to 8 , in each semiconductor chip 2200, a second separation region US may be provided between the pillars 170, and an upper surface of the second separation region US may be coplanar with an upper surface of the pillars 170.

[0141] Each semiconductor chip 2200 may include a through-interconnection 3245 electrically connected to the peripheral interconnections 3110 of the first structure 3100 and extending into the second structure 3200. The through-interconnection 3245 may penetrate the gate stack structure 3210 and may be further disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may further include an input / output connection interconnection 3265 electrically connected to the peripheral interconnections 3110 of the first structure 3100 and extending into the second structure 3200, and input / output pads 2210 electrically connected to the input / output connection interconnections 3265.

[0142] Any functional block shown in the drawings and described above can be implemented as: a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0143] The present disclosure is not limited to the above-described exemplary embodiments and drawings, but is defined by the appended claims. Therefore, various substitutions, modifications, or changes can be made by those of ordinary skill in the art without departing from the scope of the present disclosure defined by the appended claims, and these substitutions, modifications, or changes should be construed as being included within the scope of the present disclosure.

[0144] This application claims the benefit of priority of Korean Patent Application No. 10-2024-0011414, filed on January 25, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first semiconductor structure, including a substrate, circuit elements on the substrate, and circuit interconnections on the circuit elements; And A second semiconductor structure on the first semiconductor structure, Wherein the second semiconductor structure includes: A plate layer, A plurality of gate electrodes, stacked on the plate layer and spaced apart from each other in a first direction perpendicular to the upper surface of the plate layer, the plurality of gate electrodes including a lower gate electrode, a storage gate electrode, and an upper gate electrode stacked on the plate layer in sequence, An interlayer insulating layer, stacked alternately with the plurality of gate electrodes, A channel structure in a channel hole penetrating the stacked structure of the plurality of gate electrodes and the interlayer insulating layer, A unit region insulating layer on the channel structure, A plurality of pillars, penetrating the unit region insulating layer and respectively connected to the channel structure, the plurality of pillars being arranged in multiple rows in a second direction perpendicular to the first direction, A first separation region, penetrating the stacked structure and extending in the second direction, and A second separation region, penetrating the unit region insulating layer and the upper gate electrode, the second separation region extending in the second direction and between adjacent two rows of the plurality of pillars, Wherein the second separation region overlaps the pillars of the adjacent two rows in the second direction, and Wherein the upper surface of the second separation region is coplanar with the upper surfaces of the plurality of pillars.

2. The semiconductor device according to claim 1, wherein a side surface of the second separation region has a circular portion corresponding to the pillar.

3. The semiconductor device according to claim 1, wherein the second separation region contacts at least one of the pillars of the adjacent two rows.

4. The semiconductor device according to claim 3, wherein at least one of the pillars of the adjacent two rows has a recessed region from its upper end at a region in contact with the second separation region.

5. The semiconductor device according to claim 1, wherein the adjacent two rows of the plurality of pillars are arranged such that the central axes of the pillars are respectively offset from the central axis of the channel structure toward the second separation region.

6. The semiconductor device according to claim 1, wherein a diameter of the pillar is equal to or greater than a diameter of the channel structure.

7. The semiconductor device according to claim 1, wherein the second separation region is spaced apart from the channel structure in a horizontal direction.

8. The semiconductor device according to claim 7, wherein a part of the upper gate electrode is between the second separation region and the channel structure.

9. The semiconductor device according to claim 1, wherein the upper gate electrode includes a first conductive layer and a second conductive layer covering upper and lower surfaces of the first conductive layer, and Wherein the second separation region contacts both the first conductive layer and the second conductive layer.

10. The semiconductor device according to claim 9, wherein The second conductive layer covers a side surface of the first conductive layer in a region where the second conductive layer contacts the channel structure, and The second conductive layer exposes the first conductive layer in a region where the second conductive layer contacts the second separation region.

11. The semiconductor device according to claim 1, wherein the plurality of pillars comprise a material different from that of the plurality of gate electrodes.

12. The semiconductor device according to claim 1, wherein the second separation region includes an air gap therein.

13. The semiconductor device according to claim 1, wherein each of the pillars has an inclined side surface to narrow its width toward the channel structure.

14. The semiconductor device according to claim 1, wherein each of the channel structures includes a channel layer extending in the first direction and a channel pad filling the interior of the channel layer at an upper end of each of the channel structures, a lower surface of the channel pad is at a level higher than a topmost surface of the gate electrode, and each of the pillars is connected to the channel pad of a corresponding one of the channel structures.

15. A semiconductor device, comprising: a board layer; a plurality of gate electrodes stacked on the board layer and spaced apart from each other in a first direction perpendicular to an upper surface of the board layer, the plurality of gate electrodes including a lower gate electrode, a storage gate electrode, and an upper gate electrode stacked in sequence from the board layer; channel structures in channel holes penetrating the plurality of gate electrodes; a cell region insulating layer on the channel structures; a plurality of pillars penetrating the cell region insulating layer and respectively connected to the channel structures; a first separation region penetrating the plurality of gate electrodes and extending in a second direction perpendicular to the first direction; and a second separation region penetrating the cell region insulating layer and the upper gate electrode, extending in the second direction and between the plurality of pillars, wherein a side surface of the second separation region includes a circular portion surrounding the pillars and a straight portion extending in the second direction between the circular portions, wherein each of the gate electrodes includes a first conductive layer and a second conductive layer covering upper and lower surfaces of the first conductive layer, and wherein the second separation region contacts the first conductive layer and the second conductive layer of the upper gate electrode.

16. The semiconductor device according to claim 15, wherein an upper surface of the second separation region is at the same level as upper surfaces of the plurality of pillars.

17. The semiconductor device according to claim 15, wherein the pillars adjacent to the second separation region are arranged such that central axes of the pillars are respectively offset from a central axis of the channel structure toward the second separation region.

18. The semiconductor device according to claim 15, wherein an upper surface of the first separation region is at a level lower than upper surfaces of the plurality of pillars.

19. A data storage system, comprising: a semiconductor memory device including a first semiconductor structure including circuit elements, a second semiconductor structure on a surface of the first semiconductor structure, and input / output pads electrically connected to the circuit elements; and a controller electrically connected to the semiconductor memory device through the input / output pads and configured to control the semiconductor memory device, wherein the second semiconductor structure includes: Laminate, A plurality of gate electrodes, stacked on the laminate and spaced apart from each other in a first direction perpendicular to the upper surface of the laminate, the plurality of gate electrodes including a lower gate electrode, a storage gate electrode, and an upper gate electrode sequentially stacked from the laminate, A channel structure, in a channel hole penetrating the plurality of gate electrodes, A unit region insulating layer, on the channel structure, A plurality of pillars, penetrating the unit region insulating layer and respectively connected to the channel structure, A first separation region, penetrating the plurality of gate electrodes and extending in a second direction perpendicular to the first direction, and A second separation region, penetrating the unit region insulating layer and the upper gate electrode, the second separation region extending in the second direction and between the plurality of pillars, and Wherein the second separation region does not overlap with the channel structure in the first direction and overlaps with some of the plurality of pillars in the second direction.

20. The data storage system according to claim 19, wherein an upper surface of the second separation region is coplanar with upper surfaces of the plurality of pillars.

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