Semiconductor device and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and a storage system. The semiconductor device comprises a first semiconductor structure which comprises a semiconductor layer and a plurality of active regions which are located in the semiconductor layer and arranged at intervals, and each active region comprises a plurality of doped regions and gate structures located between the adjacent doped regions; and a second semiconductor structure bonded to the first semiconductor structure and including a peripheral circuit connected to the first semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to semiconductor devices, methods for manufacturing semiconductor devices, memories, and storage systems. Background Art

[0002] With the rise and development of the fields of artificial intelligence, big data, Internet of Things, mobile communication, mobile devices, and cloud storage, the requirements for the storage density and device size of semiconductor devices such as three-dimensional semiconductor memory devices are getting higher and higher. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies mentioned in the above background art part or other deficiencies in the prior art.

[0004] This application provides a semiconductor device. The semiconductor device includes: a first semiconductor structure including a semiconductor layer and a plurality of spaced-apart active regions located within the semiconductor layer, the active regions including a plurality of doped regions and a gate structure located between adjacent doped regions; and

[0005] a second semiconductor structure bonded to the first semiconductor structure and including a peripheral circuit connected to the first semiconductor structure.

[0006] In one embodiment, the plurality of doped regions include a first doped region, and a second doped region and a third doped region respectively located on opposite sides of the first doped region, wherein at least one of the gate structures is provided between the first doped region and the second doped region, and between the first doped region and the third doped region respectively.

[0007] In one embodiment, the active regions extend in a first direction, the gate structure extends in a second direction, and the semiconductor device further includes: a bit line connected to the first doped region and extending in a third direction, wherein the angle between the first direction and the second direction is an acute angle, the angle between the first direction and the third direction is an acute angle, and the second direction intersects the third direction; and a capacitor connected to the second doped region and the third doped region.

[0008] In one embodiment, the semiconductor device further includes a gate lead-out structure, a bit line lead-out structure, and a capacitor lead-out structure, wherein the gate structure, the bit line, and the capacitor are respectively connected to the peripheral circuit through the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure.

[0009] In one embodiment, the peripheral circuit includes a plurality of control circuits, wherein the gate lead structure, the bit line lead structure, and the capacitor lead structure are respectively connected to the plurality of control circuits.

[0010] In one embodiment, the gate lead structure, the bit line lead structure, and the capacitor lead structure respectively extend from a side of the capacitor away from the active region to the gate structure, the bit line, and the capacitor.

[0011] In one embodiment, the active region includes opposite first and second ends, and the first end is closer to the doped region than the second end. Wherein, the gate lead structure, the bit line lead structure, and the capacitor lead structure respectively extend from a side closer to the second end relative to the first end to the gate structure, the bit line, and the capacitor.

[0012] In one embodiment, the active region includes opposite first and second ends, and the first end is closer to the doped region than the second end. Wherein, the capacitor lead structure extends from a side of the capacitor away from the active region to the capacitor; and the gate lead structure and the bit line lead structure respectively extend from a side closer to the second end relative to the first end to the gate structure and the bit line.

[0013] In one embodiment, the second semiconductor structure further includes an interconnecting line located on the peripheral circuit and an interconnecting path connected to the interconnecting line and extending to the peripheral circuit.

[0014] In one embodiment, adjacent gate lead structures respectively extend to two sides of the gate structure along the second direction; and adjacent bit line lead structures respectively extend to two sides of the bit line along the third direction.

[0015] In one embodiment, the semiconductor device further includes: a pad lead structure that passes through the first semiconductor structure and extends to the second semiconductor structure.

[0016] On the other hand, the present application provides a method for manufacturing a semiconductor device. The method includes: forming a plurality of spaced-apart active regions in a semiconductor layer to form a first semiconductor structure, wherein the active regions include a plurality of doped regions and gate structures located between adjacent doped regions; and bonding a second semiconductor structure to the first semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit connected to the first semiconductor structure.

[0017] In one embodiment, the active regions extend in a first direction. Forming a plurality of spaced-apart active regions in the semiconductor layer includes: forming a plurality of isolation portions in the semiconductor layer, where the plurality of isolation portions divide a portion of the semiconductor layer into a plurality of initial active regions extending in the first direction; forming an initial doping region in each of the initial active regions; forming at least two grooves passing through the initial doping region, where the at least two grooves divide the initial doping region into the plurality of doping regions; and forming the gate structure in the grooves.

[0018] In one embodiment, the plurality of doping regions include a first doping region, and a second doping region and a third doping region respectively located on opposite sides of the first doping region. The gate structure extends in a second direction. The method further includes: forming a bit line connected to the first doping region and extending in a third direction, where the angle between the first direction and the second direction is an acute angle, the angle between the first direction and the third direction is an acute angle, and the second direction intersects the third direction; and forming a capacitor connected to the second doping region and the third doping region.

[0019] In one embodiment, the method further includes: forming a gate lead structure, a bit line lead structure, and a capacitor lead structure that respectively extend to the gate structure, the bit line, and the capacitor on a side of the capacitor away from the active region.

[0020] In one embodiment, the method further includes: forming a carrier wafer on one side of the first semiconductor structure; and forming a gate lead structure, a bit line lead structure, and a capacitor lead structure that respectively extend to the gate structure, the bit line, and the capacitor on the other side of the first semiconductor structure.

[0021] In one embodiment, the method further includes: forming a capacitor lead structure connected to the capacitor on a side of the capacitor away from the active region; and forming a gate lead structure and a bit line lead structure respectively connected to the gate structure and the bit line on a side of the active region away from the capacitor.

[0022] In one embodiment, the method further includes: forming an interconnecting line on the peripheral circuit; and forming an interconnecting path connected to the interconnecting line and extending to the peripheral circuit.

[0023] In one embodiment, the peripheral circuit includes a control circuit. Wherein, the step of forming the second semiconductor structure further includes: forming a plurality of the control circuits respectively connected to the gate lead structure, the bit line lead structure, and the capacitor lead structure.

[0024] In one embodiment, the method further includes: forming a pad lead-out structure that passes through the first semiconductor structure and extends to the second semiconductor structure.

[0025] On the other hand, the present application provides a storage system, which includes at least one 3D memory, each of the 3D memories including the semiconductor structure as described above; and a controller, coupled to the semiconductor structure, for controlling the 3D memory to store data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] With reference to the drawings, other features, objects, and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments. In the drawings:

[0027] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0028] Figure 2 is a partial top view structural schematic diagram of an isolation portion and an initial active region provided according to an exemplary embodiment of the present application;

[0029] Figure 3 and Figure 4 are schematic diagrams of structures formed by intercepting along the A-A direction and the B-B direction respectively on the basis of Figure 2 to form an initial doping region;

[0030] Figure 5 and Figure 6 is a partial structural schematic diagram of forming a groove provided according to an exemplary embodiment of the present application;

[0031] Figure 7 and Figure 8 is a partial structural schematic diagram of forming a gate structure provided according to an exemplary embodiment of the present application;

[0032] Figure 9 is an enlarged structural schematic diagram of the gate structure provided according to an exemplary embodiment of the present application;

[0033] Figure 10 and Figure 11 is a partial structural schematic diagram of forming a bit line provided according to an exemplary embodiment of the present application;

[0034] Figure 12 is a partial top view perspective structural schematic diagram after forming a capacitor provided according to an exemplary embodiment of the present application;

[0035] Figure 13 is Figure 12 a partial cross-sectional schematic diagram along the A-A direction;

[0036] Figure 14is Figure 12 Partial cross-sectional schematic view along the B-B direction;

[0037] Figure 15 is Figure 12 Partial perspective schematic view along the C-C direction;

[0038] Figure 16 is a schematic block diagram after bonding a second semiconductor structure to a first semiconductor structure provided according to an exemplary embodiment of the present application;

[0039] Figure 17 is a partial top-down perspective structure schematic view after forming a gate lead-out structure, a bit line lead-out structure, and a capacitor lead-out structure provided according to an exemplary embodiment of the present application;

[0040] Figure 18 is a partial structure schematic view of a second semiconductor structure provided according to an exemplary embodiment of the present application;

[0041] Figure 19 and Figure 20 is a process step diagram for forming a gate lead-out structure, a bit line lead-out structure, a capacitor lead-out structure, and bonding a second semiconductor structure to a first semiconductor structure provided according to an exemplary embodiment of the present application;

[0042] Figures 21 to 23 is a process step diagram for forming a gate lead-out structure, a bit line lead-out structure, a capacitor lead-out structure, and bonding a second semiconductor structure to a first semiconductor structure provided according to another exemplary embodiment of the present application;

[0043] Figure 24 is a partial structure schematic view of forming an interconnecting line, an interconnecting path, and a pad lead-out structure provided according to an exemplary embodiment of the present application;

[0044] Figures 25 to 27 is a process step diagram for forming a gate lead-out structure, a bit line lead-out structure, a capacitor lead-out structure, and bonding a second semiconductor structure to a first semiconductor structure provided according to another exemplary embodiment of the present application; and

[0045] Figure 28 is an exemplary block diagram of a system having a storage system provided according to an exemplary embodiment of the present application. Detailed Embodiments

[0046] To better understand the present application, more detailed descriptions of various aspects of the present application will be made with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of the exemplary embodiments of the present application and do not limit the scope of the present application in any way.

[0047] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features, especially not any order. Therefore, without departing from the teachings of the present application, the first semiconductor structure discussed in the present application may also be referred to as the second semiconductor structure, and the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0048] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0049] In addition, herein, when describing that a part is "on" another part, for example, the meanings of "on...", "above...", and "over..." should be interpreted in the broadest way, such that "on..." not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above..." or "over..." does not absolutely mean being above with respect to the direction of gravity, nor only means the meaning of "above something" or "over something", but may also include the meaning of "above something" or "over something" without intermediate features or layers therebetween (i.e., directly on something).

[0050] It should also be understood that expressions such as "comprising", "including", "having", "containing", and / or "including having" in this specification are open-ended rather than closed-ended expressions, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just individual elements in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0051] This description is made with reference to the schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and dimensions shown, but include various equivalent structures that can achieve the same functions and shape and dimension deviations caused, for example, during manufacturing. The positions shown in the drawings are essentially schematic and are not intended to limit the positions of the components.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0053] As used herein, the term "layer" refers to a portion of material that includes a region having a height. A layer can be a region of a uniform or non-uniform continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below it. A layer can include multiple layers.

[0054] In addition, in this application, when "connected" or "coupled" is used, it can indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or derivable from the context.

[0055] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Additionally, unless expressly defined or contradictory to the context, the specific steps included in the methods described in this application do not have to be limited to the recited order and can be executed in any order or executed in parallel. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0056] Figure 1 is a flowchart of a method 1000 for manufacturing a semiconductor device according to an exemplary embodiment of the present application.

[0057] As Figure 1 shown, the method 1000 for manufacturing a semiconductor device can include: S1100, forming a plurality of spaced-apart active regions in a semiconductor layer to form a first semiconductor structure, wherein the active regions include a plurality of doped regions and a gate structure located between adjacent doped regions; and S1200, bonding a second semiconductor structure to the first semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit connected to the first semiconductor structure. Steps S1100 and S1200 will be described in detail below.

[0058] Figure 7 is a schematic structural diagram of an active region 1110 according to an exemplary embodiment of the present application. Figure 8 is a schematic structural diagram of a first semiconductor structure 1100 according to an exemplary embodiment of the present application.

[0059] In an exemplary embodiment of the present application, as Figure 7 and Figure 8 shown, a plurality of spaced-apart active regions 1110 may be formed in the semiconductor layer 100 to form a first semiconductor structure 1100. Among them, the active region 1110 may include a plurality of doped regions (such as a first doped region 1111, a second doped region 1112, and a third doped region 1113) and a gate structure 1114 located between adjacent doped regions. Exemplarily, the second doped region 1112 and the third doped region 1113 may be respectively located on opposite sides of the first doped region 1111.

[0060] Exemplarily, the material of the semiconductor layer 100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0061] As Figures 2 to 8 shown, a process step diagram for forming the active region 1110 provided by the present application. It should be understood that the process for forming the active region 1110 provided by the present application is only an example and is not specifically limited. In actual processes, the process for forming the active region 1110 may be reasonably set according to actual needs.

[0062] Exemplarily, the active region 1110 may extend along the first direction X. Forming a plurality of spaced-apart active regions 1110 in the semiconductor layer 100 may include: forming a plurality of isolation portions 110 in the semiconductor layer 100, where the plurality of isolation portions 110 divide a part of the semiconductor layer 100 into a plurality of initial active regions 120 extending along the first direction X ( Figure 2 ); forming an initial doped region 130 in each initial active region 120 ( Figure 3 and Figure 4 ); forming at least two grooves 200 passing through the initial doped region 130, where the at least two grooves 200 divide the initial doped region 130 into a plurality of doped regions ( Figure 5 and Figure 6 ); and forming a gate structure 1114 in the grooves 200 ( Figure 7 and Figure 8 ).

[0063] Figure 3 and Figure 4 are schematic structural diagrams of the initial doped region formed by intercepting along the A-A direction and the B-B direction respectively on the basis of Figure 2 . Exemplarily, the angle between the first direction X and the second direction Y may be an acute angle, the angle between the first direction X and the third direction Z may be an acute angle, the second direction Y and the third direction Z may intersect, such as the second direction Y and the third direction Z may be perpendicular. The fourth direction D, the second direction Y, and the third direction Z may be perpendicular to each other in pairs.

[0064] Exemplarily, as Figure 2 shown, a plurality of isolation portions 110 may be formed in the semiconductor layer 100, and a part of the semiconductor layer 100 is divided into a plurality of initial active regions 120 extending along the first direction X by the plurality of isolation portions 110.

[0065] Exemplarily, a mask may be patterned as a mask, and the semiconductor layer 100 may be etched through one or more dry etching and / or wet etching processes to etch a plurality of trenches (not shown) in the semiconductor layer 100; and isolation portions 110 are formed in the trenches, and the semiconductor layer 100 that is not removed forms the initial active regions 120. The plurality of initial active regions 120 may be strip-shaped (such as oval and / or rectangular, etc.) spaced apart from each other in a plan view.

[0066] Exemplarily, the material of the isolation portion 110 may include, but is not limited to, insulating materials such as oxides. Exemplarily, an insulating material may be deposited in the trenches through a thin film deposition process to form the isolation portion 110, so that adjacent initial active regions 120 are isolated by the isolation portion 110. In addition, a planarization process such as a mechanical polishing process may be performed to remove the insulating material on the initial active regions 120.

[0067] Exemplarily, as Figure 3 and Figure 4 shown, an initial doping region 130 may be formed in the initial active region 120 by means of ion implantation or the like. The initial doping region 130 may be formed in the upper part of the initial active region 120. Exemplarily, doping agent ions of a conductivity type different from that of the semiconductor layer 100 may be implanted into the upper part of the initial active region 120 to form the initial doping region 130. It should be understood that the present application does not limit the sequence of the initial doping region 130 and the isolation portion 110, and the initial doping region 130 may also be formed before the isolation portion 110 is formed.

[0068] Figure 5 and Figure 6 are partial structural schematic diagrams of forming the groove 200 according to an exemplary embodiment of the present application. Exemplarily, as Figure 5 and Figure 6 shown, at least two grooves 200 passing through the initial doping region 130 may be formed, and the at least two grooves 200 divide the initial doping region 130 into a plurality of doping regions such as a first doping region 1111, a second doping region 1112, and a third doping region 1113. Exemplarily, the groove 200 may extend along the second direction Y to pass through a plurality of initial active regions 120 arranged along the second direction Y.

[0069] Due to the formation of the groove 200, the initial doping regions 130 in the initial active region 120 can be divided into, for example, a first doping region 1111, a second doping region 1112, and a third doping region 1113. In the present application, each initial active region 120 may have a first doping region 1111, and a second doping region 1112 and a third doping region 1113 located on opposite sides of the first doping region 1111, respectively. The first doping region 1111, the second doping region 1112, and the third doping region 1113 may be spaced apart from each other by the groove 200. Exemplarily, a mask may be patterned as a mask, and the initial active region 120 may be etched by one or more dry etching and / or wet etching processes to etch and form the groove 200 in the initial active region 120.

[0070] Figure 7 and Figure 8 is a partial structural schematic diagram of a gate structure 1114 provided according to an exemplary embodiment of the present application. Figure 9 is an enlarged structural schematic diagram of the gate structure 1114 provided according to an exemplary embodiment of the present application. As Figures 7 to 9 shown, forming the gate structure 1114 in the groove 200 may include: forming a gate dielectric layer 1114-1 extending along the second direction Y in the groove 200; and forming a gate layer 1114-2 on a side of the gate dielectric layer 1114-1 away from the initial active region 120. Exemplarily, the gate structure 1114 may extend along the second direction Y to form the gate structure 1114 in a plurality of initial active regions 120 arranged along the second direction Y.

[0071] Exemplarily, the gate dielectric layer 1114-1 and the gate layer 1114-2 may be sequentially deposited in the groove 200 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate dielectric layer 1114-1 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 1114-1 may include silicon oxide. The gate layer 1114-2 may include one or more conductive materials such as metals and / or metal compounds such as tungsten W and / or titanium nitride TiN. Exemplarily, a planarization process such as a chemical mechanical polishing process may be performed to remove excess conductive material and dielectric material on the surface of the active region 1110.

[0072] Exemplarily, an etch-back process may be employed to remove a portion of the gate layer 1114-2 along the fourth direction D, such that the upper end of the gate layer 1114-2 is below the top surface of the active region 1110. In addition, since the gate dielectric layer 1114-1 is not etched back, the upper end of the gate layer 1114-2 is below the upper end of the gate dielectric layer 1114-1.

[0073] In the present application, the multiple active regions 1110 are arranged at intervals, which is beneficial to reducing the coupling phenomenon between adjacent active regions 1110 and increasing the length of the gate structure 1114 in the active region 1110, thereby being beneficial to improving the performance of the active region 1110.

[0074] Figure 10 and Figure 11 are partial schematic structural diagrams of forming the bit line 1200 according to an exemplary embodiment of the present application. Exemplarily, as Figure 10 and Figure 11 shown, a bit line 1200 connected to the first doped region 1111 and extending along the third direction Z may be formed. In other words, the bit line 1200 may be connected to the first doped region 1111 among the multiple active regions 1110 arranged along the third direction Z.

[0075] Figure 12 is a partial top-down perspective structural diagram after forming the capacitor 1320 according to an exemplary embodiment of the present application. Figure 13 is Figure 12 a partial cross-sectional schematic diagram along the A-A direction, Figure 14 is Figure 12 a partial cross-sectional schematic diagram along the B-B direction, Figure 15 is Figure 12 a partial perspective schematic diagram along the C-C direction.

[0076] Exemplarily, as Figure 13 shown, a capacitor 1320 connected to the second doped region 1112 and the third doped region 1113 may be formed. For example, a capacitive contact structure 1310 ( Figure 12 and Figure 13 ) may be formed on the second doped region 1112 and the third doped region 1113; and a capacitor 1320 ( Figure 13 ) may be formed on the capacitive contact structure 1310.

[0077] Exemplarily, the capacitor 1320 may include a first electrode (not shown) connected to the capacitive contact structure 1310, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1320 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor, etc. Exemplarily, the capacitor 1320 may be a vertical capacitor, where the first electrode, the capacitor dielectric, and the second electrode are stacked along the fourth direction D, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0078] Figure 16 is a schematic block diagram of bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 according to an exemplary embodiment of the present application. Exemplarily, as Figure 16 shown, the second semiconductor structure 1200 may be bonded to the first semiconductor structure 1100, where the second semiconductor structure 1200 may include a peripheral circuit 1210 connected to the first semiconductor structure 1100.

[0079] Figure 17 is a partial top-down perspective structure schematic diagram after forming the gate lead-out structure 1410 (2410, 3410), the bit line lead-out structure 1420 (2420, 3420), and the capacitor lead-out structure 1430 (2430, 3430, Figure 19 , Figure 22 or Figure 25 ). Exemplarily, as Figure 17 shown, the gate lead-out structure 1410 (2410, 3410), the bit line lead-out structure 1420 (2420, 3420), and the capacitor lead-out structure 1430 (2430, 3430) may also be formed and connected to the gate structure 1114, the bit line 1200, and the capacitor 1320, respectively.

[0080] Exemplarily, as Figure 17 shown, adjacent gate lead-out structures 1410 (2410, 3410) may extend to both sides of the gate structure 1114 along the second direction Y; and adjacent bit line lead-out structures 1420 (2420, 3420) may extend to both sides of the bit line along the third direction Z. This arrangement is beneficial to increasing the lead-out space of the gate lead-out structure and / or the bit line lead-out structure, and reducing the coupling phenomenon between adjacent gate lead-out structures and / or bit line lead-out structures.

[0081] It should be understood that there is no sequence for the processes of forming the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100. In actual processes, the process steps of forming the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 can be reasonably set according to actual needs.

[0082] Figure 18 It is a partial structural schematic diagram of the second semiconductor structure 1200 provided according to an exemplary embodiment of the present application. The peripheral circuit 1210 (also known as the control and sensing circuit) may include any suitable digital, analog, and / or mixed-signal circuits for facilitating the operation of the memory cell array. Exemplarily, as Figure 18 shown, the peripheral circuit includes a plurality of control circuits such as a first control circuit 1211, a second control circuit 1212, and a third control circuit 1213, etc. The first control circuit 1211, the second control circuit 1212, and the third control circuit 1213 can be used to connect to the word line, the bit line, and the memory cell respectively to transmit electrical signals therebetween.

[0083] In the present application, by bonding the second semiconductor structure 1200 and the first semiconductor structure 1100, the gate lead-out structure 1410 (2410, 3410), the bit line lead-out structure 1420 (2420, 3420), and the capacitor lead-out structure 1430 (2430, 3430) can be respectively connected to the first control circuit 1211, the second control circuit 1212, and the third control circuit 1213, which is conducive to realizing signal transmission between the control circuit and the gate structure 1114, the bit line 1200, and the capacitor 1320. In addition, by arranging control circuits such as the first control circuit 1211, the second control circuit 1212, and the third control circuit 1213 in the second semiconductor structure 1200, it is beneficial to improve the integration degree of the semiconductor device and reduce the overall size of the semiconductor device.

[0084] Exemplarily, the peripheral circuit 1210 may further include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the above functional circuits (e.g., a sub-circuit), or any active or passive component of the circuit (e.g., a peripheral transistor, a diode, a resistor, or a capacitor).

[0085] Exemplarily, as Figure 18As shown, the second semiconductor structure 1200 may further include a second bonding layer 1220 located on the peripheral circuit 1210. The second bonding layer 1220 may include a plurality of second bonding contacts 1221 and a dielectric for isolating the second bonding contacts 1221. The second bonding contacts 1221 may include a conductive material, such as copper (Cu). The remaining area of the second bonding layer 1220 may be formed of a dielectric material (e.g., silicon oxide). The second bonding contacts 1221 and the surrounding dielectric in the second bonding layer 1220 may be used for hybrid bonding.

[0086] Exemplarily, the second semiconductor structure 1200 may further include an interconnect layer 1230 located between the peripheral circuit 1210 and the second bonding layer 1220 to transmit electrical signals to and from the peripheral circuit 1210. The interconnect layer 1230 may include a plurality of interconnect structures (which may also be referred to as "contact structures"), where the interconnect structures may include lateral interconnect lines and interconnect contacts. The interconnect layer 1230 may further include one or more dielectric layers for separating the plurality of interconnect lines and / or interconnect contacts. That is, the interconnect layer 1230 may include interconnect lines and interconnect contacts in a plurality of dielectric layers. Exemplarily, the peripheral circuits 1220 may be coupled to each other through the interconnect structures in the interconnect layer 1230. The material of the interconnect structures in the interconnect layer 1230 may include a conductive material, such as including but not limited to tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0087] Figure 19 and Figure 20 are process step diagrams for forming the gate lead-out structure 1410, the bit line lead-out structure 1420, and the capacitor lead-out structure 1430, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 according to an exemplary embodiment of the present application.

[0088] In an exemplary embodiment of the present application, as Figure 19As shown, a gate lead structure 1410, a bit line lead structure 1420, and a capacitor lead structure 1430 that respectively extend to the gate structure 1114, the bit line 1200, and the capacitor 1320 can be formed on a side of the capacitor 1320 away from the active region 1110. The gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430 can be respectively used to implement the connection of the gate structure 1114, the bit line 1200, and the capacitor 1320 to the control circuit. Exemplarily, the materials of the gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430 can all include conductive materials. In addition, an electrode plate 1330 for connecting the second electrodes of multiple capacitors 1320 together can also be formed, and the capacitor lead structure 1430 is connected to the capacitor 1320 through the electrode plate 1330.

[0089] Exemplarily, trenches can be formed by using a photolithography process, one or more dry etching and / or wet etching processes, etc.; then the gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430 can be formed in the removed space by using one or more thin film deposition processes.

[0090] Exemplarily, as Figure 19 shown, a conductive layer 1500 can also be formed on the gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430; and a first bonding layer 1600 can be formed on the conductive layer 1500. The first bonding layer 1600 can include multiple first bonding contacts 1610 and a dielectric for isolating the first bonding contacts 1610. The gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430 can be connected to the multiple first bonding contacts 1610 through the conductive layer 1500. The first bonding contacts 1610 can include a conductive material, such as copper (Cu). The remaining region of the first bonding layer 1600 can be formed of a dielectric material (not shown, such as silicon oxide). The first bonding contacts 1610 and the surrounding dielectric in the first bonding layer 1600 can be used for hybrid bonding.

[0091] Exemplarily, as Figure 20 shown, the second semiconductor structure 1200 can be bonded to the first semiconductor structure 1100. Exemplarily, the first bonding layer 1600 in the first semiconductor structure 1100 and the second bonding layer 1220 in the second semiconductor structure 1200 can be bonded in a face-to-face manner. After bonding, the first bonding contacts 1610 and the second bonding contacts 1221 can be in contact with each other.

[0092] Exemplarily, as Figure 20As shown, the gate structure 1114 can be coupled to the first control circuit 1211 in the peripheral circuit 1210 through the gate lead-out structure 1410, the first bonding contact 1610, and the second bonding contact 1221. The bit line 1200 can be coupled to the second control circuit 1212 in the peripheral circuit 1210 through the bit line lead-out structure 1420, the first bonding contact 1610, and the second bonding contact 1221. The capacitor 1320 can be coupled to the third control circuit 1213 in the peripheral circuit 1210 through the capacitor lead-out structure 1430, the first bonding contact 1610, and the second bonding contact 1221.

[0093] Exemplarily, as Figure 20 shown, a pad lead-out structure 1300 that passes through the first semiconductor structure 1100 and extends to the second semiconductor structure 1200 can also be formed. The pad lead-out structure 1300 can be connected to the second semiconductor structure 1200 through the conductive layer 1500, the first bonding layer 1600, and the second bonding layer 1220. The pad lead-out structure 1300 can transmit electrical signals between the semiconductor device and the external circuit.

[0094] Specifically, a pad lead-out interconnect layer can be formed on the side of the first semiconductor structure 1100 away from the bit line 1200, and then the pad lead-out structure 1300 that passes through the pad lead-out interconnect layer and extends to the conductive layer 1500 can be formed. The pad lead-out structure 1300 can include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0095] Figures 21 to 23 is a process step diagram for forming the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430, and bonding the second semiconductor structure 1200 and the first semiconductor structure 1100 according to another exemplary embodiment of the present application.

[0096] In an exemplary embodiment of the present application, a carrier wafer 300 ( Figure 21 ) can be formed on one side of the first semiconductor structure 1100; and a gate lead-out structure 2410, a bit line lead-out structure 2420, and a capacitor lead-out structure 2430 that respectively extend to the gate structure 1114, the bit line 1200, and the capacitor 1320 can be formed on the other side of the first semiconductor structure 1110 ( Figure 22 ).

[0097] Exemplarily, as Figure 21As shown, an electrode plate 2330 for connecting the second electrodes of a plurality of capacitors 1320 together can be formed on one side of the capacitor 1320, and a carrier wafer 300 can be located on one side of the electrode plate 2330 for supporting the first semiconductor structure 1100 and the like. Exemplarily, the active region 1110 can include opposite first and second ends 1 and 2, where the first end 1 is closer to a doped region such as the third doped region 1113 than the second end 2. The electrode plate 2330 and the carrier wafer 300 are closer to the first end 1 than the second end 2.

[0098] Figure 22 To Figure 21 The structural schematic diagram of the subsequent process after flipping the structure shown by 180°. Exemplarily, as Figure 22 shown, Figure 21 After flipping the structure shown by 180°, a gate lead-out structure 2410, a bit line lead-out structure 2420, and a capacitor lead-out structure 2430 can be formed on the side of the first semiconductor structure 1110 away from the carrier wafer 300. Exemplarily, the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 can extend from the side closer to the second end 2 than the first end 1 to the gate structure 1114, the bit line 1200, and the capacitor 1320 respectively. The gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 can be used to realize the connection of the gate structure 1114, the bit line 1200, and the capacitor 1320 to the control circuit respectively. Exemplarily, the materials of the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 can all include conductive materials.

[0099] Exemplarily, trenches can be formed by using a photolithography process, one or more dry etching and / or wet etching processes, etc.; then the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 can be formed in the removed space by using one or more thin film deposition processes.

[0100] Exemplarily, as Figure 22As shown, a conductive layer 2500 may also be formed on the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430; and a first bonding layer 2600 may be formed on the conductive layer 2500. The first bonding layer 2600 may include a plurality of first bonding contacts 2610 and a dielectric for isolating the first bonding contacts 2610. The gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 may be connected to the plurality of first bonding contacts 2610 through the conductive layer 2500. The first bonding contacts 2610 may include a conductive material, such as copper (Cu). The remaining area of the first bonding layer 2600 may be formed of a dielectric material (not shown, such as silicon oxide). The first bonding contacts 2610 and the surrounding dielectric in the first bonding layer 2600 may be used for hybrid bonding. Exemplarily, the carrier wafer 300 may be removed after the first bonding layer 2600 is formed.

[0101] Exemplarily, as Figure 23 shown, the second semiconductor structure 1200 may be bonded to the first semiconductor structure 1100. Exemplarily, the first bonding layer 2600 in the first semiconductor structure 1100 and the second bonding layer 1220 in the second semiconductor structure 1200 may be bonded in a face-to-face manner. After bonding, the first bonding contacts 2610 and the second bonding contacts 1221 may be in contact with each other.

[0102] Exemplarily, as Figure 23 shown, the gate structure 1114 may be coupled to the first control circuit 1211 in the peripheral circuit 1210 through the gate lead-out structure 2410, the first bonding contacts 2610, and the second bonding contacts 1221. The bit line 1200 may be coupled to the second control circuit 1212 in the peripheral circuit 1210 through the bit line lead-out structure 2420, the first bonding contacts 2610, and the second bonding contacts 1221. The capacitor 1320 may be coupled to a third control circuit (not shown) in the peripheral circuit 1210 through the capacitor lead-out structure 2430, the first bonding contacts 2610, and the second bonding contacts 1221.

[0103] Exemplarily, as Figure 24 shown, an interconnecting line 1240 may also be formed on the peripheral circuit 1210; and an interconnecting path 1250 connected to the interconnecting line 1240 and extending to the peripheral circuit 1210 may be formed. The interconnecting line 1240 and the interconnecting path 1250 may be used to connect the peripheral circuit 1210 and a power supply line (not shown), which is beneficial to shortening the length of the interconnecting structure between the peripheral circuit 1210 and the power supply line, thereby reducing the parasitic capacitance of the interconnecting structure and improving the sensing tolerance and storage density of the semiconductor device.

[0104] Exemplarily, as Figure 24As shown, a pad lead-out structure 2300 extending to the second semiconductor structure 1200 may also be formed on one side of the interconnect line 1240. The pad lead-out structure 2300 can transmit electrical signals between the semiconductor device and the external circuit.

[0105] Specifically, a pad lead-out interconnect layer may be formed on the side of the interconnect line 1240 away from the second semiconductor structure 1200, and then the pad lead-out structure 2300 passing through the pad lead-out interconnect layer and extending to the second semiconductor structure 1200 is formed. The pad lead-out structure 2300 may include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0106] Figures 25 to 27 It is a process step diagram for forming a gate lead-out structure 3410, a bit line lead-out structure 3420, and a capacitor lead-out structure 3430, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 according to another exemplary embodiment of the present application.

[0107] In an exemplary embodiment of the present application, a capacitor lead-out structure 3430 connected to the capacitor 1320 may be formed on the side of the capacitor 1320 away from the active region 1110 ( Figure 25 ); and a gate lead-out structure 3410 and a bit line lead-out structure 3420 respectively connected to the gate structure 1114 and the bit line 1200 may be formed on the side of the active region 1110 away from the capacitor 1320 ( Figure 26 ).

[0108] Exemplarily, as Figure 25 shown, the active region 1110 may include opposite first end 1 and second end 2, where the first end 1 is closer to a doped region such as the third doped region 1113 than the second end 2. An electrode plate 3330 for connecting the second electrodes of a plurality of capacitors 1320 together may be formed; then a capacitor lead-out structure 3430 connected to the electrode plate 3330 is formed. The electrode plate 3330 is closer to the first end 1 than the second end 2. The capacitor lead-out structure 3430 is connected to the capacitor 1320 through the electrode plate 3330. In other words, the capacitor lead-out structure 3430 may extend from the side closer to the first end 1 than the second end 2 to the capacitor 1320. The capacitor lead-out structure 3430 can be used to realize the connection between the capacitor 1320 and the control circuit.

[0109] Figure 26 For Figure 25 is a schematic structural diagram of the subsequent process after flipping the structure 180°. Exemplarily, as Figure 26 shown, Figure 25After the shown structure is flipped by 180°, a gate lead structure 3410 and a bit line lead structure 3420 that are respectively connected to the gate structure 1114 and the bit line 1200 are formed on a side of the active region 1110 away from the capacitor 1320. Exemplarily, the gate lead structure 3410 and the bit line lead structure 3420 can extend from a side closer to the second end 2 relative to the first end 1 to the gate structure 1114 and the bit line 1200 respectively. The gate lead structure 3410 and the bit line lead structure 3420 can be respectively used to realize the connection between the gate structure 1114 and the bit line 1200 and the control circuit. Exemplarily, the materials of the gate lead structure 2410, the bit line lead structure 2420, and the capacitor lead structure 2430 can all include conductive materials.

[0110] Exemplarily, trenches can be formed by using a photolithography process, one or more dry etching and / or wet etching processes, etc.; then, the gate lead structure 3410, the bit line lead structure 3420, and the capacitor lead structure 3430 can be formed in the removed space by using one or more thin film deposition processes.

[0111] Exemplarily, as Figure 26 shown, a conductive layer 3500 can also be formed on the gate lead structure 3410, the bit line lead structure 3420, and the capacitor lead structure 3430; and a first bonding layer 3600 can be formed on the conductive layer 3500. The first bonding layer 3600 can include a plurality of first bonding contacts 3610 and a dielectric for isolating the first bonding contacts 3610. The gate lead structure 3410, the bit line lead structure 3420, and the capacitor lead structure 3430 can be connected to the plurality of first bonding contacts 3610 through the conductive layer 3500. The first bonding contacts 3610 can include a conductive material, such as copper (Cu). The remaining region of the first bonding layer 3600 can be formed of a dielectric material (not shown, such as silicon oxide). The first bonding contacts 3610 and the surrounding dielectric in the first bonding layer 3600 can be used for hybrid bonding.

[0112] Exemplarily, as Figure 27 shown, the second semiconductor structure 1200 can be bonded to the first semiconductor structure 1100. Exemplarily, the first bonding layer 3600 in the first semiconductor structure 1100 and the second bonding layer 1220 in the second semiconductor structure 1200 can be bonded in a face-to-face manner. After bonding, the first bonding contacts 3610 and the second bonding contacts 1221 can be in contact with each other.

[0113] Exemplarily, as Figure 27As shown, the gate structure 1114 can be coupled to the first control circuit 1211 in the peripheral circuit 1210 through the gate lead-out structure 3410, the first bonding contact 3610, and the second bonding contact 1221. The bit line 1200 can be coupled to the second control circuit 1212 in the peripheral circuit 1210 through the bit line lead-out structure 3420, the first bonding contact 3610, and the second bonding contact 1221. The capacitor 1320 can be coupled to the third control circuit 1213 in the peripheral circuit 1210 through the capacitor lead-out structure 3430, the first bonding contact 3610, and the second bonding contact 1221.

[0114] Exemplarily, as Figure 27 shown, a pad lead-out structure 3300 that passes through the first semiconductor structure 1100 and extends to the second semiconductor structure 1200 can also be formed. The pad lead-out structure 3300 can be connected to the second semiconductor structure 1200 through the conductive layer 3500, the first bonding layer 3600, and the second bonding layer 1220. The pad lead-out structure 3300 can transmit electrical signals between the semiconductor device and the external circuit.

[0115] Specifically, a pad lead-out interconnect layer can be formed on the side of the first semiconductor structure 1100 away from the bit line 1200, and then the pad lead-out structure 3300 that passes through the pad lead-out interconnect layer and extends to the conductive layer 3500 can be formed. The pad lead-out structure 3300 can include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0116] This application exemplarily lists the processes of forming the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 in three embodiments. It should be understood that the processes of forming the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 provided in this application are only several examples and are not specifically limited. In actual processes, the specific processes of forming the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 can be reasonably set according to actual situations.

[0117] In this application, the process steps of forming the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure, and bonding the second semiconductor structure 1200 to the first semiconductor structure 1100 can be flexibly set, which is beneficial to improving the process freedom of the semiconductor device, and thus beneficial to improving the production efficiency and quality of the semiconductor device.

[0118] Figure 16It is a schematic block diagram of a semiconductor device according to an exemplary embodiment of the present application.

[0119] The semiconductor device may include a first semiconductor structure 1100 and a second semiconductor structure 1200 that are phase-bonded.

[0120] As Figures 12 to 15 shown, the first semiconductor structure 1100 may include a semiconductor layer 100 and a plurality of spaced-apart active regions 1110 located within the semiconductor layer 100. The active regions 1110 may include a plurality of doped regions and gate structures 1114 located between adjacent doped regions.

[0121] Exemplarily, the material of the semiconductor layer 100 may include at least one of single-crystalline silicon, polycrystalline silicon, single-crystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0122] Exemplarily, the active regions 1110 may extend along a first direction X. The active regions 1110 may be strip-shaped (such as oval and / or rectangular, etc.) spaced apart from each other in a plan view. As Figure 2 shown, a plurality of isolation portions 110 may be provided within the semiconductor layer 100, and the plurality of isolation portions 110 may divide a part of the semiconductor layer 100 into a plurality of active regions 1110 extending along the first direction X. Exemplarily, the angle between the first direction X and the second direction Y may be an acute angle, the angle between the first direction X and the third direction Z may be an acute angle, and the second direction Y and the third direction Z may intersect, such as the second direction Y and the third direction Z may be perpendicular. The fourth direction D, the second direction Y, and the third direction Z may be perpendicular to each other pairwise.

[0123] Exemplarily, the material of the isolation portion 110 may include, but is not limited to, insulating materials such as oxides. Exemplarily, an insulating material may be deposited in a trench through a thin-film deposition process to form the isolation portion 110, so that adjacent initial active regions 120 are isolated by the isolation portion 110. In addition, a planarization process such as a mechanical polishing process may be performed to remove the insulating material on the initial active regions 120.

[0124] In an exemplary embodiment of the present application, the doped region may include dopant ions of a conductivity type different from that of the semiconductor layer 100. As Figure 13 shown, the plurality of doped regions may include a first doped region 1111, and second doped regions 1112 and third doped regions 1113 respectively located on opposite sides of the first doped region 1111. Exemplarily, at least one gate structure 1114 may be provided between the first doped region 1111 and the second doped region 1112, and between the first doped region 1111 and the third doped region 1113 respectively.

[0125] Exemplarily, asFigure 12 As shown, the gate structure 1114 can extend along the second direction Y. The gate structures 1114 in the plurality of active regions 1110 arranged along the second direction Y can be a continuous structure. As Figure 9 As shown, the gate structure 1114 can include a gate dielectric layer 1114-1 and a gate layer 1114-2. The gate dielectric layer 1114-1 can extend along the second direction Y. The gate layer 1114-2 can be located on a side of the gate dielectric layer 1114-1 away from the initial active region 120. Exemplarily, the upper end of the gate layer 1114-2 can be located below the top surface of the active region 1110 and can be below the upper end of the gate dielectric layer 1114-1.

[0126] The gate dielectric layer 1114-1 can include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. For example, the gate dielectric layer 1114-1 can include silicon oxide. The gate layer 1114-2 can include one or more conductive materials such as metals and / or metal compounds such as tungsten W and / or titanium nitride TiN.

[0127] In the present application, the plurality of active regions 1110 are spaced apart, which is beneficial to reducing the coupling phenomenon between adjacent active regions 1110 and is also beneficial to increasing the length of the gate structure 1114 in the active region 1110, thereby being beneficial to improving the performance of the active region 1110.

[0128] The second semiconductor structure 1200 can include a peripheral circuit 1210 connected to the first semiconductor structure 1100. The peripheral circuit 1210 (also referred to as a control and sensing circuit) can include any suitable digital, analog, and / or mixed-signal circuits for facilitating the operation of the memory cell array. Exemplarily, as Figure 18 shown, the peripheral circuit includes a plurality of control circuits such as a first control circuit 1211, a second control circuit 1212, and a third control circuit 1213, etc. The first control circuit 1211, the second control circuit 1212, and the third control circuit 1213 can be used to be connected to the word line, the bit line, and the memory cell respectively to transmit electrical signals therebetween.

[0129] In the present application, by arranging control circuits such as the first control circuit 1211, the second control circuit 1212, and the third control circuit 1213 in the second semiconductor structure 1200, it is beneficial to improve the integration degree of the semiconductor device and reduce the overall size of the semiconductor device.

[0130] Exemplarily, the peripheral circuit 1210 may further include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the above functional circuits (e.g., a sub-circuit), or any active or passive component of the circuit (e.g., a peripheral transistor, diode, resistor, or capacitor).

[0131] Exemplarily, as Figure 18 shown, the second semiconductor structure 1200 may further include a second bonding layer 1220 located on the peripheral circuit 1210. The second bonding layer 1220 may include a plurality of second bonding contacts 1221 and a dielectric for isolating the second bonding contacts 1221. The second bonding contacts 1221 may include a conductive material, such as copper (Cu). The remaining area of the second bonding layer 1220 may be formed of a dielectric material (e.g., silicon oxide). The second bonding contacts 1221 and the surrounding dielectric in the second bonding layer 1220 may be used for hybrid bonding.

[0132] Exemplarily, the second semiconductor structure 1200 may further include an interconnect layer 1230 located between the peripheral circuit 1210 and the second bonding layer 1220 to transmit electrical signals to and from the peripheral circuit 1210. The interconnect layer 1230 may include a plurality of interconnect structures (which may also be referred to as "contact structures"), where the interconnect structures may include lateral interconnect lines and interconnect contacts. The interconnect layer 1230 may further include one or more dielectric layers for separating the plurality of interconnect lines and / or interconnect contacts. That is, the interconnect layer 1230 may include interconnect lines and interconnect contacts in a plurality of dielectric layers. Exemplarily, the peripheral circuits 1220 may be coupled to each other through the interconnect structures in the interconnect layer 1230. The material of the interconnect structures in the interconnect layer 1230 may include a conductive material, such as including but not limited to tungsten (W), copper (Cu), aluminum (Al), doped silicon, silicide, or any combination thereof. The dielectric layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0133] In an exemplary embodiment of the present application, as Figures 12 to 15As shown, the semiconductor device may further include a bit line 1200 connected to the first doped region 1111 and extending along the third direction Z. The bit line 1200 may be connected to the first doped region 1111 among a plurality of active regions 1110 arranged along the third direction Z. Exemplarily, the semiconductor device may further include a capacitor 1320 connected to the second doped region 1112 and the third doped region 1113. Exemplarily, the semiconductor device may further include a capacitive contact structure 1310, where the capacitive contact structure 1310 may be located on one side of the second doped region 1112 and the third doped region 1113, and the capacitor 1320 may be connected to the second doped region 1112 and the third doped region 1113 through the capacitive contact structure 1310.

[0134] Exemplarily, the capacitor 1320 may include a first electrode (not shown) connected to the capacitive contact structure 1310, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1320 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor, etc. Exemplarily, the capacitor 1320 may be a vertical capacitor, where the first electrode, the capacitor dielectric, and the second electrode are stacked along the fourth direction D, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0135] In an exemplary embodiment of the present application, as Figure 20 shown, the semiconductor device may further include a gate lead-out structure 1410, a bit line lead-out structure 1420, and a capacitor lead-out structure 1430. The gate structure 1114, the bit line 1200, and the capacitor 1320 may be respectively connected to an external circuit (such as the first control circuit 1211, the second control circuit 1212, and the third control circuit 1213 therein) through the gate lead-out structure 1410, the bit line lead-out structure 1420, and the capacitor lead-out structure 1430, so as to facilitate signal transmission between the control circuit and the gate structure 1114, the bit line 1200, and the capacitor 1320.

[0136] Exemplarily, as Figure 17 shown, adjacent gate lead-out structures 1410 may respectively extend to both sides of the gate structure 1114 along the second direction Y; and adjacent bit line lead-out structures 1420 may respectively extend to both sides of the bit line along the third direction Z. Such an arrangement is conducive to increasing the lead-out space of the gate lead-out structure and / or the bit line lead-out structure, and reducing the coupling phenomenon between adjacent gate lead-out structures and / or bit line lead-out structures.

[0137] Exemplarily, the gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430 can extend from the side of the capacitor 1320 away from the active region 1110 to the gate structure 1114, the bit line 1200, and the capacitor 1320, respectively. Exemplarily, the semiconductor device may further include an electrode plate 1330 for connecting the second electrodes of a plurality of capacitors 1320 together, wherein the capacitor lead structure 1430 is connected to the capacitor 1320 through the electrode plate 1330. The materials of the electrode plate 1330, the gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430 may all include conductive materials.

[0138] Exemplarily, the semiconductor device may further include a conductive layer 1500 and a first bonding layer 1600 formed on the conductive layer 1500. The conductive layer 1500 may be located on the gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430. The first bonding layer 1600 may include a plurality of first bonding contacts 1610 and a dielectric for isolating the first bonding contacts 1610. The gate lead structure 1410, the bit line lead structure 1420, and the capacitor lead structure 1430 may be connected to the plurality of first bonding contacts 1610 through the conductive layer 1500. The first bonding contacts 1610 may include a conductive material, such as copper (Cu). The remaining region of the first bonding layer 1600 may be formed of a dielectric material (not shown, such as silicon oxide). The first bonding contacts 1610 and the surrounding dielectric in the first bonding layer 1600 may be used for hybrid bonding.

[0139] Exemplarily, the first bonding contacts 1610 and the second bonding contacts 1221 may be in contact with each other. The gate structure 1114 may be coupled to the first control circuit 1211 in the peripheral circuit 1210 through the gate lead structure 1410, the first bonding contacts 1610, and the second bonding contacts 1221. The bit line 1200 may be coupled to the second control circuit 1212 in the peripheral circuit 1210 through the bit line lead structure 1420, the first bonding contacts 1610, and the second bonding contacts 1221. The capacitor 1320 may be coupled to the third control circuit 1213 in the peripheral circuit 1210 through the capacitor lead structure 1430, the first bonding contacts 1610, and the second bonding contacts 1221.

[0140] Exemplarily, the semiconductor device may further include a pad lead structure 1300 that passes through the first semiconductor structure 1100 and extends to the second semiconductor structure 1200. The pad lead structure 1300 may be connected to the second semiconductor structure 1200 through the conductive layer 1500, the first bonding layer 1600, and the second bonding layer 1220. The pad lead structure 1300 may transmit electrical signals between the semiconductor device and an external circuit.

[0141] The pad lead-out structure 1300 may include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0142] In another exemplary embodiment of the present application, as Figure 24 shown, the semiconductor device may further include a gate lead-out structure 2410, a bit line lead-out structure 2420, and a capacitor lead-out structure 2430. The gate structure 1114, the bit line 1200, and the capacitor 1320 may be connected to the peripheral circuit (such as the first control circuit 1211, the second control circuit 1212, and the third control circuit 1213 therein) through the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 respectively, so as to facilitate signal transmission between the control circuit and the gate structure 1114, the bit line 1200, and the capacitor 1320.

[0143] Exemplarily, as Figure 17 shown, adjacent gate lead-out structures 2410 may respectively extend to both sides of the gate structure 1114 along the second direction Y; and adjacent bit line lead-out structures 2420 may respectively extend to both sides of the bit line along the third direction Z. Such an arrangement is beneficial to increasing the lead-out space of the gate lead-out structure and / or the bit line lead-out structure and reducing the coupling phenomenon between adjacent gate lead-out structures and / or bit line lead-out structures.

[0144] Exemplarily, the active region 1110 may include opposite first end 1 and second end 2, where the first end 1 is closer to the doped region such as the third doped region 1113 than the second end 2. The electrode plate 2330 is closer to the first end 1 than the second end 2. Exemplarily, the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 may respectively extend from a side closer to the second end 2 than the first end 1 to the gate structure 1114, the bit line 1200, and the capacitor 1320. The gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 may be respectively used to realize the connection between the gate structure 1114, the bit line 1200, and the capacitor 1320 and the control circuit. Exemplarily, the materials of the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 may all include a conductive material.

[0145] Exemplarily, the semiconductor device may further include an electrode plate 2330 for connecting the second electrodes of the plurality of capacitors 1320 together, wherein the electrode plate 2330 is closer to the first end 1 than to the second end 2. Exemplarily, the semiconductor device may further include a conductive layer 2500 and a first bonding layer 2600 located on the conductive layer 2500. The first bonding layer 2600 may include a plurality of first bonding contacts 2610 and a dielectric for isolating the first bonding contacts 2610. The gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 may be connected to the plurality of first bonding contacts 2610 through the conductive layer 2500. The first bonding contacts 2610 may include a conductive material, such as copper (Cu). The remaining area of the first bonding layer 2600 may be formed of a dielectric material (not shown, such as silicon oxide). The first bonding contacts 2610 and the surrounding dielectric in the first bonding layer 2600 may be used for hybrid bonding.

[0146] Exemplarily, the first bonding contacts 2610 and the second bonding contacts 1221 may be in contact with each other. The gate structure 1114 may be coupled to the first control circuit 1211 in the peripheral circuit 1210 through the gate lead-out structure 2410, the first bonding contacts 2610, and the second bonding contacts 1221. The bit line 1200 may be coupled to the second control circuit 1212 in the peripheral circuit 1210 through the bit line lead-out structure 2420, the first bonding contacts 2610, and the second bonding contacts 1221. The capacitor 1320 may be coupled to a third control circuit (not shown) in the peripheral circuit 1210 through the capacitor lead-out structure 2430, the first bonding contacts 2610, and the second bonding contacts 1221.

[0147] Exemplarily, the semiconductor device may further include an interconnect line 1240 and an interconnect via 1250. The interconnect line 1240 may be located on the peripheral circuit 1210. The interconnect via 1250 may be connected to the interconnect line 1240 and extend to the peripheral circuit 1210. The interconnect line 1240 and the interconnect via 1250 may be used to connect the peripheral circuit 1210 and a power supply line (not shown), which helps to shorten the length of the interconnect structure between the peripheral circuit 1210 and the power supply line, thereby reducing the parasitic capacitance of the interconnect structure and improving the sensing tolerance and storage density of the semiconductor device.

[0148] Exemplarily, the semiconductor device may further include a pad lead-out structure 2300 located on one side of the interconnect line 1240 and extending to the second semiconductor structure 1200. The pad lead-out structure 2300 may transmit electrical signals between the semiconductor device and an external circuit. The pad lead-out structure 2300 may include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0149] In another exemplary embodiment of the present application, as Figure 27 shown, the semiconductor device may further include a gate lead-out structure 3410, a bit line lead-out structure 3420, and a capacitor lead-out structure 3430.

[0150] The gate structure 1114, the bit line 1200, and the capacitor 1320 can be connected to an external circuit (such as the first control circuit 1211, the second control circuit 1212, and the third control circuit 1213 therein) through the gate lead-out structure 3410, the bit line lead-out structure 3420, and the capacitor lead-out structure 3430 respectively, so as to facilitate the signal transmission between the control circuit and the gate structure 1114, the bit line 1200, and the capacitor 1320.

[0151] Exemplarily, as Figure 17 shown, adjacent gate lead-out structures 3410 can extend to both sides of the gate structure 1114 along the second direction Y respectively; and adjacent bit line lead-out structures 3420 can extend to both sides of the bit line along the third direction Z respectively. Such an arrangement is beneficial to improving the lead-out space of the gate lead-out structure and / or the bit line lead-out structure, and reducing the coupling phenomenon between adjacent gate lead-out structures and / or bit line lead-out structures.

[0152] Exemplarily, the active region 1110 may include opposite first end 1 and second end 2, where the first end 1 is closer to the doped region such as the third doped region 1113 than the second end 2. The semiconductor device may further include an electrode plate 3330 for connecting the second electrodes of a plurality of capacitors 1320 together. The electrode plate 3330 is closer to the first end 1 than the second end 2. The capacitor lead-out structure 3430 is connected to the capacitor 1320 through the electrode plate 3330. In other words, the capacitor lead-out structure 3430 can extend from the side closer to the first end 1 than the second end 2 to the capacitor 1320. The capacitor lead-out structure 3430 can be used to realize the connection between the capacitor 1320 and the control circuit.

[0153] Exemplarily, the gate lead-out structure 3410 and the bit line lead-out structure 3420 can extend to the gate structure 1114 and the bit line 1200 respectively from the side closer to the second end 2 than the first end 1. The gate lead-out structure 3410 and the bit line lead-out structure 3420 can be used to realize the connection between the gate structure 1114 and the bit line 1200 and the control circuit respectively. Exemplarily, the materials of the gate lead-out structure 2410, the bit line lead-out structure 2420, and the capacitor lead-out structure 2430 may all include conductive materials.

[0154] Exemplarily, the semiconductor device may further include a conductive layer 3500 and a first bonding layer 3600 located on the conductive layer 3500. The first bonding layer 3600 may include a plurality of first bonding contacts 3610 and a dielectric for isolating the first bonding contacts 3610. The gate lead-out structure 3410, the bit line lead-out structure 3420, and the capacitor lead-out structure 3430 may be connected to the plurality of first bonding contacts 3610 through the conductive layer 3500. The first bonding contacts 3610 may include a conductive material, such as copper (Cu). The remaining area of the first bonding layer 3600 may be formed of a dielectric material (not shown, such as silicon oxide). The first bonding contacts 3610 and the surrounding dielectric in the first bonding layer 3600 may be used for hybrid bonding.

[0155] Exemplarily, the first bonding contacts 3610 and the second bonding contacts 1221 may be in contact with each other. The gate structure 1114 may be coupled to the first control circuit 1211 in the peripheral circuit 1210 through the gate lead-out structure 3410, the first bonding contacts 3610, and the second bonding contacts 1221. The bit line 1200 may be coupled to the second control circuit 1212 in the peripheral circuit 1210 through the bit line lead-out structure 3420, the first bonding contacts 3610, and the second bonding contacts 1221. The capacitor 1320 may be coupled to the third control circuit 1213 in the peripheral circuit 1210 through the capacitor lead-out structure 3430, the first bonding contacts 3610, and the second bonding contacts 1221.

[0156] Exemplarily, the semiconductor device may further include a pad lead-out structure 3300 that passes through the first semiconductor structure 1100 and extends to the second semiconductor structure 1200. The pad lead-out structure 3300 may be connected to the second semiconductor structure 1200 through the conductive layer 3500, the first bonding layer 3600, and the second bonding layer 1220. The pad lead-out structure 3300 may transmit electrical signals between the semiconductor device and an external circuit. The pad lead-out structure 3300 may include a conductive material, including but not limited to W, Cu, Al, doped silicon, silicide, or any combination thereof. The pad lead-out interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material layer, or any combination thereof.

[0157] Since the content and structure involved in describing the method 1000 for manufacturing a semiconductor device above may be fully or partially applicable to the semiconductor device described herein, the related or similar content will not be repeated herein.

[0158] Although an exemplary structure and preparation method of a semiconductor device are described herein, it can be understood that one or more features may be omitted, substituted, or added from the preparation method of the semiconductor device. Additionally, the exemplified layers and their materials are merely exemplary.

[0159] Figure 28 FIG. 1 is a block diagram of a system 10 having a storage system 12 in an exemplary embodiment of the present application.

[0160] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having a storage system 12 therein). As Figure 28 shown, the system 10 may include a host 18 and a storage system 12, and the storage system 12 has one or more memories (such as may include a 3D memory 14) and a controller 16. The host 18 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the 3D memory 14.

[0161] The 3D memory 14 may include the semiconductor devices described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the 3D memory 14 and the host 18, and is configured to control the 3D memory 14. The controller 16 may manage the data stored in the 3D memory 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (such as the host 18) according to a specific communication protocol.

[0162] The above description is only a preferred embodiment of the present application and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A first semiconductor structure including a semiconductor layer and a plurality of spaced-apart active regions located within the semiconductor layer, the active regions including a plurality of doped regions and gate structures located between adjacent ones of the doped regions; And A second semiconductor structure bonded to the first semiconductor structure and including a peripheral circuit connected to the first semiconductor structure.

2. The device according to claim 1, wherein The plurality of doped regions include a first doped region, and second and third doped regions respectively located on opposite sides of the first doped region, wherein at least one of the gate structures is respectively provided between the first doped region and the second doped region, and between the first doped region and the third doped region.

3. The device according to claim 2, characterized in that, The active regions extend in a first direction, the gate structures extend in a second direction, and the semiconductor device further includes: Bit lines connected to the first doped region and extending in a third direction, wherein the angle between the first direction and the second direction is an acute angle, the angle between the first direction and the third direction is an acute angle, and the second direction intersects the third direction; and Capacitors connected to the second doped region and the third doped region.

4. The device according to claim 3, characterized in that, The semiconductor device further includes a gate lead-out structure, a bit line lead-out structure, and a capacitor lead-out structure, wherein the gate structure, the bit lines, and the capacitors are respectively connected to the peripheral circuit through the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure.

5. The device according to claim 4, characterized in that The peripheral circuit includes a plurality of control circuits, wherein the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure are respectively connected to the plurality of control circuits.

6. The device according to claim 4, characterized in that, The gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure respectively extend from a side of the capacitor away from the active region to the gate structure, the bit lines, and the capacitors.

7. The device according to claim 4, characterized in that, The active region includes opposite first and second ends, and the first end is closer to the doped region than the second end, wherein the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure respectively extend from a side closer to the second end than the first end to the gate structure, the bit lines, and the capacitors.

8. The device according to claim 4, characterized in that, The active region includes opposite first and second ends, and the first end is closer to the doped region than the second end, wherein the capacitor lead-out structure extends from a side of the capacitor away from the active region to the capacitor; and The gate lead-out structure and the bit line lead-out structure respectively extend from a side closer to the second end than the first end to the gate structure and the bit lines.

9. The device according to claim 7, wherein The second semiconductor structure further includes interconnect lines located on the peripheral circuit and interconnect vias connected to the interconnect lines and extending to the peripheral circuit.

10. The device according to any one of claims 4-9, characterized in that adjacent ones of the gate lead-out structures respectively extend to both sides of the gate structure along the second direction; and adjacent ones of the bit line lead-out structures respectively extend to both sides of the bit lines along the third direction.

11. The device according to any one of claims 1-9, characterized in that, The semiconductor device further includes: A pad lead-out structure that penetrates through the first semiconductor structure and extends to the second semiconductor structure.

12. A method of manufacturing a semiconductor device, characterized in that, The method includes: Forming a plurality of spaced-apart active regions in a semiconductor layer to form a first semiconductor structure, wherein the active regions include a plurality of doped regions and gate structures located between adjacent doped regions; and Bonding a second semiconductor structure to the first semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit connected to the first semiconductor structure.

13. The method according to claim 12, characterized in that, The active regions extend in a first direction. Forming a plurality of spaced-apart active regions in the semiconductor layer includes: Forming a plurality of isolation portions in the semiconductor layer, wherein the plurality of isolation portions divide a part of the semiconductor layer into a plurality of initial active regions extending in the first direction; Forming an initial doped region in each of the initial active regions; Forming at least two grooves penetrating through the initial doped region, wherein the at least two grooves divide the initial doped region into the plurality of doped regions; and Forming the gate structures in the grooves.

14. The method according to claim 13, wherein The plurality of doped regions include a first doped region, and second and third doped regions respectively located on opposite sides of the first doped region. The gate structures extend in a second direction. The method further includes: Forming a bit line connected to the first doped region and extending in a third direction, wherein the angle between the first direction and the second direction is an acute angle, the angle between the first direction and the third direction is an acute angle, and the second direction intersects the third direction; and Forming a capacitor connected to the second doped region and the third doped region.

15. The method according to claim 14, characterized in that, The method further includes: Forming a gate lead-out structure, a bit line lead-out structure, and a capacitor lead-out structure that respectively extend to the gate structure, the bit line, and the capacitor on a side of the capacitor away from the active region.

16. The method according to claim 14, wherein The method further includes: Forming a carrier wafer on one side of the first semiconductor structure; and Forming a gate lead-out structure, a bit line lead-out structure, and a capacitor lead-out structure that respectively extend to the gate structure, the bit line, and the capacitor on the other side of the first semiconductor structure.

17. The method according to claim 14, wherein The method further includes: Forming a capacitor lead-out structure connected to the capacitor on a side of the capacitor away from the active region; and Forming a gate lead-out structure and a bit line lead-out structure respectively connected to the gate structure and the bit line on a side of the active region away from the capacitor.

18. The method according to claim 16, wherein The method further includes: Forming interconnect lines on the peripheral circuit; and Forming an interconnect path connected to the interconnect lines and extending to the peripheral circuit.

19. The method according to claim 18, wherein The peripheral circuit includes a control circuit. The step of forming the second semiconductor structure further includes: Forming a plurality of the control circuits respectively connected to the gate lead-out structure, the bit line lead-out structure, and the capacitor lead-out structure.

20. The method according to any one of claims 12 - 19, characterized in that, The method further includes: Forming a pad lead-out structure that penetrates through the first semiconductor structure and extends to the second semiconductor structure.

21. A storage system, characterized in that, Includes: At least one 3D memory, each of the 3D memories including a semiconductor structure according to any one of claims 1 to 11; And A controller, coupled to the semiconductor structure, for controlling the three-dimensional memory to store data.

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