Silicon carbide semiconductor device and method of manufacturing the same

Abstract

The application provides a silicon carbide semiconductor device and a preparation method thereof. The device comprises a substrate, an epitaxial layer, a plurality of source region structures which are spaced apart on a side of the epitaxial layer away from the substrate, and a gate structure which is located between the source region structures and comprises a first semiconductor layer, a second semiconductor layer and a gate which are sequentially stacked along the thickness direction of the substrate, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on a side of the second semiconductor layer away from the substrate. The problem of low channel mobility of a silicon carbide device in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a silicon carbide semiconductor device and a preparation method thereof. BACKGROUND

[0002] There are some process and technical difficulties at present, which make the SiC device always not reach the theoretical performance. For example, the gate oxide channel mobility of the SiC device is low, which leads to a large proportion of channel resistance, and the switching rate of the device is difficult to improve. The main reason is that part of C atoms in the growth process of the gate oxide will remain in the SiC / SiO2 interface in the form of C clusters, which affects the SiC surface, thereby leading to poor quality of the gate oxide, low channel mobility and large channel resistance. At present, the gate oxide mobility is mainly improved by processes such as N element annealing and gate oxide front surface treatment, but the overall improvement of the gate oxide mobility is very limited, and too low mobility is still one of the problems faced by SiC devices.

[0003] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background section can include some information that is not known to those skilled in the art in the prior art in the country. SUMMARY

[0004] The main purpose of the present application is to provide a silicon carbide semiconductor device and a preparation method thereof, so as to solve the problem of low channel mobility of the silicon carbide device in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a silicon carbide semiconductor device is provided, comprising: a substrate; an epitaxial layer; a plurality of source region structures, which are spaced apart on a side of the epitaxial layer away from the substrate; a gate structure, which is located between the source region structures, the gate structure comprising a first semiconductor layer, a second semiconductor layer and a gate which are stacked in the thickness direction of the substrate in sequence, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on a side of the second semiconductor layer away from the substrate.

[0006] Optionally, the gate structure further comprises: a superlattice layer, which is located between the first semiconductor layer and the epitaxial layer.

[0007] Optionally, the material of the first semiconductor layer comprises gallium nitride and gallium arsenide, the material of the second semiconductor layer comprises aluminum gallium nitride and aluminum gallium arsenide, and the material of the gate comprises gallium nitride and gallium arsenide.

[0008] Optionally, the source region structure comprises: a first doped region and a second doped region stacked in sequence along the thickness direction of the substrate, wherein the first doped region is located on the side of the epitaxial layer away from the substrate, and the first doped region has a first doping type; the second doped region is located on the side of the first doped region away from the substrate, and the second doped region has a second doping type; the first semiconductor layer has a first surface on the side away from the substrate, and the first doped region has a second surface on the side away from the substrate, and the minimum distance from the first surface to the substrate is equal to the minimum distance from the second surface to the substrate.

[0009] Optionally, the semiconductor device further comprises a composite passivation layer located on the side of the source region structure and the gate structure away from the substrate, and the composite passivation layer comprises a metal oxide layer and a non-metal oxide layer stacked.

[0010] Optionally, the semiconductor device further comprises a first lead-out portion, a second lead-out portion and a third lead-out portion, wherein the first lead-out portion is in contact with the gate through the composite passivation layer, the second lead-out portion is in contact with the source region structure through the composite passivation layer, and the third lead-out portion is in contact with the substrate.

[0011] Optionally, the first lead-out portion has a first region in contact with the gate, and the second lead-out portion has a second region in contact with the source region structure, and the material of the first region and the second region comprises a titanium-containing metal compound.

[0012] According to another aspect of the present application, a preparation method of a silicon carbide semiconductor device is provided, for preparing the silicon carbide semiconductor device, the preparation method comprising: providing a substrate and forming an epitaxial layer on one side of the substrate; forming a plurality of spaced source region structures on one side of the epitaxial layer; forming a gate structure between the plurality of source region structures, the gate structure comprising a first semiconductor layer, a second semiconductor layer and a gate stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer being formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate being located on the side of the second semiconductor layer away from the substrate.

[0013] Optionally, the step of forming a plurality of spaced-apart source region structures on one side of the epitaxial layer includes: sequentially forming a first epitaxial layer, a second epitaxial layer and a third epitaxial layer on the substrate; performing a first injection in the third epitaxial layer to form a preliminary first doping region; performing a second injection in the preliminary first doping region to form a preliminary second doping region, the injection depth of the preliminary second doping region being less than the injection depth of the preliminary first doping region; etching the preliminary first doping region and the preliminary second doping region to form grooves in the preliminary first doping region and the preliminary second doping region, the remaining preliminary first doping region forming a first doping region, the remaining preliminary second doping region forming a second doping region, and the first doping region and the second doping region forming the source region structure.

[0014] Optionally, the step of forming the gate structure between the multiple source region structures includes: stacking a superlattice layer, the first semiconductor layer, the second semiconductor layer and the gate in sequence on the bottom of the groove, the gate protruding from the groove, and the superlattice layer, the first semiconductor layer, the second semiconductor layer and the gate forming the gate structure.

[0015] The technical solution of the present application provides a silicon carbide semiconductor device comprising a substrate, an epitaxial layer, multiple source region structures, and a gate structure, wherein the multiple source region structures are spaced apart and located on a side of the epitaxial layer facing away from the substrate; the gate structure is located between the source region structures, and the gate structure comprises a first semiconductor layer, a second semiconductor layer, and a gate layer stacked sequentially along the thickness direction of the substrate; a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer; and the gate is located on the side of the second semiconductor layer facing away from the substrate. The gate oxide structure of the silicon carbide device in the prior art is replaced by the first and second semiconductor layers formed between the epitaxial layer and the gate. A two-dimensional electron gas layer with extremely high electron mobility is formed at the contact interface between the first and second semiconductor layers. The electron mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of a conventional gate oxide structure. Therefore, by replacing the gate oxide structure with the two-dimensional electron gas layer in the silicon carbide device, electrons move faster in the channel under the same electric field strength, contributing to higher channel electron mobility for the silicon carbide semiconductor device, thereby solving the problem of low channel mobility in silicon carbide devices in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0017] Figure 1 1 shows a schematic cross-sectional structure diagram of a first silicon carbide semiconductor device proposed according to an embodiment of the present application;

[0018] Figure 2 1 shows a schematic cross-sectional structure diagram of a second silicon carbide semiconductor device proposed in an embodiment of the present application;

[0019] Figure 3 FIG4 shows a schematic cross-sectional structure diagram of a third silicon carbide semiconductor device proposed in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a process for preparing a silicon carbide semiconductor device according to an embodiment of the present application is shown;

[0021] Figure 5 Shown Figure 4 A schematic cross-sectional structure diagram of a substrate and a base body after forming an epitaxial layer is provided in a method for preparing a silicon carbide semiconductor device;

[0022] Figure 6 Shown in Figure 8 A schematic diagram of the cross-sectional structure of the substrate after the preliminary first doping region and the preliminary second doping region are formed in the epitaxial layer formed in the process;

[0023] Figure 7 Shows the Figure 6 A schematic diagram of the cross-sectional structure of the substrate after etching the prepared first doping region and the prepared second doping region formed in the process;

[0024] Figure 8 Shown in Figure 7 A schematic cross-sectional structure diagram of a superlattice layer, a first semiconductor layer, a second semiconductor layer and a gate rear base formed in the groove formed in the embodiment.

[0025] The above drawings include the following reference numerals:

[0026] 10. Substrate; 20. Epitaxial layer; 21. First epitaxial layer; 22. Second epitaxial layer; 23. Third epitaxial layer; 30. Source region structure; 31. First doped region; 32. Second doped region; 310. Preparatory first doped region; 320. Preparatory second doped region; 40. Gate structure; 41. First semiconductor layer; 42. Second semiconductor layer; 43. Gate; 44. Two-dimensional electron gas layer; 45. Superlattice layer; 50. Composite passivation layer; 60. First lead portion; 61. First region; 70. Second lead portion; 71. Second region; 80. Third lead portion. DETAILED DESCRIPTION

[0027] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0028] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0029] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being “on” another element, the element may be directly on the other element or intervening elements may be present. Furthermore, in the specification and claims, when it is described that an element is “connected to” another element, the element may be “directly connected to” the other element or “connected to” the other element through a third element.

[0031] As described in the background, the gate oxide channel mobility of existing SiC devices is relatively low, resulting in a large channel resistance ratio and difficulty in increasing the switching speed of the device. This is primarily due to the fact that during the gate oxide growth process, some carbon atoms remain at the SiC / SiO2 interface in the form of carbon clusters, affecting the SiC surface, resulting in poor gate oxide quality, low channel mobility, and increased channel resistance. Currently, processes such as nitrogen-containing annealing and pre-gate oxide surface treatment are primarily used to improve gate oxide mobility, but the overall improvement in gate oxide mobility is very limited. Low mobility remains a major challenge for SiC devices. To address the low channel mobility problem of existing silicon carbide devices, embodiments of the present application provide a silicon carbide semiconductor device and a method for preparing the same.

[0032] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0033] According to the embodiment of the present application, Figures 1 to 3As shown, a silicon carbide semiconductor device is provided, including: a substrate 10; an epitaxial layer 20; a plurality of source region structures 30, which are spaced apart and located on the side of the epitaxial layer 20 facing away from the substrate 10; a gate structure 40, which is located between the source region structures 30, and the gate structure 40 includes a first semiconductor layer 41, a second semiconductor layer 42 and a gate 43 stacked in sequence along the thickness direction of the substrate 10, a two-dimensional electron gas layer 44 is formed at the interface between the first semiconductor layer 41 and the second semiconductor layer 42, and the gate 43 is located on the side of the second semiconductor layer 42 facing away from the substrate 10.

[0034] The silicon carbide semiconductor device comprises a substrate, an epitaxial layer, multiple source region structures, and a gate structure, wherein the multiple source region structures are spaced apart and located on the side of the epitaxial layer facing away from the substrate; the gate structure is located between the source region structures, and the gate structure comprises a first semiconductor layer, a second semiconductor layer, and a gate layer stacked sequentially along the thickness direction of the substrate; a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer; and the gate is located on the side of the second semiconductor layer facing away from the substrate. The gate oxide structure of the silicon carbide device in the prior art is replaced by the first and second semiconductor layers formed between the epitaxial layer and the gate. A two-dimensional electron gas layer with extremely high electron mobility is formed at the contact interface between the first and second semiconductor layers. The mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of a conventional gate oxide structure. This application is equivalent to contributing high mobility to the silicon carbide device by replacing the gate oxide structure with a two-dimensional electron gas layer, thereby increasing the switching speed of the device and enhancing the high-frequency performance of the device. This solves the problem of low channel mobility in silicon carbide devices in the prior art.

[0035] In the above-described embodiment, both the substrate and epitaxial layer are made of silicon carbide, which imparts high thermal conductivity and high breakdown field strength to the device, making it suitable for manufacturing high-performance devices capable of operating in high-temperature, high-pressure environments. The substrate thickness can be 300-350 μm. During the subsequent process of fabricating the drain lead, the substrate is thinned to a thickness of 150-200 μm, and the epitaxial layer thickness is 5-16 μm. This epitaxial layer thickness can reduce reverse leakage, relatively protect the area below the gate from premature breakdown, and enhance the device's forward current capacity.

[0036] like Figure 1 As shown, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22. The first epitaxial layer 21 and the second epitaxial layer 22 are sequentially stacked on the substrate 10 along the thickness direction of the substrate 10, and the doping concentration of the second epitaxial layer 22 is lower than the doping concentration of the first epitaxial layer 21. The use of a double epitaxial layer enables the device to carry a higher current (increased by at least 30%) during forward conduction, while also reducing leakage current by more than 50% during reverse bias, significantly improving device performance and reliability and extending device life.

[0037] Specifically, the thickness of the first epitaxial layer can be 5-15 μm, and the doping concentration can be 9E15-1.5E16 cm -3 The thickness of the second epitaxial layer can be 200~400nm, and the doping concentration is 1E12~1E13cm -3 This can improve the device's withstand voltage. There are no specific restrictions on the doping concentration and thickness of the first and second epitaxial layers. A 5μm thick first epitaxial layer has a withstand voltage of approximately 600V, while a 15μm thick second epitaxial layer has a withstand voltage of approximately 1700V.

[0038] In some optional embodiments, the first semiconductor layer is made of gallium nitride (GaN) and gallium arsenide (GaAs), the second semiconductor layer is made of aluminum gallium nitride (AlGaN) and aluminum gallium arsenide (AlGaAs), and the gate is made of gallium nitride and gallium arsenide. When the first semiconductor layer is GaN, the second semiconductor layer is made of AlGaN, and the gate is made of GaN with p-type doping. When the first semiconductor layer is made of GaAs, the second semiconductor layer is made of AlGaAs, and the gate is made of GaAs with p-type doping. Preferably, the first semiconductor layer is made of GaN. The lattice constants of GaN and SiC are very close (the lattice constant difference is approximately 3%, while the lattice constant difference of epitaxial GaN on Si is 70%), which can reduce defects in the first semiconductor layer on SiC. The thickness of the first semiconductor layer can be 180-200 nm, the thickness of the second semiconductor layer can be 15-25 nm, and the thickness of the gate can be 80-100 nm. Setting the materials and thicknesses of the first and second semiconductor layers within the aforementioned ranges facilitates the formation of a high-mobility two-dimensional electron gas layer, thereby significantly improving the switching speed of the device, reducing the channel resistance, and enhancing the high-frequency performance of the device. This also reduces the gate capacitance and maintains good electrical performance of the gate. The two-dimensional electron gas layer is formed due to the piezoelectric polarization and spontaneous polarization effects caused by the lattice mismatch between AlGaN and GaN, which generate an internal electric field at the interface and thus form the two-dimensional electron gas layer.

[0039] Among them, the gate material is P-GaN, which can form an enhancement-mode device. The threshold voltage can be adjusted by the width of the gate structure and can be stably controlled at 1.8~2.5V.

[0040] In some optional embodiments, such as Figure 2 As shown, the gate structure further includes a superlattice layer 45, which is located between the first semiconductor layer 41 and the epitaxial layer 20. The superlattice layer 45 can suppress defects of the device caused by lattice mismatch.

[0041] The above-mentioned superlattice layer can be formed by alternating AlN material layers and GaN material layers, or by alternating AlGaN material layers and GaN material layers, or by alternating InGaN material layers and GaN material layers, or by alternating AlInN material layers and GaN material layers. Among them, it is preferred that the superlattice layer be formed by alternating AlN material layers and GaN material layers, as AlN has better barrier and passivation effects and can better limit the upward growth of defects. The thickness of the AlN, AlGaN, InGaN and AlInN material layers can be 2nm, the thickness of the GaN material layer can be 1~2nm, and the layer period is 25~30 layers, which can further optimize electron mobility, reduce defects, and improve device stability.

[0042] In some optional embodiments, such as Figure 3 As shown, the source region structure 30 includes: a first doped region 31 and a second doped region 32 stacked sequentially along the thickness direction of the substrate 10. The first doped region 31 is located on the side of the epitaxial layer 20 facing away from the substrate 10 and has a first doping type; the second doped region 32 is located on the side of the first doped region 31 facing away from the substrate 10 and has a second doping type. The first semiconductor layer 41 has a first surface on the side facing away from the substrate 10, and the first doped region 31 has a second surface on the side facing away from the substrate 10. The minimum distance from the first surface to the substrate 10 is equal to the minimum distance from the second surface to the substrate 10. The first doped region 31 ensures low contact resistance with the source lead, ensuring good ohmic contact, allowing smoother current flow when the device is in the on state, improving the device's conductivity and efficiency. The combination of the first doped region 31 and the second doped region 32 can increase current density, improve ohmic contact, and reduce contact resistance in the source region.

[0043] Specifically, the doping type of the first doping region can be P type, the doping ion can be Al element, and the doping concentration can be 1E13~E15cm -3 The doping depth can be 360~420nm; the doping type of the second doping region can be N type, the doping ion can be N element, and the doping concentration can be 1E13~5E14cm -3 The doping depth can be 100-150nm. This can further improve the contact resistance between the device and the source lead to ensure good ohmic contact, making the current transmission smoother when the device is in the on state, improving the device's conductivity and efficiency.

[0044] In some optional embodiments, such as Figures 1 to 3As shown, the semiconductor device further includes a composite passivation layer 50, which is located on the side of the source structure 30 and gate structure 40 facing away from the substrate 10. The composite passivation layer 50 includes a stacked metal oxide layer and a non-metal oxide layer. The composite passivation layer 50 can reduce surface states and gate leakage, while also having good mechanical properties and preventing corrosion and diffusion of metal materials.

[0045] The metal oxide layer can be any of Al2O3, HfO2, and ZrO2, with a thickness of 2-3 nm, preferably Al2O3. Al2O3 is cheaper, reduces costs, and allows for better control during the fabrication process. The non-metallic oxide layer can be any of silicon dioxide (PEOX) and tetraethoxysilane (PETEOS), with a thickness of 2000-3000 Å. Using the aforementioned materials and parameters for the composite passivation layer can significantly reduce the device's surface state density and gate leakage, resulting in a minimum 40% reduction in device leakage in the off state. This improves device stability and extends device life. It also provides additional mechanical protection, enhancing device durability.

[0046] In some optional embodiments, such as Figures 1 to 3 As shown, the semiconductor device further includes a first lead portion 60, a second lead portion 70, and a third lead portion 80, wherein the first lead portion 60 penetrates the composite passivation layer 50 and contacts the gate 43, the second lead portion 70 penetrates the composite passivation layer 50 and contacts the source region structure 30, and the third lead portion 80 contacts the substrate 10. By applying a voltage to the first lead portion 60, the on and off states of the device can be controlled. The second lead portion 70 forms an ohmic contact with the second doped region 32, which helps to reduce the contact resistance between the second lead portion 70 and the source region structure 30, ensuring efficient current transmission and reducing energy loss. The third lead portion 80 collects the charge injected from the second lead portion 70 and transmitted through the channel, completing the process of current flowing through the device. The thickness of the first, second, and third lead portions can be 50-100 nm. Within the above range, low contact resistance of the device can be better achieved.

[0047] In some optional embodiments, such as Figures 1 to 3As shown, the first lead portion 60 has a first region 61 in contact with the gate 43, and the second lead portion 70 has a second region 71 in contact with the source structure 30. The materials of the first region 61 and the second region 71 include a titanium-containing metal compound. The titanium-containing compound includes any one of TiAlN, TiC, and TiCN. TiN is preferably used. TiN is easier to control during the device preparation process and has a lower resistivity, that is, the contact resistance is minimized. The first lead portion 60 and the second lead portion 70 of the TiN material can form good contact characteristics with the semiconductor layers of the GaN material and the SiC material, thereby achieving low-impedance electrode connection. At the same time, TiN has high corrosion resistance and can maintain the integrity of the first lead portion 60 and the second lead portion 70 after high-temperature annealing. The first lead portion 60 of the TiN material can better form a Schottky contact with the gate 43 of the P-GaN material, reducing gate reverse leakage. The Ti in the second lead portion 70 of the TiN material forms a good ohmic contact with the second doped region of the SiC material.

[0048] Specifically, the working principle of the silicon carbide semiconductor device in this application is as follows:

[0049] When the gate voltage V g When ≤0V, the electric field generated by the negative gate voltage will repel the electrons in the second semiconductor layer, forming a depletion layer, which will reduce the density of the two-dimensional electron gas. Ultimately, there is no two-dimensional electron gas layer in the channel. The device is in the off state at this time. The reverse second epitaxial layer can reduce the device leakage in the off state.

[0050] When the gate voltage is 0V <Vg<V th When the gate voltage is positive, a two-dimensional electron gas is gradually formed between the second semiconductor layer and the first semiconductor layer, but the path is not fully formed, the channel resistance is large, the device is in the subthreshold stage, and the source-drain current is small. th is the voltage threshold of the device in the on state;

[0051] When the gate voltage V g =V th At this time, the two-dimensional electron gas layer of the channel is fully formed, the channel is fully opened, and electrons flow from the source through the two-dimensional electron gas layer, and then through the first semiconductor layer, the epitaxial layer, the substrate to the drain, forming a conductive circuit.

[0052] According to the embodiment of the present application, Figure 4 As shown, a method for preparing a silicon carbide semiconductor device is provided, and the method for preparing the silicon carbide semiconductor device includes:

[0053] Step S1, providing a substrate and forming an epitaxial layer on one side of the substrate;

[0054] Specifically, both the substrate and epitaxial layer are made of silicon carbide, which gives the device high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance devices capable of operating in high-temperature, high-pressure environments. The substrate thickness can be 300-350μm. During the subsequent drain lead fabrication process, the substrate is thinned to a thickness of 150-200μm, and the epitaxial layer thickness is 5-16μm.

[0055] Step S2, forming a plurality of spaced-apart source region structures on one side of the epitaxial layer;

[0056] Specifically, the source region structure can form a good ohmic contact with the lead portion, thereby ensuring the stability and performance of the device and avoiding signal transmission problems caused by poor contact.

[0057] In step S3, a gate structure is formed between the multiple source region structures. The gate structure includes a first semiconductor layer, a second semiconductor layer, and a gate layer stacked in sequence along the thickness direction of the substrate. A two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer. The gate is located on the side of the second semiconductor layer facing away from the substrate.

[0058] Specifically, the material of the first semiconductor layer may include gallium nitride and gallium arsenide, the material of the second semiconductor layer may include aluminum gallium nitride and aluminum gallium arsenide, and the material of the gate may include gallium nitride and gallium arsenide. The thickness of the first semiconductor layer may be 180-200 nm, the thickness of the second semiconductor layer may be 15-25 nm, and the thickness of the gate may be 80-100 nm. Setting the materials and thicknesses of the first and second semiconductor layers within the above ranges facilitates the formation of a high-mobility two-dimensional electron gas layer, thereby significantly improving the switching speed of the device and reducing the channel resistance, enhancing the high-frequency performance of the device, while also reducing the gate capacitance and maintaining good electrical performance of the gate.

[0059] The silicon carbide semiconductor device prepared by the above-mentioned method for preparing a silicon carbide semiconductor device includes a substrate, an epitaxial layer, multiple source region structures, and a gate structure, wherein the multiple source region structures are spaced apart and located on the side of the epitaxial layer facing away from the substrate; the gate structure is located between the source region structures, and the gate structure includes a first semiconductor layer, a second semiconductor layer, and a gate layer stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side of the second semiconductor layer facing away from the substrate. By forming the first semiconductor layer and the second semiconductor layer between the epitaxial layer and the gate, the gate oxide structure of the silicon carbide device in the prior art is replaced, and a two-dimensional electron gas layer with extremely high electron mobility is formed at the contact interface between the first semiconductor layer and the second semiconductor layer. The mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of the conventional gate oxide structure. This application is equivalent to contributing high mobility to the silicon carbide device by replacing the gate oxide structure with a two-dimensional electron gas layer, thereby solving the problem of low channel mobility of silicon carbide devices in the prior art.

[0060] In some optional embodiments, such as Figures 5 to 7 As shown, a plurality of spaced-apart source region structures 30 are formed on one side of the epitaxial layer, including: forming a first epitaxial layer 21, a second epitaxial layer 22 and a third epitaxial layer 23 in sequence on the substrate 10; performing a first injection into the third epitaxial layer 23 to form a preliminary first doping region 310; performing a second injection into the preliminary first doping region 310 to form a preliminary second doping region 320, wherein the injection depth of the preliminary second doping region 320 is less than the injection depth of the preliminary first doping region 310; etching the preliminary first doping region 310 and the preliminary second doping region 320 to form grooves in the preliminary first doping region 310 and the preliminary second doping region 320, the remaining preliminary first doping region 310 forms the first doping region 31, the remaining preliminary second doping region 320 forms the second doping region 32, and the first doping region 31 and the second doping region 32 form the source region structure 30.

[0061] For example, Figure 5 As shown, a first epitaxial layer 21 of SiC material is grown on the SiC substrate 10, with a thickness of 5-15 μm, and a second epitaxial layer 22 of low-doped SiC material is grown on the first epitaxial layer 21, with a doping concentration of 1E12-1E13 cm -3 , with a thickness of 200~400nm, which can reduce reverse leakage, relatively protect the position below the gate to prevent premature breakdown, and also enhance the current capacity of the device during forward conduction. Finally, a third epitaxial layer 23 of SiC material is grown, with a thickness of 360~420nm and a doping concentration of 9E15~1.5E16cm -3 .like Figure 6As shown, the Al element is implanted into the third epitaxial layer by ion implantation to form a preliminary first doped region 310. In order to ensure uniformity of implantation, multiple implantations (e.g., 5-6 times) can be used. The ion implantation energy is 50-300 keV, and the dosage is 1E13-1E15 cm -3 The implantation depth is controlled to the surface of the second epitaxial layer 22. Then, N element is implanted by ion implantation to form an N-type. The implantation is performed 2-4 times, the energy is 50-100 keV, and the dosage is 1E13-5E14 cm -3 The implantation depth is controlled by the implantation energy, and the implantation depth can be 100-150 nm. The main purpose is to align the lower surface of the second doped region with the two-dimensional electron gas layer plane region in the subsequent process. After implantation, annealing activation is performed at a temperature of 1650-1700 °C. Then, a sacrificial oxygen layer of about 10 nm is formed on the preliminary first doped region 310, and the sacrificial oxygen layer is etched away by DHF (hydrofluoric acid diluent). The purpose is to remove the SiC film layer on the surface damaged by implantation. As shown in Figure 7 The preliminary first doped region 310 and the preliminary second doped region 320 are subjected to a photolithography process. A photoresist (positive resist) with a thickness of 12000-15000 Å is coated, and a specified pattern is exposed and developed to form a mask plate. The exposure time is 10-60 s. Then, an inductively coupled plasma (ICP) etching machine is used to etch the preliminary first doped region 310 and the preliminary second doped region 320 using fluorine-based gas (SF6 / O2). The power is 500-1200 W, the pressure is 5-10 mtorr, and the etching rate is 200-500 nm / min. A groove is formed in the preliminary first doped region 310 and the preliminary second doped region 320. The depth is generally greater than 3000 Å, and the bottom of the groove is the upper surface of the second epitaxial layer 22.

[0062] The purpose of the sacrificial oxygen layer is to cause certain lattice damage to the surface SiC material during ion implantation and high-temperature activation. The surface SiC is oxidized to SiO2 by oxidation treatment, and then etched away. The newly exposed SiC surface is relatively smooth, which makes the performance of the final device better.

[0063] In some optional embodiments, as shown in Figure 8 A gate structure 40 is formed between the plurality of source region structures 30. The gate structure 40 includes a superlattice layer 45, a first semiconductor layer 41, a second semiconductor layer 42, and a gate 43 which are sequentially stacked on the bottom of the groove. The gate 43 protrudes from the groove, and the superlattice layer 45, the first semiconductor layer 41, the second semiconductor layer 42, and the gate 43 form the gate structure 40.

[0064] For example, as shown in Figure 8As shown, a thin superlattice layer 45 with a thickness of 80-100 nm is grown to suppress defects caused by lattice mismatch. Next, a first semiconductor layer 41 made of GaN and a second semiconductor layer 42 made of AlGaN are epitaxially grown. The first semiconductor layer 41 has a thickness of 180-200 nm, and the second semiconductor layer 42 has a thickness of 15-25 nm. Finally, a gate electrode 43 made of P-GaN is epitaxially grown with a thickness of 80-100 nm. The two-dimensional electron gas layer is formed by the internal electric field generated at the interface due to the piezoelectric polarization and spontaneous polarization effects caused by the lattice mismatch between the first semiconductor layer 41 and the second semiconductor layer 42. The first semiconductor layer 41 is grown using MOCVD epitaxial equipment. The lattice constant of the first semiconductor layer 41 is very close to that of the SiC material (the lattice constant difference is approximately 3%, while the lattice constant difference of GaN epitaxially grown on Si is 70%). Consequently, the defects of the first semiconductor layer 41 epitaxially grown on SiC are relatively low.

[0065] After epitaxial growth of the superlattice layer 45, the first semiconductor layer 41, the second semiconductor layer 42, and the gate 43 is completed, photolithography can be performed using the grooves as overlay marks. The photoresist used is 12,000 to 15,000 Å thick. After exposure and development, a specified pattern is formed. Etching is then performed using an inductively coupled plasma (ICP) process to remove the film layer located above the source structure 30. The ICP process can use a Cl2 / BCl3 mixed gas, with RF power controlled between 60 and 100 W and pressure between 5 and 10 mTorr. This results in a slower etching rate and minimal damage to the superlattice layer 45, the first semiconductor layer 41, the second semiconductor layer 42, and the gate. Furthermore, under these conditions, the SiC film layer is etched at a rate of approximately 10 nm / min, preventing excessive etching of the source structure 30 after etching the first semiconductor layer 41. Etching can be stopped promptly on the surface of the source structure 30. After etching, the photoresist is removed and cleaning is performed.

[0066] After forming the gate structure, the fabrication method also includes using atomic layer deposition (ALD) to grow a 2-3nm thick Al2O3 layer on the source and gate structures to reduce surface damage caused by passivation and reduce interface states. A 2000-3000Å ​​thick SiO2 layer (PEOX) is then grown using chemical vapor deposition (CVD) as a second passivation layer. Photolithography is then performed using a positive photoresist with a thickness of 14,000-16,000Å. The mask is exposed and developed to create a desired pattern, with an exposure time of 10-60 seconds. An Applied Materials 5200 etcher is used to remove the PEOX and Al2O3 layers. Process parameters include a CF4 / BCl3 / Ar gas mixture, a power of 400-600W, a pressure of 5-10mTorr, and an etch rate of 150-400nm / min. Positions for the first and second lead-outs are then prepared, and the resist is then stripped and cleaned.

[0067] After etching the composite passivation layer, a TiN layer is grown using physical vapor deposition (PVD) to serve as the ohmic contact layer for the source structure 30 and the Schottky contact layer for the gate structure 40. The layer is then subjected to high-temperature rapid annealing at 600-700°C for 2-5 minutes. This ensures that the TiN layer forms a better Schottky contact with the gate 43, reducing gate reverse leakage. The Ti in the TiN layer also forms an ohmic contact with the second doped layer of the source structure 30. An AlCu / TiN layer is then grown on the TiN layer. The AlCu layer has a thickness of 800-1000 nm, and the TiN layer has a thickness of 40-60 nm. These layers are then photolithographically or etched to define the topography of the first lead 60 and the second lead 70. The photolithography process uses a positive photoresist with a thickness of 30,000-35,000 Å and an exposure time of 20-80 seconds. The metal was etched using a North China Huachuang 508 etcher with a Cl2 / BCl3 / Ar mixed gas, a power of 400~1000W, a pressure of 5~15mTorr, and an etching rate of 200~600nm / min.

[0068] The substrate is then thinned to 150~200μm, and 80~100nm of metal Ni is grown on the back of the substrate as an ohmic contact layer. Laser annealing is performed to activate it to form an ohmic contact on the back of the device. After that, C is removed, and finally a metal layer Ti / Ni / Ag is grown, where the thickness of Ti is 60~100nm, the thickness of Ni is 100~300nm, and the thickness of Ag is 600~1000nm, to form the third lead-out portion 80.

[0069] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the method for preparing the silicon carbide semiconductor device of the present application will be described in detail below with reference to specific embodiments.

[0070] This embodiment relates to a specific method for preparing a silicon carbide semiconductor device, comprising the following steps:

[0071] Step S1: providing a substrate, and sequentially forming a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer on one side of the substrate;

[0072] Step S2: performing a first ion implantation in the third epitaxial layer to form a preliminary first doping region, and performing a second ion implantation in the first doping region to form a preliminary second doping region;

[0073] Step S3: etching the prepared first doping region and the prepared second doping region to form grooves therein, thereby forming the first doping region and the second doping region;

[0074] Step S4: forming a superlattice layer, a first semiconductor layer, a second semiconductor layer and a gate in sequence in the groove, with the gate protruding from the groove;

[0075] Step S5: covering the gate and source region structures with a composite passivation layer;

[0076] Step S6: forming a first lead portion and a second lead portion on the composite passivation layer, wherein the first lead portion penetrates the composite passivation layer and contacts the gate, and the second lead portion penetrates the composite passivation layer and contacts the first doped region;

[0077] Step S7: thinning the substrate and forming a third lead-out portion on a side of the substrate facing away from the first epitaxial layer.

[0078] The silicon carbide semiconductor device and preparation method described above can achieve the following beneficial effects:

[0079] 1) By forming a first semiconductor layer and a second semiconductor layer between the epitaxial layer and the gate, the gate oxide structure of the prior art silicon carbide device is replaced. A two-dimensional electron gas layer with extremely high electron mobility is formed at the interface between the first and second semiconductor layers. The mobility of the two-dimensional electron gas layer is 20 to 40 times higher than that of a conventional gate oxide structure. This application effectively contributes high mobility to the silicon carbide device by replacing the gate oxide structure with a two-dimensional electron gas layer, thus solving the problem of low channel mobility in prior art silicon carbide devices.

[0080] 2) The channel mobility of silicon carbide semiconductor devices is improved, which also increases the switching speed of the device and enhances the high-frequency performance of the device.

[0081] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A silicon carbide semiconductor device, characterized in that: include: substrate; an epitaxial layer, wherein the material of the epitaxial layer is silicon carbide; A plurality of source region structures are spaced apart and located on a side of the epitaxial layer facing away from the substrate, wherein the steps of forming the source region structures include: performing a first implantation in the epitaxial layer to form a preliminary first doping region; performing a second implantation in the preliminary first doping region to form a preliminary second doping region, wherein the implantation depth of the preliminary second doping region is less than the implantation depth of the preliminary first doping region; etching the preliminary first doping region and the preliminary second doping region to form grooves in the preliminary first doping region and the preliminary second doping region, wherein the remaining preliminary first doping region forms a first doping region, and the remaining preliminary second doping region forms a second doping region, and the first doping region and the second doping region form the source region structure; A gate structure is located in the groove, the gate structure including a first semiconductor layer, a second semiconductor layer and a gate stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side of the second semiconductor layer facing away from the substrate.

2. The silicon carbide semiconductor device according to claim 1, wherein The gate structure further includes a superlattice layer located between the first semiconductor layer and the epitaxial layer.

3. The silicon carbide semiconductor device according to claim 1, wherein The material of the first semiconductor layer includes gallium nitride or gallium arsenide, the material of the second semiconductor layer includes aluminum gallium nitride or aluminum gallium arsenide, and the material of the gate includes gallium nitride or gallium arsenide.

4. The silicon carbide semiconductor device according to claim 1, wherein The source region structure includes: a first doping region and a second doping region sequentially stacked along the thickness direction of the substrate, wherein: The first doping region is located on a side of the epitaxial layer away from the substrate, and the first doping region has a first doping type; the second doping region is located on a side of the first doping region away from the substrate, and the second doping region has a second doping type; The first semiconductor layer has a first surface on a side facing away from the substrate, the first doped region has a second surface on a side facing away from the substrate, and the minimum distance from the first surface to the substrate is equal to the minimum distance from the second surface to the substrate.

5. The silicon carbide semiconductor device according to claim 1, wherein The semiconductor device further includes a composite passivation layer, which is located on a side of the source region structure and the gate structure facing away from the substrate. The composite passivation layer includes a stacked metal oxide layer and a non-metal oxide layer.

6. The silicon carbide semiconductor device according to claim 5, wherein The semiconductor device further includes a first lead portion, a second lead portion and a third lead portion, wherein: The first lead portion penetrates the composite passivation layer and contacts the gate, the second lead portion penetrates the composite passivation layer and contacts the source region structure, and the third lead portion contacts the substrate.

7. The silicon carbide semiconductor device according to claim 6, wherein: The first lead portion includes a first region in contact with the gate, and the second lead portion includes a second region in contact with the source region structure. Materials of the first region and the second region include a titanium-containing metal compound.

8. A method for preparing a silicon carbide semiconductor device, characterized in that: For preparing a silicon carbide semiconductor device according to any one of claims 1 to 7, the preparation method comprising: providing a substrate, and forming an epitaxial layer on one side of the substrate; A plurality of spaced-apart source region structures are formed on one side of the epitaxial layer, wherein the epitaxial layer is made of silicon carbide. The method for forming the source region structure comprises: forming the epitaxial layer on the substrate; performing a first implantation in the epitaxial layer to form a preliminary first doping region; performing a second implantation in the preliminary first doping region to form a preliminary second doping region, wherein the implantation depth of the preliminary second doping region is less than the implantation depth of the preliminary first doping region; etching the preliminary first doping region and the preliminary second doping region to form grooves in the preliminary first doping region and the preliminary second doping region, wherein the remaining preliminary first doping region forms a first doping region, and the remaining preliminary second doping region forms a second doping region, and the first doping region and the second doping region form the source region structure; A gate structure is formed in the groove, the gate structure including a first semiconductor layer, a second semiconductor layer and a gate stacked in sequence along the thickness direction of the substrate, a two-dimensional electron gas layer is formed at the interface between the first semiconductor layer and the second semiconductor layer, and the gate is located on the side of the second semiconductor layer facing away from the substrate.

9. The preparation method according to claim 8, characterized in that The step of forming the gate structure between the plurality of source region structures comprises: A superlattice layer, the first semiconductor layer, the second semiconductor layer and the gate are sequentially stacked on the bottom of the groove, the gate protrudes from the groove, and the superlattice layer, the first semiconductor layer, the second semiconductor layer and the gate form the gate structure.

Images