Miniature light emitting diode chip

Abstract

The invention provides a micro light-emitting diode chip, which is provided with a micro mesa array area and comprises a plurality of micro mesas, each micro mesa comprises a first type semiconductor layer, a light-emitting layer and a second type semiconductor layer which are sequentially stacked from bottom to top; the first type is different from the second type; the first metal layer is located at the bottom of the micro mesa; the second metal layer is located at the bottom of the first metal layer; the third metal layer is located at the bottom of the second metal layer; the bottom dielectric layer is located at the bottom of the whole micro-mesa array area and the bottom of the third metal layer; and the metal contact hole is located in the bottom dielectric layer, located at the bottom of the third metal layer and in contact connection with the bottom of the third metal layer.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diodes, and more particularly, to a micro light-emitting diode chip. Background Art

[0002] Micro Light Emitting Diode technology is a high pixel density LED flat panel display technology that uses micron-scale LEDs as pixel elements and assembles them on a control backplane in a micron-scale period. The core structure of a micro light-emitting diode is a PN junction diode, which is composed of a direct bandgap semiconductor material. When a forward bias is applied to the micro light-emitting diode between the upper and lower electrodes to cause current to flow, electrons and holes recombine in the active region, and at the same time, single-color light photons are emitted.

[0003] Compared with traditional LEDs, micro light-emitting diodes have better strain relaxation, better light extraction efficiency, uniform current diffusion, and higher output performance. Micro LEDs also have advantages such as improved thermal effects, faster response speed, a wider operating temperature range, higher resolution, a wider color gamut, higher contrast, lower power consumption, and higher current density. Micro light-emitting diodes are regarded as the next-generation display technology and are receiving increasing attention.

[0004] The light emitted by a micro light-emitting diode is generated by spontaneous emission and is therefore non-directional, which results in a large divergence angle. The large divergence angle causes various problems in micro LED displays. Due to the large divergence angle, only a small portion of the light emitted by a micro LED pixel can be utilized. This will significantly reduce the efficiency and brightness of a micro LED display. Traditional solutions to reduce the large divergence angle may not be able to effectively handle all the light emitted by a micro LED, and only the central portion of the light emitted by the micro LED can be effectively utilized, while the light emitted at a more oblique angle is not effectively utilized.

[0005] In summary, there is a need to provide a micro light-emitting diode structure that can improve the light efficiency and can at least partially solve the problems existing in the prior art. Summary of the Invention

[0006] In view of some or all of the problems in the prior art, the object of the present invention is to provide a micro light-emitting diode chip having a micro mesa array region including a plurality of micro mesas, characterized in that each micro mesa includes:

[0007] A first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked in sequence from bottom to top; the first type and the second type are different;

[0008] A first metal layer located at the bottom of the micro mesa;

[0009] A second metal layer located at the bottom of the first metal layer;

[0010] A third metal layer, located at the bottom of the second metal layer;

[0011] A bottom dielectric layer, located at the bottom of the entire micro-tabletop array region and at the bottom of the third metal layer;

[0012] A metal contact hole, located in the bottom dielectric layer and at the bottom of the third metal layer, and in contact connection with the bottom of the third metal layer.

[0013] In some embodiments, the second metal layer further has an upward protrusion, and the protrusion covers the side wall of the first metal layer.

[0014] In some embodiments, the top height of the protrusion is the same as the top height of the first metal layer.

[0015] In some embodiments, the width of the first metal layer is not less than the top width of the second type semiconductor layer.

[0016] In some embodiments, the material of the first metal layer is an active metal.

[0017] In some embodiments, the material of the first metal layer is one of Ag, Al, Au, Cu, and Pt.

[0018] In some embodiments, the second metal layer includes one layer; or multiple sub-metal layers.

[0019] In some embodiments, the material of the single-layer second metal layer is a Ti-containing metal alloy material; among the multiple sub-metal layers, one of the sub-metal layers includes a Ti metal layer.

[0020] In some embodiments, the Ti-containing metal alloy material is TiN or TiW; the multiple sub-metal layers include a Ti metal layer and a Pt metal layer, or a Ti metal layer and a Pd metal layer, or a Ti metal layer and an Au metal layer.

[0021] In some embodiments, the material of the third metal layer is one or more of Cr, Al, Ti, Ni, Pt, Au, and Sn.

[0022] In some embodiments, the side wall of the micro-tabletop is inclined.

[0023] In some embodiments, the inclination angle range is: 60° to 85°

[0024] In some embodiments, the side wall of the first metal layer is inclined, the side wall of the second metal layer is inclined, and the side wall of the third metal layer is inclined; in the cross-sectional structure of the first metal layer, the second metal layer, and the third metal layer, the side walls of the three are inclined in the same direction; the side wall of the micro-tabletop is inclined in the same direction as the first metal layer.

[0025] In some embodiments, the sidewall inclination angle of the first metal layer is in the range of 60°-90°; the sidewall inclination angle of the second metal layer is in the range of 60°-90°; the sidewall inclination angle of the third metal layer is in the range of 60°-90°.

[0026] In some embodiments, there is also a bottom conductive layer between the bottom of the first type semiconductor layer and the first metal layer.

[0027] In some embodiments, the lateral dimensions of the bottom conductive layer and the second metal layer are greater than the lateral dimension of the first metal layer. The top surface of the first metal layer contacts the bottom surface of the bottom conductive layer, the bottom surface of the first metal layer contacts the top surface of the second metal layer, and the sidewalls of the bottom conductive layer and / or the second metal layer cover the sidewalls of the first metal layer.

[0028] In some embodiments, the sidewall dielectric layer is located in the sidewalls of the micro mesa, the sidewalls of the first metal layer, the second metal layer, the third metal layer, and the area between adjacent micro mesas; or, located in the sidewalls of the micro mesa, the sidewalls of the first metal layer, the second metal layer, the third metal layer; or, located in the sidewalls of the micro mesa, the sidewalls of the second metal layer, the third metal layer, and the area between adjacent micro mesas; or, located in the sidewalls of the micro mesa, the sidewalls of the second metal layer, the third metal layer; and,

[0029] The top conductive layer continuously covers the top surface of the micro mesa, the surface of the sidewall dielectric layer, and the area between adjacent micro mesas.

[0030] In some embodiments, the sidewall dielectric layer has an opening at the top of the micro mesa structure; the opening exposes part or all of the top of the micro mesa; the sidewall dielectric layer covers the entire sidewall of the micro mesa structure, covers the entire sidewalls of the second metal layer and the third metal layer; or covers the entire sidewall of the micro mesa structure, covers the entire sidewalls of the first metal layer, the second metal layer, and the third metal layer.

[0031] In some embodiments, the light-emitting layer is multi-layer stacked; the first type semiconductor layer is N-type and the second type semiconductor layer is P-type; or, the first type semiconductor layer is P-type and the second type semiconductor layer is N-type.

[0032] In some embodiments, the top of the second type semiconductor layer further includes a metal island layer; the metal island layer contains multiple mutually isolated metal particles.

[0033] The technical solution provided by the present invention has the following beneficial effects:

[0034] 1. In the micro light-emitting diode structure provided by the present invention, the first metal layer serving as the bottom reflection layer is coated by the bottom conductive layer and the second metal layer, preventing the first metal layer from diffusing outward from the side during the processing or after manufacturing, creating favorable conditions for the large-scale mass production of 2-micrometer pitch micro-mesa based on a silver mirror.

[0035] 2. The metal contact hole of the micro light-emitting diode structure provided by the present invention is electrically connected to the first-type semiconductor layer of the micro-mesa through the third metal layer and the bottom conductive layer, and the bottom contact structure is electrically connected to the second-type semiconductor layer of the micro-mesa through the top conductive layer. The metal contact hole and the bottom contact structure, as the positive and negative electrodes of the micro light-emitting diode, are both arranged in the bottom dielectric layer below the micro-mesa. The bottom dielectric layer is located on the top surface of the driving backplane. The metal contact hole is electrically connected to the driving circuit in the driving backplane, and the bottom contact structure is led out at the edge of the micro-mesa array and electrically connected to the external pad. Burying the bottom contact structure as the top electrode of the micro light-emitting diode into the bottom dielectric layer of the driving backplane can prevent the bottom contact structure from blocking the micro-mesa, thereby increasing the light extraction rate.

[0036] 3. The micro light-emitting diode structure provided by the present invention improves the micro lens. By improving the profile of the micro lens, the height of the lower spacer, the radius of curvature, and the lens ball height are adjusted, thereby improving the micro defects of the lens, and further effectively enhancing the brightness or light efficiency of the micro light-emitting diode chip. The specific technical effects are as follows. The advantage of increasing the height of the lower spacer lies especially in: on the premise of determining the radius of curvature, with the light source emitting mainly from the upper bottom of the pixel, as the radius of curvature increases, increasing the height of the lower spacer makes the radius of the emitted light increase, and the emission angle of the same point light source micro lens and the air interface decreases, so that the emission angle can be increased; the smaller the radius of curvature, that is, the wider the ball width of the micro lens, is beneficial to light emission. Correspondingly, increasing the ball height, that is, changing the ball height of the original hemispherical micro lens, will also allow the escaping light to be emitted from the micro lens. By changing the curvature, the total emission angle of the micro lens is increased, making it not easy to form total reflection light, which is beneficial to the light emission effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be further described below with reference to the specific embodiments in conjunction with the drawings.

[0038] Figure 1 The top view schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown.

[0039] Figure 2 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention along line AA is shown.

[0040] Figure 3 The schematic top view of the first metal layer and the second metal layer according to an embodiment of the present invention is shown.

[0041] Figure 4 A schematic diagram showing the isolation etching process of micro light-emitting diodes according to an embodiment of the present invention.

[0042] Figure 5 A schematic diagram showing the isolation etching process of micro light-emitting diodes according to an embodiment of the present invention.

[0043] Figure 6 A schematic longitudinal sectional view of a micro light-emitting diode chip according to an embodiment of the present invention.

[0044] Figure 7 A schematic top view showing the metal contact hole 111 and the bottom contact structure 112 according to an embodiment of the present invention. Detailed implementation manners

[0045] It should be noted that the components in the respective drawings may be exaggeratedly shown for illustrative purposes and are not necessarily to scale correctly. In the respective drawings, the same or functionally identical components are provided with the same reference numerals.

[0046] In the present invention, unless otherwise specified, "arranged on", "arranged above", and "arranged over" do not exclude the presence of an intermediate between the two. In addition, "arranged on or above" only represents the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted to "arranged under or below", and vice versa.

[0047] In the present invention, the respective embodiments are only intended to illustrate the solutions of the present invention and should not be construed as restrictive.

[0048] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0049] In the present invention, the term "connected" can refer to both direct connection between the two and indirect connection between the two through an intermediate element.

[0050] In the present invention, the term "configured" means setting the shape, structure, material, and / or function of an object to achieve the desired technical effect, where "configured" includes various alternative technical means for achieving this technical effect, and these technical means become obvious under the teaching of the present invention.

[0051] It should also be noted here that, in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of the components or assemblies may be shown. However, those of ordinary skill in the art can understand that, under the teachings of the present invention, the required components or assemblies can be added according to the specific scenario requirements. In addition, unless otherwise specified, the features in different embodiments of the present invention can be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the obtained embodiment also falls within the scope of the disclosure or the scope of the record of this application.

[0052] It should also be noted here that within the scope of the present invention, terms such as "identical", "equal", "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error. That is to say, the terms also cover "substantially identical", "substantially equal", "substantially equal to". By analogy, in the present invention, terms indicating directions such as "perpendicular to" and "parallel to" also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0053] In the present invention, the term "at the bottom of the micro-tabletop" refers to the side of the micro-tabletop facing away from the microlens, the term "at the top of the micro-tabletop" refers to the side of the micro-tabletop facing the microlens, and the term "side of the micro-tabletop" refers to the two sides between the top and the bottom.

[0054] In the present invention, the term "profile of the metal layer" refers to the maximum dimension, such as the length, in the plane formed by the length and width of the metal layer (or the plane perpendicular to the thickness). Similarly, the bottom profile of the micro-tabletop refers to the maximum dimension, such as the length, of the micro-tabletop in the bottom plane (i.e., the plane perpendicular to the thickness at the bottom).

[0055] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention.

[0056] Figure 1 A top view schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 2 A longitudinal sectional schematic diagram of a micro light-emitting diode chip according to an embodiment of the present invention along line AA is shown. As shown in the figure, the micro light-emitting diode chip includes a driving backplane 110, a first metal layer 191, a second metal layer 192, a third metal layer 130, a micro light-emitting diode, and a microlens 140. The first metal layer 191 is located at the bottom of the micro-tabletop of the micro light-emitting diode. The second metal layer 192 is located at the bottom of the first metal layer 191. The third metal layer 130 is located at the bottom of the second metal layer 192.

[0057] The micro light-emitting diodes are arranged on the upper surface of the driving backplane 110. The first metal layer 191, the second metal layer 192, and the third metal layer 130 are located between the driving backplane 110 and the micro light-emitting diodes. A microlens 140 is arranged on the upper surface of the micro light-emitting diodes, and adjacent microlenses 140 are spaced apart between the micro light-emitting diodes. In some embodiments of the present invention, the driving module includes the driving backplane 110.

[0058] The micro light-emitting diodes include: a bottom conductive layer 150, a micro mesa 120, a sidewall dielectric layer 160, and a top conductive layer 170. The micro light-emitting diodes are arranged on the upper surface of the driving backplane 110. The upper surface of the driving backplane 110 includes a metal contact hole 111, and a bottom contact structure 112 and a bottom dielectric layer 113 surrounding the metal contact hole 111. The bottom dielectric layer 113 is located at the bottom of the entire micro mesa array region and at the bottom of the third metal layer 130. The metal contact hole 111 is located in the bottom dielectric layer and at the bottom of the third metal layer 130, and is in contact connection with the bottom of the third metal layer 130.

[0059] The size of each micro light-emitting diode chip does not exceed 1 cm, preferably not exceeding 5 mm. The micro light-emitting diodes are formed in an array in the micro light-emitting diode chips, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro light-emitting diode structure is at the nanometer level, for example, 20 nm to 100 nm. Each micro light-emitting diode can form at least a part of the pixel element on the micro light-emitting diode chip.

[0060] Introduction to the driving backplane 110:

[0061] For convenience, "upward" is used to indicate away from the driving backplane 110, "downward" indicates toward the driving backplane 110, and other directional terms such as top, bottom, above, below, directly below, beneath, etc. are also interpreted accordingly. In some embodiments of the present invention, the driving backplane 110 includes a substrate (not shown in the figure), a driving circuit (not shown in the figure), a metal contact hole 111, and a bottom dielectric layer 113 surrounding the metal contact hole 111. The metal contact hole 111 can also be referred to as the driving electrode of the driving circuit.

[0062] In some embodiments of the present invention, the substrate is a Si substrate. In some other embodiments of the present invention, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is about 700 microns thick.

[0063] The driving circuit forms individual pixel drivers to control the operation of each single micro-LED pixel. The driving circuit includes, for example, complementary metal oxide semiconductor (CMOS) devices or TFT devices, etc.

[0064] Each metal contact hole 111 corresponds to a micro-light emitting diode, and each metal contact hole 111 is electrically connected to the third metal layer 130. In some embodiments of the present invention, the material of the metal contact hole 111 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Sn, W, Cr, Pt, and Au.

[0065] In some embodiments of the present invention, first, a light-emitting epitaxial layer structure of a micro-light emitting diode is fabricated on the surface of the epitaxial substrate. Then, the light-emitting epitaxial layer structure of the micro-light emitting diode can be bonded to the surface of the driving backplane 110 through the bottom metal layer 130, and the bonding between the driving backplane 110 and the micro-light emitting diode can be achieved by high-temperature and high-pressure bonding methods such as eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding.

[0066] Introduction to the third metal layer 130:

[0067] In some embodiments of the present invention, the third metal layer 130 may be disposed on the driving backplane 110. In some other embodiments of the present invention, the third metal layer 130 grows on the driving backplane 110. In some embodiments of the present invention, the thickness of the third metal layer 130 is from 0.1 micrometer to 3 micrometers. In a preferred embodiment, the thickness of the third metal layer 130 is 0.6 micrometers. In some embodiments of the present invention, the third metal layer 130 includes a first sub-metal layer (not shown in the figure) and a second sub-metal layer (not shown in the figure). The first sub-metal layer is in direct contact with the structure at the bottom of the micro mesa 120, and the second sub-metal layer is located at the bottom layer of the third metal layer 130. In some embodiments of the present invention, one or more third sub-metal layers are further disposed between the first sub-metal layer and the second sub-metal layer. By making the third metal layer 130 have multiple sub-metal layers, first, the total thickness of the third metal layer 130 can be flexibly controlled by depositing multiple sub-metal layers multiple times during the manufacturing process; second, the material selection of each sub-metal layer is also more flexible. For example, the first sub-metal layer in direct contact with the bottom structure of the light-emitting mesa can select a metal material that is not easily diffused or will not cause serious consequences even if diffused or a metal material with a small contact resistance with the adjacent structure. The intermediate layer can select a metal material with good conductivity, and the second sub-metal layer at the bottom layer can select a metal material with good bonding property with the driving backplane 110. In some embodiments of the present invention, the material of the first sub-metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second sub-metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the third sub-metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn.

[0068] In one embodiment of the present invention, after the bonding is completed, the epitaxial substrate can be removed by laser lift-off. The material of the epitaxial substrate can be sapphire or silicon. The corresponding lift-off process can be selected according to the material of the epitaxial substrate. After the epitaxial substrate is removed, the purpose of transferring the epitaxial light-emitting structure to the driving backplane 110 can be achieved. Removing the epitaxial substrate can further thin the epitaxial buffer layer structure, facilitating the subsequent PN step process of the epitaxial structure.

[0069] In one embodiment of the present invention, after the bonding is completed, the light-emitting epitaxial layer is etched to form the micro mesa 120, and by adjusting the lithography topography, an ion etching is performed to form a micro light-emitting diode pixel point with a positive trapezoidal structure.

[0070] As Figure 2As shown, in some embodiments, the driving backplane 110 may employ an integrated circuit (IC) board. The micro light-emitting diodes are electrically connected to the driving backplane 110, and the driving backplane 110 is used to control the lighting and extinguishing of the micro light-emitting diodes. In some embodiments, the integrated circuit board may be electrically connected to each micro light-emitting diode in the micro light-emitting diode array through separate metal interconnections. In some embodiments, each micro light-emitting diode may be individually electrically controlled by the integrated circuit board. In some embodiments, the integrated circuit board may be electrically connected to the metal contact hole 111 through metal interconnections. In some embodiments, a dielectric layer may be formed in the gap between the micro light-emitting diodes. In some embodiments, the dielectric layer may also be formed in the gap between the interconnections.

[0071] In some embodiments, the micro light-emitting diode chip includes a plurality of micro light-emitting diode arrays, and each micro light-emitting diode array includes a plurality of micro light-emitting diodes. The driving method of the micro light-emitting diodes is, for example, passive matrix (PM) driving, in which the cathodes of all the micro light-emitting diodes in each array are commonly connected to the cathode line NL, and the micro light-emitting diodes with the same number in each array are respectively connected to the corresponding anode lines PL. Thus, the on / off and light emission brightness of each micro light-emitting diode can be individually controlled by controlling the signals on the corresponding cathode line and anode line.

[0072] In some embodiments, the micro light-emitting diodes may be arranged on the upper surface of the driving module in a regular or irregular manner as the pixel points of the micro light-emitting diode chip. In the micro light-emitting diode, the bottom conductive layer 150 is located at the bottom of the micro mesa 120, and the bottom conductive layer 150 is electrically connected to the first metal layer 191, the second metal layer 192, and the third metal layer 130 in sequence. The top conductive layer 170 is located on the side and top of the micro mesa 120, and the top conductive layer 170 is electrically connected to the top electrode (not shown).

[0073] In some embodiments of the present invention, the micro mesa 120 may be a trapezoidal platform, and the bottom lateral dimension of the micro mesa 120 is larger than the top lateral dimension. In some embodiments of the present invention, the inclination angle range of the side wall of the micro mesa 120 is: 60° to 85°. In some embodiments of the present invention, the bottom lateral dimension of the micro mesa 120 does not exceed 3 microns. In some embodiments of the present invention, the top lateral dimension of the micro mesa 120 does not exceed 1.5 microns. In some embodiments of the present invention, the lateral dimensions of the bottom conductive layer 150 and the third metal layer 130 are larger than the bottom lateral dimension of the micro mesa 120.

[0074] As Figure 2As shown, the micro mesa 120 includes a first-type semiconductor layer 121, a second-type semiconductor layer 122, and a light-emitting layer 123 located therebetween. The first-type semiconductor layer 121 is electrically connected to the bottom conductive layer 150. The second-type semiconductor layer 122 is electrically connected to the top conductive layer 170. In some embodiments, the micro mesa 120 of each micro light-emitting diode in the micro light-emitting diode array can be a micron-level micro mesa 120. In some embodiments, the micron-level micro mesa 120 can include, from bottom to top, a first-type semiconductor layer 121, a light-emitting layer 123, and a second-type semiconductor layer 122. That is to say, in the three-layer structure, the first-type semiconductor layer 121 is closest to the driving backplane 110; the light-emitting layer 123 is located above the first-type semiconductor layer 121 and is farther from the driving backplane 110; the second-type semiconductor layer 122 is located above the light-emitting layer 123 and is the farthest from the driving backplane 110. In some embodiments, the light-emitting layer 123 is formed by a plurality of stacked quantum well layers, particularly superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type semiconductor layer 121 is a semiconductor material having a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first-type semiconductor layer 121 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the first-type semiconductor layer 121 can include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, the bottom conductive layer 150 can be formed below the window layer. In some embodiments, the second-type semiconductor layer 122 is a semiconductor material having a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second-type semiconductor layer 122 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the second-type semiconductor layer 122 can include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, the top conductive layer 170 can be formed on the confinement layer. In some embodiments of the present invention, the first conductivity type is different from the second conductivity type.

[0075] In some embodiments, the first-type semiconductor layer 121 is an N-type GaN layer or an N-type AlGaN layer, and the second-type semiconductor layer 122 is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second-type semiconductor layer 122 can be a material layer of the second conduction type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the first-type semiconductor layer 121 can be a material layer of the first conduction type composed of at least two or more elements including Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 123 includes a multi-quantum well layer and an electron blocking layer. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 123 further includes an electron blocking layer, and the electron blocking layer is disposed on the first side of the light-emitting layer 123, and the first side refers to the side along which electrons migrate out of the light-emitting layer 123. In other embodiments of the present invention, the first-type semiconductor layer 121 can also be a P-type GaN layer or a P-type AlGaN layer, and the second-type semiconductor layer 122 is an N-type GaN layer or an N-type AlGaN layer.

[0076] In some embodiments, the light-emitting layer 123 includes at least one quantum well layer (not shown in the figure). The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9, and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0077] In some embodiments, one of the first-type semiconductor layer 121 and the second-type semiconductor layer 122 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3。The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is from 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is from 50 nm to 75 nm, for example 65 nm.

[0078] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer 123, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is from 0.3 to 0.5, for example x is 0.5. In such an embodiment, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is from 10 nm to 30 nm, for example 20 nm.

[0079] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is from 50 nm to 70 nm, for example 65 nm.

[0080] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where the range of x is from 0.1 to 0.3 and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is from 20 nm to 40 nm, such as 30 nm.

[0081] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, such as x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, such as 20 nm.

[0082] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0083] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0084] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0085] In some embodiments, the first metal layer 191 is in contact connection with the bottom surface of the bottom conductive layer 150. The first metal layer 191 serves as a mirror layer and can reflect the light emitted from the light-emitting region, thereby improving the brightness and light-emitting efficiency of the micro light-emitting diode panel or display screen. In some embodiments, the width of the first metal layer 191 is not less than the top width of the second type semiconductor layer 122. The material of the first metal layer 191 can be an active metal. The first metal layer 191 can be a metal layer with a high reflectivity. For example, the metal layer contains one or more metals, such as silver (Ag), aluminum (Al), gold (Au), copper (Cu), platinum (Pt).

[0086] In some embodiments, the thickness of the first metal layer 191 is in the range of 300 Å - 600 Å.

[0087] In some embodiments, the second metal layer 192 is in contact connection with the bottom surface of the first metal layer 191. The second metal layer 192 serves as a barrier layer, which can prevent metal atoms in the first metal layer 191 from diffusing downward and / or laterally. In some embodiments, the second metal layer 192 includes a single layer of metal. The material of the single-layer second metal layer is a Ti-containing metal alloy material. For example, the Ti-containing metal alloy material is TiN or TiW.

[0088] In some embodiments, the second metal layer 192 includes multiple sub-metal layers. The thickness of the sub-metal layer is in the range of 5 Å - 500 Å. Among the multiple sub-metal layers, one of the sub-metal layers includes a Ti metal layer. For example, the multiple sub-metal layers include a Ti metal layer and a Pt metal layer, or a Ti metal layer and a Pd metal layer, or a Ti metal layer and an Au metal layer. That is, the second metal layer 192 can be a stack of a Ti metal layer and a Pt metal layer, a stack of a Ti metal layer and a Pd metal layer, or a stack of a Ti metal layer and an Au metal layer.

[0089] In some embodiments, the top surface of the first metal layer 191 is in contact with the bottom conductive layer 150, and the bottom surface is in contact with the second metal layer 192. The bottom conductive layer 150 and the second metal layer 192 serve as barrier layers to prevent the first metal layer 191 from diffusing in both the upward and downward directions. During the processing or after the manufacturing is completed, in order to prevent the first metal layer 191 from diffusing laterally to the outside, the present invention proposes to coat the sidewalls of the first metal layer 191 with the bottom conductive layer 150 and / or the second metal layer 192. That is, the lateral dimension of the bottom conductive layer 150 and / or the second metal layer 192 is greater than the lateral dimension of the first metal layer 191. In Figure 2 In the illustrated embodiment, the sidewalls of the first metal layer 191 are coated with the second metal layer 192. The second metal layer 192 also has an upward protrusion, and the protrusion coats the sidewalls of the first metal layer. The top height of the protrusion is the same as the top height of the first metal layer 191.

[0090] Figure 3 A top view schematic diagram of the first metal layer 191 and the second metal layer 192 according to an embodiment of the present invention is shown. The first metal layer 191 is embedded in the second metal layer 192. The top surface of the first metal layer 191 is flush with the top surface of the second metal layer 192, and the bottom surface and the side surfaces of the first metal layer 191 are covered by the second metal layer 192. The top surface of the second metal layer 192 is also in contact connection with the bottom conductive layer 150. The thickness of the second metal layer 192 is in the range of 5 Å - 500 Å. The lateral dimension of the top surface of the second metal layer 192 is substantially the same as the lateral dimension of the bottom surface of the bottom conductive layer 150.

[0091] In some embodiments, the third metal layer 130 is located at the bottom of the second metal layer 192. The lateral dimension of the top surface of the third metal layer 130 is substantially the same as the lateral dimension of the bottom surface of the second metal layer 192. The sidewalls of the first metal layer 191 are inclined, the sidewalls of the second metal layer 192 are inclined, and the sidewalls of the third metal layer 130 are inclined. In the cross-sectional structures of the first metal layer 191, the second metal layer 192, and the third metal layer 130, the sidewalls of the three are inclined in the same direction. The sidewall of the micro mesa 120 is inclined in the same direction as the first metal layer 191. The inclination angles of the sidewalls of the first metal layer 191, the second metal layer 192, and the third metal layer 130 are in the range of 60° - 90°. However, those skilled in the art should be clear that: the inclination angles of the sidewalls of the micro mesa 120, the bottom conductive layer 150, the first metal layer 191, the second metal layer 192, and the third metal layer 130 can be different, and the lateral dimensions of the micro mesa 120, the bottom conductive layer 150, the second metal layer 192, and the third metal layer 130 at the adjacent interfaces can be the same or different. When the lateral dimensions at the adjacent interfaces are different, steps will be formed at the interfaces. As Figure 2 shown, there are steps at the adjacent interface between the micro mesa 120 and the bottom conductive layer 150. Similarly, in other embodiments of the present invention, there may be steps at the adjacent interface between the bottom conductive layer 150 and the second metal layer 192; there may be steps at the adjacent interface between the second metal layer 192 and the third metal layer 130. When the lateral dimensions of the micro mesa 120, the bottom conductive layer 150, the second metal layer 192, and the third metal layer 130 are the same at the adjacent interfaces, in the interface diagram, when the sidewalls of the micro mesa 120, the bottom conductive layer 150, the second metal layer 192, and the third metal layer 130 are in a straight line.

[0092] In some embodiments, the sidewall dielectric layer 160 is located on the sidewalls of the micro mesa 120, the second metal layer 192, and the third metal layer 130. Alternatively, the sidewall dielectric layer 160 is located on the sidewalls of the micro mesa 120, the second metal layer 192, the third metal layer 130, and the region between adjacent micro mesas. In some embodiments, the sidewall dielectric layer 160 may cover a part of the top surface of the micro mesa 120. In some embodiments, materials such as silicon dioxide, silicon nitride, silicon oxide, silicon oxynitride, etc. are deposited by plasma chemical vapor deposition or atomic layer deposition processes to form the sidewall dielectric layer. A photolithography opening process is performed on the top surface of the micro mesa 120 for the sidewall dielectric layer 160 through photolithography, and at least a part or all of the surface of the top surface of the micro mesa 120 is etched to expose, and electrical contact between the micro mesa 120 and the top conductive layer 170 is achieved through the opening of the sidewall dielectric layer. In some embodiments of the present invention, adjacent sidewall dielectric layers are connected, and all sidewall dielectric layers are connected into a whole. In some embodiments of the present invention, the material of the sidewall dielectric layer is one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0093] In some embodiments, the sidewall dielectric layer 160 is located on the sidewalls of the micro mesa 120, the first metal layer 191, the second metal layer 192, and the sidewalls of the third metal layer 130. Alternatively, the sidewall dielectric layer 160 is located on the sidewalls of the micro mesa 120, the first metal layer 191, the second metal layer 192, the sidewalls of the third metal layer 130, and the regions between adjacent micro mesas.

[0094] In some embodiments, the sidewall dielectric layer 160 coats the entire sidewalls of the micro mesa 120 structure, coats the entire sidewalls of the second metal layer 192 and the third metal layer 130; or coats the entire sidewalls of the micro mesa structure 120, coats the entire sidewalls of the first metal layer 191, the second metal layer 192, and the third metal layer 130.

[0095] In some embodiments, the electrode polarity of the bottom conductive layer 150 is opposite to that of the top conductive layer 170. The bottom conductive layer 150 can be, for example, a P electrode or an anode electrode, while the top conductive layer 170 is an electrode with a polarity opposite to that of the bottom conductive layer 150, such as an N electrode or a cathode electrode. In some embodiments of the present invention, the bottom conductive layer 150, the top conductive layer 170, and their connecting components can be one or a combination of, for example, graphene, indium tin oxide (ITO), antimony doped zinc oxide (AZO), fluorine doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0096] In some embodiments of the present invention, the top conductive layer 170 can be formed on the top surface of the micro mesa 120 and the top surface of the sidewall dielectric layer 160 by using a sputtering process.

[0097] In some embodiments of the present invention, adjacent top conductive layers 170 are connected, and all top conductive layers 170 are connected into a whole. In some embodiments of the present invention, the top conductive layer 170 is a transparent electrode for the entire display area and can be made of the conductive material indium tin oxide. In some embodiments of the present invention, the top conductive layer 170 can be formed by processes such as sputtering or electron beam evaporation.

[0098] In some embodiments, the top conductive layer 170 can be shared by all the micro light emitting diodes in the micro light emitting diode array.

[0099] In some embodiments, the top conductive layer 170 is electrically connected to an electrode (not shown in the figure). The electrode can be used as a common electrode and is connected to each micro mesa in the micro light-emitting diode array. The top electrode can electrically connect the second-type semiconductor layer 122 of the micro mesa 120 to the negative electrode of an external power supply. This electrode can also be referred to as the N electrode. In some embodiments, this electrode layer can be located above the top conductive layer 170 between the micro light-emitting diodes and surround the micro light-emitting diodes. In some embodiments, this electrode can be located below the top conductive layer 170 and buried in the bottom dielectric layer 113.

[0100] In some embodiments, a metal island layer 180 is further included on the top of the second-type semiconductor layer 122. The metal island layer 180 contains multiple isolated metal particles.

[0101] Figure 2 In [the figure], the lateral dimension of the bottom of the microlens 140 is larger than the lateral dimension of the light-emitting area of the micro light-emitting diode. In some embodiments, the lateral dimension of the bottom of the microlens 140 can be equal to the lateral dimension of the light-emitting area of the micro light-emitting diode.

[0102] In some embodiments, one microlens 140 can cover multiple lensless micro light-emitting diodes. Multiple microlenses form a microlens array. The microlens array is disposed above the micro light-emitting diode array, where at least one microlens is disposed on the surface of the top conductive layer of the micro light-emitting diode, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro light-emitting diode. The microlens is mainly used to converge and / or collimate light. For example, by adjusting parameters such as the thickness and curvature of the microlens, the focal point of the microlens can be located in the micro mesa 120 of the micro light-emitting diode. The microlenses in the microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. As Figure 2 shown, in some embodiments of the present invention, the microlens 140 includes an upper curvature portion and a lower spacer portion. In some embodiments of the present invention, the typical shape of the lower spacer portion of each microlens 140 includes a circle, a square, a rectangle, and a hexagon. The microlenses in the microlens array of the display panel can be the same or different in terms of shape, curvature, optical power, size, base, spacer, etc.

[0103] In some embodiments of the present invention, the center of curvature of each position of the side wall of the lower spacer does not coincide with the center of curvature of each position of the upper curvature. The thickness of the lower spacer is set so that the focus of the microlens is located in the micro-table 120 of the micro-LED. In some embodiments of the present invention, the height of the lower spacer of the microlens is 0.5 to 3 microns, and / or the height of the upper curvature of the microlens is 0.5 to 2 microns, and / or the spherical width of the microlens is 3 to 4 microns. In another embodiment, the microlens can be, for example, a positive hemispherical shape.

[0104] In some embodiments, the shape of the microlens 140 may be a curved hemispherical shape. In some embodiments, the height of the microlens 140 is no greater than 2 microns. In some embodiments, the height of the microlens 140 is no greater than 1 micron. In some embodiments, the height of the microlens 140 is no greater than 0.5 microns. In some embodiments, the width of the microlens 140 is no greater than 4 microns. In some embodiments, the width of the microlens 140 is no greater than 3 microns. In some embodiments, the width of the microlens 140 is no greater than 2 microns. In some embodiments, the width of the microlens 140 is no greater than 1 micron. In some embodiments, the ratio of the width to the height of the microlens 140 is greater than 1.5.

[0105] In some embodiments, microlens 140 can be made of various materials that are transparent to the wavelengths of light emitted by the micro-LED. Exemplary transparent materials for microlens 140 include polymers, dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, microlens 140 is made of photoresist.

[0106] In some embodiments, the manufacturing process of the microlens 140 is mainly based on CVD deposition of SiO2 film layer. Since the actual deposited film thickness varies from 2.5 to 4um, the deposition procedure used is generally a high deposition rate film forming method, which will cause deposition defects and micro cracks in the deep groove area. After the deposition is completed, a photoresist with suitable viscosity is selected, such as a positive photoresist, to coat the wafer surface, and then the light shielding area of the exposure photomask is overlapped with the pixel position, and then exposed to form the microlens 140 photolithography pattern, and the photoresist morphology is fully exposed for a second time and the hard film is baked to improve it, so that the photoresist shrinks due to the photosensitivity and thermal characteristics, and the cross-section forms a hemispherical morphology. At this point, the photolithography process is completed, and ICP dry etching is performed subsequently, which is ion etching dominated by chemical etching. Then, based on the photolithography hemispherical morphology, according to the actual deposited SiO2 thickness, a certain SiO2 etching time is set to obtain the remaining etching margin, and a similar etching pattern can be formed at this time. Figure 1Appearance of the microlens 140 shown. Since the etching rate of SiO2 is relatively stable and highly controllable, the desired etching depth can be achieved by setting the etching time. The position of the microlens 140 is lithographed to form a hemispherical SiO2 morphology. Here, the sphere height refers to the height of the hemispherical SiO2, which is generally between 1.5 and 1.8 um. Similarly, the sphere width is the diameter width of the arc-shaped hemisphere. The height from the sphere height down to the upper base of the pixel is the height of the lower spacer. The radius of curvature can be considered as the degree of bending of the SiO2 hemispherical curve. The larger the radius of curvature, the larger the circle it represents, and the curve becomes flatter. The smaller the radius of curvature, the smaller the circle it represents, and the curve becomes more curved, with a greater curvature.

[0107] However, through data simulation and multiple experimental verifications, the inventor found that the smaller the radius of curvature, that is, the larger the sphere width of the microlens 140, is beneficial to light output. Correspondingly, when the sphere height increases, that is, by changing the original sphere height of the hemispherical microlens 140, the escaping light can also be emitted from the microlens 140. By changing the curvature, the total emission angle of the microlens 140 is increased, making it difficult to form total reflection light, which is beneficial to the light output effect. In addition, to achieve a uniform lithography pattern, the photoresist is generally not too thick because the photoresist is also consumed as a mask layer during the etching process, and too much or too little etching cannot obtain an ideal sphere height of the microlens 140. When the sphere width and sphere height can form a positive semi-circular shape, that is, when twice the sphere height is equal to the sphere width, the effect is the best.

[0108] The inventor further found that the remaining amount of the lower spacer also affects the light output effect. For the same sphere height and sphere width, the lower spacer generally does not exceed the sphere height. Under the current process, there are micro-gap defects on both sides of the SiO2 of the lower spacer, and light sources are prone to diffuse reflection here. If the lithography size of the microlens 140 is adjusted, this defect can be eliminated or reduced during the previous etching of the microlens 140, and the defect repair effect can be achieved through secondary SiO2 deposition subsequently.

[0109] In the existing process steps, it is inevitable that the ball width and ball height of the microlens 140 are not in the best conditions after etching. For example, the SiO2 film layer of the microlens 140 is deposited for the first time by PECVD, approximately 2.5 - 3.5 microns. Subsequently, by adjusting the lithography topography of the microlens 140, such as the photoresist thickness, exposure energy, and hardening film temperature, the lithography array topography at the corresponding pixel positions is completed. The passivation protection layer SIO2 material of the microlens 140 is etched by ions to form a hemispherical SIO2 microlens 140 with a lens-like topography. After the etching of the microlens 140 SIO2 is completed, due to the lithography size and ion etching of the microlens 140, the overall curvature radius, the height of the lower spacer, the ball height, and the lens ball width of the microlens 140 are all somewhat smaller. Therefore, a secondary SIO2 deposition is performed on the microlens 140 to increase the curvature radius, the height of the lower spacer, the ball height, and the lens ball width of the microlens 140. The film thickness of the secondary SIO2 deposition needs to be based on the film thickness of the SIO2 deposited on the microlens 140 in the previous process and the etching topography of the microlens 140. The secondary deposition is generally 0.2 - 1 micron and can be a single or multiple deposition operations. The inventor of the present invention has found through research that the secondary deposition can achieve a better brightness improvement effect.

[0110] Based on this, the present invention provides a micro light-emitting diode chip and a manufacturing method thereof. The microlens 140 is formed by multiple depositions to change the height of the lower spacer, the curvature radius, and the lens ball height of the microlens 140, improve the micro-defects of the lens, and effectively improve the light efficiency of the micro light-emitting diode chip.

[0111] Figure 4 The schematic diagram showing the isolation etching process of the micro light-emitting diode according to an embodiment of the present invention is as follows. As Figure 4 shown, the side wall and the bottom surface of the first metal layer 191 are covered by the second metal layer 192, and the top surface is covered by the bottom conductive layer 150. The isolation etching of the bottom conductive layer 150, the second metal layer 192, and the third metal layer 130 will not expose the material of the first metal layer 191. Therefore, the active metal atoms in the first metal layer 191 will not diffuse or adhere to the side wall of the micro mesa.

[0112] Figure 5 The schematic diagram showing the isolation etching process of the micro light-emitting diode according to an embodiment of the present invention is as follows. As Figure 5 shown, the bottom surface of the first metal layer 191 is covered by the second metal layer 192, and the side wall and the top surface are covered by the bottom conductive layer 150. The isolation etching of the bottom conductive layer 150, the second metal layer 192, and the third metal layer 130 will not expose the material of the first metal layer 191. Therefore, the active metal atoms in the first metal layer 191 will not diffuse or adhere to the side wall of the micro mesa.

[0113] In the pixel isolation process based on ion beam etching (IBE) or inductively coupled plasma (ICP) process, active metals such as silver are extremely prone to diffusion, which can cause extremely serious damage to the mesa. The structure provided by the present invention can prevent such situations from occurring, creating favorable conditions for the large-scale mass production of 2-micron pitch micro-mesas based on silver mirrors.

[0114] Figure 6 Shows a schematic longitudinal cross-sectional view of a micro light-emitting diode chip according to an embodiment of the present invention. Figure 6 Further shows the structure of the electrode 112 connected to the top conductive layer 170. The electrode 112 can be located under the top conductive layer 170 and buried in the bottom dielectric layer 113. Hereinafter, the electrode 112 is referred to as the bottom contact structure.

[0115] In some embodiments, the bottom contact structure 112 is located in the trench of the bottom dielectric layer 113. Figure 7 Shows a schematic top view of the metal contact hole 111 and the bottom contact structure 112 according to an embodiment of the present invention. As Figure 7 shown, the metal contact holes 111 and the bottom contact structures 112 are arranged alternately. The bottom contact structures 112 are arranged in a horizontal strip-like longitudinal cross-interconnection around the metal contact holes 111 under each micro-mesa, and the trenches are also arranged in a horizontal and vertical cross-interconnection in the bottom dielectric layer 113 and around the metal contact holes 111 under each micro-mesa 120. In some embodiments, the bottom contact structure 112 extends under the micro-mesa and leads out at the edge of the micro-mesa array, and is electrically connected to an external pad. In some embodiments, the material of the metal contact hole 111 is metal, and the material of the bottom contact structure 112 is metal. For example, it is one or more of copper, gold, tin, platinum, tungsten, and chromium.

[0116] In some embodiments, the top conductive layer 170 covers at least a part of the top surface of the bottom contact structure 112. In order to prevent the first type semiconductor layer 121 and the second type semiconductor layer 122 of the micro-mesa 120 from short-circuiting, the bottom contact structure 112 cannot contact the third metal layer 130.

[0117] In an embodiment of the present invention, the metal contact hole 111 is electrically connected to the first-type semiconductor layer 121 of the micro mesa 120 through the third metal layer 130, the second metal layer 192, the first metal layer 191, and the bottom conductive layer 150, and the bottom contact structure 112 is electrically connected to the second-type semiconductor layer 122 of the micro mesa 120 through the top conductive layer 170. The metal contact hole 111 and the bottom contact structure 112, as the positive and negative electrodes of the micro light-emitting diode, are both disposed in the bottom dielectric layer 113 below the micro mesa. The bottom dielectric layer 113 is located on the top surface of the driving backplane 110. The metal contact hole 111 is electrically connected to the driving circuit in the driving backplane 110, and the bottom contact structure 112 is led out at the edge of the micro mesa array and electrically connected to an external pad. Burying the bottom contact structure 112 as the top electrode of the micro light-emitting diode into the bottom dielectric layer 113 of the driving backplane 110 can prevent the bottom contact structure 112 from blocking the micro mesa, thereby increasing the light extraction rate. In addition, the structure proposed by the present invention avoids arranging the top electrode on the side of the micro mesa, and the beam collimation effect of the microlens is better.

[0118] In some embodiments, the bottom contact structure 112 is buried as the top electrode of the micro light-emitting diode into the bottom dielectric layer 113 of the driving backplane 110. In order to prevent the bottom contact structure 112 from contacting the third metal layer 130 and causing a short circuit between the positive and negative electrodes of the micro light-emitting diode, the top of the bottom contact structure 112 can be designed to be lower than the bottom of the third metal layer 130. As Figure 6 shown, the top of the bottom contact structure 112 is lower than the top of the trench where it is located. Thus, the bottom contact structure 112 is spaced apart from the third metal layer 130 in the vertical direction.

[0119] In some embodiments, there is an upper connection part (not shown) between the top conductive layer 170 and the top surface of the second-type semiconductor layer 122, and the upper connection part is electrically connected to the top conductive layer 170 and the second-type semiconductor layer 122. The material of the upper connection part can be metal, and the metal can include one or more of the following: aluminum (Al), gold (Au), rhodium (Rh), silver (Ag), chromium (Cr), titanium (Ti), platinum (Pt), tin (Sn), copper (Cu), gold-tin alloy (AuSn), titanium-tungsten alloy (TiW), etc. Alternatively, the material of the upper connection part can be a conductive transparent electrode, such as indium tin oxide (ITO) or fluorine-doped tin oxide (FTO).

[0120] In some embodiments, the micro mesa 120 may further include a lower connecting portion (not shown) located between the bottom conductive layer 150 and the bottom surface of the first type semiconductor layer 121, and the lower connecting portion is electrically connected to the bottom conductive layer 150 and the first type semiconductor layer 121. The material of the lower connecting portion is metal, including one or more of aluminum (Al), gold (Au), rhodium (Rh), silver (Ag), chromium (Cr), titanium (Ti), platinum (Pt), tin (Sn), copper (Cu), gold-tin alloy (AuSn), titanium-tungsten alloy (TiW), etc.

[0121] In some embodiments, the micro light emitting diode chip may include red, blue, and / or green micro light emitting diodes. In some embodiments, the pitch of the micro light emitting diode array, that is, the minimum center-to-center distance between the micro light emitting diodes, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro light emitting diode chip may be between several thousand and several million.

[0122] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It will be apparent to those skilled in the relevant art that various combinations, deformations, and changes can be made to them without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined only by the appended claims and their equivalents.

Claims

1. A micro light-emitting diode chip having a micro mesa array region including a plurality of micro mesas; characterized in that, Each micro mesa includes: A first-type semiconductor layer, a light-emitting layer, and a second-type semiconductor layer stacked in sequence from bottom to top; the first type and the second type are different; A first metal layer located at the bottom of the micro mesa; A second metal layer located at the bottom of the first metal layer; A third metal layer located at the bottom of the second metal layer; A bottom dielectric layer located at the bottom of the entire micro mesa array region and at the bottom of the third metal layer; A metal contact hole located in the bottom dielectric layer and at the bottom of the third metal layer, in contact connection with the bottom of the third metal layer.

2. The micro light-emitting diode chip according to claim 1, wherein The second metal layer further has an upward protrusion that covers the side wall of the first metal layer.

3. The micro light-emitting diode chip according to claim 2, characterized in that The top height of the protrusion is the same as the top height of the first metal layer.

4. The micro light-emitting diode chip according to claim 2, wherein The width of the first metal layer is not less than the top width of the second-type semiconductor layer.

5. The micro light-emitting diode chip according to claim 1, wherein, The material of the first metal layer is an active metal.

6. The micro light-emitting diode chip according to claim 4, wherein The material of the first metal layer is one of Ag, Al, Au, Cu, and Pt.

7. The micro light-emitting diode chip according to claim 1, wherein, The second metal layer includes one layer; or multiple sub-metal layers.

8. The micro light-emitting diode chip according to claim 6, wherein, The material of the single-layer second metal layer is a Ti-containing metal alloy material; among the multiple sub-metal layers, one of the sub-metal layers includes a Ti metal layer.

9. The micro light-emitting diode chip according to claim 7, wherein, The Ti-containing metal alloy material is TiN or TiW; the multiple sub-metal layers include a Ti metal layer and a Pt metal layer, or a Ti metal layer and a Pd metal layer, or a Ti metal layer and an Au metal layer.

10. The micro light-emitting diode chip according to claim 1, characterized in that, The material of the third metal layer is one or more of Cr, Al, Ti, Ni, Pt, Au, and Sn.

11. The micro light-emitting diode chip according to claim 1, wherein, The side wall of the micro mesa is inclined.

12. The micro light-emitting diode chip according to claim 11, wherein, The inclination angle range is: 60° to 85°.

13. The micro light-emitting diode chip according to claim 10, wherein, The side wall of the first metal layer is inclined, the side wall of the second metal layer is inclined, and the side wall of the third metal layer is inclined; in the cross-sectional structure of the first metal layer, the second metal layer, and the third metal layer, the side walls of the three are inclined in the same direction; the side wall of the micro mesa is inclined in the same direction as the first metal layer.

14. The micro light-emitting diode chip according to claim 13, wherein, The inclination angle of the side wall of the first metal layer is in the range of 60° - 90°; the inclination angle of the side wall of the second metal layer is in the range of 60° - 90°; the inclination angle of the side wall of the third metal layer is in the range of 60° - 90°.

15. The micro light-emitting diode chip according to claim 1, wherein There is also a bottom conductive layer between the bottom of the first-type semiconductor layer and the first metal layer.

16. The micro light-emitting diode chip according to claim 15, wherein The lateral dimensions of the bottom conductive layer and the second metal layer are larger than the lateral dimension of the first metal layer, The top surface of the first metal layer is in contact with the bottom surface of the bottom conductive layer, the bottom surface of the first metal layer is in contact with the top surface of the second metal layer, and the bottom conductive layer and / or the second metal layer cover the side wall of the first metal layer.

17. The micro light-emitting diode chip according to claim 1, wherein, It further includes: A side wall dielectric layer located in the region of the side wall of the micro mesa, the side walls of the first metal layer, the second metal layer, the third metal layer, and between adjacent micro mesas; Or, located on the side wall of the micro mesa, the side walls of the first metal layer, the second metal layer, and the third metal layer; or, located on the side wall of the micro mesa, the side walls of the second metal layer and the third metal layer, and in the region between adjacent micro mesas; or, located on the side wall of the micro mesa, the side walls of the second metal layer and the third metal layer; and, The top conductive layer continuously covers the top surface of the micro mesa, the surface of the sidewall dielectric layer, and the area between adjacent micro mesas.

18. The micro light-emitting diode chip according to claim 1, wherein The sidewall dielectric layer has an opening at the top of the micro mesa structure; the opening exposes part or all of the top of the micro mesa. The sidewall dielectric layer covers the entire sidewall of the micro mesa structure, covers the entire sidewalls of the second metal layer and the third metal layer. Or it covers the entire sidewall of the micro mesa structure, covers the entire sidewalls of the first metal layer, the second metal layer, and the third metal layer.

19. The micro light-emitting diode chip according to claim 1, wherein The light-emitting layer is multi-layer stacked; the first type semiconductor layer is N-type and the second type semiconductor layer is P-type; or the first type semiconductor layer is P-type and the second type semiconductor layer is N-type.

20. The micro light-emitting diode chip according to claim 1, wherein The top of the second type semiconductor layer further includes a metal island layer; the metal island layer contains multiple mutually isolated metal particles.

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