Latch circuit capable of suppressing trigger and structure of semiconductor substrate including the same

Abstract

The present invention proposes a latch circuit capable of suppressing a trigger operation of the latch circuit formed of a parasitic resistor and a parasitic bipolar transistor in a semiconductor substrate in which a plurality of wells are formed, and a semiconductor substrate having a structure capable of suppressing the trigger operation of the latch circuit.

Description

Technical Field

[0001] The present invention relates to a latch circuit, and more particularly, to a latch circuit including an additional parasitic resistor capable of suppressing a trigger operation of a latch circuit formed by a parasitic resistor and a parasitic bipolar transistor of a semiconductor substrate having a plurality of wells formed therein, and a structure of a semiconductor substrate including the latch circuit. Background Art

[0002] A CMOS circuit is a circuit that uses both P-type MOS transistors and N-type MOS transistors. A semiconductor integrated circuit including a component having a CMOS circuit can be implemented by first forming at least two wells on a semiconductor substrate, integrating P-type MOS transistors in an N-type well, integrating N-type MOS transistors in a P-type well, and electrically connecting the P-type MOS transistors and the N-type MOS transistors according to a circuit configuration.

[0003] Figure 1 Two wells for implementing a conventional CMOS circuit and power supplies applied thereto are illustrated.

[0004] Reference Figure 1 , a high-voltage N-type well 120, a high-voltage P-type well 130, and a high-voltage N-type well 140 are formed on a substrate 110, and a high-voltage power supply (HV power supply) of 18 V, a low-voltage power supply (LV power supply) of 1.8 V, and a ground power supply (GND) are applied thereto, respectively.

[0005] Generally, the latch phenomenon is caused by the structure of a semiconductor substrate having a plurality of wells formed therein.

[0006] Reference Figure 1 , the vertical structure and the horizontal structure of a plurality of regions formed on a semiconductor substrate correspond to two bipolar transistors (PNP, NPN) and a plurality of resistors (R HV P-Well , R Emitter ), and the latch circuit is represented as a corresponding circuit of these components (PNP, NPN, R HV P-Well , R Emitter ), and the latch circuit is not intended by a semiconductor circuit designer.

[0007] Figure 2 Separate illustration of Figure 1 the latch circuit shown.

[0008] Reference Figure 2 , the latch circuit is a closed-loop circuit formed by two bipolar transistors (PNP, NPN) and two resistors (R HV P-Well , R Emitter ).

[0009] Since the operations and electrical characteristics of the latch circuit have been disclosed in multiple patents and multiple documents (including Korean Patent No. 10-0641954 (October 26, 2006)), the operation characteristics are only briefly described here to assist in understanding the present invention.

[0010] For ease of explanation, the flow of current is described in the same direction as the flow of holes, and in Figure 1 and Figure 2 holes are depicted as + marks located inside circles.

[0011] Referring to Figure 1 and Figure 2 , the active region (P+) that supplies the ground voltage (GND) to the high-voltage P-type well 130 and the high-voltage P-type well 130 correspond to the base terminal of the second bipolar transistor (NPN), and the low-voltage N-type well 140 corresponds to the emitter terminal.

[0012] To suppress the operations of the first bipolar transistor (PNP) and the second bipolar transistor (NPN), an alternative method of increasing the resistance value (resistance) of the emitter resistor (R Emitter ) formed between the emitter terminal of the second bipolar transistor (NPN) and the low-voltage power supply (LV power supply) terminal can be proposed by increasing the area of the high-voltage P-type well 130.

[0013] Here, increasing the area of the high-voltage P-type well 130 means increasing the width (W width ) of the high-voltage P-type well 130, and means increasing the distance between the emitter terminal of the second bipolar transistor (NPN) and the low-voltage power supply (LV power supply) terminal. This alternative increases the area used on the semiconductor substrate, and thus does not conform to the recent technological trend of attempting to reduce the chip size. Summary of the Invention

[0014] Technical Problem

[0015] The technical problem to be solved by the present invention is to provide a structure of a semiconductor substrate having a structure including an additional parasitic resistor that can suppress the triggering operation of a latch circuit formed by the parasitic resistors and parasitic bipolar transistors of the semiconductor substrate having multiple wells formed therein.

[0016] Technical Solution

[0017] According to one aspect of the present invention for solving the above technical problems, a semiconductor substrate structure may include a first bipolar transistor, a second bipolar transistor, and an emitter resistor, and includes a latch circuit capable of suppressing triggering, the latch circuit having a structure that increases the resistance value of the emitter resistor formed between the emitter terminal of the second bipolar transistor and the low-voltage power supply or forms an additional resistor between the emitter terminal of the second bipolar transistor and the emitter resistor.

[0018] According to another aspect of the present invention for solving the above technical problems, a semiconductor substrate structure may include a first bipolar transistor, a second bipolar transistor, and an emitter resistor, wherein the second bipolar transistor has a first well as a base region and a second well of a different type from the first well as an emitter region, and includes a latch circuit capable of suppressing triggering, the latch circuit increasing the resistance value of the emitter resistor or forming an additional resistor by using at least one of the number of contact fillings formed between the power supply active region formed in the second well and the contact line located above the power supply active region, the installation position of the contact fillings, and the barrier film covering a part of the upper portion of the power supply active region.

[0019] Advantages of the Invention

[0020] The structure of a semiconductor substrate including a latch circuit capable of suppressing triggering according to the present invention as described above and the latch circuit capable of suppressing triggering have the following advantages: It is possible to increase or add the resistance value of the emitter resistor of the latch circuit for suppressing triggering without increasing the process or mask. Description of the Drawings

[0021] Figure 1 Illustrates two wells for implementing a conventional CMOS circuit and the power supply applied thereto.

[0022] Figure 2 Illustrated separately Figure 1 The latch circuit shown.

[0023] Figure 3 Illustrates an embodiment of a latch circuit capable of suppressing triggering according to the present invention.

[0024] Figure 4 Illustrates the structure of a semiconductor substrate that parasitically generates a latch circuit capable of suppressing triggering according to the present invention.

[0025] Figure 5 Illustrates the structure of another embodiment of a semiconductor substrate including a latch circuit capable of suppressing triggering according to the present invention. Detailed Description

[0026] To fully understand the present invention and its operational advantages and the purposes achieved by practicing the present invention, reference should be made to the accompanying drawings and the content described therein, which illustrate exemplary embodiments of the present invention.

[0027] Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. The same reference numerals presented in each drawing denote the same components.

[0028] Figure 3 An embodiment of a latch circuit capable of suppressing triggering according to the present invention is illustrated.

[0029] Figure 4 The structure of a semiconductor substrate that parasitically generates a latch circuit capable of suppressing triggering according to the present invention is illustrated.

[0030] Figure 4 The upper part is a vertical cross-sectional view (A - A') of the semiconductor substrate, and the lower part is a plan view.

[0031] Reference Figure 3 , a latch circuit capable of suppressing triggering according to the present invention (hereinafter, latch circuit 300) includes a first bipolar transistor (PNP), a second bipolar transistor (NPN), a first collector resistor (R1), a first emitter resistor (R2), and an additional resistor (R Add ).

[0032] As described above, when explaining the conventional technology, Figure 3 the latch circuit 300 shown is parasitically generated by the vertical and horizontal structures of the semiconductor substrate and is not a circuit designed by a circuit designer, and in the present invention, the added additional resistor (R Add ) is not included in the circuit designed by the designer.

[0033] Reference Figure 3 and Figure 4 , it can be seen that the emitter terminal and base terminal of the first bipolar transistor (PNP) and the first collector resistor (R1) are formed in the high-voltage N-type well 320 region, the collector terminal of the first bipolar transistor (PNP) and the base terminal of the second bipolar transistor (NPN) are formed in the high-voltage P-type well 330 region, and the emitter terminal of the second bipolar transistor (NPN) is formed in the low-voltage N-type well 340 region.

[0034] The first bipolar transistor (PNP) has an emitter terminal connected to the input / output pad (IO pad), a base terminal connected to the high-voltage power supply (HVP), and a collector terminal connected to the ground power supply (GND).

[0035] The second bipolar transistor (NPN) has a collector terminal connected to a high voltage power supply (HVP) and a base terminal connected to a ground power supply (GND).

[0036] The first collector resistor (R1) is connected between the collector terminal of the first bipolar transistor (PNP) and the low voltage power supply (LVP).

[0037] The first emitter resistor (R2) is mounted between one terminal of the low voltage power supply (LVP).

[0038] The additional resistor (R Add ) is mounted between the emitter terminal of the second bipolar transistor (NPN) and the other terminal of the first emitter resistor (R2).

[0039] Here, the expression that the resistor is mounted between two terminals means the same as electrically connecting two terminals to the resistor. That is, the first emitter resistor (R2) connects the additional resistor (R Add ) to the low voltage power supply (LVP) while having a constant resistance value.

[0040] Reference Figure 4 , the additional resistor (R Add ) can be generated by a barrier film 353 formed in the space between the contact line 351 supplying the low voltage power supply (LVP) and the active region 341 for supplying power to the low voltage N-type well 340. The additional resistor (R Add ) is used to indicate that it is added between the first emitter resistor (R2) (the first emitter resistor (R2) is the resistor connected to the emitter terminal of the second bipolar transistor (NPN)), but it is also the same as Figure 2 the concept of increasing the resistance value of the emitter resistor (R Emitter ) in the conventional latch circuit shown.

[0041] The resistance value of the first emitter resistor (R2) is proportional to the length between the active region 331 formed in the high voltage P-type well 330 and the active region 341 formed in the low voltage N-type well 340.

[0042] For the sake of helping understanding, assume that charges move in the arrow direction along Figure 4 the two moving paths (Path 1, Path 2) formed between the active region 331 formed in the high voltage P-type well 330 and the active region 341 formed in the low voltage N-type well 340 in

[0043] Reference Figure 4 As can be seen, the first path (Path 1) and the second path (Path 2) are determined according to the position of the contact filling 352 formed in the space between the contact line 351 supplying the low-voltage power supply (LVP) and the active region 341. That is, the place where there is no contact filling 352 becomes the first path (Path 1), and the place where the contact filling 352 is formed becomes the second path (Path 2).

[0044] Here, the contact filling 352 is a device that electrically connects the contact line 351 and the active region 341 by filling a hole (not shown) formed between the contact line 351 and the active region 341 with a conductive material such as metal.

[0045] For example, the place where there is no contact filling 352 is the region in contact with the field oxide film 354 formed between the high-voltage P-type well 330 and the low-voltage N-type well 340, and the place where the contact filling 352 is formed will be at a certain distance from the field oxide film 354.

[0046] Reference Figure 1 , since a plurality of contact fillings 142 were widely formed in the space between the contact line 141 supplying the low-voltage power supply (LVP) and the active region 143 in the past, the resistance value of the first emitter resistor (R2) is the parallel sum of the resistance values of the first path (Path 1) and the second path (Path 2). That is, in Figure 1 's case, since charges can move through the first path (Path 1) and the second path (Path 2), the resistance value of the first emitter resistor (R2) should consider the charges moving through the two paths (Path 1, Path 2).

[0047] In the present invention, since there is no contact filling 352 at one end of the first path (Path 1), the movement length increases compared to the Figure 1 shown first path (Path 1), which will increase the resistance value of the emitter resistor connected to the emitter terminal of the second bipolar transistor (NPN). Here, since there is no contact filling 352 at one end of the additional resistor (R Add ), the resistance values of the formed additional resistor (R Add ) and the first emitter resistance (R2) can be the sum.

[0048] The present invention must also consider the two paths (Path 1, Path 2), but the resistance value of the first path (Path 1) and thus Figure 4 the additional resistor (R Add ) shown in the present invention is greater than Figure 1The resistance value of the first path (Path 1) in the conventional technology shown. Therefore, when the resistors on the two paths are combined in parallel, the emitter resistance value of the second bipolar transistor (NPN) in the present invention will be greater than that of the conventional technology.

[0049] In addition, as the number of contact fillings 352 decreases and the contact fillings 352 are formed to be farther away from the field oxide film 354, obviously, the resistance value of the first emitter resistor (R2) will increase. When multiple contact fillings 352 are formed, assuming the distance between the contact filling 352 farthest from the field oxide film 354 and the field oxide film 354 is 1 (one), preferably, the contact filling 352 formed closest to the field oxide film 354 is about 0.1 to 0.5 away from the field oxide film 354, so as to increase the resistance value of the first emitter resistor (R2). The number and formation position of the contact fillings 352 can be determined by a mask that defines the contact fillings 352.

[0050] The present invention proposes to form a blocking film 353 in the space between the contact line 351 supplying the low-voltage power supply (LVP) and the active region 341, and no silicide layer is formed in the lower region of the blocking film 353, thereby increasing the surface resistance of the diffusion region 341 corresponding to the blocking film 353. At the same time, no contact filling 352 is formed in the corresponding region, so as to increase the path of the moving charge by forming the contact filling at a position far from the field oxide film 354, and finally increase the resistance value of the first emitter resistor (R2) by reducing the number of contact fillings 352. Refer to Figure 4 , the blocking film 353 can cover a part of the field oxide film 354 and the upper part of the power supply active region in contact with the field oxide film 354.

[0051] As described above, as the resistance value of the first emitter resistor (R2) increases, Figure 3 the operation start (trigger) of the latch circuit 300 shown becomes more difficult.

[0052] In the previous example, for the sake of easy understanding, two paths (Path 1, Path 2) were assumed and explained. Since most of the charges forming the current move along the surface of the conductor, the resistance value of the resistance caused by the additional resistance (R Add ) or the first path (Path 1) increases the resistance value of the path moving to the contact line 351 through the blocking film 353.

[0053] That is, the absence of the silicide layer not formed by the blocking film 353 increases the resistance value of the resistance seen from the emitter terminal of the second bipolar transistor (NPN).

[0054] Below, the relationship between the resistance value of an emitter resistor connected to the emitter terminal of a second bipolar transistor (NPN) and the triggering of a latch circuit is explained.

[0055] For ease of explanation, it is assumed that the voltage level of the high voltage power supply (HVP) is 18V, the voltage level of the low voltage power supply (LVP) is 1.8V, and the voltage level of the ground power supply (GND) is 0V (zero volts).

[0056] In the above explanation, the first bipolar transistor (PNP), the second bipolar transistor (NPN), the first collector resistor (R1), the first emitter resistor (R2), and the additional resistor (R Add ) are not circuit elements included in the circuit that the designer wants to implement, but are parasitic elements automatically generated by the vertical and horizontal patterns of the semiconductor substrate, and the term parasitic is not included to simplify the terminology.

[0057] In order for the two bipolar transistors (PNP, NPN) to conduct continuously while being complementary to each other through the current applied from the outside to the input / output pad (IO pad), the moment (trigger) when the second bipolar transistor (NPN) that has been turned off needs to be turned on is completely required. In order for the second bipolar transistor (NPN) to conduct, the voltage level (V B ) of the base terminal of the second bipolar transistor (NPN) must be 0.7V or higher than the voltage level (V E ) of the emitter terminal. Here, 0.7V is the threshold voltage (which is the condition for the second bipolar transistor (NPN) to conduct), and it can vary according to the process conditions and is specific for ease of explanation.

[0058] Refer to Figure 3 , before the second bipolar transistor (NPN) conducts, the voltage level (V E ) of the emitter terminal of the second bipolar transistor (NPN) becomes the same as the voltage level of the low voltage power supply (LVP). In order for the second bipolar transistor (NPN) to conduct, the base - emitter voltage level (V B ), which is the differential voltage between the voltage level (V E ) of the base terminal and the voltage level (V BE ) of the emitter terminal of the second bipolar transistor (NPN), must be 0.7V or higher.

[0059] The conduction condition (V BE ) of the second bipolar transistor (NPN) can be derived through a process such as Mathematical Expression 1.

[0060] [Mathematical Expression 1]

[0061] V > V E - 0.7V

[0062] V E = I E × (R Add + R2)

[0063] V BE (V E - V E ) > 0.7V + I E × (R Add + R2)

[0064] Referring to Mathematical Expression 1, it can be seen that the voltage level (V E ) of the emitter terminal of the second bipolar transistor (NPN) is determined by the sum of the first emitter resistor (R2) and the additional resistor (R Add ). Here, the first emitter resistor (R2) is the same as the resistor in the conventional structure, and the additional resistor (R Add ) is proposed in the present invention.

[0065] That is to say, in the present invention, by forcibly generating an additional resistor (R Add ) between the emitter terminal of the second bipolar transistor (NPN) and the first emitter resistor (R2), it can be seen that the voltage level (V B ), which is the triggering condition for turning on the second bipolar transistor (NPN), must be added to the following terms: the voltage level corresponding to the product of the first emitter resistor (R2) and the emitter current (I E ) plus the sum of 0.7V and the voltage level corresponding to the product of the emitter current (I Add ) flowing through the additional resistor (R E ).

[0066] In the conventional structure without the additional resistor (R Add ) proposed in the present invention, if the voltage level (V B ) of the base terminal of the second bipolar transistor (NPN) is greater than the sum of the voltage level corresponding to the product of the first emitter resistor (R2) and the emitter current (I E ) and 0.7V, the second bipolar transistor (NPN) is turned on.

[0067] In the present invention, as Figure 4 shown, the contact filler 352 is not formed at the position where the barrier film 353 is formed, so that an additional resistor (R Add ) can be added to the latch circuit.

[0068] If it is specified to form an additional resistor (R AddIf an additional mask (MASK) or additional process is required for the barrier film 353 at the position of (), the effects and manufacturing costs when introducing an additional resistor (R Add ) should be compared, and the present invention also proposes a method that can use existing masks and processes, as described below.

[0069] A silicide is a compound of silicon and a metal, and is used to reduce the resistance of a gate electrode or the contact resistance of a source / drain junction during semiconductor manufacturing. Tungsten (W), molybdenum (Mo), and cobalt (Co) are used as the metal.

[0070] The present invention proposes to use a silicide generation and etching process that has already been used, which is performed before the process of forming the contact filling 352. In other words, the present invention proposes to use a silicide process that has already been used to use a silicide film (silicide block) as the barrier film 353.

[0071] Silicide is the compound term for self-aligned silicide, and it is named because the metal to be used for the silicide is deposited and then heat-treated so that the silicide is generated only in the part where the metal and silicon are in contact, and the metal that does not react with silicon after heat treatment can be removed by selective etching. That is, no separate mask is required to generate the silicide film.

[0072] In semiconductor processes, when a silicide pattern that cannot be generated by silicide is required, a method of using a mask during the silicide process is applied, but the present invention proposes to generate a barrier film while using an already used silicide mask. That is, this is achieved by the following process: additionally defining a barrier film pattern on the already used mask so that no additional mask or additional process is required.

[0073] Figure 5 is a structure of another embodiment of a semiconductor substrate including a latch circuit capable of suppressing triggering according to the present invention.

[0074] Figure 5 The upper part of () is a vertical cross-sectional view of a semiconductor substrate, and the lower part is a plan view.

[0075] Reference Figure 5 , according to another embodiment of the present invention, a structure of a semiconductor substrate having a contact filling 352 in the space between the contact line 351 and the active region 341 is formed, and the contact filling 352 functions to electrically connect the contact line 351 and the active region 341.

[0076] Figure 5 The inside of the dashed circle in () is formed Figure 4At the location of the barrier film 353 shown, however, in this embodiment, instead of forming the barrier film 353 to generate an additional resistance component, it is proposed to generate an additional resistance component by adjusting the number and position of the contact fillings 352 during the process of generating the contact fillings 352.

[0077] That is to say, by not generating the contact fillings 352 near the field oxide film 354 and forming the contact fillings 352 only far away from the field oxide film 354, an additional resistance component can be generated through the first path (Path 1).

[0078] Figure 4 and Figure 5 The plan view and cross-sectional view of are simply illustrated to help understand the present invention, and since those skilled in the art can easily understand Figure 4 and Figure 5 the technical content of, it will not be described in detail here.

[0079] The reference exemplifies the Figure 1 of the conventional technology and the Figure 4 and Figure 5 exemplifying the embodiments of the present invention. According to the structure of the present invention, the width (W width2 ) of the high-voltage P-well is smaller than the width (W width1 ) of the high-voltage P-well according to the conventional technology, but has the advantage of suppressing the triggering of the latch-up circuit.

[0080] Industrial Applicability

[0081] The present invention relates to a technology capable of suppressing the triggering of the parasitic latch-up circuit of a semiconductor substrate, and can be applied to all substrates for industrial manufacturing of semiconductor circuits.

Claims

1. A semiconductor substrate structure, the semiconductor substrate structure including a first bipolar transistor, a second bipolar transistor, and an emitter resistor, the semiconductor substrate structure comprising: A latch circuit capable of suppressing triggering, the latch circuit having a structure that increases the resistance value of the emitter resistor formed between the emitter terminal of the second bipolar transistor and the low-voltage power supply or forms an additional resistance between the emitter terminal of the second bipolar transistor and the emitter resistor.

2. The semiconductor substrate structure according to claim 1, wherein, The second bipolar transistor has a first well as a base region, a second well of a different type from the first well as an emitter region, and is configured to increase the resistance value of the emitter resistor or form the additional resistance by using the number of contact fillers formed between a power supply active region formed in the second well and a contact line located above the power supply active region.

3. The semiconductor substrate structure according to claim 1, wherein, The second bipolar transistor has a first well as a base region, a second well of a different type from the first well as an emitter region, and is configured to increase the resistance value of the emitter resistor or form the additional resistance by using the installation position of the contact fillers formed between a power supply active region formed in the second well and a contact line located above the power supply active region.

4. The semiconductor substrate structure according to claim 2 or 3, wherein, The contact fillers are formed away from the field oxide film instead of being formed close to the field oxide film formed between the surface of the first well and the surface of the second well, and wherein the close position is a position that is at least 1 / 10 of the distance between the contact filler that is the farthest from the field oxide film and the field oxide film.

5. The semiconductor substrate structure according to claim 4, wherein, The portion where the plurality of contact fillers are not formed is defined by a mask used in the manufacturing process of the contact fillers.

6. The semiconductor substrate structure according to claim 2 or 3, wherein, A barrier film is formed to cover a part of the upper portion of the power supply active region.

7. The semiconductor substrate structure according to claim 6, wherein, The barrier film is formed adjacent to the field oxide film.

8. The semiconductor substrate structure according to claim 6, wherein, The barrier film further covers a part of the field oxide film.

9. The semiconductor substrate structure according to claim 6, wherein, The barrier film is defined by using a mask used in the silicide manufacturing process.

10. A semiconductor substrate structure, the semiconductor substrate structure including a first bipolar transistor, a second bipolar transistor, and an emitter resistor, Among them, The second bipolar transistor has a first well as a base region, a second well of a different type from the first well as an emitter region, The semiconductor substrate structure includes a latch circuit capable of suppressing triggering, the latch circuit increasing the resistance value of the emitter resistor or forming an additional resistance by using at least one of the number of contact fillers formed between a power supply active region formed in the second well and a contact line located above the power supply active region, the installation position of the contact fillers, and a barrier film covering a part of the upper portion of the power supply active region.

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