Modeling method, device and system for floating body effect of silicon-on-insulator device and medium

Abstract

The invention relates to a modeling method, device, system and medium for a floating body effect of a silicon-on-insulator device, and the method comprises the steps: building a set of strong nonlinear coupling equation set which takes channel current, threshold voltage, parasitic bipolar transistor current, body source voltage and a weak multiplication ionization factor as variables; four key physical processes of collision ionization, body charge accumulation, body bias effect and parasitic transistor conduction and interaction thereof are integrated in the model completely and explicitly, so that the model ensures the prediction completeness from the physical mechanism; therefore, the complex warping effect of the silicon-on-insulator device under high drain-source voltage can be simulated with high precision, and an accurate device model basis is provided for the design of a high-performance and high-reliability integrated circuit.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to a modeling method, apparatus, system and medium for the floating body effect of silicon-on-insulator devices. Background Technology

[0002] Silicon-on-insulator (SiI) technology is an advanced semiconductor process that manufactures transistors by growing a thin silicon film on an insulating layer. This structure effectively isolates devices, reduces power consumption and parasitic effects, and is widely used in high-performance chips. Depending on the thickness of the silicon film, silicon-on-insulator (SiI) transistors can be classified into partially depleted and fully depleted types. In partially depleted devices, a "floating body" region with weak connection to the outside world is formed under the silicon film, which triggers a series of floating body effects. Among these, when the device operates at a high drain-source voltage, a large number of holes generated by the collisional ionization of charge carriers near the drain end accumulate in the floating body, causing the floating body potential to rise. This, in turn, triggers two secondary effects: first, it lowers the threshold voltage of the transistor (body bias effect); second, it activates the inherent parasitic bipolar transistors inside the device. These effects are coupled with each other, typically manifesting as an abnormal upward tilt of the output current curve under high drain voltage, i.e., the "warping effect." The warping effect can seriously affect the performance and reliability of the circuit.

[0003] However, existing modeling methods present an irreconcilable contradiction between physical integrity and practicality: some models based on simplified physics (such as those considering only volume bias effects) are concise in form but cannot explain experimental phenomena under wide gate voltages; while other models, although attempting to include parasitic bipolar transistor effects, often simplify or ignore the details of the source process of collisional ionization; in addition, some models based on empirical formulas, although capable of local fitting, lack physical basis, have poor parameter extrapolation and are difficult to apply to different operating conditions and device sizes. Summary of the Invention

[0004] The purpose of this application is to provide a modeling method, apparatus, system, and medium for the floating effect of silicon-on-insulator (SiI) devices. The modeling method, apparatus, system, and medium for the floating effect of SiI devices provided in this application can accurately simulate the complex warping effect of SiI devices under high drain-source voltage, providing an accurate device model basis for high-performance and high-reliability integrated circuit design.

[0005] This application provides a modeling method for the floating body effect of silicon-on-insulator devices, including: An equivalent circuit model is established to simulate the electrical characteristics of the silicon-on-insulator device under weak multiplication ionization conditions. Based on the equivalent circuit model, a strongly nonlinear coupled set of equations is established, including channel current, threshold voltage, parasitic bipolar transistor current, body source voltage, and weak multiplication ionization factor. The weak multiplication ionization factor is used to characterize the weak multiplication ionization effect, and the value of the body source voltage is determined by the equation including the weak multiplication ionization factor. Based on the strongly nonlinear coupled equations, the drain current of the silicon-on-insulator device under high drain-source voltage is predicted.

[0006] Optionally, the equivalent circuit model includes: a first current branch characterizing the channel current, a second current branch characterizing the emitter current of the parasitic bipolar transistor, a third current branch characterizing the hole current generated by the weak multiplication ionization effect, and a resistance branch characterizing the bulk contact resistance. The second current branch and the third current branch are both connected to a common internal body node.

[0007] Optionally, the strongly nonlinear coupling equation set includes the channel current equation, the threshold voltage equation, the parasitic bipolar transistor emitter current equation, the body source voltage equation, and the weak multiplication ionization factor equation, wherein the body source voltage equation includes the weak multiplication ionization factor.

[0008] Optionally, the weak multiplication ionization factor equation is a function of the drain-source voltage, the gate-source voltage, and the threshold voltage.

[0009] Optionally, predicting the drain current of the silicon-on-insulator device under high drain-source voltage based on the strongly nonlinear coupling equations includes: The strongly nonlinear coupled equations under different bias voltages are solved using the fixed-point iteration method. The process continues until the current iteration value of all variables in the system of equations satisfies the preset convergence criterion with the previous iteration value, and the corresponding drain current value is used as the predicted value.

[0010] Optionally, when solving the strongly nonlinear coupled equations under different bias voltages, the iterative solutions of each variable of the equations that satisfy the preset convergence criterion under the previous bias voltage are used as the initial values ​​of each variable of the equations under the current bias voltage.

[0011] Optionally, the method further includes: Obtain the measured current-voltage data set of the silicon-on-insulator device; Based on the measured current-voltage dataset, the parameters in the equivalent circuit model and / or the strongly nonlinear coupling equations are adjusted so that the predicted drain currents of the silicon-on-insulator device under different high drain-source voltages fit the measured current-voltage dataset.

[0012] This application also provides a modeling apparatus for the floating body effect of silicon-on-insulator devices, including: a processor, a memory, and a communication bus; The communication bus is used to realize the connection and communication between the processor and the memory; The processor is used to execute a modeling processing program for the floating effect of silicon-on-insulator devices stored in the memory, so as to implement the steps of the modeling method for the floating effect of silicon-on-insulator devices as described in any of the above.

[0013] This application also provides a modeling system for the floating effect of silicon-on-insulator devices, including: the modeling device as described above, and a human-computer interaction device connected to the modeling device; The human-computer interaction device is used to allow users to input operation commands and measured current-voltage datasets, and to display the prediction results output by the modeling device.

[0014] This application also provides a readable storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the steps of the modeling method for the floating body effect of silicon-on-insulator devices as described in any of the preceding claims.

[0015] Compared with existing technologies, this application provides a modeling method, apparatus, system, and dielectric for the floating body effect of silicon-on-insulator (SiI) devices. It establishes an equivalent circuit model to simulate the electrical characteristics of SiI devices under weak multiplication ionization conditions. Based on the equivalent circuit model, it establishes a strongly nonlinear coupled equation set with variables including channel current, threshold voltage, parasitic bipolar transistor current, body source voltage, and a weak multiplication ionization factor. The weak multiplication ionization factor characterizes the weak multiplication ionization effect, and the body source voltage is determined by equations including the weak multiplication ionization factor. Finally, based on the strongly nonlinear coupled equation set, it predicts the floating body effect of SiI devices under weak multiplication ionization conditions. Regarding the drain current under high drain-source voltage, this application establishes a set of strongly nonlinear coupled equations with channel current, threshold voltage, parasitic bipolar transistor current, body source voltage, and weak multiplication ionization factor as variables. The model fully and explicitly integrates the four key physical processes and their interactions: collisional ionization, body charge accumulation, body bias effect, and parasitic transistor conduction. This ensures the completeness of the model's predictions from a physical mechanism perspective, enabling high-precision simulation of the complex warpage effect of silicon-on-insulator devices under high drain-source voltage. This provides an accurate device model foundation for high-performance and high-reliability integrated circuit design. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a modeling method for the floating body effect of a silicon-on-insulator device disclosed in an embodiment of this application. Figure 2 This is a schematic layout diagram of a PDSOI NMOSFET with a T-shaped gate contact structure disclosed in an embodiment of this application; Figure 3 For along Figure 2 A schematic diagram of the cross-sectional structure of the device with the cutting line AA in the middle; Figure 4 This is a schematic diagram of the equivalent circuit model disclosed in an embodiment of this application for characterizing the weak multiplication ionization-induced warping effect; Figure 5 This is a measured output characteristic curve of the silicon-on-insulator device disclosed in the embodiments of this application; Figure 6 This is a graphical user interface diagram of the model parameter extraction and simulation software system disclosed in the embodiments of this application; Figure 7 This is a comparison chart of the output characteristic curves of the model prediction data and the measured data after parameter fitting, as disclosed in the embodiments of this application. Figure 8 This is a quantitative decomposition diagram showing the contribution of each current component to the warping effect obtained from the model calculations disclosed in the embodiments of this application. Figure 9 The parasitic bipolar transistor emitter current calculated using the model disclosed in the embodiments of this application. With drain-source voltage The change graph; Figure 10 The volume source voltage calculated using the model disclosed in the embodiments of this application. Threshold voltage and the weakly multiplying ionization factor M varies with drain-source voltage The change graph; Figure 11 The model (M) disclosed in the embodiments of this application is calculated to obtain (M) 1) With body source voltage Linear relationship diagram between them; Figure 12 This is a schematic diagram of the structure of a modeling device for the floating body effect of silicon-on-insulator devices disclosed in an embodiment of this application; Figure 13 This is a schematic diagram of the structure of a modeling system for the floating body effect of a silicon-on-insulator device disclosed in an embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly set on the other component; when a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to the other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" or "several" means two or more, unless otherwise explicitly specified.

[0022] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0023] like Figure 1 As shown in the figure, this application provides a modeling method for the floating body effect of silicon-on-insulator devices, including: S11. Establish an equivalent circuit model to simulate the electrical characteristics of silicon-on-insulator devices under weak multiplication ionization conditions. In this embodiment, the silicon-on-insulator device can specifically be a partially depleted silicon-on-insulator (PDSOI) N-type metal-oxide-semiconductor field-effect transistor (i.e., NMOSFET).

[0024] Specifically, such as Figure 2 and Figure 3 As shown, the device, from bottom to top, includes a substrate 11, a buried oxide layer 12, and a top silicon film. A shallow trench 13 isolates and defines an active region around the top silicon film. Within the active region, an N-type heavily doped source region 14 and a drain region 15, a P-type channel region 16 located between them, and a P-type heavily doped body contact 17 adjacent to the channel region 16 are formed in the top silicon film. From a layout perspective, the gate 18 of the device is T-shaped. The lateral extension of the gate 18 and the corresponding region of the body contact 17 are arranged adjacent to each other in the silicon film plane. They are electrically connected through metal interconnects or silicides. This specific spatial and electrical integration relationship between the gate 18 and the body contact constitutes a T-shaped gate-body contact structure. The body contact 17 is used to extract the potential of the floating body region below the channel that is not completely depleted. This specific layout results in a high parasitic resistance in the current path from the internal floating body node to the external circuit node corresponding to the body contact 17, which is represented as the body contact resistance in the equivalent circuit model of this application. Key parameters.

[0025] The equivalent circuit model can be as follows: Figure 4 The specific circuit shown can also be other equivalent circuit forms that can be conceived based on the physical coupling relationships it reveals. This equivalent circuit model provides a clear and physically consistent circuit framework for subsequent establishment of accurate mathematical models by abstracting the complex physical effects of two-dimensional / three-dimensional devices into lumped parameter elements and their connections. It is the foundation for achieving efficient and solvable numerical calculations.

[0026] S12. Based on the equivalent circuit model, a strongly nonlinear coupled set of equations is established with variables including channel current, threshold voltage, parasitic bipolar transistor current, body source voltage and weak multiplication ionization factor. The weak multiplication ionization factor is used to characterize the weak multiplication ionization effect, and the value of the body source voltage is determined by the equation including the weak multiplication ionization factor. In this embodiment, the parasitic bipolar transistor current can specifically be the emitter current of the parasitic bipolar transistor. The establishment process of the strongly nonlinear coupling equation set is as follows: based on the physical definition of each branch and the node current balance relationship in the equivalent circuit model, the channel current, parasitic bipolar transistor current (such as the emitter current of the parasitic bipolar transistor), and hole current generated by weak multiplication ionization can be expressed as functions of key electrical variables (including gate-source voltage, drain-source voltage, body-source voltage, and threshold voltage). At the same time, based on the principles of semiconductor physics, a functional relationship is established between the threshold voltage reflecting the body bias effect and the body-source voltage, as well as a functional relationship is established between the weak multiplication ionization factor characterizing the collisional ionization intensity and the voltage variables related to the electric field. The key is that by introducing a constraint equation that directly relates the body-source voltage to the weak multiplication ionization factor and the aforementioned currents, the value of the body-source voltage must satisfy the dynamic balance condition of the hole charge generated by weak multiplication ionization within the float.

[0027] Thus, the established set of equations forms a closed mathematical system, in which the volume source voltage is a core coupled variable whose value is explicitly determined by the equation containing the weak multiplication ionization factor, and simultaneously affects the threshold voltage and the parasitic bipolar transistor current. In this way, a complete and self-consistent unified description of the four physical processes of weak multiplication ionization, volume charge accumulation, volume bias effect and parasitic transistor conduction is achieved in the mathematical model. The establishment of this set of equations is the core link from physical principles and circuit topology to quantitative numerical prediction.

[0028] S13. Based on a strongly nonlinear coupled set of equations, predict the drain current of silicon-on-insulator devices under high drain-source voltage.

[0029] In this embodiment, the static operating points of the silicon-on-insulator (SiI) device under different bias conditions are obtained by numerically solving a set of strongly nonlinear coupled equations. Specifically, for the target operating voltage range, a numerical method suitable for strongly nonlinear equations is used to systematically solve the equations. The solution process ensures that at each bias point, the numerical solutions of the five variables—channel current, threshold voltage, parasitic bipolar transistor current, body source voltage, and weak multiplication ionization factor—satisfy the physical constraints and balance relationships defined by the equations. Finally, by systematically obtaining and integrating the solutions at each bias point, the complete output characteristic curve of the SiI device over a wide voltage range can be reconstructed. This curve not only accurately characterizes the current-voltage relationship of the device in the conventional operating region (linear region, saturation region), but more importantly, it accurately reveals and quantifies the current "warping" phenomenon caused by the floating body effect under specific high drain-source voltages, thereby achieving reliable prediction of the nonlinear behavior of the device.

[0030] Compared with existing technologies, this application provides a modeling method, apparatus, system, and dielectric for the floating body effect of silicon-on-insulator (SiI) devices. It establishes an equivalent circuit model to simulate the electrical characteristics of SiI devices under weak multiplication ionization conditions. Based on the equivalent circuit model, it establishes a strongly nonlinear coupled equation set with variables including channel current, threshold voltage, parasitic bipolar transistor current, body source voltage, and a weak multiplication ionization factor. The weak multiplication ionization factor characterizes the weak multiplication ionization effect, and the body source voltage is determined by equations including the weak multiplication ionization factor. Finally, based on the strongly nonlinear coupled equation set, it predicts the floating body effect of SiI devices under weak multiplication ionization conditions. Regarding the drain current under high drain-source voltage, this application establishes a set of strongly nonlinear coupled equations with channel current, threshold voltage, parasitic bipolar transistor current, body source voltage, and weak multiplication ionization factor as variables. The model fully and explicitly integrates the four key physical processes and their interactions: collisional ionization, body charge accumulation, body bias effect, and parasitic transistor conduction. This ensures the completeness of the model's predictions from a physical mechanism perspective, enabling high-precision simulation of the complex warpage effect of silicon-on-insulator devices under high drain-source voltage. This provides an accurate device model foundation for high-performance and high-reliability integrated circuit design.

[0031] As one implementation method, in this application embodiment, the equivalent circuit model includes: a first current branch representing the channel current, a second current branch representing the emitter current of the parasitic bipolar transistor, a third current branch representing the hole current generated by the weak multiplication ionization effect, and a resistance branch representing the body contact resistance; wherein the second current branch and the third current branch are both connected to a common internal body node.

[0032] In this embodiment, specifically, the equivalent circuit model can be referred to... Figure 4 The components and their connections are as follows: Channel current source Connected between drain node d and source node s, its current value is affected by the gate-source voltage. and threshold voltage control; The weak multiplication ionization effect is manifested through a multiplication current source: its input is the total electron current injected into the pinch-off region. The output current is divided into two parts: the multiplied electron current. The current flows to the drain d, and the resulting hole current. Flows to internal volume node b; Parasitic bipolar transistor emitter current source Connected between the source node s and the internal body node b, its current value is subject to the source-body voltage. control; The collector current of the parasitic bipolar transistor Divided into two parts: one part Injected into the pinch-off region, it participates in the weak multiplication ionization process; another part (1-k)α It flows directly to the drain d, where, This is the proportionality coefficient of the collector current flowing through the pinch-off region of the parasitic bipolar transistor. This represents the common-base current amplification factor of the parasitic bipolar transistor. Body contact resistance The current at the internal body node b, connected between the internal body node b and the external body contact electrode bc, satisfies Kirchhoff's current law. in For flowing through The contact current of the body.

[0033] In this embodiment, the shared internal body node b corresponds to the floating body region in the silicon-on-insulator device on the circuit, and its potential is the body source voltage. This topology is key to modeling physical coupling relationships: the second current branch (parasitic bipolar transistor emitter current). Simulated body potential Forward bias of the emitter junction of the parasitic bipolar transistor; third current branch (hole current generated by weak multiplication ionization effect) This represents the cavitation current generated by impact ionization and injected into the float. The shunting of the collector current ( The participation of ionization and the current balance at node b together constitute the basis for deriving the "body source voltage" from circuit principles. The core mathematical relationship is determined by equations including the weak multiplication ionization factor. Therefore, this circuit model is not a simple assembly of components, but rather a practical and solid foundation of circuit principles for the next step of transforming physical ideas into a solvable set of mathematical equations by mapping key physical effects into lumped parameter components with clear physical meaning and carefully designing their connections.

[0034] As one implementation method, in this embodiment of the application, the strongly nonlinear coupling equation set includes the channel current equation, the threshold voltage equation, the parasitic bipolar transistor emitter current equation, the body source voltage equation, and the weak multiplication ionization factor equation, wherein the body source voltage equation includes the weak multiplication ionization factor.

[0035] In this embodiment, the five equations together constitute a closed mathematical system, which fully describes the physical mechanism of the buoyancy effect through the interdependence between variables: The channel current equation establishes the fundamental relationship between gate voltage, threshold voltage, and drain current. The threshold voltage equation reflects the modulation effect of the body potential on the switching characteristics of the device (body bias effect). The emitter current equation of a parasitic bipolar transistor describes the exponential driving effect of body potential rise on the turn-on behavior of the parasitic bipolar transistor. The volume source voltage equation, as the core constraint of the system, explicitly includes a weak multiplication ionization factor that directly correlates the hole current generated by collisional ionization with the volume potential, thus embodying the principle of charge conservation. The weak multiplication ionization factor equation quantifies the collisional ionization intensity under high electric fields. In particular, the volume source voltage equation plays a crucial coupling hub role, not only receiving input from the weak multiplication ionization factor equation, but also having its output (volume source voltage value) serve as the input variable for both the threshold voltage equation and the parasitic bipolar transistor emitter current equation. This closed-loop, strongly nonlinear coupling structure enables the model to consistently simulate the complex interactions between weak multiplication ionization, charge accumulation, volume bias effects, and parasitic transistor conduction, thereby accurately predicting current warpage characteristics under high drain voltage.

[0036] In one embodiment of this application, the weak multiplication ionization factor equation is a function of the drain-source voltage, the gate-source voltage, and the threshold voltage.

[0037] In this embodiment, the functional relationship specifically characterizes the key physical factor determining the intensity of collisional ionization: the transverse electric field within the drain-end pinch-off region, which approximates... This voltage combination includes: It provides the main accelerating electric field for the drain-source voltage; The gate-source voltage affects the channel carrier concentration and the pinch-off point location. The threshold voltage reflects the device's turn-on characteristics. Therefore, the weak multiplication ionization factor equation essentially establishes an analytical expression that combines the macroscopic effects of collisional ionization (carrier multiplication) with the device's terminal voltage ( , ) and internal state variables ( Directly linked, the equation not only has a clear physical meaning, but its relatively concise mathematical form also facilitates efficient numerical solutions for embedded coupled systems. Through this functional relationship, the model can accurately reflect the nonlinear characteristics of the collision ionization rate as a function of the bias voltage, providing an important physical basis for subsequent simulation of current warping.

[0038] Specifically, the channel current equation is: , in, Channel current; It is the conductivity factor; Gate-source voltage; Threshold voltage; This is the drain-source voltage; Capacitance per unit area of ​​the top silicon film capacitance per unit area of ​​gate oxide layer The ratio, that is ; The channel length modulation coefficient, This is the saturation drain-source voltage; The threshold voltage equation is: , in, Threshold voltage; This is the zero-body bias threshold voltage; The body bias effect coefficient. For the body Fermi potential; This is the body source voltage; The emitter current equation of a parasitic bipolar transistor is: , in, This refers to the emitter current of a parasitic bipolar transistor. It is the reverse saturation current; This is the body source voltage; The emission coefficient; Thermoelectric potential; The equation for the volume source voltage is: , in, This is the body source voltage; For body contact resistance; This is the proportionality coefficient of the collector current flowing through the pinch-off region of the parasitic bipolar transistor. This represents the common-base current amplification factor of the parasitic bipolar transistor. The equation for the weak multiplication ionization factor is: , Where M is the weak multiplication ionization factor; and To multiply the ionization parameters; This is the drain-source voltage; Gate-source voltage; This is the threshold voltage.

[0039] These five equations are derived from the variable source voltage. The weak multiplication factor M forms a strongly coupled closed-loop system: the increase of the weak multiplication factor M determines... The increase, and the increase after It will also lower the threshold voltage at the same time. And exponentially increase the emitter current of the parasitic bipolar transistor Threshold voltage The changes in this factor, in turn, affect the calculation of the weak multiplication ionization factor M. This closed-loop feedback mechanism, for the first time, completely and explicitly unifies the four physical processes of weak multiplication ionization, volume charge accumulation, volume bias effect, and parasitic transistor conduction in the model, thereby fundamentally describing the complex current warping behavior under high drain voltage.

[0040] As one implementation method, in this embodiment of the application, step S13 includes: S131. Solve the strongly nonlinear coupled equations under different bias voltages using the fixed-point iteration method. In this embodiment, since the strongly nonlinear coupled equations cannot be solved analytically directly, a numerical method is used for solving them. The fixed-point iteration method is chosen because of its simple format, ease of implementation, and applicability to such coupled systems composed of explicit functional relationships.

[0041] For the system of five strongly nonlinearly coupled equations, a fixed-point iteration method is used for numerical solution. For each given bias voltage point ( The first iteration calculation process is as follows: First, initialize the source voltage. The estimated value (e.g.) = 0), using body source voltage The initial values ​​are used to calculate the threshold voltage based on the threshold voltage equation and the parasitic bipolar transistor emitter current equation. The first iteration value, the emitter current of the parasitic bipolar transistor The first iteration value; based on the channel current equation and the weak multiplication ionization factor equation, using the threshold voltage. The first iteration value is used to calculate the channel current. The first iteration value of the weakly multiplying ionization factor M; based on the volume source voltage equation, using the first iteration value of the weakly multiplying ionization factor M and the channel current. The first iteration value and Bipolar transistor emitter current The first iteration value is used to calculate the first iteration value of the body source voltage; For the (n+1)th iteration, the variable values ​​from the nth iteration are used sequentially to update each variable, which can be done using the volume source voltage. The threshold voltage is calculated based on the threshold voltage equation and the parasitic bipolar transistor emitter current equation for the nth iteration value. The (n+1)th iteration value, the emitter current of the parasitic bipolar transistor The (n+1)th iteration value; based on the channel current equation and the weak multiplication ionization factor equation, using the threshold voltage. The nth iteration value is used to calculate the channel current. The (n+1)th iteration value and the (n+1)th iteration value of the weakly multiplying ionization factor M; based on the volume source voltage equation, using the nth iteration value of the weakly multiplying ionization factor M and the channel current. The sum of the nth iteration value Bipolar transistor emitter current The nth iteration value is used to calculate the (n+1)th iteration value of the volume source voltage; Alternatively, it can be based on the channel current equation, using the threshold voltage. The nth iteration value is used to calculate the channel current. The (n+1)th iteration value; based on the threshold voltage equation, using the volume source voltage. The threshold voltage is calculated based on the nth iteration value. The (n+1)th iteration value; based on the emitter current equation of a parasitic bipolar transistor, using the body source voltage. The nth iteration value is used to calculate the emitter current of the parasitic bipolar transistor. The (n+1)th iteration value; based on the weakly multiplying ionization factor equation, using the threshold voltage. The nth iteration value is used to calculate the (n+1)th iteration value of the weakly multiplying ionization factor M; based on the body source voltage equation, the nth iteration value of the weakly multiplying ionization factor M and the channel current are used. The sum of the nth iteration value Bipolar transistor emitter current The nth iteration value is used to calculate the (n+1)th iteration value of the source voltage, where n is a positive integer greater than or equal to 1.

[0042] S132. Continue until the current iteration value of all variables in the equation system satisfies the preset convergence criterion with the previous iteration value, and use the corresponding drain current value as the predicted value.

[0043] In this embodiment, a preset convergence criterion is used to determine whether the iterative calculation has reached the required accuracy. Specifically, for any variable x, when | - |<ε | When | ε is reached, the variable can be considered to have converged, where ε is a preset tolerance (e.g., ...). When all five variables in the system of equations ( , , , When both M and M satisfy this criterion, it indicates that the iterative solution is sufficiently self-consistent and the system of equations has reached equilibrium. At this point, the iteration is terminated, and the total drain current (composed of channel current and part of parasitic bipolar transistor collector current) calculated at this moment is taken as the final prediction under this bias voltage point.

[0044] As one implementation method, in this embodiment of the application, when solving the strongly nonlinear coupled equations under different bias voltages, the iterative solutions of each variable of the equations that satisfy the preset convergence criterion under the previous bias voltage are used as the initial values ​​of each variable of the equations under the current bias voltage.

[0045] In this embodiment, this method can be called a "hot start" strategy. Its principle is that when along the voltage axis (e.g., ...) When solving continuously, the internal states of the device (body potential, threshold voltage, etc.) at adjacent bias points usually change gradually. Therefore, using the complete solution vector of the previous converged bias point as the initial value for the iterative calculation of the next bias point can provide a starting point that is very close to the new solution. This strategy can significantly accelerate the convergence process of subsequent bias points and reduce the number of iterations. At the same time, since the initial value is closer to the true solution, it also greatly improves the numerical stability of the iterative algorithm in the strongly nonlinear region and avoids the divergence problem caused by improper initial value setting. This is the key to achieving efficient and robust simulation.

[0046] In one embodiment of this application, before or after step S13, the method further includes: S21. Obtain the measured current-voltage data set of silicon-on-insulator devices; In this embodiment, specific silicon-on-insulator devices (e.g.) can be used. Figure 2 and Figure 3 The partially depletion-type silicon-on-insulator (PDSOI) NMOSFET with a T-shaped gate contact structure was tested. During the test, multiple different gate-source voltages were fixed, and the drain-source voltage was scanned under each gate-source voltage to measure the corresponding drain current.

[0047] For example, in a specific test, four gate-source voltages are selected. The values ​​are 0.8V, 1.6335V, 2.4665V, and 3.3V, and the gate-source voltage is... Next, the drain-source voltage will be... The drain-source voltage is varied from 0 to 3.65V in steps of approximately 50mV (or by uniformly selecting approximately 73 voltage points). And using equipment such as the Keithley 4200B semiconductor parameter analyzer, each bias condition was precisely measured. , Drain current under ) .

[0048] By combining all these measured bias points with their corresponding drain current values, a measured current-voltage dataset is constructed. This dataset can be visually plotted as follows: Figure 5 The series of output characteristic curves shown ( - (Curve family).

[0049] S22. Based on the measured current-voltage dataset, adjust the parameters in the equivalent circuit model and / or the strongly nonlinear coupled equations so that the predicted drain currents of the silicon-on-insulator device under different drain-source voltages fit the measured current-voltage dataset.

[0050] In this embodiment, the silicon-on-insulator device can be a partially depletion-type silicon-on-insulator (PDSOI) NMOSFET with a T-shaped gate contact structure. Its key device parameters include: a bulk doping concentration of Na of 2.5 × 10⁻⁶. cm - ³, the device width-to-length ratio is W / L=1.2 / 0.35 μm, and the operating voltage is VDD=3.3V.

[0051] The fitting process was based on measured current-voltage datasets obtained under specific test conditions, including: a test temperature of room temperature (300 K); the use of a Keithley 4200B semiconductor parameter analyzer as the test equipment; and gate-source voltage. Select multiple fixed values ​​(e.g., 0.8 V, 1.6335 V, 2.4665 V, 3.3 V) within the range of 0 V to 2.5 V; drain-source voltage Scanning was performed in the range of 0 V to 3.65 V; body contact voltage Fixed at 0 V.

[0052] Parameter tuning and fitting can be performed using a dedicated software system that integrates numerical solution algorithms for strongly nonlinear coupled equations (such as...). Figure 6 (As shown) This process is completed, specifically including the following steps: 1. Model initialization and parameter input: In a dedicated software system with an integrated numerical solver, a set of initial values ​​for the model parameters to be adjusted are input. These parameters at least include: the reverse saturation current of the parasitic bipolar transistor. Emission coefficient n, equivalent volume contact resistance The proportionality coefficient k of collector current participating in collisional ionization, the common base current amplification factor α, and the weak multiplication ionization model parameters A and B. 2. Numerical solution and current prediction: For each bias point in the measured dataset ( , The system calls a fixed-point iterative algorithm to solve the strongly nonlinear coupled equations and calculates the predicted drain current under this condition. .

[0053] 3. Iterative optimization and parameter calibration: The system iteratively adjusts the model parameters using optimization algorithms (such as least squares or gradient descent) to minimize the overall error (e.g., root mean square error) between the predicted current sequence and the measured current values. This iterative process continues until the predicted current sequence is found to be accurate. - The family of curves achieves optimal fit with measured data across the entire range of gate and drain voltages, such as... Figure 7 As shown in the figure, the solid lines represent predicted data, and the dashed lines represent measured data. 4. Model Validation and Physical Consistency Analysis: After obtaining the optimal parameter set, the evolution curves of the internal physical variables output by the model can be further utilized, such as quantitatively decomposing the contribution of each current component to the warping effect (e.g., Figure 8 As shown), parasitic bipolar transistor emitter current As the drain-source voltage changes (e.g.) Figure 9 (As shown), body source voltage Threshold voltage and the weakly multiplying ionization factor M varies with drain-source voltage Changes (such as) Figure 10 As shown), these analyses can be used to verify the physical correctness of the internal coupling relationships of the model, for example (M 1) With body source voltage The linear relationship that should exist between them (e.g.) Figure 11 (As shown). 5. Final parameters determined: After calibration using the above process, a set of model parameter values ​​matching the specific device process and test conditions are obtained (examples are shown in Table 1 below), thereby establishing a reliable model that can be used to accurately simulate the electrical characteristics of this type of PDSOI device in high leakage voltage and even the entire operating range.

[0054] Table 1

[0055] After fitting, the accuracy and physical consistency of the model were verified through comparative analysis. The drain current-drain source voltage curves predicted by the model after parameter adjustment are shown below. Figure 7 As shown, at different gate voltages ( The results showed a high degree of agreement with the measured data, accurately reproducing the voltage and current jump amplitude at the onset of the warping effect. Furthermore, the fitted model was used to analyze internal physical quantities and decompose current components to verify the completeness of its physical mechanism. = 1.6335V as an example (e.g.) Figure 8As shown, the model quantifies the contribution of each physical effect to the total current: the channel current increment caused solely by the body bias effect is approximately 7.4%, while the measured total current increment reaches approximately 34.8%, with the difference mainly contributed by the collector current of the activated parasitic bipolar transistor. This decomposition result demonstrates that the established coupled model simultaneously captures both the body bias effect and the parasitic bipolar transistor conduction effect; their combined action is necessary to fully explain the warping phenomenon under high drain voltage, reflecting the physical completeness of the modeling method. Meanwhile, the model outputs the internal key variable (volume source voltage). Threshold voltage and the weakly multiplying ionization factor M) varies with drain-source voltage The relationship of change is as follows Figure 10 As shown. In the region where warping occurs, these variables exhibit strong nonlinearity and mutual coupling characteristics. In particular, as... Figure 11 As shown, (M) 1) With body source voltage The equations exhibit a significant linear relationship, directly confirming the physical correctness of equation four in the strongly nonlinear coupling equation set (i.e., the current balance equation established by the hole current dominated by the body potential generated by weak multiplication ionization). Therefore, the parameter adjustment process not only achieves data fitting at the curve level, but also ensures the self-consistency and authenticity of the physical relationships within the model, thus obtaining a reliable simulation model with both high prediction accuracy and clear physical meaning.

[0056] like Figure 12 As shown, this application embodiment also provides a modeling device 200 for the floating body effect of silicon-on-insulator devices, including: a processor 21, a memory 22 and a communication bus 23; Communication bus 23 is used to realize the connection and communication between processor 21 and memory 22; The processor 21 is used to execute the modeling processing program for the floating effect of silicon-on-insulator devices stored in the memory 22, so as to implement the steps of any of the above-described modeling methods for the floating effect of silicon-on-insulator devices.

[0057] like Figure 13 As shown, this application also provides a modeling system for the floating body effect of silicon-on-insulator devices, including: the modeling device 200 as described above, and a human-computer interaction device 300 connected to the modeling device 200; The human-computer interaction device 300 is used to allow users to input operation commands and measured current-voltage datasets, and to display the prediction results output by the modeling device 200.

[0058] In this embodiment, the modeling device 200 is a hardware computing platform that executes the modeling method. Its built-in processor runs a dedicated program stored in the memory to specifically realize the construction of the equivalent circuit model, the establishment of a strongly nonlinear coupled equation system, and the numerical solution and prediction functions based on the fixed-point iteration method.

[0059] The human-computer interaction device 300 is an input / output terminal connected to the modeling device, which provides a graphical user interface (such as...). Figure 6 As shown), it is used to receive model parameters and measured datasets input by the user, and to visualize the prediction curves calculated by the modeling device (such as...). Figure 7 ), parameter fitting results (as shown in Table 1) and internal physical quantity analysis charts (as shown in Table 2) Figures 8 to 11 The system encapsulates the complex physical modeling and numerical calculation process in the backend and provides a complete parameter extraction and simulation verification process through a user-friendly human-computer interface.

[0060] This application also provides a readable storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the steps of any of the above-described methods for modeling the floating body effect of silicon-on-insulator devices.

[0061] The embodiments in this specification are described in a progressive manner, with each embodiment focusing on the aspects related to... For any differences between the embodiments, or for the same or similar parts between the embodiments, please refer to each other.

[0062] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for modeling the floating body effect of silicon-on-insulator devices, characterized in that, include: An equivalent circuit model is established to simulate the electrical characteristics of the silicon-on-insulator device under weak multiplication ionization conditions. Based on the equivalent circuit model, a strongly nonlinear coupled set of equations is established, including channel current, threshold voltage, parasitic bipolar transistor current, body source voltage, and weak multiplication ionization factor. The weak multiplication ionization factor is used to characterize the weak multiplication ionization effect, and the value of the body source voltage is determined by the equation including the weak multiplication ionization factor. Based on the strongly nonlinear coupled equations, the drain current of the silicon-on-insulator device under high drain-source voltage is predicted.

2. The method according to claim 1, characterized in that, The equivalent circuit model includes: a first current branch representing the channel current, a second current branch representing the emitter current of the parasitic bipolar transistor, a third current branch representing the hole current generated by the weak multiplication ionization effect, and a resistance branch representing the bulk contact resistance. The second current branch and the third current branch are both connected to a common internal body node.

3. The method according to claim 1, characterized in that, The strongly nonlinear coupling equation set includes the channel current equation, the threshold voltage equation, the parasitic bipolar transistor emitter current equation, the volume source voltage equation, and the weak multiplication ionization factor equation, wherein the volume source voltage equation includes the weak multiplication ionization factor.

4. The method according to claim 3, characterized in that, The weak multiplication ionization factor equation is a function of drain-source voltage, gate-source voltage, and threshold voltage.

5. The method according to claim 1, characterized in that, The prediction of the drain current of the silicon-on-insulator device under high drain-source voltage based on the strongly nonlinear coupled equations includes: The strongly nonlinear coupled equations under different bias voltages are solved using the fixed-point iteration method. The process continues until the current iteration value of all variables in the system of equations satisfies the preset convergence criterion with the previous iteration value, and the corresponding drain current value is used as the predicted value.

6. The method according to claim 5, characterized in that, When solving the strongly nonlinear coupled equations under different bias voltages, the iterative solutions of each variable of the equations that satisfy the preset convergence criterion under the previous bias voltage are used as the initial values ​​of each variable of the equations under the current bias voltage.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: Obtain the measured current-voltage data set of the silicon-on-insulator device; Based on the measured current-voltage dataset, the parameters in the equivalent circuit model and / or the strongly nonlinear coupling equations are adjusted so that the predicted drain currents of the silicon-on-insulator device at different drain-source voltages fit the measured current-voltage dataset.

8. A modeling apparatus for the floating body effect of silicon-on-insulator devices, characterized in that, include: Processor, memory, and communication bus; The communication bus is used to realize the connection and communication between the processor and the memory; The processor is used to execute a modeling processing program for the floating effect of silicon-on-insulator devices stored in the memory, so as to implement the steps of the modeling method for the floating effect of silicon-on-insulator devices as described in any one of claims 1-7.

9. A modeling system for the floating body effect of silicon-on-insulator devices, characterized in that, include: The modeling apparatus as described in claim 8, and the human-computer interaction device connected to the modeling apparatus; The human-computer interaction device is used to allow users to input operation commands and measured current-voltage datasets, and to display the prediction results output by the modeling device.

10. A readable storage medium, characterized in that, The readable storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the steps of the modeling method for the floating body effect of silicon-on-insulator devices as described in any one of claims 1 to 7.

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