Transistor structure, semiconductor structure and preparation method thereof

Abstract

The invention discloses a transistor structure, a semiconductor structure and a preparation method thereof, and the transistor structure comprises a dielectric structure which is provided with a first side wall parallel to a first direction; the first source and drain electrode structure and the second source and drain electrode structure are located on the two sides of the dielectric structure in the first direction respectively, the first source and drain electrode structure is provided with a second side wall parallel to the first direction, and the second source and drain electrode structure is provided with a third side wall parallel to the first direction; the gate stack surrounds the first side wall of the dielectric structure, a part of the second side wall of the first source and drain electrode structure and a part of the third side wall of the second source and drain electrode structure, the gate stack comprises a channel layer, a gate dielectric layer and a gate conductive layer which are stacked in sequence, and the channel layer is in contact with the first source and drain electrode structure and the second source and drain electrode structure. The transistor structure at least can improve the floating body effect.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a transistor structure, a semiconductor structure, and a method for fabricating the same. Background Technology

[0002] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technological barriers encountered by existing structures are becoming increasingly apparent. Therefore, developing more novel structures based on existing structures is a powerful means to break through existing technological barriers.

[0003] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM that includes multilayer horizontal cell (MHC), typically comprising multiple transistors stacked on a substrate, has met the above requirements.

[0004] However, since the transistor is suspended on the substrate, charge tends to accumulate in the channel region of the transistor, resulting in a floating body effect. This leads to problems such as warping, parasitic bipolar transistor effect, and threshold voltage drift, which affect the performance of the semiconductor structure. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a transistor structure is provided, comprising: a dielectric structure having a first sidewall parallel to a first direction; a first source-drain structure and a second source-drain structure, the first source-drain structure and the second source-drain structure being located on opposite sides of the dielectric structure along the first direction, the first source-drain structure having a second sidewall parallel to the first direction, and the second source-drain structure having a third sidewall parallel to the first direction; and a gate stack surrounding the first sidewall of the dielectric structure, a portion of the second sidewall of the first source-drain structure, and a portion of the third sidewall of the second source-drain structure, the gate stack comprising a channel layer, a gate dielectric layer, and a gate conductive layer stacked sequentially, the channel layer being in contact with the first source-drain structure and the second source-drain structure.

[0006] In some embodiments, the first sidewall of the dielectric structure, the second sidewall of the first source-drain structure, and the third sidewall of the second source-drain structure are flush.

[0007] In some embodiments, the ends of the channel layer, gate dielectric layer, and gate conductive layer along the first direction are all flush with the vertical direction.

[0008] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a stacked group, the stacked group including a plurality of transistor structures stacked along a vertical direction, each transistor structure including a dielectric structure, a gate stack, a first source-drain structure, and a second source-drain structure; wherein the plurality of dielectric structures are spaced apart along the vertical direction, each dielectric structure having a first sidewall parallel to a first direction; the first source-drain structure and the second source-drain structure are respectively located on both sides of each dielectric structure along the first direction, the first source-drain structure having a second sidewall parallel to the first direction, and the second source-drain structure having a third sidewall parallel to the first direction; the gate stack surrounds the first sidewall of the dielectric structure, a portion of the second sidewall of the first source-drain structure, and a portion of the third sidewall of the second source-drain structure, the gate stack including a channel layer, a gate dielectric layer, and a gate conductive layer stacked sequentially, the gate conductive layer extending along the vertical direction, and the plurality of transistor structures being coupled to each other through the gate conductive layer.

[0009] In some embodiments, a plurality of stacked groups are arranged at intervals along a second direction, and the semiconductor structure further includes a word line isolation structure located between the plurality of stacked groups, wherein the dimension of the word line isolation structure along a first direction is greater than or equal to the dimension of the gate stack along the first direction.

[0010] In some embodiments, the dimension of the word line isolation structure along the first direction is smaller than the spacing between the opposite ends of the first source-drain structure and the second source-drain structure, and the semiconductor structure further includes a first isolation structure and a second isolation structure located on both sides of the word line isolation structure along the first direction.

[0011] In some embodiments, the semiconductor structure further includes source-drain isolation structures located on both sides of the gate stack along a first direction, the source-drain isolation structures being sandwiched between adjacent first source-drain structures in the vertical direction and between adjacent second source-drain structures in the vertical direction.

[0012] In some embodiments, the first sidewall of the dielectric structure, the second sidewall of the first source-drain structure, and the third sidewall of the second source-drain structure are flush.

[0013] According to a third aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising: forming a stacked structure, the stacked structure including a first dielectric layer and a second dielectric layer alternately stacked along a vertical direction; removing the first dielectric layer to form a word line trench exposing a first sidewall of the second dielectric layer, and sacrificial portions located on both sides of the word line trench along a first direction; forming an initial gate stack in the word line trench; removing the sacrificial portions to form a first gap trench; and removing a portion of the exposed initial gate stack along the first gap trench to form a gate stack, the gate stack including a channel layer, a gate dielectric layer, and a gate conductor stacked sequentially. An electrical layer and a gate conductive layer extend vertically; a portion of the second dielectric layer is removed to form a dielectric structure and second gap trenches located on both sides of the dielectric structure, the size of the second gap trenches along the first direction being larger than the size of the first gap trenches along the first direction; a first source-drain structure and a second source-drain structure are formed on both sides of the dielectric structure along the first direction, the first source-drain structure having a second sidewall parallel to the first direction, the second source-drain structure having a third sidewall parallel to the first direction, and a gate stack surrounding the first sidewall of the dielectric structure, a portion of the second sidewall of the first source-drain structure, and a portion of the third sidewall of the second source-drain structure.

[0014] In some embodiments, after the plurality of stacked structures are spaced apart along the second direction to form the plurality of stacked structures, the method further includes: forming a first sacrificial structure and a first isolation structure and a second isolation structure located on both sides of the first sacrificial structure along the second direction in a first spacing groove between the plurality of stacked structures.

[0015] In some embodiments, removing the first dielectric layer includes: performing lateral etching along two end faces of the first dielectric layer in a first direction to remove a portion of the first dielectric layer and form a first gap trench; filling the first gap trench with a sacrificial portion; and removing the remaining first dielectric layer and the first sacrificial structure to form a word line trench.

[0016] In some embodiments, the initial gate stack includes a channel material layer and a gate dielectric material layer sequentially formed on the surface of the first sidewall and the sacrificial portion of the second dielectric layer exposed in the word line trench, and a conductive material layer filled in the word line trench; removing a portion of the exposed initial gate stack along the first gap trench includes: removing a portion of the exposed channel material layer along the first gap trench to form a channel layer; and removing a portion of the exposed gate dielectric material layer along the first gap trench to form a gate dielectric layer.

[0017] In some embodiments, after removing the exposed portion of the initial gate stack along the first gap trench, the method further includes: forming a second gap trench that extends vertically through the initial gate stack, the second gap trench dividing the initial gate stack into a plurality of gate stacks spaced apart along a second direction; and filling the second gap trench with word line isolation structures.

[0018] In this embodiment of the present disclosure, by forming a channel layer on the surface of the dielectric structure and reducing the thickness of the channel layer, the floating body effect is improved and the performance of the transistor in the semiconductor structure is enhanced. In addition, while ensuring the electrical connection between the channel layer and the first source-drain structure and the second source-drain structure, the overlap area between the channel layer and the first source-drain structure and the second source-drain structure can be reduced, effectively reducing parasitic capacitance and improving the response speed of the transistor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1A This is a three-dimensional schematic diagram of a transistor structure according to an exemplary embodiment;

[0021] Figure 1B This is a three-dimensional schematic diagram of a transistor structure according to another exemplary embodiment;

[0022] Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0023] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0024] Figures 4A-16B This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an exemplary embodiment, wherein, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8 , Figure 9 , Figure 10A , Figure 11A , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A This is a partial three-dimensional schematic diagram of a semiconductor structure during the fabrication process. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 10B , Figure 11B , Figure 16B This is a partial cross-sectional schematic diagram of a semiconductor structure during its fabrication process. Detailed Implementation

[0025] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0026] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0027] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0028] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0029] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0030] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0031] Figure 1A This is a three-dimensional schematic diagram of a transistor structure TR according to an exemplary embodiment. Figure 1B This is a three-dimensional schematic diagram of a transistor structure TR according to another exemplary embodiment. Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0032] The following will combine Figure 1A and Figure 1BThe transistor structure TR provided in the embodiments of this disclosure will be described in detail.

[0033] Reference Figure 1A and Figure 1B As shown, the transistor structure TR includes a dielectric structure 122, which has a first sidewall s1 parallel to the first direction D1; a first source-drain structure 310 and a second source-drain structure 320, which are located on opposite sides of the dielectric structure 122 along the first direction D1, respectively. The first source-drain structure 310 has a second sidewall s2 parallel to the first direction D1, and the second source-drain structure 320 has a third sidewall s3 parallel to the first direction D1; and a gate stack 410, which at least partially surrounds the first sidewall s1 of the dielectric structure 122, a portion of the second sidewall s2 of the first source-drain structure 310, and a portion of the third sidewall s3 of the second source-drain structure 320. The gate stack 410 includes a channel layer 411, a gate dielectric layer 412, and a gate conductive layer 413 stacked sequentially, with the channel layer 411 in contact with the first source-drain structure 310 and the second source-drain structure 320.

[0034] In the transistor structure provided in this disclosure, firstly, by forming a channel layer on the surface of the dielectric structure and reducing the thickness of the channel layer, the floating body effect is improved, thereby enhancing the transistor's performance. Secondly, while ensuring the electrical connection between the channel layer and the first source-drain structure and the second source-drain structure, the overlap area between the channel layer and the first source-drain structure and the second source-drain structure can be reduced, effectively reducing parasitic capacitance and improving the transistor's response speed.

[0035] In some embodiments, the material of the channel layer 411 may be monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, and oxide semiconductor materials (e.g., zinc tin oxide (ZnO)). x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn) x O), Indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium silicon oxide (In) x Ga y Si z O, commonly known as "IGSO"), indium tin oxide (In) x Sn yHafnium oxide (commonly known as "ITO") and one or more other similar materials. In one example, the channel material layer 411' is made of IGZO. The gate dielectric layer 412 can be made of a high-dielectric-constant dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The high-dielectric-constant dielectric material may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, etc. The gate conductive layer 413, the first source-drain structure 310, and the second source-drain structure 320 are all made of conductive materials. The conductive material may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). In one example, the channel layer 411 is made of IGZO, the gate conductive layer 413 is indium tin oxide (ITO), and the first source-drain structure 310 and the second source-drain structure 320 are bilayer structures composed of titanium nitride layers and tungsten layers, respectively.

[0036] In some examples, refer to Figure 1A As shown, the gate stack 410 covers a portion of the first sidewall s1 of the dielectric structure 122, such as two opposite sidewalls in the vertical direction D3, i.e., the transistor structure TR can be a dual-gate transistor.

[0037] In some examples, refer to Figure 1B As shown, the gate stack 410 covers all the first sidewalls s1 of the dielectric structure 122, such as the two opposite sidewalls in the vertical direction D3 and the two opposite sidewalls in the second direction D2, that is, the transistor structure TR can be a full-ring gate transistor.

[0038] In some embodiments, the first sidewall s1 of the dielectric structure 122, the second sidewall s2 of the first source-drain structure 310, and the third sidewall s3 of the second source-drain structure 320 are flush. The first sidewall s1, the second sidewall s2, and the third sidewall s3 are located in the same plane, that is, the dielectric structure 122, the first source-drain structure 310, and the second source-drain structure 320 have substantially the same dimensions in the vertical direction D3, and their dimensions in the second direction D2 are also substantially the same. By improving structural uniformity, leakage current in the transistor structure can be avoided, thereby improving the performance of the transistor structure.

[0039] In some embodiments, the dielectric structure 122 may be made of dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride. For example, the dielectric structure 122 may be made of silicon oxide. The dimension of the gate stack 410 along the first direction D1 is larger than the dimension of the dielectric structure 122 along the first direction D1. By providing the dielectric structure 122, the floating body effect caused by charge accumulation in the transistor structure can be avoided.

[0040] In some embodiments, the ends of the channel layer 411, the gate dielectric layer 412, and the gate conductive layer 413 along the first direction D1 are all flush with the vertical direction D3. That is, the dimensions of the channel layer 411, the gate dielectric layer 412, and the gate conductive layer 413 along the first direction D1 are substantially the same.

[0041] The following will combine Figure 2 The semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0042] Reference Figure 2 As shown, the semiconductor structure includes a stacked group SG, which includes multiple transistor structures TR stacked along the vertical direction D3. Each transistor structure TR includes a dielectric structure 122, a gate stack 410, a first source-drain structure 310, and a second source-drain structure 320. The multiple dielectric structures 122 are spaced apart along the vertical direction D3, and each dielectric structure 122 has a first sidewall s1 parallel to the first direction D1. The first source-drain structure 310 and the second source-drain structure 320 are located on opposite sides of each dielectric structure 122 along the first direction D2. Structure 310 has a second sidewall s2 parallel to the first direction D1, and the second source-drain structure 320 has a third sidewall s3 parallel to the first direction D1; the gate stack 410 surrounds the first sidewall s1 of the dielectric structure 122, a portion of the second sidewall s2 of the first source-drain structure 310 and a portion of the third sidewall s3 of the second source-drain structure 320. The gate stack 410 includes a channel layer 411, a gate dielectric layer 412 and a gate conductive layer 413 stacked sequentially. The gate conductive layer 413 extends along the vertical direction D3, and multiple transistor structures TR are coupled to each other through the gate conductive layer 413.

[0043] In the semiconductor structure provided in this disclosure, firstly, by providing transistor structures stacked in the vertical direction, the integration density of the semiconductor structure can be improved. Secondly, in the transistor structure, by forming a channel layer on the surface of the dielectric structure and reducing the thickness of the channel layer, the floating body effect can be improved, thereby enhancing the performance of the transistor in the semiconductor structure. Thirdly, while ensuring the electrical connection between the channel layer and the first source-drain structure and the second source-drain structure, the overlap area between the channel layer and the first source-drain structure and the second source-drain structure can be reduced, effectively reducing parasitic capacitance and improving the response speed of the transistor.

[0044] It is understandable that multiple transistor structures TR are coupled to each other through the gate conductive layer 413, meaning that multiple transistor structures TR in the same stack group SG are controlled to turn on and off through the same gate conductive layer 413.

[0045] In some embodiments, a plurality of stacked groups SG are spaced apart along a second direction D2. The semiconductor structure further includes a word line isolation structure 510 located between the plurality of stacked groups SG. The size of the word line isolation structure 510 along a first direction D1 is greater than or equal to the size of the gate stack 410 along the first direction D1. Each stacked group SG is surrounded by a gate stack 410. Adjacent gate stacks 410 are spaced apart along the second direction D2 and separated by word line isolation structures 510.

[0046] In some embodiments, the dimension of the word line isolation structure 510 along the first direction D1 is smaller than the spacing between the opposite ends of the first source-drain structure 310 and the second source-drain structure 320. The semiconductor structure further includes a first isolation structure 211 and a second isolation structure 212 located on both sides of the word line isolation structure 510 along the first direction D1. The first isolation structure 211 and the second isolation structure 212 can be formed simultaneously and extend along the vertical direction D3. The top surfaces of the first isolation structure 211 and the second isolation structure 212 are flush with the top surface of the word line isolation structure 510, and may also be flush with the top surface of the gate stack 410. The bottom surfaces of the first isolation structure 211 and the second isolation structure 212 may be lower than or flush with the bottom surface of the gate stack 410.

[0047] In some embodiments, the semiconductor structure further includes source-drain isolation structures 302 located on both sides of the gate stack 410 along the first direction D1, the source-drain isolation structures 302 being sandwiched between adjacent first source-drain structures 310 in the vertical direction D3 and between adjacent second source-drain structures 320 in the vertical direction D3. The material of the source-drain isolation structure 302 can be a dielectric material. In one example, the material of the source-drain isolation structure 302 is aluminum oxide.

[0048] In some embodiments, in the semiconductor structure, the first sidewall s1 of the dielectric structure 122, the second sidewall s2 of the first source-drain structure 310, and the third sidewall s3 of the second source-drain structure 320 are flush.

[0049] In some embodiments, in the semiconductor structure, the ends of the channel layer 411, the gate dielectric layer 412, and the gate conductive layer 413 along the first direction D1 are all flush with the vertical direction D3.

[0050] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 3 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; Figures 4A-16BThis is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an exemplary embodiment, wherein, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8 , Figure 9 , Figure 10A , Figure 11A , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16A This is a partial three-dimensional schematic diagram of a semiconductor structure during the fabrication process. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 10B , Figure 11B , Figure 16B This is a partial cross-sectional schematic diagram of a semiconductor structure during its fabrication process.

[0051] Reference Figure 3 As shown, the preparation method includes at least the following steps:

[0052] S11: Forming a stacked structure, the stacked structure including a first dielectric layer and a second dielectric layer alternately stacked in the vertical direction;

[0053] S12: Remove the first dielectric layer to form a word line groove that exposes the first sidewall of the second dielectric layer, and a sacrificial portion located on both sides of the word line groove along the first direction;

[0054] S13: Form the initial gate stack in the word line trench;

[0055] S14: Remove the sacrificial part to form the first gap groove;

[0056] S15: Remove the exposed portion of the initial gate stack along the first gap trench to form a gate stack, the gate stack including a channel layer, a gate dielectric layer and a gate conductive layer stacked sequentially, the gate conductive layer extending in the vertical direction;

[0057] S16: Remove part of the second dielectric layer to form a dielectric structure and second gap grooves located on both sides of the dielectric structure, wherein the size of the second gap groove along the first direction is larger than the size of the first gap groove along the first direction;

[0058] S17: A first source-drain structure and a second source-drain structure are formed on both sides of the dielectric structure along the first direction. The first source-drain structure has a second sidewall parallel to the first direction, and the second source-drain structure has a third sidewall parallel to the first direction. The gate stack surrounds the first sidewall of the dielectric structure, a portion of the second sidewall of the first source-drain structure, and a portion of the third sidewall of the second source-drain structure.

[0059] It should be understood that Figure 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 3 The steps shown can be adjusted in order according to actual needs.

[0060] In the semiconductor structure fabrication method disclosed herein, firstly, by first forming a sacrificial portion and then forming an initial gate stack, the initial gate stack can be partially etched by removing the first gap trench exposed by the sacrificial portion to disconnect the channel layer between different transistors. This reduces the process difficulty of removing parasitic channels and allows for precise control of the channel layer length. Secondly, by covering the surface of the dielectric structure with a channel layer and reducing the thickness of the channel layer, the floating body effect can be improved, thereby enhancing the performance of transistors in the semiconductor structure. Thirdly, while ensuring the electrical connection between the channel layer and the first source-drain structure and the second source-drain structure, the overlap area between the channel layer and the first source-drain structure and the second source-drain structure can be reduced, effectively reducing parasitic capacitance.

[0061] The following will combine Figures 4A-16B The method for fabricating the semiconductor structure provided in this disclosure will be described in detail. It should be noted that the first direction D1 and the second direction D2 used in this disclosure are horizontal directions parallel to the plane of the substrate 101, and the first direction D1 intersects the second direction D2. For example, the first direction D1 may be perpendicular to the second direction D2. The vertical direction D3 is a direction that intersects the plane of the substrate 101. For example, the vertical direction D3 is perpendicular to the plane of the substrate 101. That is, the first direction D1, the second direction D2, and the vertical direction D3 are all perpendicular to each other.

[0062] In some embodiments, refer to Figure 4A and 4B As shown, where, Figure 4B The middle left image is Figure 4A A schematic cross-sectional view along section AA'. Figure 4B The right image in the middle is Figure 4AA cross-sectional view along section BB' is shown. An initial stacked structure 110' is formed on substrate 101, comprising a first dielectric layer 111 and a second dielectric layer 112 alternately stacked along the vertical direction D3. The substrate 101 is made of semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The first dielectric layer 111 and the second dielectric layer 112 are made of dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride, and the material of the first dielectric layer 111 is different from the material of the second dielectric layer 112. In one example, the first dielectric layer 111, which is in direct contact with the substrate 101, is made of silicon nitride, and the second dielectric layer 112 is made of silicon oxide. In another example, the first dielectric layer 111, which is in direct contact with the substrate 101, is made of silicon oxide, and the second dielectric layer 112 is made of silicon nitride.

[0063] In some embodiments, refer to Figure 5A and 5B As shown, where, Figure 5B The middle left image is Figure 5A A schematic cross-sectional view along section AA'. Figure 5B The right image in the middle is Figure 5A A cross-sectional view along section BB'. A first spacer T1 is formed through the initial stacked structure 110'. The first spacer T1 extends along the first direction D1. The size of the first spacer T1 along the first direction D1 is larger than the size of the first spacer T1 along the second direction D2. The first spacer T1 exposes part of the surface of the substrate 101. The remaining portions of the initial stacked structure 110' located on both sides of the first spacer T1 along the second direction D2 are used as the stacked structure 110. Multiple stacked structures 110 are arranged at intervals along the second direction D2.

[0064] In some embodiments, refer to Figure 6A and 6B As shown, where, Figure 6B The middle left image is Figure 6A A schematic cross-sectional view along section AA'. Figure 6B The right image in the middle is Figure 6AA cross-sectional view along section BB'. After forming multiple stacked structures 110, the method further includes: forming a first sacrificial structure 201 and a first isolation structure 211 and a second isolation structure 212 located on both sides of the first sacrificial structure 201 along the second direction D2 in a first spacer groove T1 between the multiple stacked structures 110. The first sacrificial structure 210, the first isolation structure 211 and the second isolation structure 212 fill the first spacer groove T1, and the top surfaces of the first sacrificial structure 210, the first isolation structure 211 and the second isolation structure 212 are flush with and may be higher than the top surface of the stacked structure 110.

[0065] In some embodiments, the materials of the first isolation structure 211 and the second isolation structure 212 are low dielectric constant materials, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide carbon oxide, silicon oxynitride, boron nitride, silicon boron carbon nitride, or silicon oxynitride carbon oxide. The first sacrificial structure 201 is a material with a high etch selectivity to the first isolation structure 211, the second isolation structure 212, the first dielectric layer 111, and the second dielectric layer 112, such as polysilicon, spin-coated carbon, etc.

[0066] In some embodiments, the first isolation structure 211 and the second isolation structure 212 may be formed simultaneously. After the first spacer T1 is filled with isolation material, a portion of the isolation material is removed to form a sacrificial hole exposing a portion of the surface of the substrate 101. The sacrificial hole is located in the middle of the first spacer T1, and a first sacrificial structure 201 is formed by filling the sacrificial hole with sacrificial material. The first sacrificial structure 201 contacts the two sidewalls of the first spacer T1 opposite to each other along the second direction D2, but does not contact the two sidewalls of the first spacer T1 opposite to each other along the first direction D1.

[0067] In some embodiments, refer to Figure 7A and 7B As shown, where, Figure 7B The middle left image is Figure 7A A schematic cross-sectional view along section AA'. Figure 7B The right image in the middle is Figure 7AA cross-sectional view along section BB'. A portion of the remaining initial stacked structure 110' is removed to form a first through hole K1 and a second through hole K2. The first through hole K1 and the second through hole K2 extend along the second direction D2 and expose both sides of the multiple stacked structures 110 along the first direction D1, including exposing the two end faces e1 / e2 of the first dielectric layer 111 along the first direction D1. The first through hole K1 and the second through hole K2 also expose the two opposite sides of the first isolation structure 211 and the second isolation structure 212 along the first direction D1; that is, the first through hole K1 exposes the side of the first isolation structure 211, and the second through hole K2 exposes the side of the second isolation structure 212. The first through hole K1 and the second through hole K2 are connected to the two opposite sidewalls of the first spacer groove T1 along the first direction D1.

[0068] In some embodiments, refer to Figure 7A , Figure 7B and Figure 8 As shown, removing the first dielectric layer 111 includes: performing lateral etching along the two end faces e1 / e2 of the first dielectric layer 111 in the first direction D1 to remove a portion of the first dielectric layer 111 and form a first gap groove P1; refer to Figure 9 As shown, the sacrificial portion 301 is filled in the first gap groove P1; the remaining first dielectric layer and the first sacrificial structure are removed to form a word line groove.

[0069] In some embodiments, a portion of the first dielectric layer 111 is removed by a lateral etching process (e.g., a wet etching process) to form first gap trenches P1 located on both sides of the remaining first dielectric layer 111 along the first direction D1. The remaining first dielectric layer 111 is used to define the length of the subsequently formed channel layer. Therefore, the length of the channel layer can be controlled by controlling the depth of the first gap trenches P1. The dimension of the remaining first dielectric layer 111 along the first direction D1 can be substantially equal to the dimension of the first sacrificial structure 201 along the first direction D1. For example, the ratio of the dimension of the remaining first dielectric layer 111 along the first direction D1 to the dimension of the first sacrificial structure 201 along the first direction D1 ranges from 0.9 to 1.

[0070] In some embodiments, the etching selectivity ratios of the first dielectric layer 111 and the second dielectric layer 112, the first isolation structure 211 and the second isolation structure 212 are all relatively large, for example, the etching selectivity ratio is greater than 20:1, so that the loss of the second dielectric layer 112, the first isolation structure 211 and the second isolation structure 212 is small during the lateral etching of the first dielectric layer 111.

[0071] In some embodiments, refer to Figure 9As shown, the sacrificial portion 301 may be located only in the first gap P1. For example, after depositing the sacrificial material, the sacrificial material located in the first through hole K1 and the second through hole K2 is removed, leaving only the sacrificial material located in the first gap P1 as the sacrificial portion 301. In other examples, the sacrificial portion 301 may also be located in the first through hole K1 and the second through hole K2. The material of the sacrificial portion 301 may be alumina.

[0072] In some embodiments, refer to Figure 10A and 10B As shown, where, Figure 10B The middle left image is Figure 10A A schematic cross-sectional view along section AA'. Figure 10B The right image in the middle is Figure 10A A cross-sectional view along section BB'. The remaining first dielectric layer 111 and the first sacrificial structure 201 are removed to form a word groove WT exposing the first sidewall s1 of the second dielectric layer 112. The word groove WT also exposes the surfaces of the sacrificial portion 301 opposite each other along the first direction D1. In one example, the first sacrificial structure 201 may be removed first to expose the remaining sidewall of the first dielectric layer 111 along the second direction D2 through a sacrificial hole, and then the remaining first dielectric layer 111 may be removed along the sacrificial hole. The first sidewall s1 of the second dielectric layer 112 exposed by the word groove WT is parallel to the first direction D1. The first sidewall s1 may include two sidewalls opposite each other along the second direction D2 and two sidewalls opposite each other along the vertical direction D3.

[0073] In some embodiments, refer to Figure 11A and 11B As shown, where, Figure 11B The middle left image is Figure 11A A schematic cross-sectional view along section AA'. Figure 11B The right image in the middle is Figure 11A A cross-sectional view along section BB' is shown. An initial gate stack 410' is formed in the word line trench WT. The initial gate stack 410' includes a channel material layer 411' and a gate dielectric material layer 412' sequentially formed on the surface of the first sidewall s1 and the sacrificial portion 301 of the second dielectric layer 112 exposed in the word line trench WT, and a conductive material layer 413' filling the word line trench WT. The channel material layer 411' conformally covers the surface of the first sidewall s1 and the sacrificial portion 301 of the second dielectric layer 112, the gate dielectric material layer 412' conformally covers the surface of the channel material layer 411', and the conductive material layer 413' covers the surface of the gate dielectric layer 412' and fills the word line trench WT. The initial gate stack 410' surrounds the first sidewall s1 of the second dielectric layer 112 in each layer, and the channel material layer 411' and the gate dielectric material layer 412' located on the surface of the second dielectric layer 112 in adjacent layers are integrally connected.

[0074] The channel material layer 411' can be made of monocrystalline silicon, polycrystalline silicon, germanium, silicon-germanium, or oxide semiconductor materials. In one example, the channel material layer 411' is made of IGZO. The gate dielectric material layer 412' can be made of a high-dielectric-constant dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The conductive material layer 413' can also be a multilayer structure, for example, containing a titanium nitride layer and a tungsten layer. In one example, the conductive material layer 413' is made of indium tin oxide (ITO). ITO material has low resistance.

[0075] In some embodiments, the initial gate stack 410' is also formed in the first through-hole K1 and the second through-hole K2, and the method further includes removing a portion of the initial gate stack 410' in the first through-hole K1 and the second through-hole K2.

[0076] In some embodiments, refer to Figure 12 As shown, the sacrificial portion 301 is removed along the first through hole K1 and the second through hole K2 to expose the first gap trench P1. The first gap trench P1 exposes the two opposite sidewalls of the initial gate stack 410' along the first direction D1, that is, the first gap trench P1 exposes the two opposite sidewalls of the channel material layer 411' along the first direction D1.

[0077] In some embodiments, refer to Figure 13 As shown, a portion of the exposed initial gate stack 410' is removed along the first gap groove P1 to form a gate stack 410. The gate stack 410 includes a channel layer 411, a gate dielectric layer 412, and a gate conductive layer 413 stacked sequentially. The gate conductive layer 413 extends along the vertical direction D3. Two opposite portions of the channel material layer 411' along the first direction D1 and two opposite portions of the gate dielectric material layer 412' along the first direction D1 are sequentially removed along the first gap groove P1, thereby exposing two opposite sidewalls of the conductive material layer 413' along the first direction D1. Etching can be stopped when the conductive material layer 413' is exposed, retaining the conductive material layer 413', or the conductive material layer 413' can be partially removed to form the gate conductive layer 413. The remaining channel material layer 411' serves as the channel layer 411, and the remaining gate dielectric material layer 412' serves as the gate dielectric layer 412. By removing the exposed portion of the initial gate stack 410' along the first gap groove P1, the channel material layer 411' and the gate dielectric material layer 412' located on the surface of the second dielectric layer 112 in different layers can be disconnected, and the length of the remaining channel material layer 411' can be precisely controlled.

[0078] In some embodiments, refer to Figure 14As shown, a source-drain isolation structure 302 is filled in the first gap P1. The source-drain isolation structure 302 contacts the two opposite sidewalls of the gate stack 410 along the first direction D1 and is sandwiched between adjacent second dielectric layers 112 in the vertical direction D3. The source-drain isolation structure 302 may be located only in the first gap P1. For example, after depositing the isolation material, the isolation material located in the first through-hole K1 and the second through-hole K2 is removed, leaving only the isolation material located in the first gap P1 as the source-drain isolation structure 302. In other examples, the source-drain isolation structure 302 may also be located in the first through-hole K1 and the second through-hole K2. The material of the source-drain isolation structure 302 may be a low dielectric constant material. In one example, the material of the source-drain isolation structure 302 is alumina.

[0079] In some embodiments, refer to Figure 15 As shown, a portion of the second dielectric layer 112 is removed to form a dielectric structure 122 and second gap trenches P2 located on both sides of the dielectric structure 122. The dimension w2 of the second gap trenches P2 along the first direction D1 is larger than the dimension w1 of the first gap trenches P1 along the first direction D1. A first source-drain structure 310 and a second source-drain structure 320 are formed on both sides of the dielectric structure 122 along the first direction D1. The first source-drain structure 310 has a second sidewall s2 parallel to the first direction D1, and the second source-drain structure 320 has a third sidewall s3 parallel to the first direction D1. A gate stack 410 surrounds the first sidewall s1 of the dielectric structure 122, a portion of the second sidewall s2 of the first source-drain structure 310, and a portion of the third sidewall s3 of the second source-drain structure 320. The first source-drain structure 310 and the second source-drain structure 320 can be single-layer or multi-layer structures. For example, both the first source-drain structure 310 and the second source-drain structure 320 are double-layer structures including a titanium nitride layer and a tungsten layer. By setting the first source-drain structure 310 and the second source-drain structure 320 as a double-layer structure, the diffusion contamination of the tungsten layer can be avoided, and its contact resistance with the channel layer 411 can be reduced.

[0080] Since the dimension w2 of the second gap groove P2 along the first direction D1 is greater than the dimension w1 of the first gap groove P1 along the first direction D1, it can be understood that the dimension w2 of the first source-drain structure 310 and the second source-drain structure 320 along the first direction D1 is greater than the dimension w1 of the source-drain isolation structure 302 along the first direction D1. Alternatively, it can be understood that the dimension of the dielectric structure 122 along the first direction D1 is smaller than the dimension of the gate stack 410 along the first direction D1. This results in the gate stack 410 fully covering the first sidewall s1 of the dielectric structure 122 and protruding from the dielectric structure 122 at both ends, and contacting the second sidewall s2 of the first source-drain structure 310 and the third sidewall s3 of the second source-drain structure 320. The projection of the gate stack 410 on the substrate 101 partially overlaps with the projections of the first source-drain structure 310 and the second source-drain structure 320 on the substrate 101 to ensure electrical contact between the channel layer 411 and the source-drain.

[0081] In some embodiments, one of the first source-drain structure 310 and the second source-drain structure 320 is electrically connected to a bit line, and the other is electrically connected to a capacitor to form a memory cell. For example, multiple first source-drain structures 310 located on the same layer are electrically connected to a corresponding bit line extending along the second direction D2, and multiple second source-drain structures 320 are electrically connected to the lower electrodes of multiple capacitors in a one-to-one correspondence to form a three-dimensional dynamic random access memory.

[0082] In some embodiments, refer to Figure 16A and 16B As shown, where, Figure 16B The middle left image is Figure 16A A schematic cross-sectional view along section AA'. Figure 16B The right image in the middle is Figure 16A A cross-sectional view along section BB'. After removing the exposed portion of the initial gate stack 410' along the first gap trench P1, either after filling the source-drain isolation structure 311 or after forming the first source-drain structure 310 and the second source-drain structure 320, the process further includes: forming a second gap trench T2 penetrating the initial gate stack 410' along the vertical direction D3, the second gap trench T2 dividing the initial gate stack 410' into multiple gate stacks 410 spaced apart along the second direction D2; and filling the second gap trench T2 with word line isolation structures 510. Multiple stack groups spaced apart along the second direction D2 are formed on the substrate 101, each stack group including multiple transistor structures stacked in the vertical direction D3. The stack groups are isolated from each other by word line isolation structures 510, first isolation structures 211, and second isolation structures 212.

[0083] In some embodiments, the dimension of the second spacer T2 along the first direction D1 is greater than or equal to the dimension of the initial gate stack 410' along the first direction D1, to ensure that the plurality of gate stacks 410 are not connected. The dimension of the second spacer T2 along the first direction D1 may be smaller than the dimension of the first spacer T1 along the first direction D1.

[0084] In some embodiments, the width of the second spacer T2 along the second direction D2 is smaller than the width of the first spacer T1 along the second direction D2, to ensure that the gate stacks 410 located on the two opposite sidewalls of the dielectric structure 122 along the second direction D2 are not separated in the vertical direction D3. The ratio of the width of the second spacer T2 along the second direction D2 to the width of the first spacer T1 along the second direction D2 is 0.5-0.9. By controlling the width of the second spacer T2, the width of the word line isolation structure 510 along the second direction D2 is improved, thereby reducing the parasitic capacitance between the gate conductive layers 413 in adjacent gate stacks 410. The material of the word line isolation structure 510 may be the same as the material of the first isolation structure 211 and the second isolation structure 212.

[0085] In some embodiments, the semiconductor structure includes a memory, which may be a dynamic random access memory or a memory known in the art, such as a phase change memory or a ferroelectric memory.

[0086] The various semiconductor structures illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0087] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A transistor structure, characterized in that, include: A dielectric structure having a first sidewall parallel to a first direction; A first source-drain structure and a second source-drain structure are respectively located on both sides of the dielectric structure along the first direction. The first source-drain structure has a second sidewall parallel to the first direction, and the second source-drain structure has a third sidewall parallel to the first direction. A gate stack surrounds a first sidewall of a dielectric structure, a portion of a second sidewall of a first source-drain structure, and a portion of a third sidewall of a second source-drain structure. The gate stack includes a channel layer, a gate dielectric layer, and a gate conductive layer stacked sequentially. The channel layer is in contact with the first source-drain structure and the second source-drain structure.

2. The transistor structure according to claim 1, characterized in that, The first sidewall of the dielectric structure, the second sidewall of the first source-drain structure, and the third sidewall of the second source-drain structure are flush.

3. The transistor structure according to claim 1, characterized in that, The ends of the channel layer, the gate dielectric layer, and the gate conductive layer along the first direction are all aligned vertically.

4. A semiconductor structure, characterized in that, include: A stacked group, the stacked group comprising a plurality of transistor structures stacked in a vertical direction, each of the transistor structures comprising a dielectric structure, a gate stack, a first source-drain structure, and a second source-drain structure; The plurality of said medium structures are arranged at intervals along the vertical direction, and each said medium structure has a first sidewall parallel to the first direction; The first source-drain structure and the second source-drain structure are respectively located on both sides of each dielectric structure along the first direction. The first source-drain structure has a second sidewall parallel to the first direction, and the second source-drain structure has a third sidewall parallel to the first direction. The gate stack surrounds the first sidewall of the dielectric structure, a portion of the second sidewall of the first source-drain structure, and a portion of the third sidewall of the second source-drain structure. The gate stack includes a channel layer, a gate dielectric layer, and a gate conductive layer stacked sequentially. The gate conductive layer extends in a vertical direction, and the plurality of transistor structures are coupled to each other through the gate conductive layer.

5. The semiconductor structure according to claim 4, characterized in that, The plurality of stacked groups are spaced apart along a second direction, and the semiconductor structure further includes a word line isolation structure located between the plurality of stacked groups, wherein the dimension of the word line isolation structure along the first direction is greater than or equal to the dimension of the gate stack along the first direction.

6. The semiconductor structure according to claim 5, characterized in that, The dimension of the word line isolation structure along the first direction is smaller than the spacing between the opposite ends of the first source-drain structure and the second source-drain structure. The semiconductor structure also includes a first isolation structure and a second isolation structure located on both sides of the word line isolation structure along the first direction.

7. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure further includes source-drain isolation structures located on both sides of the gate stack along the first direction, the source-drain isolation structures being sandwiched between adjacent first source-drain structures in the vertical direction and between adjacent second source-drain structures in the vertical direction.

8. The semiconductor structure according to any one of claims 4-7, characterized in that, The first sidewall of the dielectric structure, the second sidewall of the first source-drain structure, and the third sidewall of the second source-drain structure are flush.

9. The semiconductor structure according to any one of claims 4-7, characterized in that, The ends of the channel layer, the gate dielectric layer, and the gate conductive layer along the first direction are all aligned vertically.

10. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is formed, the stacked structure comprising a first dielectric layer and a second dielectric layer alternately stacked in a vertical direction; Remove the first dielectric layer to form a word line groove that exposes the first sidewall of the second dielectric layer, and sacrificial portions located on both sides of the word line groove along a first direction; An initial gate stack is formed in the word line trench; Remove the sacrificial portion to form a first gap groove; The exposed portion of the initial gate stack is removed along the first gap trench to form a gate stack comprising a channel layer, a gate dielectric layer and a gate conductive layer stacked sequentially, the gate conductive layer extending in a vertical direction; A portion of the second dielectric layer is removed to form a dielectric structure and second gap grooves located on both sides of the dielectric structure, wherein the dimension of the second gap groove along the first direction is larger than the dimension of the first gap groove along the first direction; A first source-drain structure and a second source-drain structure are formed on both sides of the dielectric structure along a first direction. The first source-drain structure has a second sidewall parallel to the first direction, and the second source-drain structure has a third sidewall parallel to the first direction. The gate stack surrounds the first sidewall of the dielectric structure, a portion of the second sidewall of the first source-drain structure, and a portion of the third sidewall of the second source-drain structure.

11. The preparation method according to claim 10, characterized in that, After the plurality of stacked structures are arranged at intervals along the second direction to form the plurality of stacked structures, the method further includes: A first sacrificial structure and a first isolation structure and a second isolation structure located on both sides of the first sacrificial structure along a second direction are formed in a first gap between multiple stacked structures.

12. The preparation method according to claim 11, characterized in that, The removal of the first dielectric layer includes: Laterally etch along the two end faces of the first dielectric layer in the first direction to remove part of the first dielectric layer and form a first gap groove; The sacrificial portion is filled into the first gap groove; Remove the remaining first dielectric layer and the first sacrificial structure to form word line trenches.

13. The preparation method according to claim 11, characterized in that, The initial gate stack includes a channel material layer and a gate dielectric material layer sequentially formed on the first sidewall of the second dielectric layer exposed in the word line trench and the surface of the sacrificial portion, as well as a conductive material layer filled in the word line trench. The removal of the exposed portion of the initial gate stack along the first gap groove includes: Remove the exposed portion of the channel material layer along the first gap groove to form a channel layer; The exposed portion of the gate dielectric material layer is removed along the first gap groove to form a gate dielectric layer.

14. The preparation method according to claim 11, characterized in that, After removing the exposed portion of the initial gate stack along the first gap trench, the process further includes: A second spacer groove is formed that penetrates the initial gate stack in a vertical direction, and the second spacer groove divides the initial gate stack into a plurality of gate stacks spaced apart in a second direction; The second spacer slot is filled with word line isolation structures.

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