Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device includes a substrate, a first semiconductor pillar extending in a direction perpendicular to the substrate and including a first sidewall and a second sidewall, a second semiconductor pillar extending in a direction perpendicular to the substrate and connected to the first sidewall of the first semiconductor pillar, a first word line extending in a direction perpendicular to the substrate and connected to the second sidewall of the first semiconductor pillar, and a second word line extending in a direction perpendicular to the substrate and connected to the second sidewall of the second semiconductor pillar. And the second semiconductor column is arranged on the second side wall of the first semiconductor column, the material of the first semiconductor column has a first lattice constant, the material of the second semiconductor column has a second lattice constant, and the second lattice constant is greater than the first lattice constant. In the semiconductor device, the first semiconductor column and the second semiconductor column extend along the direction vertical to the substrate and are connected together, so that the occupied area can be reduced, and the storage density is provided. In addition, the first semiconductor column and the second semiconductor column have a first lattice constant and a second lattice constant respectively, the conductivity of the first semiconductor column can be improved, and meanwhile the floating body effect of the vertical transistor can be relieved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for fabricating a semiconductor device. Background Technology

[0002] As memory devices are continuously demanded to increase density and performance, transistor fabrication technology faces physical limitations. For example, as the size of memory cells decreases, the size of transistors also decreases. This inevitably reduces the channel length of the transistor. When the channel length of a transistor decreases, the characteristics of the memory device deteriorate due to various problems, such as a reduction in data retention characteristics.

[0003] Dynamic random access memory (DRAM) with vertical channel transistors has attracted widespread attention due to its small footprint, high storage density, and minimal short-channel effect. Summary of the Invention

[0004] Based on this, the embodiments of this application provide a semiconductor device and a method for fabricating a semiconductor device, which have advantages such as high storage density and strong channel conductivity.

[0005] In a first aspect, this application provides a semiconductor device according to some embodiments, characterized in that it comprises: Substrate; A first semiconductor pillar is located on the substrate and extends along a third direction perpendicular to the substrate. The first semiconductor pillar includes a first sidewall and a second sidewall disposed opposite to each other along a first direction, the first direction being parallel to the substrate. The second semiconductor pillar is located on the substrate, extends along a third direction perpendicular to the substrate, and is connected to the first sidewall of the first semiconductor pillar. The first character line extends along the second direction and is disposed on the second sidewall of the first semiconductor pillar; The first semiconductor pillar is made of a material with a first lattice constant, and the second semiconductor pillar is made of a material with a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.

[0006] In some embodiments, the semiconductor device further includes: A third semiconductor pillar is located on the substrate and extends along a third direction perpendicular to the substrate. The third semiconductor pillar includes a third sidewall and a fourth sidewall that are disposed opposite to each other along a first direction. A fourth semiconductor pillar is located on the substrate, extends along a third direction perpendicular to the substrate, and is connected to the fourth sidewall of the third semiconductor pillar. The fourth semiconductor pillar is disposed face-to-face with the second semiconductor pillar. The second word line extends along the second direction and is disposed on the third sidewall of the third semiconductor pillar; The material of the third semiconductor pillar has a first lattice constant, and the material of the fourth semiconductor pillar has a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.

[0007] In some embodiments, the first semiconductor pillar and the third semiconductor pillar comprise silicon material; The second semiconductor pillar and the fourth semiconductor pillar include at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, ZnS, ZnSe, ZnTe, CdS, CdSe, or CdTe.

[0008] In some embodiments, the first semiconductor pillar and the third semiconductor pillar include a source region, a channel region, and a drain region disposed along the third direction; The channel region is doped with at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, ZnS, ZnSe, ZnTe, CdS, CdSe, or CdTe.

[0009] In some embodiments, the shapes of the second semiconductor pillar and the fourth semiconductor pillar may include at least one of a cuboid, a semi-cylinder, or a semi-cone.

[0010] In some embodiments, the semiconductor device further includes: A first connecting block is located between the second semiconductor pillar and the fourth semiconductor pillar, and is in contact with the second semiconductor pillar and the fourth semiconductor pillar respectively. The first connecting block is located near one end of the source region or the drain region.

[0011] In some embodiments, the semiconductor device further includes: The second connecting block is located between the second semiconductor pillar and the fourth semiconductor pillar, and is in contact with the second semiconductor pillar and the fourth semiconductor pillar respectively. The first connecting block is located near one end of the source region or the drain region. The second connecting block and the first connecting block are not in contact.

[0012] In some embodiments, the semiconductor device further includes: A third connecting block is located between the second semiconductor pillar and the fourth semiconductor pillar, and is in contact with the second semiconductor pillar and the fourth semiconductor pillar respectively. The third connecting block, the second semiconductor pillar and the fourth semiconductor pillar are at the same height in the third direction.

[0013] In some embodiments, the first word line is further disposed on two sidewalls of the first semiconductor pillar that are disposed opposite to each other along the second direction; The second word line is also disposed on two sidewalls of the third semiconductor pillar that are positioned opposite each other along the second direction.

[0014] In some embodiments, the semiconductor device further includes: Bit lines, which extend along a first direction and connect the source or drain of the first semiconductor pillars and the third semiconductor pillars arranged along the first direction; A storage cell extending in a third direction, the storage cell being connected to the drain or source of the first semiconductor pillar and the third semiconductor pillar.

[0015] Secondly, according to some embodiments, this application also provides a method for fabricating a semiconductor device, characterized in that it includes: Provide substrate; A first semiconductor pillar is formed on the substrate. The first semiconductor pillar extends along a third direction perpendicular to the substrate. The first semiconductor pillar includes a first sidewall and a second sidewall disposed opposite to each other along a first direction parallel to the substrate. A second semiconductor pillar is formed by epitaxial growth on the first sidewall. The second semiconductor pillar is located on the substrate, extends along a third direction perpendicular to the substrate, and is connected to the first sidewall of the first semiconductor pillar. A first word line is formed, which extends along a second direction and is disposed on the second sidewall of the first semiconductor pillar; The first semiconductor pillar is made of a material with a first lattice constant, and the second semiconductor pillar is made of a material with a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.

[0016] In some embodiments, a third semiconductor pillar is further formed on the substrate, the third semiconductor pillar extending along a third direction perpendicular to the substrate, the third semiconductor pillar including a third sidewall and a fourth sidewall disposed opposite to each other along a first direction; A fourth semiconductor pillar is formed by epitaxial growth on the fourth sidewall of the third semiconductor pillar. The fourth semiconductor pillar extends along a third direction perpendicular to the substrate and is connected to the fourth sidewall of the third semiconductor pillar. The fourth semiconductor pillar and the second semiconductor pillar are arranged face to face. A second word line is formed, which extends along a second direction and is disposed on the third sidewall of the third semiconductor pillar; The first semiconductor pillar is made of a material with a first lattice constant, and the second semiconductor pillar is made of a material with a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.

[0017] The semiconductor structure and its fabrication method provided in this application have at least the following beneficial effects: The semiconductor device and its fabrication method provided in this application involve a first semiconductor pillar and a second semiconductor pillar extending perpendicular to the substrate and connected together, which reduces the occupied area and increases storage density. Furthermore, the first and second semiconductor pillars have a first lattice constant and a second lattice constant, respectively. The second lattice constant is greater than the first lattice constant, which improves the conductivity of the first semiconductor pillar and alleviates the floating body effect of vertical transistors. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 10 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application; Figure 11-13 The manufacturing process provided in the embodiments of this application Figure 10 A schematic diagram of the structure of a method for using a semiconductor device; Explanation of reference numerals in the attached figures: 100: Substrate; 101: First semiconductor pillar; 102: Second semiconductor pillar; 103: First word line; 201: Third semiconductor pillar; 202: Third semiconductor pillar; 203: Second word line; 301, 301': First interconnect block; 302: Second interconnect block; 303: Third interconnect block; 401: Bit line; 501: Memory cell. Detailed Implementation

[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to," it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms "first," "second," etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0023] Spatial relation terms such as “on top of” can be used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “on top of” will be oriented “below” other elements or features. Therefore, the exemplary term “on top of” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items. Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures) of this application, thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0025] Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of this application. In some embodiments, the semiconductor device includes a substrate 100, a first semiconductor pillar 101 located on the substrate 100, extending along a third direction perpendicular to the substrate (e.g., the Z direction), including a first sidewall and a second sidewall disposed opposite each other along a first direction (e.g., the X direction), a second semiconductor pillar 102 located on the substrate 100, extending along a third direction perpendicular to the substrate (e.g., the Z direction), and connected to the first sidewall of the first semiconductor pillar 101, and a first word line 103 extending along a second direction (e.g., the Y direction) and disposed on the second sidewall of the first semiconductor pillar 101, wherein the material of the first semiconductor pillar 101 has a first lattice constant, the material of the second semiconductor pillar 102 has a second lattice constant, and the second lattice constant is greater than the first lattice constant. In the semiconductor device, the first semiconductor pillar 101 and the second semiconductor pillar 102 extend along a direction perpendicular to the substrate and are connected together, which can reduce the occupied area and provide storage density. In addition, the first semiconductor pillar 101 and the second semiconductor pillar 102 have a first lattice constant and a second lattice constant, respectively. The second lattice constant is greater than the first lattice constant, which can improve the conductivity of the first semiconductor pillar 101 and at the same time alleviate the floating body effect of the vertical transistor.

[0026] In some embodiments of this application, the substrate 100 may be a single-crystal silicon substrate, a polycrystalline silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (e.g., silicon nitride or gallium arsenide), an oxide semiconductor substrate, or a substrate on which semiconductor devices are formed. The substrate 100 may also include other peripheral circuits such as bit-line amplifier circuits, word-line drive circuits, electrostatic discharge protection circuits, and interface circuits. The material of the first word line 103 is a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), or ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc.

[0027] Continue to refer to Figure 1In some embodiments, the first semiconductor pillar 101 extends along a third direction (e.g., the Z direction) perpendicular to the substrate 100. The first semiconductor pillar 101 can be directly connected to the substrate 100 or connected to the substrate through other media. A source region, a channel region, and a drain region are disposed on the first semiconductor pillar 101 along the third direction (e.g., the Z direction) perpendicular to the substrate 100. The source region and drain region are respectively disposed on opposite sides of the channel region along the third direction (e.g., the Z direction). The horizontal cross-sectional shape of the first semiconductor pillar 101 can be a rectangle, square, circle, ellipse, or other regular or irregular shapes. In this embodiment, only a rectangle is used as an example. The first semiconductor pillar 101 includes a first sidewall and a second sidewall disposed opposite each other along a first direction (e.g., the X direction). The first sidewall and the second sidewall are identical and interchangeable; they are named here for distinction. The second semiconductor pillar 102 extends along a third direction (e.g., the Z direction) perpendicular to the substrate 100. The second semiconductor pillar 102 can be directly connected to the substrate 100 or connected to the substrate through other media. The second semiconductor pillar 102 is connected to the first sidewall of the first semiconductor pillar 101, and can completely overlap with the first sidewall of the first semiconductor pillar 101, or partially overlap with the channel region of the first sidewall of the first semiconductor pillar 101. The horizontal cross-sectional shape of the second semiconductor pillar 102 can be rectangular, square, circular, elliptical, or other regular or irregular shapes. The horizontal cross-sectional shape of the second semiconductor pillar 102 can be rectangular, meaning it completely fits the first semiconductor pillar 101, or it can be square, partially fitting the first sidewall of the first semiconductor pillar 101. The horizontal cross-sectional shape of the second semiconductor pillar 102 can be circular or elliptical, meaning that along the first direction, one sidewall fits the first sidewall of the first semiconductor pillar 101, and the other sidewall is arc-shaped, which can increase the fabrication process window and reduce the fabrication process difficulty. (See reference...) Figure 2 The horizontal cross-sectional shape of the second semiconductor pillar 102 can be conical, meaning that one sidewall along the first direction is attached to the first sidewall of the first semiconductor pillar 101, and the other sidewall is arc-shaped. Furthermore, the two ends along the third direction have different areas, which can further increase the fabrication process window and reduce the fabrication process difficulty. (Refer to...) Figure 3 .

[0028] Continue to refer to Figure 1In some embodiments, the material of the first semiconductor pillar 101 has a first lattice constant, and the material of the second semiconductor pillar 102 has a second lattice constant. The second lattice constant of the second semiconductor pillar 102 is greater than the first lattice constant of the first semiconductor pillar 101 (the lattice constant refers to the edge length of a unit cell, that is, the edge length of each parallelepiped unit; it is an important basic parameter of crystal structure). The first semiconductor pillar 101 comprises silicon material, and the second semiconductor pillar 102 comprises at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe, or CdTe. Because the second lattice constant is greater than the first lattice constant, strain can be applied to the silicon material within the first semiconductor pillar 101, increasing the carrier mobility within the first semiconductor pillar 101, reducing the resistance of the first semiconductor pillar 101, and improving the conductivity of the first semiconductor pillar 101. In addition, the channel region of the first semiconductor pillar 101 may be doped with at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe, or CdTe to further improve the carrier mobility in the first semiconductor pillar 101, reduce the resistance of the first semiconductor pillar 101, and improve the conductivity of the first semiconductor pillar 101.

[0029] Figure 4This is a schematic diagram of another semiconductor device provided in an embodiment of this application. In some embodiments, the semiconductor device further includes a third semiconductor pillar 201, which is located on a substrate 100 and extends along a third direction (e.g., the Z direction) perpendicular to the substrate. The third semiconductor pillar 201 includes a third sidewall and a fourth sidewall disposed opposite each other along a first direction (e.g., the X direction). A fourth semiconductor pillar 202, located on the substrate 100, extends along a third direction (e.g., the Z direction) perpendicular to the substrate and is connected to the fourth sidewall of the third semiconductor pillar 201. The fourth semiconductor pillar 202 is disposed face-to-face with the second semiconductor pillar 102. A second word line 203 extends along a second direction (e.g., the Y direction) and is disposed on the third sidewall of the third semiconductor pillar 201. The material of the third semiconductor pillar 201 has a first lattice constant, and the material of the fourth semiconductor pillar 202 has a second lattice constant, the second lattice constant being greater than the first lattice constant. In the semiconductor device, the third semiconductor pillar 202 and the fourth semiconductor pillar 203 extend along a direction perpendicular to the substrate and are connected together, which can reduce the occupied area and provide storage density. In addition, the third semiconductor pillar 202 and the fourth semiconductor pillar 203 have a first lattice constant and a second lattice constant, respectively. The second lattice constant is greater than the first lattice constant, which can improve the conductivity of the third semiconductor pillar 201 and at the same time alleviate the floating effect of the vertical transistor.

[0030] Continue to refer to Figure 4In some embodiments, the third semiconductor pillar 201 extends along a third direction (e.g., the Z direction) perpendicular to the substrate 100. The third semiconductor pillar 201 can be directly connected to the substrate 100 or connected to the substrate through other media. The third semiconductor pillar 201 is provided with a source region, a channel region, and a drain region along a third direction perpendicular to the substrate 100. The source region and the drain region are respectively located on opposite sides of the channel region along the third direction (e.g., the Z direction). The horizontal cross-sectional shape of the third semiconductor pillar 201 can be a rectangle, a square, a circle, an ellipse, or other regular or irregular shapes. In this embodiment, only a rectangle is used as an example. The third semiconductor pillar 201 includes a third sidewall and a fourth sidewall that are arranged opposite each other along a first direction (e.g., the X direction). The third sidewall and the fourth sidewall are the same and can be interchanged. They are named here for distinction. The fourth semiconductor pillar 202 extends along a third direction (e.g., the Z direction) perpendicular to the substrate 100. Semiconductor pillar 202 can be directly connected to substrate 100 or connected to substrate through other media. The fourth semiconductor pillar 202 is connected to the fourth sidewall of the third semiconductor pillar 201, and can completely overlap with the fourth sidewall of the third semiconductor pillar 201, or partially overlap with the channel region of the fourth sidewall of the third semiconductor pillar 201. The horizontal cross-sectional shape of the fourth semiconductor pillar 202 can be rectangular, square, circular, elliptical, or other regular or irregular shapes. The horizontal cross-sectional shape of the fourth semiconductor pillar 202 can be rectangular, completely attached to the third semiconductor pillar 201, or square, partially attached to the fourth sidewall of the third semiconductor pillar 201. The horizontal cross-sectional shape of the fourth semiconductor pillar 202 can be circular or elliptical, meaning that along the first direction, one sidewall is attached to the first sidewall of the third semiconductor pillar 201, and the other sidewall is arc-shaped. This can increase the fabrication process window and reduce the fabrication process difficulty. (See reference...) Figure 2 The horizontal cross-sectional shape of the fourth semiconductor pillar 202 can be conical, meaning that one sidewall along the first direction is attached to the first sidewall of the third semiconductor pillar 201, and the other sidewall is arc-shaped. Furthermore, the two ends along the third direction have different areas, which can further increase the fabrication process window and reduce the fabrication process difficulty. (Refer to...) Figure 3 .

[0031] Continue to refer to Figure 4In some embodiments, the material of the third semiconductor pillar 201 has a first lattice constant, and the fourth semiconductor pillar 202 has a second lattice constant. The second lattice constant of the fourth semiconductor pillar 202 is greater than the first lattice constant of the third semiconductor pillar 201 (the lattice constant refers to the edge length of a unit cell, that is, the edge length of each parallelepiped unit; it is an important basic parameter of crystal structure). The third semiconductor pillar 201 comprises silicon material, and the fourth semiconductor pillar 202 comprises at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe, or CdTe. Because the second lattice constant is greater than the first lattice constant, strain can be applied to the silicon material within the third semiconductor pillar 201, increasing the carrier mobility in the third semiconductor pillar 201, reducing the resistance of the third semiconductor pillar 201, and improving the conductivity of the third semiconductor pillar 201. In addition, the channel region of the third semiconductor pillar 201 may be doped with at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe, or CdTe to further improve the carrier mobility in the third semiconductor pillar 201, reduce the resistance of the third semiconductor pillar 201, and improve the conductivity of the third semiconductor pillar 201.

[0032] Continue to refer to Figure 4 In some embodiments, the first word line 103 is also disposed on two sidewalls of the first semiconductor pillar 101 that are arranged opposite each other along the second direction (e.g., the Y direction), and the second word line 203 is also disposed on two sidewalls of the third semiconductor pillar 201 that are arranged opposite each other along the second direction (e.g., the Y direction). This is equivalent to the three surfaces of the first semiconductor pillar 102 being surrounded by the first word line 103 and the three surfaces of the third semiconductor pillar 201 being surrounded by the second word line 203. This can improve the control capability of the first word line 103 and the second word line 203 over the first semiconductor pillar 101 and the third semiconductor pillar 201, respectively, reduce leakage current, and improve the stability of the semiconductor device.

[0033] Continue to refer to Figure 4In some embodiments, the third semiconductor pillar 201 is identical to the first semiconductor pillar 101 and can be interchanged; the fourth semiconductor pillar 201 is identical to the second semiconductor pillar 102 and can be interchanged; and the first word line 103 is identical to the second word line 203 and can be interchanged. The first semiconductor pillar 101, the second semiconductor pillar 102, and the first word line 103 are symmetrically arranged face-to-face with the third semiconductor pillar 201, the third semiconductor pillar 202, and the second word line 203, respectively. The first semiconductor pillar 101, the second semiconductor pillar 102, the first word line 103, the third semiconductor pillar 201, the third semiconductor pillar 202, and the second word line 203 form a minimum unit.

[0034] Figure 5 and Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application. In some embodiments, the semiconductor device structure further includes a first connecting block 301, which is located between the second semiconductor pillar 102 and the fourth semiconductor pillar 202, and is in contact with the second semiconductor pillar 102 and the fourth semiconductor pillar 202. The material of the first connecting block 301 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials such as tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides can be used. The first connecting block 301 can connect the second semiconductor pillar 102 and the fourth semiconductor pillar 202. This allows the other semiconductor pillar to release the charge that causes the floating body effect when either one is working, thus mitigating the floating body effect. Furthermore, the first connecting block 301 can be made of the same material as the second semiconductor pillar 102 and the fourth semiconductor pillar 202, and can be integrally formed with them, reducing the difficulty of the manufacturing process. The first connecting block 301 can be located at one end of the second semiconductor pillar 102 and the fourth semiconductor pillar 202. (Refer to...) Figure 5 The first connection block 301 is located in the source or drain region of the second semiconductor pillar 102 and the fourth semiconductor pillar 202 near the substrate, as referenced. Figure 6 The first connecting block 301' is located in the source or drain region at the end of the second semiconductor pillar 102 and the fourth semiconductor pillar 202 away from the substrate.

[0035] Figure 7This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application. In some embodiments, the semiconductor device structure further includes a second connecting block 302. The second connecting block 302 is located between the second semiconductor pillar 102 and the fourth semiconductor pillar 202, and is in contact with the second semiconductor pillar 102 and the fourth semiconductor pillar 202. The material of the second connecting block 302 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the second connecting block 302 and the first connecting block 301 can be the same or different. The second connecting block 302 and the first connecting block 301 are located in the source or drain regions of the second semiconductor pillar 102 and the fourth semiconductor pillar 202, respectively, at the end near the substrate and the end away from the substrate. The second connecting block 302 and the first connecting block 301 are not connected, forming a hollow structure in the middle channel region of the second semiconductor pillar 102 and the fourth semiconductor pillar 202. The second connecting block 302 and the first connecting block 301 can also be made of the same material as the second semiconductor pillar 102 and the fourth semiconductor pillar 202, and be integrally formed with the second semiconductor pillar 102 and the fourth semiconductor pillar 202, which can increase the manufacturing process window and reduce the process difficulty.

[0036] Figure 8 and Figure 9 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application. In some embodiments, the semiconductor device structure further includes a third connecting block 303, which is located between the second semiconductor pillar 102 and the fourth semiconductor pillar 202, and is in contact with the second semiconductor pillar 102 and the fourth semiconductor pillar 202. The material of the third connecting block 303 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The third connecting block 303 overlaps with and is at the same height as the second and fourth semiconductor pillars 102 and 202. The third connecting block 303 can also be made of the same material as the second and fourth semiconductor pillars 102 and be integrally formed with them, which can increase the fabrication process window and reduce process difficulty. (Reference) Figure 9 The third connecting block 303 can also directly contact and connect with the first semiconductor pillar 101 and the second semiconductor pillar 201, overlapping with the first semiconductor pillar 101 and the second semiconductor pillar 201. That is, the third connecting block 303 is integrated with the second semiconductor pillar 102 and the fourth semiconductor pillar 202. The material of the third connecting block 303 has a second lattice constant, and the material of the third connecting block 303 includes at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe, or CdTe. Since the second lattice constant is greater than the first lattice constant, it can cause strain in the silicon material in the first semiconductor pillar 101 and the third semiconductor pillar 201, increasing the carrier mobility in the first semiconductor pillar 101 and the third semiconductor pillar 201, reducing the resistance value of the first semiconductor pillar 101 and the third semiconductor pillar 201, and increasing the conductivity of the first semiconductor pillar 101 and the third semiconductor pillar 201. In addition, the third connecting block 303 can also be directly connected to the first semiconductor pillar 101 and the second semiconductor pillar 201, which can increase the fabrication process window and reduce the fabrication process difficulty.

[0037] Figure 10 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application. In some embodiments, multiple such... Figure 9The semiconductor devices shown are arranged in an array along a first direction (e.g., the X direction) and a second direction (e.g., the Y direction). A first word line 103 extends along the second direction (e.g., the Y direction) and connects to a first semiconductor pillar 101 arranged along the second direction (e.g., the Y direction). A second word line 203 extends along the second direction (e.g., the Y direction) and connects to a third semiconductor pillar 201 arranged along the second direction (e.g., the Y direction). The semiconductor device also includes a bit line 401 extending along a first direction (e.g., the X direction) and connecting a first semiconductor pillar 101, a third semiconductor pillar 201 arranged along the first direction, and a third connecting block 303 located between the first semiconductor pillar 101 and the third semiconductor pillar 201. The bit line 401 is located on a substrate 100 and is connected to the source or drain regions of the first semiconductor pillar 101 and the third semiconductor pillar 201 near the substrate. The material of the bit line 401 is a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x ), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc. See also... Figure 10 The semiconductor device also includes a memory cell 501, which is located on the first semiconductor pillar 101 and the third semiconductor pillar 201 and is connected to the source region and / or drain region of the end of the first semiconductor pillar 101 and the third semiconductor pillar 201 away from the substrate, respectively. The memory cell 501 can be one or more of the following memory cells: capacitor, ferroelectric memory cell, phase change memory cell, resistive switching memory cell, magnetic switching memory cell, etc. In this application, a capacitor is used as an example. The capacitor includes a lower electrode, a high-k dielectric and an upper electrode. The lower electrode can have various shapes such as columnar or barrel-shaped, and the lower electrode can be supported by multiple support layers.

[0038] Figures 11-13 The manufacturing process provided in the embodiments of this application Figure 10 A schematic diagram of a method for manufacturing a semiconductor device. (Reference) Figure 11In some embodiments, a substrate 100 is provided. The substrate 100 may be a single-crystal silicon substrate, a polycrystalline silicon substrate, a germanium-silicon substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (e.g., silicon nitride or gallium arsenide), an oxide semiconductor substrate, or a substrate on which semiconductor devices are formed. The substrate 100 may also include other peripheral circuits such as bit line amplifier circuits, word line drive circuits, electrostatic discharge protection circuits, and interface circuits. A first semiconductor pillar 101 and a third semiconductor pillar 201 are formed on a substrate 100. The first semiconductor pillar 101 and the third semiconductor pillar 201 extend along a third direction (e.g., the Z direction) perpendicular to the substrate 100 and can be directly connected to the substrate 100 or connected to the substrate through other media. A source region, a channel region, and a drain region are disposed on the first semiconductor pillar 101 and the third semiconductor pillar 201 along the third direction (e.g., the Z direction) perpendicular to the substrate 100. The source region and the drain region are respectively disposed on opposite sides of the channel region along the third direction (e.g., the Z direction). The horizontal cross-sectional shape of 201 can be a rectangle, square, circle, ellipse, or other regular or irregular shapes. In this embodiment, only a rectangle is used as an example. The first semiconductor pillar 101 includes a first sidewall and a second sidewall that are arranged opposite each other along a first direction (e.g., the X direction). The first sidewall and the second sidewall are the same and can be interchanged. The third semiconductor pillar 201 includes a third sidewall and a fourth sidewall that are arranged opposite each other along a first direction (e.g., the X direction). The third sidewall and the fourth sidewall are the same and can be interchanged. The first semiconductor pillar 101 and the third semiconductor pillar 201 are the same and can be interchanged; they are named here for distinction. A mask layer can be deposited on the substrate to form a patterned mask layer. Using the patterned mask layer as a mask, the substrate 100 is etched using multiple exposure etching technology or multiple exposure self-alignment technology to form the first semiconductor pillar 101 and the third semiconductor pillar 201 arranged in an array along the first direction (e.g., the X direction) and the second direction (e.g., the Y direction), respectively. The material of the first semiconductor pillar 101 and the third semiconductor pillar 201 has a first lattice constant and can be silicon.

[0039] refer to Figure 12In some embodiments, connecting blocks 303 are formed by epitaxial growth on the first sidewall of the first semiconductor pillar 101, the second semiconductor pillar 102, and the fourth sidewall of the third semiconductor pillar 201. Connecting blocks 303 connect the first semiconductor pillar 101 and the third semiconductor pillar 201, respectively. Connecting blocks 303 have a second lattice constant and include at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe, or CdTe. Since the second lattice constant is greater than the first lattice constant, strain can be applied to the silicon material with the first lattice constant, increasing the carrier mobility in the first semiconductor pillar 101 and the third semiconductor pillar 201, reducing the resistance of the first semiconductor pillar 101 and the third semiconductor pillar 201, and increasing the conductivity of the first semiconductor pillar 101 and the third semiconductor pillar 201. Furthermore, the channel regions of the first semiconductor pillar 101 and the third semiconductor pillar 201 may be doped with at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, MaTe, ZnS, ZnSe, ZnTe, AlP, GaP, AlAs, AlSb, CdS, CdSe, or CdTe to further improve the carrier mobility in the first semiconductor pillar 101 and the third semiconductor pillar 201, reduce the resistance of the first semiconductor pillar 101 and the third semiconductor pillar 201, and improve the conductivity of the first semiconductor pillar 101 and the third semiconductor pillar 201.

[0040] Continue to refer to Figure 12 In some embodiments, in Figure 11 Based on the provided embodiment, a sacrificial layer is deposited, ground and flattened, and then a mask layer is deposited and patterned. Using the patterned mask layer as a mask, the sacrificial layer is etched to expose the first sidewall of the first semiconductor pillar 101 and the fourth sidewall of the third semiconductor pillar 201. Connecting blocks 303 are epitaxially grown on the first sidewall of the first semiconductor pillar 101 and the fourth sidewall of the third semiconductor pillar 201, respectively. The connecting blocks 303 connect the first semiconductor pillar 101 and the third semiconductor pillar 201, respectively.

[0041] refer to Figure 13In some embodiments, a first word line 103 and a second word line 203 are formed, respectively. The first word line 103 and the second word line 203 extend along a second direction (e.g., the Y direction). The first word line 103 is disposed on the second sidewall of the first semiconductor pillar 101. In some embodiments, the first word line 103 is also disposed on two surfaces of the first semiconductor pillar 101 that are opposite to each other along the second direction (e.g., the Y direction), forming three surfaces of the first semiconductor pillar 101 surrounded by the first word line 101, thereby improving the control capability of the first semiconductor pillar 101. Similarly, the second word line 203 is disposed on the third sidewall of the third semiconductor pillar 201. In some embodiments, the second word line 203 is also disposed on two surfaces of the third semiconductor pillar 201 that are opposite to each other along the second direction (e.g., the Y direction), forming three surfaces of the third semiconductor pillar 201 surrounded by the second word line 203, thereby improving the control capability of the third semiconductor pillar 201. The first character line 103 and the second character line 203 are made of materials with electrical conductivity, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) x Materials used include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The materials of the first letter 103 and the second letter 203 can be the same or different.

[0042] Continue to refer to Figure 10 In some embodiments, bit lines 401 and memory cells 501 are formed at both ends of the first semiconductor pillar 101 and the third semiconductor pillar 201 along a third direction (e.g., the Z direction). Bit lines 401 extend along a first direction (e.g., the X direction), connecting the first semiconductor pillar 101, the third semiconductor pillar 201 arranged along the first direction (e.g., the X direction), and a third connecting block 303 located between the first semiconductor pillar 101 and the third semiconductor pillar 201. They are connected to the source or drain regions at one end of the first semiconductor pillar 101 and the third semiconductor pillar 201. The material of bit lines 401 is a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO). x ), iridium (Ir), iridium oxide (IrO) xMaterials include tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), and metal silicides. The memory cell 501 is located on the first semiconductor pillar 101 and the third semiconductor pillar 201, and is connected to the source region and / or drain region at one end of the first semiconductor pillar 101 and the third semiconductor pillar 201, respectively. The memory cell 501 can be one or more of the following: capacitor, ferroelectric memory cell, phase-change memory cell, resistive switching memory cell, magnetic switching memory cell, etc. This application uses a capacitor as an example. The capacitor includes a lower electrode, a high-k dielectric, and an upper electrode. The lower electrode can have various shapes such as columnar or barrel-shaped, and can be supported by multiple support layers.

[0043] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0044] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first semiconductor pillar is located on the substrate and extends along a third direction perpendicular to the substrate. The first semiconductor pillar includes a first sidewall and a second sidewall disposed opposite to each other along a first direction, the first direction being parallel to the substrate. The second semiconductor pillar is located on the substrate, extends along a third direction perpendicular to the substrate, and is connected to the first sidewall of the first semiconductor pillar. The first character line extends along the second direction and is disposed on the second sidewall of the first semiconductor pillar; The first semiconductor pillar is made of a material with a first lattice constant, and the second semiconductor pillar is made of a material with a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A third semiconductor pillar is located on the substrate and extends along a third direction perpendicular to the substrate. The third semiconductor pillar includes a third sidewall and a fourth sidewall that are disposed opposite to each other along a first direction. A fourth semiconductor pillar is located on the substrate and extends along a third direction perpendicular to the substrate. It is connected to the fourth sidewall of the third semiconductor pillar. The fourth semiconductor pillar and the second semiconductor pillar are arranged face to face along a first direction. The second word line extends along the second direction and is disposed on the third sidewall of the third semiconductor pillar.

3. The semiconductor device according to claim 2, characterized in that, The first semiconductor pillar and the third semiconductor pillar are made of silicon material; The materials of the second semiconductor pillar and the fourth semiconductor pillar include at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, ZnS, ZnSe, ZnTe, CdS, CdSe, or CdTe.

4. The semiconductor device according to claim 3, characterized in that, The first semiconductor pillar and the third semiconductor pillar include a source region, a channel region, and a drain region disposed along the third direction; The channel region is doped with at least one of SiGe, GaAs, InAs, GaSb, InSb, InP, MgS, MgSe, ZnS, ZnSe, ZnTe, CdS, CdSe, or CdTe.

5. The semiconductor device according to claim 2, characterized in that, The shapes of the second semiconductor pillar and the fourth semiconductor pillar may include at least one of cuboid, semi-cylinder or semi-cone.

6. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: A first connecting block is located between the second semiconductor pillar and the fourth semiconductor pillar, and is in contact with the second semiconductor pillar and the fourth semiconductor pillar respectively. The first connecting block is located near one end of the source region or the drain region.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes: The second connecting block is located between the second semiconductor pillar and the fourth semiconductor pillar, and is in contact with the second semiconductor pillar and the fourth semiconductor pillar respectively. The first connecting block is located near one end of the source region or the drain region. The second connecting block and the first connecting block are not in contact.

8. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: A third connecting block is located between the second semiconductor pillar and the fourth semiconductor pillar, and is in contact with the second semiconductor pillar and the fourth semiconductor pillar respectively. The third connecting block, the second semiconductor pillar and the fourth semiconductor pillar are at the same height in the third direction.

9. The semiconductor device according to claim 2, characterized in that, The first word line is also disposed on two sidewalls of the first semiconductor pillar that are arranged opposite to each other along the second direction; The second word line is also disposed on two sidewalls of the third semiconductor pillar that are positioned opposite each other along the second direction.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The semiconductor device further includes: Bit lines extend along a first direction and connect the source or drain regions of the first semiconductor pillars and the third semiconductor pillars arranged along the first direction. A storage cell extending in a third direction, the storage cell being connected to the drain or source of the first semiconductor pillar and the third semiconductor pillar.

11. A method for fabricating a semiconductor device, characterized in that, Provide substrate; A first semiconductor pillar is formed on the substrate. The first semiconductor pillar extends along a third direction perpendicular to the substrate. The first semiconductor pillar includes a first sidewall and a second sidewall disposed opposite to each other along a first direction parallel to the substrate. A second semiconductor pillar is formed by epitaxial growth on the first sidewall. The second semiconductor pillar is located on the substrate, extends along a third direction perpendicular to the substrate, and is connected to the first sidewall of the first semiconductor pillar. A first word line is formed, which extends along a second direction and is disposed on the second sidewall of the first semiconductor pillar; The first semiconductor pillar is made of a material with a first lattice constant, and the second semiconductor pillar is made of a material with a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, A third semiconductor pillar is also formed on the substrate, the third semiconductor pillar extending along a third direction perpendicular to the substrate, the third semiconductor pillar including a third sidewall and a fourth sidewall disposed opposite to each other along a first direction; A fourth semiconductor pillar is formed by epitaxial growth on the fourth sidewall of the third semiconductor pillar. The fourth semiconductor pillar extends along a third direction perpendicular to the substrate and is connected to the fourth sidewall of the third semiconductor pillar. The fourth semiconductor pillar and the second semiconductor pillar are arranged face to face. A second word line is formed, which extends along a second direction and is disposed on the third sidewall of the third semiconductor pillar; The first semiconductor pillar is made of a material with a first lattice constant, and the second semiconductor pillar is made of a material with a second lattice constant, wherein the second lattice constant is greater than the first lattice constant.

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