Semiconductor device and power conversion device

Abstract

To provide a semiconductor device that suppresses the operation of a parasitic bipolar transistor during recovery switching and achieves both low loss and high recovery tolerance.SOLUTION: A semiconductor device 100 has a gate-controlled diode 101 including: a first semiconductor layer 1 of a first conductivity type; a second semiconductor layer 2 of the first conductivity type having a lower impurity concentration than the first semiconductor layer; a third semiconductor layer 3 of a second conductivity type; a fourth semiconductor layer 4 of the second conductivity type having a higher impurity concentration than the third semiconductor layer; a fifth semiconductor layer 5 of the second conductivity type having a higher impurity concentration than the fourth semiconductor layer 4; a sixth semiconductor layer 6 of the first conductivity type; a first electrode 11; a second electrode 12; a gate insulating film 23; and a gate electrode 22. The second electrode includes a protrusion 12A in contact with the fifth semiconductor layer and the sixth semiconductor layer, and the fourth semiconductor layer is in contact with the fifth semiconductor layer and the gate insulating film and is arranged such that the fourth semiconductor layer 4 and the sixth semiconductor layer do not overlap when viewed in a plane.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a power conversion device. [Background technology]

[0002] Global warming has become a major, urgent issue shared worldwide, and expectations are rising for power electronics technology to contribute as one of the countermeasures. In particular, in order to increase the efficiency and miniaturization of power conversion devices such as inverters and converters that control power conversion functions, it is desirable to realize low-cost reductions in power consumption of power semiconductor devices, primarily IGBTs (Insulated Gate Bipolar Transistors) that perform the power switching function and diodes that perform the rectification function.

[0003] In recent years, technological development has been progressing to surpass the limits of low-loss performance of conventional IGBTs and diodes by combining power semiconductors and their control technology, which use silicon (Si), a material that is inexpensive and can utilize the vast assets cultivated in LSI. Conventional diodes are generally pn diodes made up of p-type and n-type semiconductors, but a new gate-controlled diode has been announced, which adds a MOS (Metal Oxide Semiconductor) gate and controls the gate to reduce loss.

[0004] The power consumption of power conversion devices such as inverters and converters is caused by power losses during the operation of power semiconductor devices. In particular, in diodes, these losses can be divided into conduction losses that occur during conduction and recovery losses that occur during recovery switching. Reducing both losses can achieve low-loss performance, but these losses depend on the charge concentration stored inside the diode, and there is a trade-off between them; reducing one will increase the other. While conventional Si pn diodes are low cost, the trade-off limits how much loss they can achieve. Gate-controlled diodes have a structure that allows the stored charge concentration to be controlled by the gate. By adjusting the timing of switching the applied gate bias, both conduction loss and recovery loss can be reduced, representing an innovative structure and concept that overcomes this trade-off.

[0005] An example of technology related to gate-controlled diodes is Patent Document 1. Figure 12 of Patent Document 1 shows a MOS-controlled diode (3) having an n+ layer (11), an n- layer (12), a p- layer (13), a p+ layer (14), a p layer (15), an n+ layer (132), a cathode electrode (21), an anode electrode (22, 220), a gate electrode (23), a gate insulating film (32), and an insulating film (31). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2023 / 219135 Summary of the Invention [Problem to be solved by the invention]

[0007] Miniaturization of power conversion equipment requires not only low loss in power semiconductor devices but also high breakdown voltage to allow for increased current density. In diodes, recovery switching involves a large current flowing from the cathode to the anode, while a high voltage is applied between the cathode and anode, resulting in high internal power loss. This power loss increases the temperature and can lead to breakdown. The increased power loss, especially as the current increases, increases the risk of breakdown. Therefore, diode characteristics stipulate a reverse recovery safe operating area (RRSOA), which is defined by the maximum allowable current and voltage, determined by breakdown voltage, in addition to loss performance. By improving recovery voltage and increasing RRSOA along with low loss performance, the current density permitted to users can be increased, enabling smaller power conversion equipment and increased power capacity.

[0008] In the MOS-controlled diode (3) (corresponding to a gate-controlled diode) shown in FIG. 12 of Patent Document 1, by applying a voltage to the gate electrode (23) immediately before reverse recovery, electrons accumulated in the n- layer (12) can be discharged to the anode electrode (220) via the n+ layer (132). This reduces the concentration of accumulated charge, reduces the reverse recovery current during reverse recovery (corresponding to recovery switching), and also reduces reverse recovery loss.

[0009] However, in the MOS-controlled diode (3) shown in Figure 12 of Patent Document 1, the n+ layer (132) in contact with the anode electrode (220) forms a parasitic bipolar transistor together with the underlying p layer (15), p- layer (13), and n- layer (12), and when this parasitic bipolar transistor operates, it becomes a source of electrons for the n- layer (12). Specifically, when holes flow into the anode electrode (220) via the p layer (15) during recovery operation, a voltage drop occurs in the p layer (15) due to the resistance of the p layer (15). Since the potential of the p layer (15) is higher than that of the n+ layer (132), particularly near the gate insulating film (32), the parasitic bipolar transistor operates, and electrons flow from the n+ layer (132) to the n- layer (12) via the p layer (15) and p- layer (13). The electrons thus supplied to the n-layer (12) induce holes, which leads to an amplification of the recovery current and is one of the factors that can lead to recovery breakdown.

[0010] Therefore, in gate-controlled diodes, it is important to suppress the operation of the parasitic bipolar transistor during recovery switching in order to achieve both low loss and high recovery capability.

[0011] The problem to be solved by the present invention is to provide a semiconductor device and a power conversion device that can suppress the operation of a parasitic bipolar transistor during recovery switching in a gate-controlled diode and achieve both low loss and high recovery tolerance. [Means for solving the problem]

[0012] In order to solve the above-mentioned problems, the semiconductor device of the present invention includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on a surface side of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on a surface side of the second semiconductor layer, a fourth semiconductor layer of the second conductivity type provided in a part of the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer, a fifth semiconductor layer of the second conductivity type provided in a part of the third semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer, a sixth semiconductor layer of the first conductivity type provided on the surface side of the third semiconductor layer, and a sixth semiconductor layer of the first conductivity type provided on a surface side of the third semiconductor layer. the gate electrode is disposed opposite the third semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer via the gate insulating film; the second electrode has a protrusion in contact with the fifth semiconductor layer and the sixth semiconductor layer; the fourth semiconductor layer is in contact with the fifth semiconductor layer; and the fourth semiconductor layer and the sixth semiconductor layer are disposed so as not to overlap each other in a plan view.

[0013] A power conversion device according to the present invention is characterized by using the semiconductor device described above. [Effects of the Invention]

[0014] According to the present invention, it is possible to realize a semiconductor device and a power conversion device that can suppress the operation of a parasitic bipolar transistor in a gate-controlled diode during recovery switching and achieve both low loss and high recovery tolerance. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a top view of a semiconductor device according to a first embodiment. [Figure 2] A-A' and B-B' cross-sectional views of Figure 1. [Figure 3]2 shows a circuit symbol and an equivalent circuit of the semiconductor device of Example 1. [Figure 4] FIG. 1 is a circuit diagram of a power conversion device according to a first embodiment. [Figure 5] 4 is a timing chart illustrating the operation of the power conversion device and the semiconductor device according to the first embodiment. [Figure 6] 6 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment during a period T1a in FIG. 5. [Figure 7] 6 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment during a period T1b in FIG. 5. [Figure 8] 6 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment in a period T2 in FIG. 5. [Figure 9] 6 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment in a period T3 in FIG. 5. [Figure 10] 3A to 3C are diagrams illustrating characteristics of the semiconductor device of Example 1. [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 12] FIG. 10 is a waveform diagram illustrating the operation of a semiconductor device of a comparative example. [Figure 13] FIG. 3 is a waveform diagram illustrating the operation of the semiconductor device according to the first embodiment. [Figure 14] 4A and 4B are diagrams illustrating the characteristics of semiconductor devices according to Example 1 and Comparative Example. [Figure 15] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment, corresponding to FIG. 2 of the first embodiment. [Figure 16] FIG. 10 is a top view of a semiconductor device according to a third embodiment. [Figure 17] 17A and 17B are cross-sectional views taken along the lines A-A' and B-B' in FIG. 16. [Figure 18] FIG. 10 is a top view of a semiconductor device according to a fourth embodiment. [Figure 19] 10A to 10C are diagrams illustrating characteristics of the semiconductor device of Example 4. [Figure 20] FIG. 10 is a top view of a semiconductor device according to a fifth embodiment. [Figure 21] Cross-sectional view taken along the line C-C' in Figure 20. [Figure 22] 10 is a cross-sectional view of a semiconductor device according to a sixth embodiment, corresponding to FIG. 2 of the first embodiment. [Figure 23]FIG. 13 is a top view of a semiconductor device according to a seventh embodiment. [Figure 24] A cross-sectional view taken along the line A-A' in Figure 23. [Figure 25] FIG. 13 is a top view of a semiconductor device according to an eighth embodiment. [Figure 26] 25A and 25B are cross-sectional views taken along the lines X-X', A-A', and B-B', respectively. [Figure 27] 10 is a circuit symbol of the semiconductor device of Example 8. [Figure 28] 13A to 13C are diagrams illustrating characteristics of the semiconductor device of Example 8. [Figure 29] FIG. 13 is a circuit diagram of a power conversion device according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted. [Example]

[0017] Fig. 1 is a top view of the semiconductor device of Example 1. Fig. 2 is a cross-sectional view taken along lines A-A' and B-B' in Fig. 1. Note that Fig. 1 corresponds to a cross-sectional view taken along line D-D' in Fig. 2, but in order to explain the arrangement in a plan view, the fourth semiconductor layer 4 and the gate electrode 22 are illustrated transparently with respect to the third semiconductor layer 3 on the surface side of the fourth semiconductor layer 4 and the interlayer insulating film 24 on the surface side of the gate electrode 22. This also applies to the subsequent figures.

[0018] In this embodiment, the first conductivity type of the semiconductor layer is n-type and the second conductivity type is p-type. However, this is not limiting, and the first conductivity type may be p-type and the second conductivity type may be n-type. When the first conductivity type is p-type and the second conductivity type is n-type, carrier holes and electrons are interchanged, and the anode and cathode are interchanged.

[0019] Also, the impurity concentration of the semiconductor layer increases in the order of n- < n < n+ and p- < p < p+. n+ and p+ mean high concentrations at which ohmic contact can be made with the electrodes. Note that the impurity concentration of the semiconductor layer in the embodiments is an example, and can be appropriately changed within the range where the operations intended in the embodiments can be realized.

[0020] Regarding the directions, the vertical direction in FIG. 2 is defined as the first direction D1, the horizontal direction between FIG. 2 and FIG. 1 is defined as the second direction D2, and the vertical direction in FIG. 1 is defined as the third direction D3 for explanation.

[0021] The semiconductor device 100 of this embodiment is a gate-controlled diode 101.

[0022] The semiconductor device 100 of this embodiment includes a first semiconductor layer 1 of a first conductivity type, a second semiconductor layer 2 of the first conductivity type provided on the surface side of the first semiconductor layer 1 and having an impurity concentration lower than that of the first semiconductor layer 1, a third semiconductor layer 3 of a second conductivity type provided on the surface side of the second semiconductor layer 2, a fourth semiconductor layer 4 of the second conductivity type provided in a part of the third semiconductor layer 3 and having an impurity concentration higher than that of the third semiconductor layer 3, a fifth semiconductor layer 5 of the second conductivity type provided in a part of the third semiconductor layer 3 and having an impurity concentration higher than that of the fourth semiconductor layer 4, a sixth semiconductor layer 6 of the first conductivity type provided on the surface side of the third semiconductor layer 3, a first electrode 11 provided on the back side of the first semiconductor layer 1 and in contact with the first semiconductor layer 1, a second electrode 12 provided on the surface side of the third semiconductor layer 3, a gate insulating film 23 in contact with the third semiconductor layer 3, the fourth semiconductor layer 4, and the sixth semiconductor layer 6, and a gate electrode 22 disposed to face the third semiconductor layer 3, the fourth semiconductor layer 4, and the sixth semiconductor layer 6 through the gate insulating film 23.

[0023] The first semiconductor layer 1 has an impurity concentration of, for example, a high concentration of n+, and functions as a cathode region. The second semiconductor layer 2 has an impurity concentration of, for example, a low concentration of n-, and functions as a drift region that relaxes the electric field and ensures high breakdown voltage. The third semiconductor layer 3 has an impurity concentration of, for example, a low concentration of p-, and functions as an anode region. The fourth semiconductor layer 4 has an impurity concentration of, for example, a medium concentration of p, and functions as a channel connection region. The fifth semiconductor layer 5 has an impurity concentration of, for example, a high concentration of p+, and functions as an anode injection region. The sixth semiconductor layer 6 has an impurity concentration of, for example, a high concentration of n+, and functions as an electron extraction region. The functions of these semiconductor layers will be explained in detail in the explanation of operation below. For example, Si can be used as the semiconductor layer.

[0024] The first electrode 11 is made of, for example, a conductive metal, and functions as a cathode electrode.

[0025] The second electrode 12 is formed of, for example, a conductive metal and functions as an anode electrode. The second electrode 12 has a protrusion 12A. In plan view, the protrusion 12A extends along a third direction D3. The protrusion 12A contacts the fifth semiconductor layer 5 and the sixth semiconductor layer 6 and forms ohmic contact therewith. In this example, the bottom of the protrusion 12A is located closer to the first semiconductor layer 1 than the sixth semiconductor layer 6, and the fifth semiconductor layer 5 contacts the bottom of the protrusion 12A, but this is not limiting.

[0026] The fourth semiconductor layer 4 is in contact with the fifth semiconductor layer 5. It is desirable that the fourth semiconductor layer 4 also be in contact with the protruding portion 12A, but since the fourth semiconductor layer 4 is connected to the protruding portion 12A at least via the fifth semiconductor layer 5, it does not have to be in contact with the protruding portion 12A. The fourth semiconductor layer 4 is provided in a partial region in the depth direction of the third semiconductor layer 3. In this example, an example is shown in which the third semiconductor layer 3 is also present on the surface side of the fourth semiconductor layer 4, but this is not limiting.

[0027] In this embodiment, the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged so as not to overlap each other in a planar view. Specifically, in this embodiment, the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged alternately so as not to overlap each other along the third direction D3 in which the protrusion 12A extends in a planar view. Therefore, in the region including the A-A' cross-sectional view, only the fourth semiconductor layer 4 of the fourth semiconductor layer 4 and the sixth semiconductor layer 6 is arranged, and in the region including the B-B' cross-sectional view, only the sixth semiconductor layer 6 of the fourth semiconductor layer 4 and the sixth semiconductor layer 6 is arranged, and these two regions are arranged alternately along the third direction D3. Note that the region including the A-A' cross-sectional view and the region including the B-B' cross-sectional view differ only in the presence or absence of the fourth semiconductor layer 4 and the sixth semiconductor layer 6, and otherwise have the same configuration, and are continuously formed along the third direction D3.

[0028] According to this embodiment, the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged so as not to overlap, and therefore there is no parasitic bipolar transistor formed by the sixth semiconductor layer 6, the fourth semiconductor layer 4, the third semiconductor layer 3, and the second semiconductor layer 2 as in the comparative example described below. This makes it possible to suppress the operation of the parasitic bipolar transistor during recovery switching, thereby achieving a high recovery tolerance. Details of this effect will be described later using a comparative example.

[0029] To enhance its function as an anode injection region, the fifth semiconductor layer 5 is desirably provided also in a cross section (e.g., cross section B-B') where the fourth semiconductor layer 4 is not provided when viewed in a cross section including the gate electrode 22 and the protrusion 12A. The fifth semiconductor layer 5 is not in contact with the gate insulating film. Furthermore, the fifth semiconductor layer 5 is desirably disposed closer to the first semiconductor layer 1 than the sixth semiconductor layer 6 in order to concentrate holes that constitute a recovery current in this region, as will be described later.

[0030] The gate electrode 22 is made of, for example, polysilicon, and the gate insulating film 23 is made of, for example, an oxide film.

[0031] The semiconductor device 100 of this embodiment also has a trench 21 and an interlayer insulating film 24. In this embodiment, an example will be described in which a so-called side gate structure is used as the structure of the gate electrode 22. However, this is not limiting, and a general trench gate structure in which a gate insulating film 23 and a gate electrode 22 are provided inside the trench 21 may also be applied.

[0032] In the side gate structure, a wide trench is used as the trench 21. Although not shown in FIG. 1, in a plan view, a plurality of protrusions 12A having a longitudinal direction in the third direction D3 are arranged side by side in the second direction D2, which is the lateral direction. A plurality of gate electrodes 22 are also arranged side by side in the second direction D2 corresponding to each of the plurality of protrusions 12A.

[0033] The wide trench 21 is disposed between the two protruding portions 12A. A gate insulating film 23, a gate electrode 22, and an interlayer insulating film 24 are provided inside the trench 21. Gate electrodes 22 corresponding to different protruding portions 12A are provided on one sidewall and the other sidewall of the trench 21, separated by the interlayer insulating film 24. That is, the sidewall side of the gate electrode 22 formed on the sidewall of the trench 21 is covered with the gate insulating film 23, and the opposite side is covered with the thick interlayer insulating film 24. The lower part of the gate electrode 22 is in contact with the gate insulating film 23, and the upper part is covered with the interlayer insulating film 24. The shape of the gate electrode 22 may be a so-called sidewall shape in which the width increases from top to bottom, but is not limited to this.

[0034] The interlayer insulating film 24 is formed of, for example, an oxide film. The interlayer insulating film 24 is also formed between the upper surface of the third semiconductor layer 3 and the second electrode 12, between the upper surface of the sixth semiconductor layer 6 and the second electrode 12, and between the upper surface of the gate electrode 22 and the second electrode 12. The interlayer insulating film 24 has contact holes in the portions of the protruding portions 12A.

[0035] FIG. 3 shows a circuit symbol and an equivalent circuit of the semiconductor device of the first embodiment.

[0036] As shown in the circuit symbol on the left side of FIG. 3, the semiconductor device 100 of this embodiment is a gate-controlled diode 101 that is composed of three terminals: an anode A, a cathode K, and a gate G, and operates as a diode by applying a voltage or current to each terminal.

[0037] As shown in the equivalent circuit on the right side of FIG. 3, the semiconductor device 100 of this embodiment is a gate-controlled diode 101 having a configuration including a pn diode 111 and an n-channel MOSFET 112 .

[0038] The pn diode 111 has an anode composed of a fifth semiconductor layer 5(p+), a fourth semiconductor layer 4(p), and a third semiconductor layer 3(p-), and a cathode composed of a second semiconductor layer 2(n-) and a first semiconductor layer 1(n+).

[0039] The n-channel MOSFET 112 has a source formed by the sixth semiconductor layer 6(n+), a body region formed by the third semiconductor layer 3(p-) and the fourth semiconductor layer 4(p), a drain formed by the second semiconductor layer 2(n-), and a gate formed by the gate electrode 22. The second semiconductor layer 2(n-) which is the drain of the n-channel MOSFET 112 is connected to the third semiconductor layer 3(p-) which is the anode of the pn diode 111.

[0040] In the gate-controlled diode 101, the n-channel MOSFET 112 is turned off when a voltage less than the threshold voltage is applied between the gate G and the anode A. In this state, a voltage less than the threshold voltage is applied between the gate electrode 22 and the second electrode 12, and a first state is reached in which a hole accumulation layer, which is an accumulation layer of first carriers (holes), is generated at the contact surface with the gate insulating film 23 of the third semiconductor layer 3 and the contact surface with the gate insulating film 23 of the fourth semiconductor layer 4.

[0041] On the other hand, in the gate-controlled diode 101, when a voltage equal to or greater than the threshold voltage is applied between the gate G and the anode A, the n-channel MOSFET 112 turns on. In this state, a voltage equal to or greater than the threshold voltage is applied between the gate electrode 22 and the second electrode 12, and the gate-controlled diode 101 enters a second state in which an electron inversion layer, which is an inversion layer of second carriers (electrons), is generated at the contact surface between the third semiconductor layer 3 and the gate insulating film 23. In the second state, an electron inversion layer is also generated at the contact surface between the fourth semiconductor layer 4 and the gate insulating film 23.

[0042] In the second state, the n-channel MOSFET 112 is turned on, creating a path for electrons to escape from the drain to the source. In the first state, the n-channel MOSFET 112 is turned off, eliminating the path for electrons to escape. By controlling the creation and disappearance of this path for electrons to escape, the electrical conductivity of the diode in the forward direction and during recovery can be controlled.

[0043] Next, the timing of control of the gate-controlled diode 101 will be described.

[0044] FIG. 4 is a circuit diagram of the power conversion device of the first embodiment.

[0045] The power conversion device 200 of this embodiment is an inverter that converts DC power from a DC power supply 210 having a voltage VCC into AC power and outputs it to an AC load 220 such as a motor. The AC load 220 has a load inductance.

[0046] The power conversion device 200 has an upper arm and a lower arm connected in series. The upper arm has an IGBT 102 (not shown) which is an upper arm switching element, and a gate-controlled diode 101 (not shown) which is an upper arm freewheel diode connected in anti-parallel to the IGBT 102. The lower arm has an IGBT 102 (not shown) which is a lower arm switching element, and a gate-controlled diode 101 (not shown) which is a lower arm freewheel diode connected in anti-parallel to the IGBT 102. The semiconductor device 100 of this embodiment is used as the gate-controlled diode 101. Here, attention is focused on the upper arm freewheel diode, and an example will be described in which a freewheel current IA from the AC load 220 flows back to the upper arm freewheel diode, so the upper arm switching element of the own arm and the lower arm freewheel diode of the opposite arm are not shown.

[0047] Fig. 5 is a timing chart illustrating the operation of the power conversion device and the semiconductor device of Example 1. The vertical axis of Fig. 5 represents current or voltage, and the horizontal axis represents time t.

[0048] FIG. 5 shows current or voltage waveforms for gate-controlled diode 101 in the upper arm, which is the arm of interest, and IGBT 102 in the lower arm, which is the paired arm.

[0049] During period T1, a voltage less than the threshold voltage, for example, −15 V or 0 V, is applied as gate voltage VGE to the IGBT 102 of the paired arm, and the IGBT 102 of the paired arm is in an off-state, non-conducting period. Thereafter, during periods T2 and T3, a voltage equal to or greater than the threshold voltage, for example, +15 V, is applied as gate voltage VGE to the IGBT 102 of the paired arm, and the IGBT 102 of the paired arm is in an on-state, conducting period. At this time, a current IC from the AC load 220 flows through the IGBT 102 of the paired arm in the direction from collector C to emitter E. Note that during periods T1 to T3 shown in FIG. 5, the IGBT 102 of the own arm is off.

[0050] On the other hand, in the gate-controlled diode 101 of the own arm, a first period T1 is a conduction period in which a positive voltage is applied to the second electrode 12 (anode A) with respect to the first electrode 11 (cathode K), and a current IA flows from the second electrode 12 to the first electrode 11. Therefore, the voltage VKA between the anode A and the cathode K is small.

[0051] Thereafter, in period T2, which is the second period, as a result of the IGBT 102 of the paired arm being turned on, the voltage VKA of the gate-controlled diode 101 of the own arm becomes substantially equal to the voltage VCC of the DC power supply 210, and a positive voltage is applied to the first electrode 11 (cathode K) relative to the second electrode 12 (anode A). Period T2 is the recovery period, and the current IA decreases, and after a recovery current temporarily flows in the reverse direction (from the first electrode 11 to the second electrode 12), the current stops flowing.

[0052] Then, during the third period T3, the gate-controlled diode 101 of the own arm continues to have a positive voltage applied to the first electrode 11 (cathode K) relative to the second electrode 12 (anode A), and the recovery period ends and the non-conducting period begins. During the non-conducting period, no current flows in the reverse direction (from the first electrode 11 to the second electrode 12), and the current IA is zero.

[0053] During periods T1a and T3 of period T1, a voltage less than the threshold voltage, for example, 0 V or −15 V, is applied to the voltage VGA between the gate G and anode A of the gate-controlled diode 101 of the own arm, and the voltage VGA is controlled to be in a first state in which the n-channel MOSFET 112 of the gate-controlled diode 101 is turned off. During periods T1b and T2 of period T1, a voltage equal to or greater than the threshold voltage, for example, +15 V, is applied to the voltage VGA, and the voltage VGA is controlled to be in a second state in which the n-channel MOSFET 112 of the gate-controlled diode 101 is turned on.

[0054] That is, the gate-controlled diode 101 of the own arm is switched from the first state to the second state in the period T1, the second state is maintained in the period T2, and the gate-controlled diode 101 of the own arm is switched from the second state to the first state in the period T3. The reason for this control will be explained below.

[0055] FIG. 6 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment during the period T1a in FIG.

[0056] During period T1a, which is a conduction period, a voltage less than the threshold voltage, for example, −15 V, is applied between gate G and anode A, and the n-channel MOSFET 112 is in the first state where it is turned off. In this state, hole accumulation layers are generated at the contact surface of the third semiconductor layer 3 with the gate insulating film 23 and at the contact surface of the fourth semiconductor layer 4 with the gate insulating film 23.

[0057] As a result, in the A-A' cross section where the fourth semiconductor layer 4 is provided, holes 32 are supplied from the fifth semiconductor layer 5, which functions as an anode injection region, to the hole accumulation layer of the third semiconductor layer 3, which functions as an anode region, via the fourth semiconductor layer 4, which functions as a channel connection region, and a high concentration of holes 32 is supplied from the third semiconductor layer 3 to the second semiconductor layer 2, which functions as a drift region. In response to this, a high concentration of electrons 31 is supplied from the first semiconductor layer 1, which functions as a cathode region, to the second semiconductor layer 2, causing conductivity modulation. As a result, a high concentration of holes 32 and electrons 31 is accumulated in the second semiconductor layer 2, reducing the forward voltage drop (VF) of the diode and achieving low conduction loss performance.

[0058] In the B-B' cross section where the fourth semiconductor layer 4 is not provided, the holes 32 supplied from the fifth semiconductor layer 5 are supplied directly to the second semiconductor layer 2 via the third semiconductor layer 3 without passing through the hole accumulation layer. Therefore, the concentration of the supplied holes 32 and electrons 31 is lower than in the A-A' cross section.

[0059] FIG. 7 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment during the period T1b in FIG.

[0060] Period T1b is the conduction period immediately before the recovery period, and a voltage equal to or greater than the threshold voltage, for example, +15 V, is applied between gate G and anode A. An electron inversion layer is generated at the contact surface between the third semiconductor layer 3 and the gate insulating film 23, and the n-channel MOSFET 112 is in the second state in which it is turned on.

[0061] In this state, an electron path to the sixth semiconductor layer 6 is generated in the B-B' cross section where the sixth semiconductor layer 6, which functions as an electron extraction region, is provided. As a result, the electrons 31 accumulated in the second semiconductor layer 2 reach the sixth semiconductor layer 6 via this electron path and are released to the second electrode 12, which is an anode electrode. This suppresses conductivity modulation and reduces the concentrations of the electrons 31 and holes 32 accumulated in the second semiconductor layer 2. When a recovery operation is performed from this state in the next period T2, the recovery current decreases, resulting in low recovery loss.

[0062] Furthermore, in the A-A' cross section, the hole accumulation layer disappears, resulting in a state similar to that of the B-B' cross section in period T1a, and the concentration of holes 32 supplied to the second semiconductor layer 2 decreases, which also contributes to reducing the concentration of electrons 31 and holes 32 accumulated in the second semiconductor layer 2.

[0063] The period T1b requires a time tpre_rr (see FIG. 5) to reduce and stabilize the concentration of the accumulated charges (electrons 31 and holes 32) accumulated in the second semiconductor layer 2, which takes several microseconds to several tens of microseconds, and the timing to switch to the period T1b is set taking this time into consideration. In particular, the thicker the second semiconductor layer 2 is in the semiconductor device 100 and the higher the breakdown voltage, the longer the time required to remove the accumulated charges.

[0064] FIG. 8 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment during the period T2 in FIG.

[0065] The period T2 is a recovery period, and the second state in which the n-channel MOSFET 112 is turned on is maintained.

[0066] In this state, holes 32 accumulated in the second semiconductor layer 2 pass through the fourth semiconductor layer 4 and / or the fifth semiconductor layer 5 in the A-A' cross section, and through the fifth semiconductor layer 5 in the B-B' cross section, and then pass through the fifth semiconductor layer 5 to the second electrode 12, which serves as the anode electrode. Also, electrons 31 accumulated in the second semiconductor layer 2 pass through the first semiconductor layer 1 to the first electrode 11, which serves as the cathode electrode. As a result, a recovery current temporarily flows in the reverse direction of the current IA. At this time, a high voltage, approximately the same as the power supply voltage VCC, is applied to the cathode-anode voltage VKA, and therefore a recovery loss occurs.

[0067] At this time, in this embodiment, the concentration of electrons 31 and holes 32 accumulated in the second semiconductor layer 2 is reduced in advance during the period T1b, so that the recovery current during the period T2 is reduced, and low recovery loss performance is obtained.

[0068] Furthermore, since the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged so as not to overlap, there is no parasitic bipolar transistor. Therefore, in the period T2, the operation of the parasitic bipolar transistor during recovery switching can be suppressed, thereby achieving a high recovery withstand capability.

[0069] Furthermore, in the B-B' cross section, the fifth semiconductor layer 5 is positioned closer to the first semiconductor layer 1 than the sixth semiconductor layer 6, so that the holes 32 that constitute the recovery current can be concentrated in this area.

[0070] If the concentration of the third semiconductor layer 3 is adjusted for a high cathode-anode voltage VKA, the extension of depletion stops within the third semiconductor layer 3, as shown by the depletion layer edge 33, and the depletion layer can be prevented from reaching the interface with the gate insulating film 23. A large number of electrons 31 exist in the third semiconductor layer 3 near the gate insulating film 23. If the depletion layer collides with this, the electrons 31 flow downward, increasing the leakage current and making it impossible to ensure a high breakdown voltage. Therefore, by preventing the depletion layer from reaching the interface with the gate insulating film 23, the leakage current can be suppressed and high breakdown voltage performance can be ensured.

[0071] FIG. 9 is a cross-sectional view illustrating the operation of the semiconductor device of the first embodiment during the period T3 in FIG.

[0072] In period T3, recovery switching is completed, the second semiconductor layer 2 and the third semiconductor layer 3 block the high voltage, and this is a non-conduction period waiting for the next conduction timing. In preparation for the next conduction period, during this period, a voltage less than the threshold voltage, for example, −15 V, is applied between the gate G and the anode A, and the n-channel MOSFET 112 is kept in the first state in which it is turned off.

[0073] Fig. 10 is a diagram illustrating the characteristics of the semiconductor device of Example 1. Fig. 10 shows the forward characteristics of the gate-controlled diode 101 of this example, with the horizontal axis representing the forward voltage drop VF (V) and the vertical axis representing the forward current IF (A).

[0074] As shown in FIG. 10 , the gate-controlled diode 101 of this embodiment exhibits a change in forward voltage drop VF when a voltage less than the threshold voltage, e.g., −15 V, is applied between the gate G and the anode A (VGA = −15 V) and a voltage greater than or equal to the threshold voltage, e.g., +15 V, is applied (VGA = +15 V). Applying a voltage less than the threshold voltage between the gate G and the anode A provides a low VF across a wide range of forward currents IA. The low VF characteristic results in low conduction loss. Since the threshold voltage of the third semiconductor layer 3 is typically positive, a low VF equivalent to −15 V can be achieved even when the bias between the gate G and the anode A is 0 V. On the other hand, applying a voltage greater than or equal to the threshold voltage between the gate G and the anode A provides a high VF characteristic. The high VF characteristic results from a low amount of charge stored in the second semiconductor layer 2, which reduces the recovery current and recovery loss. Therefore, by controlling the voltage between the gate G and the anode A as in this embodiment, it is possible to achieve both low conduction loss and low recovery loss.

[0075] FIG. 11 is a cross-sectional view of a semiconductor device of a comparative example.

[0076] 11 , the semiconductor device 100 of the comparative example differs from this embodiment in that the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged to overlap each other. Therefore, the semiconductor device 100 of the comparative example has a parasitic bipolar transistor configured by the sixth semiconductor layer 6, the fourth semiconductor layer 4, the third semiconductor layer 3, and the second semiconductor layer 2.

[0077] During recovery switching, holes 32 accumulated in the second semiconductor layer 2 flow into the second electrode 12, which serves as an anode electrode, via the third semiconductor layer 3 and the fourth semiconductor layer 4 and / or the fifth semiconductor layer 5. At this time, when the holes 32 flow through the fourth semiconductor layer 4, a voltage drop occurs in the fourth semiconductor layer 4 due to the resistance of the fourth semiconductor layer 4, and the potential of the fourth semiconductor layer 4 becomes higher than that of the sixth semiconductor layer 6, particularly near the gate insulating film 23. As a result, a parasitic bipolar transistor operates, and electrons 31 supplied from the second electrode 12 to the sixth semiconductor layer 6 flow from the sixth semiconductor layer 6 to the second semiconductor layer 2 via the fourth semiconductor layer 4 and the third semiconductor layer 3. During recovery switching, the high voltage between the cathode K and the anode A causes impact ionization in the second semiconductor layer 2. Electrons 31 flowing into the second semiconductor layer 2 further accelerate the impact ions, generating holes 32. The generated holes 32 flow into the second electrode 12 as a recovery current and attract electrons 31 from the second electrode 12, increasing the recovery current and creating positive feedback. As a result, during recovery switching under high current conditions, the operation of this parasitic bipolar transistor increases the recovery current, causing power loss and a rise in temperature, which may lead to breakdown. In other words, the operation of this parasitic bipolar transistor is a factor that determines the recovery tolerance.

[0078] 12 is a waveform diagram illustrating the operation of the semiconductor device of the comparative example, in which the vertical axis represents current or voltage, and the horizontal axis represents time t.

[0079] As shown in Figure 12, during recovery operation, current IA flows in the reverse direction, causing voltage VKA to rise. At time t1, when the impact ionization rate increases in the second semiconductor layer 2, the risk of breakdown increases, resulting in breakdown. When breakdown occurs, the high voltage between cathode K and anode A cannot be maintained, causing a short circuit. Current IA increases infinitely until it is limited by an external resistor or other device, making normal recovery difficult. The magnitude of the current that does not cause this breakdown phenomenon is the diode's recovery capability, which is the current that can flow through the diode. Therefore, recovery capability, along with low-loss performance, is an important indicator for increasing the diode's current density.

[0080] Fig. 13 is a waveform diagram illustrating the operation of the semiconductor device of Example 1. In Fig. 13, the vertical axis represents current or voltage, and the horizontal axis represents time t.

[0081] In this embodiment, the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged so as not to overlap, and therefore there is no parasitic bipolar transistor formed by the sixth semiconductor layer 6, the fourth semiconductor layer 4, the third semiconductor layer 3, and the second semiconductor layer 2 as in the comparative example. This makes it possible to suppress the operation of the parasitic bipolar transistor during recovery switching. As a result, even at time t1, no breakdown occurs and the recovery operation can be completed normally, thereby achieving a high recovery tolerance.

[0082] Figure 14 is a diagram illustrating the characteristics of the semiconductor devices of Example 1 and Comparative Example. The vertical axis represents the recovery tolerance under maximum voltage conditions, increasing toward the top and decreasing toward the bottom. The horizontal axis represents the loss (conduction loss + recovery loss) under rated conditions, decreasing toward the left and increasing toward the right. Therefore, in Figure 14, the performance is better the further to the top left.

[0083] Characteristic P1 is a characteristic of a general pn diode, with a low recovery tolerance and a large conduction loss + recovery loss. With general pn diodes, there is a trade-off between conduction loss and recovery loss, and there is a limit to how much loss can be reduced.

[0084] Characteristic P2 is the characteristic of a gate-controlled diode of the comparative example, and similarly to the present embodiment, by controlling the gate and switching the characteristics as shown in Fig. 10, the trade-off between conduction loss and recovery loss is overcome, and low-loss performance that cannot be obtained with a general pn diode is obtained. On the other hand, the comparative example has a problem in that the recovery withstand capability cannot be increased due to the influence of the operation of a parasitic bipolar transistor during recovery switching.

[0085] Characteristic P3 is the characteristic of an improved gate-controlled diode for comparison. To solve the problem of characteristic P2, an improvement was made to reduce the lifetime of the drift region. Specifically, by irradiating the drift region with a lifetime killer, conductivity modulation in the drift region is suppressed and the recovery current is reduced. However, this improvement method has the side effect of increasing conduction loss. As shown in Figure 14, characteristic P3 is shifted to the upper right from characteristic P2.

[0086] On the other hand, characteristic P4 is a characteristic of the gate-controlled diode of Example 1, and by arranging the fourth semiconductor layer 4 and the sixth semiconductor layer 6 so that they do not overlap, it is possible to suppress the operation of a parasitic bipolar transistor during recovery switching, and improve the recovery tolerance while maintaining low-loss performance, without making any improvements to reduce the lifetime of the drift region.

[0087] As described above, according to this embodiment, in the gate-controlled diode 101, it is possible to suppress the operation of a parasitic bipolar transistor during recovery switching, thereby realizing the semiconductor device 100 and the power conversion device 200 that can achieve both low loss and high recovery tolerance. [Example]

[0088] 15 is a cross-sectional view of a semiconductor device of Example 2, corresponding to FIG. 2 of Example 1. The top view is the same as FIG.

[0089] Example 2 is a modification of Example 1, in which the third semiconductor layer 3 is not present on the surface side of the fourth semiconductor layer 4, and the upper surface of the fourth semiconductor layer 4 is at approximately the same height as the upper surface of the sixth semiconductor layer 6. Since the fourth semiconductor layer 4 is formed by thermal diffusion after implanting p-type impurities into the semiconductor layer, it is actually conceivable that the fourth semiconductor layer 4 will extend up to the upper surface of the semiconductor layer in this way. Even with this configuration, the same effects as in Example 1 can be obtained. [Example]

[0090] Fig. 16 is a top view of a semiconductor device according to Example 3. Fig. 17 is a cross-sectional view taken along line AA' and BB' in Fig. 16 .

[0091] Example 3 is a modification of Example 1, in which the bottom of the protrusion 12A of the second electrode 12 does not extend into the semiconductor layer but contacts the surface side of the semiconductor layer.

[0092] In the A-A' cross section, the fifth semiconductor layer 5 and the fourth semiconductor layer 4 are disposed on the surface side of the semiconductor layer, and the fourth semiconductor layer 4 is in contact with the fifth semiconductor layer 5. The bottom of the protruding portion 12A is in contact with at least the fifth semiconductor layer 5.

[0093] In the B-B' cross section, a fifth semiconductor layer 5 and a sixth semiconductor layer 6 are disposed on the surface side of the semiconductor layer, and the sixth semiconductor layer 6 is in contact with the fifth semiconductor layer 5. The bottom of the protruding portion 12A is in contact with at least the fifth semiconductor layer 5. The bottom of the fifth semiconductor layer 5 is formed to a position closer to the first semiconductor layer 1 than the bottom of the sixth semiconductor layer 6, and is in contact with the third semiconductor layer 3. This allows the recovery current in the B-B' cross section to be concentrated in the fifth semiconductor layer 5, and reduces the risk of parasitic bipolar transistor operation in the B-B' cross section.

[0094] In this embodiment, the same effect as in embodiment 1 can be obtained, and when forming the protrusion 12A of the second electrode 12, it can be achieved by etching only the interlayer insulating film 24, and etching of the semiconductor layer is not necessary, so it can be achieved at a lower cost than embodiment 1. [Example]

[0095] 18 is a top view of the semiconductor device of Example 4. The cross-sectional view is the same as FIG.

[0096] Example 4 is a modification of Example 1, and in plan view, the length α of the fourth semiconductor layer 4 along the extending direction of the protruding portion 12A (third direction D3) is different from the length β of the sixth semiconductor layer 6 along the extending direction of the protruding portion 12A. By adjusting the lengths α and β, it is possible to adjust the characteristics of the gate-controlled diode 101 of this example.

[0097] 19 is a diagram illustrating the characteristics of the semiconductor device of Example 4. FIG. 19 is a diagram corresponding to FIG.

[0098] The ratio of the sixth semiconductor layer 6 is defined as β / (α+β). Fig. 19 shows the forward characteristics of the gate-controlled diode 101 of this example when β / (α+β) is changed. When β / (α+β)=0.5, α and β are in the same ratio, which is the same as in Example 1.

[0099] When β / (α+β)>0.5, the increase in forward voltage drop VF is greater than in Example 1. Because the proportion of the sixth semiconductor layer 6 is greater than in Example 1, the effect of suppressing electrical conductivity at voltage VGA=+15V, as described in FIG. 7, is greater than in Example 1, the recovery current, as described in FIG. 8, is smaller than in Example 1, and the effect of reducing recovery loss is greater than in Example 1. On the other hand, because the proportion of the fourth semiconductor layer 4 is smaller than in Example 1, the effect of supplying holes 32 in the A-A' cross section at voltage VGA=-15V, as described in FIG. 6, is smaller than in Example 1, and the forward voltage drop VF and conduction loss are also slightly higher than in Example 1. However, the increase in forward voltage drop VF at voltage VGA=-15V is smaller than when voltage VGA=+15V. Therefore, although the forward voltage drop VF is slightly higher than in Example 1, the low VF characteristic remains unchanged compared to a typical pn diode.

[0100] When β / (α+β)<0.5, the opposite occurs to when β / (α+β)>0.5, and the increase in forward voltage drop VF is smaller than in Example 1. Therefore, the effect of reducing recovery loss when voltage VGA=+15V is smaller than in Example 1, but the conduction loss when voltage VGA=−15V is slightly smaller than in Example 1.

[0101] Therefore, by adjusting β / (α+β), it is possible to adjust the trade-off between conduction loss and recovery loss. The proportion of conduction loss and recovery loss in the total loss of the power conversion device 200 varies depending on the drive frequency of the power conversion device 200. Therefore, by adjusting β / (α+β) according to how the power conversion device 200 is used, i.e., the drive frequency, it is possible to optimize the total loss by reducing the conduction loss and recovery loss. [Example]

[0102] Fig. 20 is a top view of the semiconductor device of Example 5. Fig. 21 is a cross-sectional view taken along CC' in Fig. 20. Note that the cross-sectional views AA' and BB' in Fig. 20 are the same as Fig. 2.

[0103] Example 5 is a modified example of Example 1, in which, when viewed in a plane, the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged alternately along the direction in which the protrusion 12A extends (third direction D3), with a region in between where neither the fourth semiconductor layer 4 nor the sixth semiconductor layer 6 is arranged.

[0104] Between the A-A' cross-sectional area and the B-B' cross-sectional area is the C-C' cross-sectional area, where neither the fourth semiconductor layer 4 nor the sixth semiconductor layer 6 is disposed. The fifth semiconductor layer 5 is also disposed in the C-C' cross-section.

[0105] In this embodiment, the same effects as in the first embodiment can be obtained, and unintended overlapping of the fourth semiconductor layer 4 and the sixth semiconductor layer 6 can be prevented, thereby reducing the risk of forming a parasitic bipolar transistor more than in the first embodiment. Since the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are formed by patterning using photolithography and implantation, the accuracy of mask alignment must be taken into consideration. Therefore, by providing a region of the C-C' cross section, unintended overlapping can be prevented and reliability can be improved. [Example]

[0106] 22 is a cross-sectional view of a semiconductor device of Example 6, corresponding to FIG. 2 of Example 1. The top view is the same as FIG.

[0107] Example 6 is a modification of Example 1, and is an example in which a low lifetime region 41 having a locally low carrier lifetime is provided in a partial region in the depth direction inside the second semiconductor layer 2, including at least a region overlapping with the sixth semiconductor layer 6. The low lifetime region 41 is locally formed by irradiation with a lifetime killer such as protons. Note that, although FIG. 22 shows an example in which the low lifetime region 41 is provided in the second semiconductor layer 2 in the B-B' cross section and the low lifetime region 41 is not provided in the second semiconductor layer 2 in the A-A' cross section, the present invention is not limited to this.

[0108] By providing the low lifetime region 41 as in this embodiment, the accumulated charge concentration in the B-B' cross section during the period T1b described in Fig. 7 is further reduced than in Example 1, and the recovery current generated by the recovery switching during the period T2 described in Fig. 8 can be further reduced than in Example 1. In addition, since the concentration of holes 32 returning to the fifth semiconductor layer 5 is reduced, the operation risk of a parasitic bipolar transistor can be further reduced, and the recovery tolerance can be improved.

[0109] Furthermore, by not providing the low lifetime region 41 in the A-A' cross section and instead introducing the low lifetime region 41 locally in the B-B' cross section, the amount of holes 32 injected from the A-A' cross section is not affected in the conductive state during the period T1a described in Fig. 6, and therefore the side effect of an increase in forward voltage drop VF is less likely to occur. Therefore, it is possible to further improve the recovery tolerance while maintaining low-loss performance.

[0110] Even if the low lifetime region 41 is provided on the A-A' cross section, the effect of lower loss than a general pn diode can be obtained.

[0111] Furthermore, the low lifetime region 41 may also be formed in a semiconductor layer other than the second semiconductor layer 2. Even in this case, the effects of this embodiment can be obtained. For example, when a lifetime killer is irradiated from above, the low lifetime region 41 may be formed in a semiconductor layer above the second semiconductor layer 2, in addition to the second semiconductor layer 2. Similarly, when a lifetime killer is irradiated from below, the low lifetime region 41 may be formed in a semiconductor layer below the second semiconductor layer 2, in addition to the second semiconductor layer 2. [Example]

[0112] Fig. 23 is a top view of the semiconductor device of Example 7. Fig. 24 is a cross-sectional view taken along line AA' of Fig. 23.

[0113] Example 7 is a modified example of Example 1, and when viewed in a plane, multiple protrusions 12A are arranged side by side, and protrusions 12A that contact the sixth semiconductor layer 6 and protrusions 12A that do not contact the sixth semiconductor layer 6 are arranged alternately.

[0114] The protruding portion 12A on the left side of FIG. 24 does not have a corresponding sixth semiconductor layer 6 formed thereon, but has a fourth semiconductor layer 4 formed thereon. That is, it has a structure similar to the A-A' cross section of FIG. 2. On the other hand, the protruding portion 12A on the right side of FIG. 24 has a corresponding sixth semiconductor layer 6 formed thereon, but has no fourth semiconductor layer 4 formed thereon. That is, it has a structure similar to the B-B' cross section of FIG. 2.

[0115] In this embodiment, as in the first embodiment, the fourth semiconductor layer 4 and the sixth semiconductor layer 6 are arranged so as not to overlap, so that the operation of a parasitic bipolar transistor during recovery switching can be suppressed, and a high recovery withstand capability can be achieved. Other effects of the first embodiment can also be obtained in the same way. [Example]

[0116] Fig. 25 is a top view of a semiconductor device of Example 8. Fig. 26 is a cross-sectional view taken along lines XX', AA', and BB' of Fig. 25.

[0117] The eighth embodiment is a modification of the first embodiment, and is an embodiment of an RC-IGBT 103 (RC: Reverse-Conducting IGBT) in which the IGBT 102 and the gate-controlled diode 101 are built in the same chip.

[0118] The semiconductor device 100 of this embodiment is an RC-IGBT 103 having an IGBT 102 and a gate-controlled diode 101 on the same semiconductor substrate. Therefore, the second semiconductor layer 2 is common to the IGBT 102 and the gate-controlled diode 101, and at least some of the other semiconductor layers and electrodes can be formed simultaneously.

[0119] As shown in FIG. 26, the structure of the gate-controlled diode 101 of the semiconductor device 100 of this embodiment taken along the lines AA' and BB' is the same as that shown in FIG.

[0120] As shown in the X-X' cross section, the IGBT 102 of the semiconductor device 100 of this embodiment has a seventh semiconductor layer 7 of the second conductivity type, which is provided on the back surface side of the second semiconductor layer 2 in a region that does not overlap with the first semiconductor layer 1 in a plan view and is in contact with the first electrode 11. In the region overlapping with the seventh semiconductor layer 7, the IGBT 102 has the second semiconductor layer 2, the third semiconductor layer 3, the fifth semiconductor layer 5, the sixth semiconductor layer 6, the gate insulating film 23, the gate electrode 22, the first electrode 11, the second electrode 12, and the protrusion 12A, but does not have the fourth semiconductor layer 4. The gate insulating film 23 is in contact with the second semiconductor layer 2, the third semiconductor layer 3, and the sixth semiconductor layer 6, and the gate electrode 22 is arranged opposite the second semiconductor layer 2, the third semiconductor layer 3, and the sixth semiconductor layer 6 with the gate insulating film 23 interposed therebetween.

[0121] That is, in the IGBT 102, there is no fourth semiconductor layer 4, the third semiconductor layer 3 has a shallower bottom than the gate-controlled diode 101, and the trench 21 is formed deep enough to reach the second semiconductor layer 2.

[0122] In the IGBT 102, the seventh semiconductor layer 7 has an impurity concentration of, for example, a high concentration of p+ and functions as a collector region, the second semiconductor layer 2 functions as a drift region, the third semiconductor layer 3 functions as a body region, the fifth semiconductor layer 5 functions as a contact region, the sixth semiconductor layer 6 functions as an emitter region, the first electrode 11 functions as a collector electrode, and the second electrode 12 functions as an emitter electrode.

[0123] The gate electrode 22 of the IGBT 102 in the region overlapping with the seventh semiconductor layer 7 and the gate electrode 22 of the gate-controlled diode 101 in the region overlapping with the first semiconductor layer 1 can be driven independently of each other. Therefore, in order to distinguish between them, in this embodiment, the gate of the IGBT 102 will be referred to as an IGBT gate Gi, and the gate of the gate-controlled diode 101 (gate G in the first embodiment) will be referred to as a diode gate Gd. The operation of the gate-controlled diode 101 is the same as in the first embodiment, and the operation of the IGBT 102 is the same as that of a general IGBT, so detailed description will be omitted.

[0124] FIG. 27 shows a circuit symbol of the semiconductor device of the eighth embodiment.

[0125] The semiconductor device 100 of this embodiment is composed of three terminals: a collector C, an emitter E, an IGBT gate Gi, and a diode gate Gd. Since the gate-controlled diode 101 is connected in antiparallel to the IGBT 102, the collector C is connected to the cathode K of the gate-controlled diode 101, and the emitter E is connected to the anode A of the gate-controlled diode 101, forming an RC-IGBT 103.

[0126] Fig. 28 is a diagram illustrating the characteristics of the semiconductor device of Example 8. Fig. 28 shows the forward and reverse conduction characteristics of the RC-IGBT 103 of this example. In Fig. 28, the vertical axis represents the current I, and the horizontal axis represents the voltage VCE between the collector C and the emitter E.

[0127] By applying a positive bias to the voltage VCE and applying a voltage equal to or greater than the threshold voltage, for example, +15 V, to the voltage VGiE between the IGBT gate Gi and the emitter E, the IGBT 102 becomes conductive and a current Ii flows in the positive direction. Note that the direction of the current I and the current Ii is defined as the downward direction from the collector C to the emitter E in FIG. 27.

[0128] Furthermore, by applying a negative bias to the voltage VCE, a current Id flows in the opposite direction to the current Ii. This is due to the conduction of the gate-controlled diode 101. The electrical conductivity is controlled by applying a voltage equal to or greater than the threshold voltage, for example, +15 V, or a voltage less than the threshold voltage, for example, −15 V, as the voltage VGdE between the diode gate Gd and the emitter E, thereby achieving the effect of the gate-controlled diode 101 described in the first embodiment.

[0129] Therefore, in this embodiment, current can be passed in both directions as the RC-IGBT 103, and in diode operation, the effects of the first embodiment, such as low loss and high recovery tolerance, can be obtained. [Example]

[0130] FIG. 29 is a circuit diagram of a power conversion device according to a ninth embodiment.

[0131] The power conversion device 200 of this embodiment is an inverter that converts DC power from a DC power supply 210 having a voltage VCC into AC power and outputs it to an AC load 220 such as a motor.

[0132] The power conversion device 200 has an upper arm and a lower arm connected in series. The upper arm has an IGBT 102 which is an upper arm switching element, and a gate-controlled diode 101 which is an upper arm freewheel diode connected in anti-parallel to the IGBT 102. The lower arm has an IGBT 102 which is a lower arm switching element, and a gate-controlled diode 101 which is a lower arm freewheel diode connected in anti-parallel to the IGBT 102. An alternating current is output from a connection node between the upper arm and the lower arm. Although FIG. 29 shows a configuration having upper arms and lower arms for three phases, the configuration is not limited to this.

[0133] The power conversion device 200 also includes a gate drive circuit 201 and a command unit 202. The gate drive circuit 201 applies drive signals to the gate of the IGBT 102 and the gate of the gate-controlled diode 101 based on a command from the command unit 202, thereby driving the IGBT 102 and the gate-controlled diode 101.

[0134] Here, the gate-controlled diode 101 can be the gate-controlled diode 101 of the semiconductor device 100 of Examples 1 to 7. Alternatively, the IGBT 102 and the gate-controlled diode 101 can be the RC-IGBT 103 of the semiconductor device 100 of Example 8.

[0135] In this embodiment, an inverter that converts DC power into AC power has been described as an example of the power conversion device 200 using the semiconductor device 100, but the present invention is not limited to this and may be a converter that converts AC power into DC power, or a power conversion device that has the functions of both an inverter and a converter.

[0136] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0137] 1: First semiconductor layer (cathode region) (n+) 2: Second semiconductor layer (drift region) (n-) 3: Third semiconductor layer (anode region, body region) (p-) 4: Fourth semiconductor layer (channel connection region) (p) 5: Fifth semiconductor layer (anode injection region, contact region) (p+) 6: Sixth semiconductor layer (electron extraction region, emitter region) (n+) 7: Seventh semiconductor layer (collector region) (p+) 11: First electrode (cathode electrode, collector electrode) 12: Second electrode (anode electrode, emitter electrode) 12A: Protrusion 21: Trench 22: Gate electrode 23: Gate insulating film 24: Interlayer insulating film 31:Electronic 32: Hole 33: Depletion layer edge 41: Low lifetime region 100: Semiconductor device 101: Gate-controlled diode 102:IGBT 103:RC-IGBT 111: pn diode 112: n-channel MOSFET 200: Power conversion device 201: Gate drive circuit 202: Command Department 210: DC power supply 220:AC load A: Anode K: Cathode G: Gate Gd: Diode gate Gi: IGBT gate C: Collector E: Emitter D1: First direction D2: Second direction D3: The third direction t: time

Claims

1. a first semiconductor layer of a first conductivity type; a second semiconductor layer of a first conductivity type provided closer to the surface than the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the surface than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided in a part of the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer; a fifth semiconductor layer of the second conductivity type provided in a part of the third semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the first conductivity type provided on a surface side of the third semiconductor layer; a first electrode provided on a back surface side of the first semiconductor layer and in contact with the first semiconductor layer; a second electrode provided on a surface side of the third semiconductor layer; a gate insulating film in contact with the third semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer; a gate electrode disposed opposite the third semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer via the gate insulating film; the second electrode has a protruding portion in contact with the fifth semiconductor layer and the sixth semiconductor layer, the fourth semiconductor layer is in contact with the fifth semiconductor layer, A semiconductor device, characterized in that the fourth semiconductor layer and the sixth semiconductor layer are arranged so as not to overlap each other when viewed in a plane.

2. In claim 1, When viewed in cross section along a cross section including the gate electrode and the protrusion, the fifth semiconductor layer is also provided in a cross section where the fourth semiconductor layer is not provided.

3. In claim 1, A semiconductor device, characterized in that, in a plan view, the fourth semiconductor layers and the sixth semiconductor layers are alternately arranged along a direction in which the protrusions extend.

4. In claim 3, A semiconductor device characterized in that, when viewed in a plane, the length of the fourth semiconductor layer along the direction in which the protrusion extends is different from the length of the sixth semiconductor layer along the direction in which the protrusion extends.

5. In claim 3, A semiconductor device characterized in that, when viewed in a plane, the fourth semiconductor layer and the sixth semiconductor layer are alternately arranged along the direction in which the protrusion extends, with an area in between where neither the fourth semiconductor layer nor the sixth semiconductor layer is arranged.

6. In claim 1, When viewed in a plane, the protrusions are arranged in a row, and protrusions that contact the sixth semiconductor layer and protrusions that do not contact the sixth semiconductor layer are arranged alternately.

7. In claim 1, The semiconductor device according to claim 1, wherein the fifth semiconductor layer is not in contact with the gate insulating film and is located closer to the first semiconductor layer than the sixth semiconductor layer.

8. In claim 1, a bottom of the protrusion is located closer to the first semiconductor layer than to the sixth semiconductor layer; The semiconductor device is characterized in that the fifth semiconductor layer is in contact with the bottom of the protrusion.

9. In claim 1, a trench provided therein with the gate insulating film, the gate electrode, and an interlayer insulating film; When viewed in a plan view, the protrusions are arranged in a row, a gate electrode provided on one side wall and the other side wall of the trench, the gate electrode being spaced apart with the interlayer insulating film therebetween and corresponding to the different protrusions, said gate electrode being provided on one side wall and the other side wall of the trench, the gate electrode being spaced apart with the interlayer insulating film therebetween and corresponding to the different protrusions,

10. In claim 1, A semiconductor device comprising: a low lifetime region having a locally low carrier lifetime in a portion of a depth direction inside the second semiconductor layer, the low lifetime region including at least a region overlapping with the sixth semiconductor layer.

11. In claim 1, a first state in which a voltage less than a threshold voltage is applied between the gate electrode and the second electrode, and a first carrier accumulation layer is generated at a contact surface between the third semiconductor layer and the gate insulating film and a contact surface between the fourth semiconductor layer and the gate insulating film; a second state in which a voltage equal to or greater than a threshold voltage is applied between the gate electrode and the second electrode, and a second carrier inversion layer is generated at a contact surface of the third semiconductor layer with the gate insulating film.

12. In claim 11, a first conductivity type being n-type, a second conductivity type being p-type, the first electrode being a cathode electrode, the second electrode being an anode electrode, the first carriers being holes, and the second carriers being electrons.

13. In claim 11, a positive voltage is applied to the second electrode with respect to the first electrode, and during a first period in which a current flows from the second electrode to the first electrode, the first state is switched to the second state; After the first period, a positive voltage is applied to the first electrode with respect to the second electrode, and the second state is maintained during a second period in which a current flows from the first electrode to the second electrode; After the second period, a positive voltage is applied to the first electrode with respect to the second electrode, and in a third period in which no current flows from the first electrode to the second electrode, the semiconductor device is switched from the second state to the first state.

14. In claim 1, a seventh semiconductor layer of a second conductivity type provided on the back surface side of the second semiconductor layer in a region not overlapping with the first semiconductor layer in a plan view, and in contact with the first electrode; a region overlapping with the seventh semiconductor layer includes the second semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, the sixth semiconductor layer, the gate insulating film, the gate electrode, the first electrode, the second electrode, and the protruding portion, and does not include the fourth semiconductor layer; the gate insulating film contacts the second semiconductor layer, the third semiconductor layer, and the sixth semiconductor layer; and the gate electrode is disposed opposite the second semiconductor layer, the third semiconductor layer, and the sixth semiconductor layer via the gate insulating film; a gate electrode in a region overlapping with the seventh semiconductor layer and a gate electrode in a region overlapping with the first semiconductor layer, the gate electrode being capable of being driven independently of each other;

15. A power conversion device using the semiconductor device according to any one of claims 1 to 14.

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