Display device and display system

Abstract

The display device includes an array substrate, an opposing substrate, and a liquid crystal layer. The array substrate includes a signal line, a scan line, a common electrode overlapping a plurality of pixel electrodes, and a grid-shaped light-shielding conductive layer. The conductive layer has a frame portion that overlaps the scan line and the signal line, and a dividing line portion that divides the pixel into two regions, namely a first region and a second region. The common electrode has a first slit and a second slit for each pixel. The distance between the first side and the second side of the first slit gradually decreases as the second slit approaches, and the distance between the third side and the fourth side of the second slit gradually decreases as the first slit approaches. The dividing line portion is disposed between the first side and the third side and between the second side and the fourth side.

Description

Technical Field

[0001] The present disclosure relates to a display device and a display system. Background Art

[0002] Display devices that improve response speed and transmittance are disclosed in Patent Document 1 and Patent Document 2.

[0003] Prior Art Documents

[0004] Patent Document 1: JP-A-2014-232136

[0005] Patent Document 2: JP-A-2019-113584 Summary of the Invention

[0006] In Patent Document 1, when the pixel is highly refined, it becomes difficult to form comb teeth for the electrodes. In Patent Document 2, there are formed a plurality of liquid crystal domains and a plurality of dark regions where the liquid crystal molecules basically do not change in orientation. In Patent Document 2, the slit is located inside the opening surrounded by the signal line and the scanning line. However, in Patent Document 2, when the pixel is highly refined, the slit may overlap with the signal line or the scanning line, and the transmittance may decrease.

[0007] An object of the present disclosure is to provide a display device and a display system that improve transmittance even when the pixel is highly refined.

[0008] A display device on one side includes: an array substrate; a counter substrate opposed to the array substrate; and a liquid crystal layer including liquid crystal molecules between the array substrate and the counter substrate. The array substrate has: a plurality of signal lines arranged at intervals in a first direction; a plurality of scan lines arranged at intervals in a second direction; a plurality of pixel electrodes arranged for each opening of a pixel surrounded by two adjacent signal lines and two adjacent scan lines, a plurality of semiconductors arranged for each pixel; a common electrode overlapping with the plurality of pixel electrodes with an insulating film therebetween; and a conductive layer in a lattice shape and having a light-shielding property, which is directly laminated with the common electrode. The conductive layer has a frame portion overlapping with the scan line and the signal line, and a dividing line portion dividing the pixel into two divided areas, a first divided area and a second divided area. The common electrode has a first slit arranged in the first divided area and a second slit arranged in the second divided area for each pixel. The first slit has at least a first side and a second side opposed to the first side in a top view. The second slit has at least a third side and a fourth side opposed to the third side in a top view. The interval between the first side and the second side gradually decreases as approaching the second slit. The interval between the third side and the fourth side gradually decreases as approaching the first slit. The dividing line portion is arranged between the first side and the third side, and between the second side and the fourth side.

[0009] A display system on one side includes the above display device and a control device that outputs an image to the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a configuration diagram showing an example of the display system of Embodiment 1.

[0011] Figure 2 It is a schematic diagram showing an example of the relative relationship between the display device and the user's eyes.

[0012] Figure 3 It is a block diagram showing an example of the configuration of the display system of Embodiment 1.

[0013] Figure 4 It is a circuit diagram showing the pixel arrangement of the display area of Embodiment 1.

[0014] Figure 5 It is a schematic diagram showing an example of the display panel of Embodiment 1.

[0015] Figure 6 It is a schematic diagram schematically showing an enlarged part of the display area in Embodiment 1.

[0016] Figure 7 It schematically shows Figure 6Cross-sectional view of the VII-VII' cross-section.

[0017] Figure 8 It is a cross-sectional view schematically showing the boundary between the display area and the peripheral area of Embodiment 1.

[0018] Figure 9 It schematically shows Figure 8 Cross-sectional view of the IX-IX' cross-section.

[0019] Figure 10 It is a plan view schematically showing the relationship between the slit and the liquid crystal domains.

[0020] Figure 11 It is a plan view schematically showing the relationship between the slit and the liquid crystal domains of the comparative example.

[0021] Figure 12 It is a schematic enlarged view showing a part of the display area in Embodiment 2.

[0022] Figure 13 It schematically shows Figure 12 Cross-sectional view of the XIII-XIII' cross-section.

[0023] Among them, the reference numerals are explained as follows:

[0024] 1 Display system

[0025] 10 First insulating substrate

[0026] 20 Second insulating substrate

[0027] 100 Display device

[0028] 110 Display panel

[0029] 112 Display control circuit

[0030] 200 Control device

[0031] 410 Lens

[0032] AA Display area

[0033] BM Light-shielding layer

[0034] CE Common electrode

[0035] CES Slit

[0036] CES1 First slit

[0037] CES2 Second slit

[0038] CES3 Third slit

[0039] CESB11, CESB12, CESB21, CESB22 rectangular regions

[0040] CEST1 First trapezoidal region

[0041] CEST2 Second trapezoidal region

[0042] Peripheral region of GA

[0043] GL Scanning line

[0044] LC Liquid crystal layer

[0045] Lcm Liquid crystal molecules

[0046] LS Light-shielding layer

[0047] PE Pixel electrode

[0048] Pix, PixB, PixG, PixR Pixels

[0049] Pixd1 First partition

[0050] Pixd2 Second partition

[0051] Qt11 First side

[0052] Qt12 Second side

[0053] Qt21 Third side

[0054] Qt22 Fourth side

[0055] Qa1 Fifth side

[0056] Qa2 Sixth side

[0057] Qb3 Seventh side

[0058] Qb4 Eighth side

[0059] Qb1 Ninth side

[0060] Qb2 Tenth side

[0061] Qs11 Eleventh side

[0062] Qs12 Twelfth side

[0063] Qs21 Thirteenth side

[0064] Qs22 Fourteenth side

[0065] Qd1 Fifteenth side

[0066] Qd2 Sixteenth side

[0067] Qc11 Seventeenth side

[0068] 18th side of Qc12

[0069] 19th side of Qc21

[0070] 20th side of Qc22

[0071] Corners of Qbp11, Qbp12, Qbp21, Qbp22

[0072] SL signal line

[0073] SUB1 array substrate

[0074] SUB2 opposed substrate

[0075] TL conductive layer

[0076] TLA dividing line part

[0077] TLB first frame part

[0078] TLC second frame part Detailed implementation mode

[0079] With reference to the accompanying drawings, the mode (implementation mode) for implementing the invention will be described in detail. The present disclosure is not limited by the content described in the following implementation modes. In addition, the constituent elements described below include constituent elements that can be easily conceived by those skilled in the art and substantially identical constituent elements. Moreover, the constituent elements described below can be appropriately combined. It should be noted that the disclosure is only an example, and appropriate changes that can be easily conceived by those skilled in the art and maintain the gist of the invention are of course included in the scope of the present disclosure. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part of the accompanying drawings may be schematically shown compared with the actual form, but this is only an example and does not limit the interpretation of the present disclosure. In addition, in this specification and each figure, sometimes the same reference numerals are given to the same elements as those described in the accompanying drawings that have already appeared, and the detailed description is appropriately omitted.

[0080] (Embodiment 1)

[0081] Figure 1 It is a configuration diagram showing an example of the display system of Embodiment 1. Figure 2 It is a schematic diagram showing an example of the relative relationship between the display device and the user's eyes.

[0082] In the present embodiment, the display system 1 is a display system that changes the display according to the movement of the user. For example, the display system 1 is a VR (Virtual Reality) system that stereoscopically displays a three-dimensional object in a virtual space, etc., and changes the stereoscopic display according to the orientation (position) of the user's head, giving the user a sense of virtual reality.

[0083] The display system 1 has, for example, a display device 100 and a control device 200. The display device 100 and the control device 200 are configured to be able to input and output information (signals) via a cable 300. The cable 300 includes, for example, cables such as USB (Universal Serial Bus) and HDMI (registered trademark) (High-Definition Multimedia Interface). The display device 100 and the control device 200 may also be configured to be able to input and output information via wireless communication.

[0084] In addition, the display device 100 is supplied with power from the control device 200 via the cable 300. For example, the display device 100 has a power receiving unit that is supplied with power from the power supply unit of the control device 200 via the cable 300, and each component such as the display panel 110 and the sensor 120 of the display device 100 may also be driven using the power supplied from the control device 200. By setting it in this way, a battery or the like can be removed from the display device 100, and a cheaper and lighter display device 100 can be provided. It should be noted that a battery may also be installed in the wearable component 400 or the display device 100 and supplied to the display device.

[0085] The display device 100 has a display panel. The display panel is, for example, a liquid crystal display.

[0086] The display device 100 is fixed to the wearable component 400. The wearable component 400 includes, for example, a head-mounted device, goggles, a helmet covering the user's eyes, and a face mask. The wearable component 400 is worn on the user's head. The wearable component 400 is arranged in front of the user in a manner that covers the user's eyes when worn. The wearable component 400 positions the display device 100 fixed inside in front of the user's eyes, and thus functions as an immersive wearable component. The wearable component 400 may also have an output unit that outputs a sound signal or the like output from the control device 200. In addition, the wearable component 400 may be configured to incorporate the function of the control device 200.

[0087] In Figure 1 In an example shown, the display device 100 is shown inserted into the wearable component 400, but it may also be fixed to the wearable component 400. In other words, the display system may also be composed of a wearable display device including the wearable component 400 and the display device 100 and the control device 200.

[0088] As Figure 2As shown, the wearable component 400 has lenses 410 corresponding to the user's two eyes, for example. The lenses 410 are magnifying lenses for imaging an image on the user's eyes. When the wearable component 400 is worn on the user's head, the lenses 410 are positioned in front of the user's eyes E. The user visually confirms the display area of the display device 100 magnified by the lenses 410. Therefore, in order to clearly display an image (screen), the display device 100 needs to improve the resolution. It should be noted that in the present disclosure, one lens is illustrated as an example, but for example, it may also have a plurality of lenses, and the display device 100 may be arranged at a position different from in front of the eyes.

[0089] The control device 200 causes the display device 100 to display an image, for example. The control device 200 can use an electronic device such as a personal computer or a game console, for example. The virtual image includes, for example, an image such as a computer graphics image or a 360-degree real scene image. The control device 200 outputs a three-dimensional image utilizing the parallax of the user's two eyes to the display device 100. The control device 200 outputs an image for the right eye and an image for the left eye that follow the orientation of the user's head to the display device 100.

[0090] Figure 3 It is a block diagram showing an example of the configuration of the display system according to Embodiment 1. As Figure 3 shown, the display device 100 has two display panels 110, a sensor 120, a setting circuit 130, a storage unit 140, an image separation circuit 150, and an interface 160. A control program 141, setting data 142, etc. are stored in the storage unit 140.

[0091] The display device 100 is composed of two display panels 110. One is used as the display panel 110 for the left eye, and the other is used as the display panel 110 for the right eye.

[0092] The two display panels 110 each have a display area AA and a display control circuit 112. It should be noted that the display panel 110 has a light source device (not shown) that irradiates the display area AA from behind.

[0093] The pixels Pix in the display area AA are arranged in a two-dimensional matrix (row-column pattern) of P0×Q0 (P0 in the row direction and Q0 in the column direction). In the present embodiment, it is assumed that P0 = 2880 and Q0 = 1700. In Figure 3 it, the arrangement of a plurality of pixels Pix is schematically shown, and the detailed arrangement of the pixels Pix will be described later. Since the pixels of the display device are visually confirmed through the lens, the pixel pitch is, for example, 3 μm or more and 10 μm or less, and the display area AA has a high-definition arrangement of pixels Pix. The display area AA is surrounded by a peripheral area GA.

[0094] The display panel 110 has scan lines extending in the X direction and signal lines extending in the Y direction that intersects the X direction. For example, the display panel 110 has 2,880 signal lines SL and 1,700 scan lines GL. In the display panel 110, pixels Pix are arranged in regions surrounded by the signal lines SL and the scan lines GL. Each pixel Pix has a switching element SW (TFT: thin film transistor) connected to the signal line SL and the scan line GL, and a pixel electrode connected to the switching element SW. A plurality of pixels Pix arranged along the extension direction of a scan line GL are connected to one scan line GL. Additionally, a plurality of pixels Pix arranged along the extension direction of a signal line SL are connected to one signal line SL.

[0095] Of the two display panels 110, the display area AA of one display panel 110 is for the right eye, and the display area AA of the other display panel 110 is for the left eye. In Embodiment 1, the case where the display panel 110 includes two display panels 110, one for the left eye and one for the right eye, is described. However, the display device 100 is not limited to a configuration using two display panels 110 in the above manner. For example, there is one display panel 110, and the display area of the one display panel 110 is divided into two such that an image for the right eye is displayed in the right half region and an image for the left eye is displayed in the left half region.

[0096] The display control circuit 112 includes a driver IC (Integrated Circuit) 115, a signal line connection circuit 113, and a scan line drive circuit 114. The signal line connection circuit 113 is electrically connected to the signal line SL. The driver IC 115 controls the on / off of a switching element (e.g., TFT) for controlling the operation (light transmittance) of the pixel Pix through the scan line drive circuit 114. The scan line drive circuit 114 is electrically connected to the scan line GL.

[0097] The sensor 120 detects information that can infer the orientation of the user's head. For example, the sensor 120 detects information indicating the dynamics of the display device 100 and the wearable member 400, and the display system 1 infers the orientation of the head of the user wearing the display device 100 based on the information indicating the dynamics of the display device 100 and the wearable member 400.

[0098] The sensor 120 detects information capable of inferring the direction of the line of sight, for example, using at least one of the angle, acceleration, angular velocity, orientation, and distance of the display device 100 and the wearable component 400. The sensor 120 can use, for example, a gyro sensor, an acceleration sensor, an orientation sensor, etc. The sensor 120 can also detect, for example, the angle and angular velocity of the display device 100 and the wearable component 400 through the gyro sensor. The sensor 120 can also detect, for example, the direction and magnitude of the acceleration acting on the wearable component 400 of the display device 100 through the acceleration sensor. The sensor 120 can also detect the orientation of the display device 100 through, for example, the orientation sensor. The sensor 120 can also detect the movement of the display device 100 and the wearable component 400 through, for example, a distance sensor, a GPS (Global Positioning System) receiver, etc. The sensor 120 only needs to be a sensor for detecting the orientation of the user's head, changes in the line of sight, movement, etc., and can be other sensors such as a light sensor, or multiple sensors can be combined for use. The sensor 120 is electrically connected to the image separation circuit 150 via the interface 160 described later.

[0099] The image separation circuit 150 receives the left-eye image data and the right-eye image data sent from the control device 200 via the cable 300, sends the left-eye image data to the display panel 110 for displaying the left-eye image, and sends the right-eye image data to the display panel 110 for displaying the right-eye image.

[0100] The interface 160 includes a connector to which the cable 300 ( Figure 1 ) is connected. The interface 160 receives the signal from the control device 200 via the connected cable 300. The image separation circuit 150 outputs the signal input from the sensor 120 to the control device 200 via the interface 160 and the interface 240. Here, the signal input from the sensor 120 includes information capable of inferring the direction of the above-mentioned line of sight. Or the signal input from the sensor 120 can also be directly output to the control unit 230 of the control device 200 via the interface 160. The interface 160 is, for example, a wireless communication device, and can also perform information transmission and reception with the control device 200 via wireless communication.

[0101] The control device 200 has an operation unit 210, a storage unit 220, a control unit 230, and an interface 240.

[0102] The operation unit 210 receives the user's operation. The operation unit 210 can use, for example, input devices such as a keyboard, buttons, and a touch screen. The operation unit 210 is electrically connected to the control unit 230. The operation unit 210 outputs the information corresponding to the operation to the control unit 230.

[0103] The storage unit 220 stores programs and data. The storage unit 220 temporarily stores the processing results of the control unit 230. The storage unit 220 includes a storage medium. The storage medium includes, for example, a ROM, a RAM, a memory card, an optical disc, or an optical disk, etc. The storage unit 220 may also store the data of the image displayed on the display device 100.

[0104] The storage unit 220 stores, for example, the control program 211, the VR application 212, etc. The control program 211 can provide functions related to various controls for operating the control device 200, for example. The VR application 212 can provide a function of displaying a virtual reality image on the display device 100. The storage unit 220 can store various information input from the display device 100, such as data representing the detection results of the sensor 120, etc., for example.

[0105] The control unit 230 includes, for example, an MCU (Micro Control Unit), a CPU (Central Processing Unit), etc. The control unit 230 can uniformly control the operations of the control device 200. Various functions of the control unit 230 are implemented based on the control of the control unit 230.

[0106] The control unit 230 includes, for example, a GPU (Graphics Processing Unit) that generates the image to be displayed. The GPU generates the image to be displayed on the display device 100. The control unit 230 outputs the image generated by the GPU to the display device 100 via the interface 240. In the present embodiment, the case where the control unit 230 of the control device 200 includes a GPU is described, but it is not limited thereto. For example, the GPU may also be provided in the display device 100 or the image separation circuit 150 of the display device 100. In this case, the display device 100 obtains data from the control device 200, an external electronic device, etc., and only needs to generate an image based on this data by the GPU.

[0107] The interface 240 includes a connector to which a cable 300 (refer to Figure 1 ) is connected. The interface 240 receives the signal from the display device 100 via the cable 300. The interface 240 outputs the signal input from the control unit 230 to the display device 100 via the cable 300. The interface 240 is, for example, a wireless communication device, and may also perform information transmission and reception with the display device 100 via wireless communication.

[0108] When executing the VR application 212, the control unit 230 displays an image corresponding to the dynamics of the user (display device 100) on the display device 100. If the control unit 230 detects a change in the user (display device 100) while an image is being displayed on the display device 100, it changes the image displayed on the display device 100 to an image in the direction of the change. When starting to create an image, the control unit 230 creates an image based on the reference viewpoint and reference line of sight in the virtual space. When detecting a change in the user (display device 100), it changes the viewpoint or line of sight when creating the displayed image from the reference viewpoint or reference line of sight direction according to the dynamics of the user (display device 100), and displays an image based on the changed viewpoint or line of sight on the display device 100.

[0109] For example, based on the detection result of the sensor 120, the control unit 230 detects that the user's head moves to the right direction. In this case, the control unit 230 changes the image to the case where the line of sight changes to the right direction from the currently displayed image. The user can visually confirm the image in the right direction of the image displayed on the display device 100.

[0110] For example, when the control unit 230 detects the movement of the display device 100 based on the detection result of the sensor 120, it changes the image according to the detected movement. When the control unit 230 detects that the display device 100 moves forward, it changes to the image in the case of moving forward from the currently displayed image. When the control unit 230 detects that the display device 100 moves in the backward direction, it changes to the image in the case of moving backward from the currently displayed image. The user can visually confirm the image of their own moving direction from the image being displayed on the display device 100.

[0111] Figure 4 It is a circuit diagram showing the pixel arrangement of the display area of Embodiment 1. Figure 5 It is a schematic diagram showing an example of the display panel of Embodiment 1. In the present disclosure, the scan lines GL and signal lines SL are not limited to intersecting at a right angle, but in Figure 4 for the sake of convenience of explanation, the scan lines GL and signal lines SL are at right angles.

[0112] In the display area AA, there are formed Figure 4 the switching elements SW, signal lines SL, scan lines GL, etc. of the respective pixels PixR, PixG, PixB shown. The signal line SL is a wiring for supplying pixel signals to each pixel electrode PE (refer to Figure 6 ). The scan line GL is a wiring for supplying a gate signal for driving each switching element SW.

[0113] As Figure 4As shown, pixels PixR, PixG, and PixB respectively have a switching element SW and a capacitance of a liquid crystal layer LC. The switching element SW is composed of a thin film transistor, and in this example, it is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT. An insulating film is provided between a pixel electrode PE and a common electrode CE described later, and a holding capacitance Cs is formed between the pixel electrode PE and the common electrode CE. Figure 4 The holding capacitance Cs shown.

[0114] Figure 5 The color filters CFR1, CFG1, and CFB1 shown are arranged such that color regions colored, for example, red (first color: R), green (second color: G), and blue (third color: B) are periodically arranged. In the above Figure 4 Each of the pixels PixR, PixG, and PixB shown corresponds to and is associated with color regions of the three colors R, G, and B. Moreover, the pixels PixR, PixG, and PixB corresponding to the color regions of the three colors form a group of pixels. It should be noted that the color filter may also include color regions of four or more colors. The pixels PixR, PixG, and PixB may also be referred to as sub-pixels respectively.

[0115] Figure 5 The color filters CFR1, CFG1, and CFB1 shown are arranged in an opening surrounded by two signal lines SL and two scan lines GL.

[0116] As Figure 4 and Figure 5 shown, directions Vx (first direction), direction Vy (second direction), and direction Vz that are orthogonal to each other are defined. In the direction Vx (first direction), the pixel PixR is sandwiched between the pixel PixB and the pixel PixG, and in the direction Vy (second direction), the pixel PixR is sandwiched between the pixel PixB and the pixel PixG.

[0117] In addition, in the direction Vx, the pixel PixG is sandwiched between the pixel PixR and the pixel PixB, and in the direction Vy, the pixel PixG is sandwiched between the pixel PixR and the pixel PixB.

[0118] In addition, in the direction Vx, the pixel PixB is sandwiched between the pixel PixG and the pixel PixR, and in the direction Vy, the pixel PixB is sandwiched between the pixel PixG and the pixel PixR.

[0119] In the direction Vx, pixels PixR, PixG, and PixB are arranged repeatedly in this order. In the direction Vy, pixels PixR, PixB, and PixG are arranged repeatedly in this order. It should be noted that the arrangement in the direction Vy may also be repeated in the order of pixels PixR, PixG, and PixB.

[0120] Color filters CFR1 are connected to each other by color filters CFR2 of the same red color. If color filters CFR1 and CFR2 are connected, color filters of the same color are arranged in an inclined direction that intersects the direction Vx and the direction Vy, respectively. Similarly, color filters CFG1 are connected to each other by color filters CFG2 of the same green color, and color filters CFB1 are connected to each other by color filters CFB2 of the same blue color.

[0121] Color filters CFR1 and CFR2 are integrally formed. Therefore, for the sake of convenience of explanation, hereinafter, without distinguishing between color filters CFR1 and CFR2, they are collectively referred to as color filter CFR. Similarly, without distinguishing between color filters CFG1 and CFG2, they are hereinafter referred to as color filter CFG. Without distinguishing between color filters CFB1 and CFB2, they are hereinafter referred to as color filter CFB. Moreover, without distinguishing between color filter CFR, color filter CFG, and color filter CFB, color filter CFR, color filter CFG, and color filter CFB are referred to as color filter CF.

[0122] Figure 5 The illustrated spacer SP is a component that limits the distance between the array substrate SUB1 and the counter substrate SUB2. The material of the spacer SP is, for example, acrylic resin. The spacer SP is cylindrical, and Figure 5 shows the maximum diameter of the spacer SP. It should be noted that the shape of the spacer SP is not limited to a cylinder and may also be formed as a spacer in the shape of a prism, for example. In Figure 5 one spacer is illustrated, but actually, a plurality of spacers are arranged.

[0123] Figure 6 It is a schematic diagram that schematically shows a part of the display area in Embodiment 1 in an enlarged manner. Figure 6 The illustrated pixel Pix is one of pixels PixR, PixG, and PixB. Hereinafter, without distinguishing between pixels PixR, PixG, and PixB, pixels PixR, PixG, and PixB are referred to as pixel Pix.

[0124] A plurality of signal lines SL are arranged at intervals in the direction Vx. A plurality of scan lines GL are arranged at intervals in the direction Vy. The conductive layer TL overlaps the plurality of signal lines SL and the plurality of scan lines GL in a plan view and has a lattice shape. The common electrode CE is octagonal and island-shaped. The common electrode CE is formed of a light-transmissive conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGO (Indium Gallium Oxide). The conductive layer TL overlaps the common electrode CE. The conductive layer TL electrically connects the plurality of island-shaped common electrodes CE. Since the resistance of the conductive layer TL is smaller than that of the common electrode CE, deviation of the voltage distribution of each pixel Pix due to voltage drop is suppressed.

[0125] As Figure 6 shown, the conductive layer TL of Embodiment 1 has a first frame portion TLB that overlaps the plurality of signal lines SL in a plan view, a second frame portion TLC that overlaps the plurality of scan lines GL in a plan view, and a dividing line portion TLA located between two adjacent scan lines GL (second frame portion TLC). The dividing line portion TLA divides the pixel Pix into a first division region Pixd1 and a second division region Pixd2. Thereby, the light-transmissive regions of the openings of the pixel Pix become two regions surrounded by the scan line GL and the dividing line portion TLA (conductive layer TL). As Figure 6 shown, the second division region Pixd2 is smaller than the first division region Pixd1.

[0126] At the portion where the first frame portion TLB is connected to the second frame portion TLC, the width TLWX1 in the direction Vx becomes smaller to the width TLWX2 in the direction Vx. The width TLWX2 in the direction Vx is larger than the width of the signal line SL in the direction Vx. The width of the second frame portion TLC in the direction Vy is larger than the width of the scan line GL in the direction Vy.

[0127] In the pixel Pix, a pixel electrode PE and a switching element SW are disposed in each opening surrounded by two signal lines SL and two scan lines GL. The common electrode CE is an electrode shared by a plurality of pixels Pix. The common electrode CE has a first slit CES1, a second slit CES2, and a third slit CES3 for each opening portion surrounded by two signal lines SL and two scan lines GL.

[0128] The first slit CES1, the second slit CES2, and the third slit CES3 are portions of the common electrode CE that do not have a light-transmissive conductive material. The first slit CES1, the second slit CES2, and the third slit CES3 overlap with the pixel electrode PE. In the following description, the first slit CES1, the second slit CES2, and the third slit CES3 may also be collectively referred to as the slit CES. The first slit CES1 is disposed in the first division Pixd1, and the second slit CES2 is disposed in the second division Pixd2.

[0129] The substantial slit in the first division Pixd1 is a region without the common electrode CE and the conductive layer TL. A part of the first frame portion TLB exists inside a part of the first slit CES1. Thereby, a concave portion TLn11 and a concave portion TLn12 are formed in the narrow portion of the first frame portion TLB. Moreover, the substantial slit in the first division Pixd1 has a shape combining a trapezoidal region and a rectangular region.

[0130] The substantial slit in the second division Pixd2 is a region without the common electrode CE and the conductive layer TL. A part of the first frame portion TLB exists inside a part of the second slit CES2. Thereby, a concave portion TLn21 and a concave portion TLn22 are formed in the narrow portion of the first frame portion TLB. Moreover, the substantial slit in the second division Pixd2 has a shape combining a trapezoidal region and a rectangular region.

[0131] As a region of the common electrode CE without a conductive material, the third slit CES3 connects the first slit CES1 and the second slit CES2. The third slit CES3 is covered by the dividing line portion TLA, and the first slit CES1 and the second slit CES2 are separated by the dividing line portion TLA. The third slit CES3 is covered by the dividing line portion TLA and is not substantially a slit. The third slit CES3 is quadrilateral.

[0132] As shown in Figure 6 the semiconductor SC is formed in a U shape. The signal line SL is electrically connected to the semiconductor SC via the contact hole CH1. The semiconductor SC is electrically connected to the relay electrode RE via the contact hole CH2. The relay electrode RE is electrically connected to the pixel electrode PE via the contact hole CH3.

[0133] The contact hole CH3 is disposed in the first division Pixd1, and the area of the first division Pixd1 is larger than the area of the second division Pixd2.

[0134] Figure 7 is a cross-sectional view schematically showing the Figure 6 VII-VII' cross-section. Embodiment 1 is as shown in Figure 5As shown, a color filter CF is provided on an array substrate SUB1. The display device 100 has a so-called COA (Color Filter On Array) structure in which the color filter CF, pixel electrodes PE, and a common electrode CE are arranged on the array substrate SUB1.

[0135] As Figure 7 shown, the array substrate SUB1 has a light-transmissive first insulating substrate 10 such as a glass substrate or a resin substrate as a base. The array substrate SUB1 has a first layer GL1 of a scanning line GL, a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a color filter CF, a fifth insulating film 15, pixel electrodes PE, a sixth insulating film 16, pixel electrodes PE, a seventh insulating film 17, a conductive layer TL, a common electrode CE, a first alignment film AL1, etc. on the side of the first insulating substrate 10 facing the counter substrate SUB2. In the following description, the direction from the array substrate SUB1 toward the counter substrate SUB2 is referred to as upward or simply as up.

[0136] The first layer GL1 of the scanning line GL is located above the first insulating substrate 10. The first insulating film 11 is located above the first layer GL1 of the scanning line GL and the inner side surface 10A of the first insulating substrate 10. The second insulating film 12 is located above the first insulating film 11. The semiconductor SC is located above the second insulating film 12. The third insulating film 13 is located above the semiconductor SC and the second insulating film 12. The second layer GL2 of the scanning line GL is located above the third insulating film 13. It should be noted that in the first layer GL1 and the second layer GL2 of the scanning line GL, the portions overlapping the semiconductor SC are used as gate electrodes.

[0137] The fourth insulating film 14 is located above the second layer GL2 of the scanning line GL and the third insulating film 13. At positions overlapping the semiconductor SC, contact holes CH1 are formed by opening holes in the third insulating film 13 and the fourth insulating film 14, and a signal line SL formed above the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact holes CH1.

[0138] At positions overlapping the semiconductor SC, contact holes CH2 are formed by opening holes in the third insulating film 13 and the fourth insulating film 14, and a relay electrode RE formed above the fourth insulating film 14 is electrically connected to the semiconductor SC via the contact holes CH2.

[0139] The fifth insulating film 15 is located above the signal line SL, the relay electrode RE, and the fourth insulating film 14. The color filter CF is located above the fifth insulating film 15. The sixth insulating film 16 is located above the color filter CF and the fifth insulating film 15.

[0140] At a position overlapping with the relay electrode RE, contact holes CH3 are formed by opening holes in the fifth insulating film 15 and the sixth insulating film 16, and the pixel electrode PE formed above the sixth insulating film 16 is electrically connected to the relay electrode RE via the contact holes CH3. The pixel electrode PE is formed of a light-transmissive conductive material such as ITO, IZO, or IGO, for example.

[0141] The common electrode CE is located above the seventh insulating film 17. The common electrode CE is formed of a light-transmissive conductive material such as ITO, IZO, or IGO, for example.

[0142] The conductive layer TL is located above the seventh insulating film 17. The conductive layer TL is a conductor and is electrically connected to the common electrode CE. Therefore, the resistance value per unit area of the common electrode CE and the conductive layer TL becomes smaller. The conductive layer TL may be a single layer of a metal such as aluminum (Al), for example, but titanium (Ti) and molybdenum (Mo) may also be disposed on the upper and lower layers of aluminum, and formed of multiple metal layers such as titanium / aluminum / titanium or molybdenum / aluminum / molybdenum.

[0143] The seventh insulating film 17 exposed in the common electrode CE, the first slit CES1, and the second slit CES2 is covered by the first alignment film AL1.

[0144] The counter substrate SUB2 has a light-transmissive second insulating substrate 20 such as a glass substrate or a resin substrate as a base. The counter substrate SUB2 has an outer coating 21 and a second alignment film AL2 on the side facing the array substrate SUB1 of the second insulating substrate 20 (i.e., the inner surface 20A).

[0145] The above-mentioned array substrate SUB1 and counter substrate SUB2 are arranged such that the first alignment film AL1 and the second alignment film AL2 face each other. The liquid crystal layer LC is sealed between the first alignment film AL1 and the second alignment film AL2. Using the first alignment film AL1 and the second alignment film AL2, the long axis of the liquid crystal molecules is oriented to be orthogonal or parallel to the Figure 6 shown initial alignment direction AD. The liquid crystal layer LC is composed of a negative liquid crystal material with a negative dielectric anisotropy or a positive liquid crystal material with a positive dielectric anisotropy. The liquid crystal layer LC has a stable orientation in a state where a voltage is applied to the liquid crystal layer LC and is easy to maintain the high-speed response of the liquid crystal molecules. As long as the liquid crystal layer LC is composed of a positive liquid crystal material, the long axis of the liquid crystal molecules is along the direction parallel to the Figure 6 shown initial alignment direction AD. As long as the liquid crystal layer LC is composed of a negative liquid crystal material, the long axis of the liquid crystal molecules is along the direction orthogonal to the Figure 6 shown initial alignment direction AD.

[0146] The array substrate SUB1 faces the backlight unit, and the counter substrate SUB2 is located on the display surface side. As the backlight unit, various forms can be applied, and a detailed description of its structure is omitted.

[0147] The first optical element OD1 including the first polarizer PL1 is disposed on the outer side surface 10B of the first insulating substrate 10 or on the surface facing the backlight unit. The second optical element OD2 including the second polarizer PL2 is disposed on the outer side surface 20B of the second insulating substrate 20 or on the surface on the observation position side. The first polarization axis of the first polarizer PL1 and the second polarization axis of the second polarizer PL2 are, for example, in a crossed Nicol's positional relationship in the Vx-Vy plane. It should be noted that the first optical element OD1 and the second optical element OD2 may include other optical functional elements such as a retardation plate.

[0148] Figure 8 It is a cross-sectional view schematically showing the boundary between the display area and the peripheral area of Embodiment 1. Figure 9 It is schematically shown Figure 8 a cross-sectional view of the IX-IX' section. As Figure 8 and Figure 9 shown, in the peripheral area GA, the wiring COM for supplying the common potential is disposed on the fourth insulating film 14. The fifth insulating film 15 covers and protects the wiring COM. A contact hole CHG is provided in a part of the fifth insulating film 15, and the wiring COM is electrically connected to the conductive layer TL and the common electrode CE led out from the display area AA via the contact hole CHG.

[0149] As Figure 8 and Figure 9 shown, in the peripheral area GA, a light-shielding layer BM is provided on the counter substrate SUB2, and the light-shielding layer BM can shield the peripheral area GA of the array substrate SUB1. It should be noted that, in the examples shown in Figure 7 and Figure 9 the light-shielding layer BM is not provided on the counter substrate SUB2 in the display area AA, but the light-shielding layer BM may also be provided. The light-shielding layer BM is formed of a black resin material.

[0150] Different from Embodiment 1, when adopting the structure of a comparative example in which a color filter is provided on the counter substrate SUB2 and a light-shielding layer is provided at the boundary of each color of the color filter, the smaller the pixel Pix is, the greater the possibility that the opening of the pixel Pix of the array substrate coincides with the position of the light-shielding layer in the display area AA of the counter substrate SUB2. In contrast, in Figure 8 and Figure 9In the COA structure of Embodiment 1 shown, there is no color filter CF and no light-shielding layer at the boundaries of the respective colors of the color filter CF in the display area AA of the counter substrate SUB2. Therefore, the required level of the alignment accuracy between the array substrate SUB1 and the counter substrate SUB2 can be reduced.

[0151] Figure 10 It is a plan view schematically showing the relationship between the slit and the liquid crystal domains. Figure 11 It is a plan view schematically showing the relationship between the slit and the liquid crystal domains of the comparative example. With respect to Figure 10 the conductive layer TL of Embodiment 1 shown has a dividing line portion TLA. In Figure 11 the conductive layer TL of the comparative example shown, there is no dividing line portion TLA. Thus, in Figure 11 the pixels of the comparative example shown generate Figure 10 a dark region NDMC that the pixels of Embodiment 1 shown do not have. As a result, Figure 10 Embodiment 1 shown and Figure 11 the comparative example shown, the liquid crystal domains DM are more stable. Also, compared with the dark region NDMC, the dividing line portion TLA blocks light more, so Figure 10 Embodiment 1 shown and Figure 11 the comparative example shown, the contrast is improved.

[0152] The first slit CES1 is a polygonal shape having a first trapezoidal region CEST1, a rectangular region CESB11, and a rectangular region CESB12. Similarly, the second slit CES2 is a polygonal shape having a second trapezoidal region CEST2, a rectangular region CESB21, and a rectangular region CESB22. Above all, the first slit CES1 and the second slit CES2 include trapezoidal shapes in portions corresponding to the openings of the pixels Pix ( Figure 6 refer to).

[0153] As Figure 10 shown, the dividing line portion TLA is disposed between the first side Qt11 and the third side Qt21, and between the second side Qt12 and the fourth side Qt22. Thus, the fifth side Qa1 and the sixth side Qa2 extend along the direction in which the dividing line portion TLA extends.

[0154] As Figure 10As shown, the first trapezoidal region CEST1 has a first side Qt11, a second side Qt12, a fifth side Qa1, and a seventh side Qb3. In Embodiment 1, the fifth side Qa1 is along the dividing line portion TLA. The fifth side Qa1 is the upper side of the trapezoid, connecting the first side Qt11 and the second side Qt12. The seventh side Qb3 is the bottom side of the trapezoid, connecting the first side Qt11 and the second side Qt12. The first side Qt11 and the second side Qt12 are opposite and non-parallel. The distance between the first side Qt11 and the second side Qt12 becomes smaller as it approaches the fifth side Qa1. Thus, the interval between the first side Qt11 and the second side Qt12 gradually becomes smaller as it approaches the second slit CES2.

[0155] The second trapezoidal region CEST2 has a third side Qt21, a fourth side Qt22, a sixth side Qa2, and an eighth side Qb4. In Embodiment 1, the sixth side Qa2 is along the dividing line portion TLA. The sixth side Qa2 is the upper side of the trapezoid, connecting the third side Qt21 and the fourth side Qt22. The eighth side Qb4 is the bottom side of the trapezoid, connecting the third side Qt21 and the fourth side Qt22. The third side Qt21 and the fourth side Qt22 are opposite and non-parallel. The distance between the third side Qt21 and the fourth side Qt22 becomes smaller as it approaches the sixth side Qa2. Thus, the interval between the third side Qt21 and the fourth side Qt22 gradually becomes smaller as it approaches the first slit CES1.

[0156] As Figure 10 shown, the second trapezoidal region CEST2 is smaller than the first trapezoidal region CEST1. Therefore, the angle α formed by Vy (the second direction) and the second side Qt12 is smaller than the angle β formed by the direction Vy (the second direction) and the fourth side Qt22. Similarly, the angle α formed by Vy (the second direction) and the first side Qt11 is smaller than the angle β formed by the direction Vy (the second direction) and the third side Qt21. Moreover, in a top view, a part of each of the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22 intersects the dividing line portion TLA and the first frame portion TLB, and the portion surrounded by one of the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22, the dividing line portion TLA, and the first frame portion TLB is a triangle. Thus, the liquid crystal domains DM are stabilized along the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22, and the transmittance can be improved.

[0157] The rectangular region CESB12 has a seventh side Qb3, a ninth side Qb1, an eleventh side Qs11, and a twelfth side Qs12. The eleventh side Qs11 and the twelfth side Qs12 are the edges of the first frame portion TLB that are adjacent and are part of the first frame portion TLB that is smaller than the shortest distance in the direction Vx between the first side Qt11 and the second side Qt12. The seventh side Qb3 is parallel to the ninth side Qb1. The eleventh side Qs11 is parallel to the twelfth side Qs12. The eleventh side Qs11 and the twelfth side Qs12 are straight lines along the first frame portion TLB. The ninth side Qb1 is a straight line that is adjacent to the recess TLn11 and the recess TLn12 and connects the corner portion Qbp11 and the corner portion Qbp12 of the first frame portion TLB.

[0158] The rectangular region CESB22 has an eighth side Qb4, a tenth side Qb2, a thirteenth side Qs21, and a fourteenth side Qs22. The eighth side Qb4 is parallel to the tenth side Qb2. The thirteenth side Qs21 and the fourteenth side Qs22 are the edges of the first frame portion TLB that are adjacent and are part of the first frame portion TLB that is smaller than the shortest distance in the direction Vx between the third side Qt21 and the fourth side Qt22. The thirteenth side Qs21 is parallel to the fourteenth side Qs22. The thirteenth side Qs21 and the fourteenth side Qs22 are straight lines along the first frame portion TLB. The tenth side Qb2 is a straight line that is adjacent to the recess TLn21 and the recess TLn22 and connects the corner portion Qbp21 and the corner portion Qbp22 of the first frame portion TLB.

[0159] The rectangular region CESB11 has a ninth side Qb1, a fifteenth side Qd1, a seventeenth side Qc11, and an eighteenth side Qc12. The ninth side Qb1 is parallel to the fifteenth side Qd1. The seventeenth side Qc11 is parallel to the eighteenth side Qc12. The seventeenth side Qc11 is a straight line along the bottom of the recess TLn11. The eighteenth side Qc12 is a straight line along the bottom of the recess TLn12.

[0160] The rectangular region CESB21 has a tenth side Qb2, a sixteenth side Qd2, a nineteenth side Qc21, and a twentieth side Qc22. The tenth side Qb2 is parallel to the sixteenth side Qd2. The nineteenth side Qc21 is parallel to the twentieth side Qc22. The nineteenth side Qc21 is a straight line along the bottom of the recess TLn21. The twentieth side Qc22 is a straight line along the bottom of the recess TLn22.

[0161] In Embodiment 1, the length of the first side Qt11 is equal to the length of the second side Qt12. Thus, the first trapezoidal region CEST1 becomes an isosceles trapezoid. The length of the third side Qt21 is equal to the length of the fourth side Qt22. Thus, the second trapezoidal region CEST2 becomes an isosceles trapezoid. The first trapezoidal region CEST1 may also be an asymmetric trapezoid in which the length of the first side Qt11 is different from the length of the second side Qt12. The second trapezoidal region CEST2 may be an asymmetric trapezoid in which the length of the third side Qt21 is different from the length of the fourth side Qt22.

[0162] As Figure 10 shown, for example, in a state where no voltage is applied to the liquid crystal layer LC, near the first side Qt11 and near the second side Qt12, the initial orientation of the liquid crystal molecules is such that the long axes of the liquid crystal molecules face the inside of the first slit CES1. The liquid crystal molecules in the vicinity of the first side Qt11 and the vicinity of the second side Qt12 are inclined in opposite directions with respect to the direction Vy. Similarly, in a state where no voltage is applied to the liquid crystal layer LC, near the third side Qt21 and near the fourth side Qt22, the initial orientation of the liquid crystal molecules is such that the long axes of the liquid crystal molecules face the inside of the second slit CES2. The liquid crystal molecules in the vicinity of the third side Qt21 and the vicinity of the fourth side Qt22 are inclined in opposite directions with respect to the direction Vy.

[0163] On the other hand, in a state where a voltage is applied to the liquid crystal layer LC, that is, when an electric field is formed between the pixel electrode PE and the common electrode CE, the liquid crystal molecules are affected by the electric field and their orientation states change. Liquid crystal domains DM are generated near the first side Qt11 and near the second side Qt12, and the transmittance corresponding to the voltage is controlled. Similarly, liquid crystal domains DM are generated near the third side Qt21 and near the fourth side Qt22, and the transmittance corresponding to the voltage is controlled. Dark regions NDM where the orientation change of the liquid crystal molecules hardly occurs even when a voltage is applied to the liquid crystal layer LC are generated in the liquid crystal domains DM.

[0164] When a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules in the vicinity of the first side Qt11 and the vicinity of the second side Qt12 rotate in opposite directions to each other. In addition, when a voltage is applied between the pixel electrode PE and the common electrode CE, the liquid crystal molecules in the vicinity of the third side Qt21 and the vicinity of the fourth side Qt22 rotate in opposite directions to each other.

[0165] For example, when a voltage is applied between the pixel electrode PE and the common electrode CE, the long axis direction of the liquid crystal molecules rotates clockwise in the vicinity of the first side Qt11 and counterclockwise in the vicinity of the second side Qt12. When a voltage is applied between the pixel electrode PE and the common electrode CE, the long axis direction of the liquid crystal molecules rotates clockwise in the vicinity of the fourth side Qt22 and counterclockwise in the vicinity of the third side Qt21. In this way, when a voltage is applied between the pixel electrode PE and the common electrode CE, the incident linearly polarized light changes corresponding to the orientation state of the liquid crystal molecules when passing through the liquid crystal layer LC in this polarization state. It should be noted that the example of the rotation direction of the long axis direction of the liquid crystal molecules can also be opposite to the direction described above.

[0166] Two liquid crystal domains DM are divided by a dark region NDM. The liquid crystal molecules in the liquid crystal domain DM have a high-speed response compared to those in a transverse electric field type liquid crystal display device such as FFS (Fringe Field Switching) and IPS (In Plane Switching).

[0167] Due to the existence of the rectangular region CESB11, the rectangular region CESB12, the rectangular region CESB21, and the rectangular region CESB22, the liquid crystal domain DM is stable. In the display device of Embodiment 1, even if the pixel Pix is highly refined and becomes smaller, the region of the liquid crystal domain DM can be ensured. Therefore, in the display device of Embodiment 1, the transmittance is increased.

[0168] In the manner described above, the interval between the first side Qt11 and the second side Qt12 gradually decreases as it approaches the second slit CES2. The interval between the third side Qt21 and the fourth side Qt22 gradually decreases as it approaches the first slit CES1. As a result, compared with the case where the first side Qt11 and the second side Qt12 are parallel, the stability of the liquid crystal orientation of the first slit CES1 is improved, and the liquid crystal molecules are dynamically stable. Compared with the case where the third side Qt21 and the fourth side Qt22 are parallel, the stability of the liquid crystal orientation of the second slit CES2 is improved, and the liquid crystal molecules are dynamically stable.

[0169] It should be noted that there is no light-shielding layer in the display area AA of the counter substrate SUB2. As a result, the influence of the misalignment between the array substrate SUB1 and the counter substrate SUB2 is reduced.

[0170] The display device 100 according to Embodiment 1 includes an array substrate SUB1, a counter substrate SUB2 opposed to the array substrate SUB1, and a liquid crystal layer LC including liquid crystal molecules between the array substrate SUB1 and the counter substrate SUB2. The array substrate SUB1 has: a plurality of signal lines SL arranged at intervals in the direction Vx; a plurality of scan lines GL arranged at intervals in the direction Vy; a plurality of pixel electrodes PE disposed at each opening of a pixel Pix surrounded by two adjacent signal lines SL and two adjacent scan lines GL; a plurality of semiconductors SC disposed in each pixel Pix; a common electrode CE overlapping with the plurality of pixel electrodes PE via a seventh insulating film 17; and a lattice-shaped and light-shielding conductive layer TL directly laminated with the common electrode CE.

[0171] The conductive layer TL has a dividing line portion TLA that divides the pixel Pix into two, a first frame portion TLB overlapping with the signal line SL, and a second frame portion TLC overlapping with the scan line GL. The common electrode CE has a first slit CES1 and a second slit CES2 for each pixel Pix. The first slit CES1 is disposed in the first partition Pixd1 and has at least a first side Qt11 and a second side Qt12 opposed to the first side Qt11 in a plan view. The second slit CES2 is disposed in the second partition Pixd2 and has at least a third side Qt21 and a fourth side Qt22 opposed to the third side Qt21 in a plan view.

[0172] Moreover, the interval between the first side Qt11 and the second side Qt12 gradually decreases as it approaches the second slit CES2. Similarly, the interval between the third side Qt21 and the fourth side Qt22 gradually decreases as it approaches the first slit CES1. The dividing line portion TLA is disposed between the first side Qt11 and the third side Qt21, and between the second side Qt12 and the fourth side Qt22.

[0173] Thus, by multi-domainization of the pixel Pix according to Embodiment 1, the influence of the dark region NDM between the first slit CES1 and the second slit CES2 is suppressed, and the dynamic stability of the liquid crystal molecules near one of the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22 is improved, thereby increasing the transmittance.

[0174] (Embodiment 2)

[0175] Figure 12 It is a schematic enlarged view showing a part of the display area in Embodiment 2. Figure 1 It schematically shows ​In the following description, the same reference numerals are sometimes used to designate the same components as those in Embodiment 1. In addition, repeated descriptions are omitted. In Embodiment 1, there is a third slit CES3 that connects the first slit CES1 and the second slit CES2 by a portion of the common electrode CE that does not have a light-transmitting conductive material. However, in Embodiment 2, there is also a common electrode in the area overlapping with the dividing line portion TLA, and this point is different from Embodiment 1 in that the first slit CES1 and the second slit CES2 are separated by the conductive material of the common electrode CE.

[0176] like ​ as well as ​ As shown, the slit CES includes a first slit CES1 and a second slit CES2 for each pixel Pix.

[0177] In contrast, in the first slit CES1 of the second embodiment, the intersections of the first side Qt11 and the fifth side Qa1, and the intersections of the second side Qt12 and the fifth side Qa1, tend to become rounded due to exposure wraparound. In the second slit CES2 of the first embodiment, the intersections of the third side Qt21 and the sixth side Qa2, and the intersections of the fourth side Qt22 and the sixth side Qa2, tend to become rounded due to exposure wraparound. In contrast, in the first embodiment, the first slit CES1, the second slit CES2, and the third slit CES3 are formed simultaneously. Thus, in the absence of the dividing line portion TLA, since there is no intersection between the first side Qt11 and the fifth side Qa1, the second side Qt12 and the fifth side Qa1, the third side Qt21 and the sixth side Qa2, and the fourth side Qt22 and the sixth side Qa2, the shapes of the first side Qt11, the second side Qt12, the third side Qt21, and the fourth side Qt22 are less likely to become rounded, and their linear shapes are stable. Furthermore, if the dividing line portion TLA is formed so as to cover the third slit CES3, the intersection line of the dividing line portion TLA and the first slit CES1 becomes the fifth side Qa1, and the intersection line of the dividing line portion TLA and the second slit CES2 becomes the sixth side Qa2.

[0178] The above describes a preferred embodiment, but the present disclosure is not limited to this embodiment. The content disclosed in the embodiment is only an example, and various changes can be made within the scope of the present disclosure. Appropriate changes made within the scope of the present disclosure also fall within the technical scope of the present disclosure.

Claims

1. A display device, characterized in that, comprising: an array substrate; a counter substrate opposed to the array substrate; and a liquid crystal layer including liquid crystal molecules between the array substrate and the counter substrate, the array substrate includes: a plurality of signal lines arranged at intervals in a first direction; a plurality of scanning lines arranged at intervals in a second direction; a plurality of pixel electrodes disposed for each opening of a pixel surrounded by two adjacent signal lines and two adjacent scanning lines; a plurality of semiconductors disposed for each pixel; a common electrode overlapping with the plurality of pixel electrodes with an insulating film therebetween; and a conductive layer in a lattice shape and having light-shielding properties, which is directly laminated on the common electrode, the conductive layer has a frame portion overlapping with the scanning line and the signal line, and a dividing line portion dividing the pixel into two divided areas, a first divided area and a second divided area, the common electrode has a first slit disposed in the first divided area and a second slit disposed in the second divided area for each pixel, the first slit has at least a first side and a second side opposed to the first side in a top view, the second slit has at least a third side and a fourth side opposed to the third side in a top view, the interval between the first side and the second side gradually becomes smaller as it approaches the second slit, the interval between the third side and the fourth side gradually becomes smaller as it approaches the first slit, the dividing line portion is disposed between the first side and the third side, and between the second side and the fourth side.

2. The display device according to claim 1, wherein the connection between the semiconductor and the pixel electrode is disposed in the first divided area, and the area of the first divided area is larger than the area of the second divided area.

3. The display device according to claim 1, wherein in a top view, the first side, the second side, the third side, and the fourth side intersect with the frame portion, in a top view, a portion surrounded by one of the first side, the second side, the third side, and the fourth side, the dividing line portion, and the frame portion is triangular.

4. The display device according to claim 1, wherein there is a portion smaller than between the first side and the second side, or between the third side and the fourth side in adjacent frame portions.

5. The display device according to claim 1, wherein the first slit includes a trapezoidal shape having a fifth side connecting the first side and the second side, and the fifth side extends along the dividing line portion, the second slit includes a trapezoidal shape having a sixth side connecting the third side and the fourth side, and the sixth side extends along the dividing line portion.

6. The display device according to claim 1, wherein it further includes a third slit connecting the first slit and the second slit, and the third slit is covered by the dividing line portion.

7. The display device according to claim 1, wherein When a voltage is applied between the pixel electrode and the common electrode, the long axis directions of the liquid crystal molecules in the vicinity of the first side and the third side rotate in opposite rotation directions, and the long axis directions of the liquid crystal molecules in the vicinity of the second side and the fourth side rotate in opposite rotation directions.

8. A display system, characterized in that, Comprising: A lens; The display device according to any one of claims 1 to 7; and A control device that outputs an image to the display device.

Images