Data operation method and device, electronic equipment and storage medium

Abstract

The application provides a data operation method and device, electronic equipment and storage medium. The method comprises: obtaining a data operation request comprising an operation starting position and an operation number of a logical block; determining a first target logical block to which historical data of a target cache area belongs in an RPMB; matching the first target logical block according to the operation starting position and the operation number; when a matching result indicates that the data to be operated this time does not completely match the first target logical block, determining a second target logical block corresponding to target data in the data to be operated this time and not matching the first target logical block in the RPMB based on the operation starting position, the operation number and the first target logical block; copying the historical data to a first operation cache area and the data of the second target logical block to a second operation cache area, performing data operation through the first and second operation cache areas; and copying current data of the second operation cache area to the target cache area. The application can improve the performance of flash media.

Description

Technical Field

[0001] This application relates to the field of storage product technology, and in particular to a data operation method, apparatus, electronic device and storage medium. Background Technology

[0002] In related technologies, the Replay Protected Memory Block (RPMB) is a partition set in the Nand Flash memory medium. This partition is mainly used to store important user information in a small storage partition that is protected against replay attacks and passes user verification.

[0003] In this process, when data needs to be written, the old data must first be read from the RPMB, then replaced, and then written; when data needs to be read, the existing data must be read directly from the RPMB. It is easy to see that the more times the RPMB is read from during data read and write operations, the lower the performance of the flash memory medium becomes. Summary of the Invention

[0004] The main objective of this application is to provide a data operation method, apparatus, electronic device, and storage medium, which aims to reduce the number of times data is read from the RPMB in order to improve the performance of the flash memory medium.

[0005] To achieve the above objectives, a first aspect of this application provides a data operation method, comprising: acquiring a data operation request, wherein the data operation request includes the operation start position and operation quantity of a logic block;

[0006] Determine the first target logical block in the Replay Protection Memory Block (RPMB) to which the historical data stored in the target cache belongs, wherein the historical data is the data from the previous operation;

[0007] The first target logic block is matched according to the operation start position and the operation number to obtain the matching result;

[0008] If the matching result indicates that the data operated on this time does not completely match the first target logic block, a second target logic block is determined based on the operation start position, the number of operations, and the first target logic block. The second target logic block is the logic block in the RPMB corresponding to the target data in the data operated on this time that does not match the first target logic block.

[0009] The historical data is copied to the first operation cache and the data of the second target logic block is copied to the second operation cache, and data operations are performed through the first operation cache and the second operation cache.

[0010] The current data in the second operation cache is copied as new historical data to the target cache.

[0011] In some embodiments, when the data operation is reading data, the data operation through the first operation buffer and the second operation buffer includes:

[0012] Using the current data in the first operation buffer and the second operation buffer, a data return response is sent to the host that sent the data operation request.

[0013] In some embodiments, when the data operation is to write data, the data operation request may further include data to be written.

[0014] The data operations performed through the first operation buffer and the second operation buffer include:

[0015] The data in the first operation buffer and the second operation buffer are replaced based on the data to be written.

[0016] Data is written using the current data in the first operation buffer and the second operation buffer.

[0017] In some embodiments, after copying the current data of the second operation cache as new historical data to the target cache, the method further includes:

[0018] The write count of the RPMB is updated incrementally;

[0019] Redundant data writing is performed on the flash media with the RPMB configured, based on the number of writes to be updated.

[0020] In some embodiments, after updating the write count of the RPMB, the method further includes:

[0021] If a data write fails, the current write count is decremented.

[0022] Redundant data is written to the flash memory medium based on the number of updates, and data is discarded from the target cache.

[0023] In some embodiments, when the data operation is to write data, the data operation request may further include data to be written.

[0024] After obtaining the matching result, the method further includes:

[0025] When the matching result indicates that the data operated on this time completely matches the first target logic block, the historical data is copied to the first operation cache area;

[0026] The data in the first operation buffer is replaced based on the data to be written;

[0027] Data is written to the current data in the first operation buffer;

[0028] The current data in the first operation cache is copied as new historical data to the target cache.

[0029] In some embodiments, the target cache, the first operation cache, and the second operation cache are all configured to store 32 logical blocks of data, and the amount of historical data and data copied to the second operation cache is 32 logical blocks.

[0030] To achieve the above objectives, a second aspect of this application provides a data processing apparatus, the apparatus comprising:

[0031] A data operation request acquisition module is used to acquire data operation requests, wherein the data operation request includes the start position and number of operations of the logic block;

[0032] The first target logical block determination module is used to determine the first target logical block to which the historical data stored in the target cache belongs in the replay protection memory block RPMB, wherein the historical data is the data from the previous operation;

[0033] The matching module is used to match the first target logic block according to the operation start position and the number of operations to obtain a matching result;

[0034] The second target logic block determination module is used to determine a second target logic block based on the operation start position, the number of operations, and the first target logic block when the matching result indicates that the data operated on this time does not completely match the first target logic block. The second target logic block is the logic block in the RPMB corresponding to the target data in the data operated on this time that does not match the first target logic block.

[0035] The data operation module is used to copy the historical data to the first operation cache and the data of the second target logic block to the second operation cache, and to perform data operations through the first operation cache and the second operation cache.

[0036] The target cache data update module is used to copy the current data of the second operation cache as new historical data to the target cache.

[0037] To achieve the above objectives, a third aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described in the first aspect.

[0038] To achieve the above objectives, a fourth aspect of the present application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect.

[0039] This application proposes a data operation method, apparatus, electronic device, and storage medium. The method first obtains a data operation request, which includes the start position and number of operations for a logical block. Next, it determines the first target logical block in the Replay Protection Memory Block (RPMB) to which historical data stored in the target cache belongs, where the historical data is the data from the previous operation. Then, it matches the first target logical block according to the start position and number of operations to obtain a matching result. If the matching result indicates that the data to be operated on does not completely match the first target logical block, it determines a second target logical block based on the start position, number of operations, and the first target logical block, where the second target logical block is the logical block in the RPMB corresponding to the target data in the data to be operated on that does not match the first target logical block. Then, it copies the historical data to the first operation cache and the data of the second target logical block to the second operation cache, and performs data operations through the first and second operation caches. Finally, it copies the current data in the second operation cache as new historical data to the target cache. Since the target cache stores the data from the previous operation (i.e., historical data), upon receiving a data source operation request, the first target logical block can be matched based on the operation start position and operation quantity to determine if a complete overlay match exists. This determines whether data needs to be read from the RPMB. When the matching result indicates that the data being operated on does not completely match the first target logical block, it means that part of the data being operated on involves historical data. Therefore, historical data can be copied to the first operation cache, and only the target data that does not match the first target logical block is copied from the second target logical block in the RPMB. This eliminates the need to read historical data from the first target logical block of the RPMB, reducing the number of data reads and thus improving the performance of the flash memory medium. Furthermore, since the current data in the second operation cache is copied as new historical data to the target cache after a data operation, if the next data operation involves the current data in the second operation cache, the steps of reading the current data from the second operation cache in the next data operation can be reduced, further reducing the number of data reads and improving the performance of the flash memory medium. Attached Figure Description

[0040] Figure 1 This is a flowchart of a data manipulation method provided in one embodiment of this application;

[0041] Figure 2 This is a flowchart of an embodiment of a sub-step of step 150 when the data operation is writing data;

[0042] Figure 3This is a flowchart of a data manipulation method provided in another embodiment of this application;

[0043] Figure 4 This is a flowchart of a data manipulation method provided in another embodiment of this application;

[0044] Figure 5 This is a flowchart of a data manipulation method provided in another embodiment of this application;

[0045] Figure 6 This is a schematic diagram of the structure of the data manipulation device provided in the embodiments of this application;

[0046] Figure 7 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0050] In RPMB (Remote Resource Block) technology, when writing data, old data must first be read from the RPMB, then replaced, and then written. When reading data, existing data must be read directly from the RPMB. Therefore, it's clear that the more times the RPMB is read from the flash memory, the lower its performance becomes.

[0051] To improve the performance of flash memory media by reducing the number of times data is read from the Replay Protection Memory Block (RPMB), embodiments of this application provide a data operation method, a data operation device, an electronic device, and a computer-readable storage medium. The method first obtains a data operation request, which includes the start position and number of operations for a logical block. Next, it determines the first target logical block in the Replay Protection Memory Block (RPMB) to which historical data stored in the target cache belongs, where the historical data is the data from the previous operation. Then, it matches the first target logical block according to the start position and number of operations to obtain a matching result. If the matching result indicates that the data being operated on does not completely match the first target logical block, it determines a second target logical block based on the start position, number of operations, and the first target logical block, where the second target logical block is the logical block in the RPMB corresponding to the target data in the data being operated on that does not match the first target logical block. Then, it copies the historical data to the first operation cache and the data of the second target logical block to the second operation cache, and performs data operations through the first and second operation caches. Finally, it copies the current data in the second operation cache as new historical data to the target cache. Since the target cache stores the data from the previous operation (i.e., historical data), upon receiving a data source operation request, the first target logical block can be matched based on the operation start position and operation quantity to determine if a complete overlay match exists. This determines whether data needs to be read from the RPMB. When the matching result indicates that the data being operated on does not completely match the first target logical block, it means that part of the data being operated on involves historical data. Therefore, historical data can be copied to the first operation cache, and only the target data that does not match the first target logical block is copied from the second target logical block in the RPMB. This eliminates the need to read historical data from the first target logical block of the RPMB, reducing the number of data reads and thus improving the performance of the flash memory medium. Furthermore, since the current data in the second operation cache is copied as new historical data to the target cache after a data operation, if the next data operation involves the current data in the second operation cache, the steps of reading the current data from the second operation cache in the next data operation can be reduced, further reducing the number of data reads and improving the performance of the flash memory medium.

[0052] See Figure 1 , Figure 1 The flowchart of a data operation method provided in one embodiment of this application is shown. In this embodiment, the information processing method may include steps 110 to 160.

[0053] Step 110: Obtain a data operation request, wherein the data operation request includes the start position and number of operations of the logic block;

[0054] Step 120: Determine the first target logical block in the Replay Protection Memory Block (RPMB) to which the historical data stored in the target cache belongs, where the historical data is the data from the previous operation;

[0055] Step 130: Match the first target logic block according to the operation start position and the number of operations to obtain the matching result;

[0056] Step 140: If the matching result indicates that the data operated on this time does not completely match the first target logic block, determine the second target logic block based on the operation start position, the number of operations and the first target logic block. The second target logic block is the logic block in RPMB corresponding to the target data in the data operated on this time that does not match the first target logic block.

[0057] Step 150: Copy historical data to the first operation cache and the data of the second target logic block to the second operation cache, and perform data operations through the first operation cache and the second operation cache;

[0058] Step 160: Copy the data corresponding to the second target logic block in the current data of the second operation buffer as new historical data to the target buffer.

[0059] In one embodiment, a data operation request refers to a request to operate on all data within the logical block to which the data to be operated in the Replay Protected Memory Block (RPMB) belongs, using logical blocks as the unit of operation. The data operation in the data operation request can be either reading or writing data, without specific limitation. Furthermore, the data operation request can be issued by a host (specifically, a terminal, etc.). Additionally, the size of the data stored in the logical block can be a data frame (i.e., 256 bytes).

[0060] For example, suppose the data to be operated on according to the data operation request is A, and data A is stored in logical block A32 in RPMB. Then, when data A is operated on, all the data in logical block A32 will be operated on at the same time.

[0061] In one embodiment, the starting position of the logical block operation refers to the position of the first logical block that operates on the RPMB during the data operation process. Specifically, the starting position of the logical block operation can be the absolute address of the logical block, the relative offset address of the logical block, etc., and is not limited here.

[0062] In one embodiment, the number of operations of a logic block refers to the number of operations of logic blocks other than the logic block at which the operation begins. For example, assuming the logic block operation starts at position M and the number of operations is N, then the logic blocks ultimately operated on are M to M+N.

[0063] In one embodiment, the target buffer refers to a buffer used to store historical data. The target buffer can be any free buffer in memory or a specifically designated buffer; no specific limitation is made here. Furthermore, the size of the target buffer can be determined based on a multiple of the maximum number of data frames allowed by a single data operation command (i.e., an instruction indicating whether to read or write data) of the storage device. Examples include a size of 16 data frames (2K), a size of 32 data frames (4K), etc.; no specific limitation is made here.

[0064] In one embodiment, if the historical data is the size of a single logical block, the target cache stores the data of that single logical block. If the historical data is the size of multiple logical blocks, data storage begins from the last logical block in the historical data sequence, based on the storage capacity of the target cache. For example, assuming the target cache can store data of two logical blocks, and the logical blocks to which the data being operated belongs are M to M+N, then the historical data stored in the target cache consists of the data of logical blocks M+N-1 and M+N. As another example, assuming the target cache can store data of two logical blocks, and the logical blocks to which the data being operated belongs are M, then the historical data stored in the target cache consists of the data of logical block M.

[0065] In one embodiment, when the target cache contains historical data and no data operation is performed on RPMB within a preset operation waiting time, the historical data in the target cache can be released to reduce the invalid occupation of cache resources and improve the utilization rate of cache resources.

[0066] In one embodiment, the first target logic block can be one or more, and the second target logic block can be one or more; no specific limitation is made here.

[0067] In one embodiment, before determining the first target logical block to which the historical data stored in the target cache belongs in the replay protected memory block RPMB, it can be specifically confirmed whether the storage device supports data operations on the RPMB according to the storage protocol, operation protocol, and other protocols. If it supports the operation, subsequent steps including step 120 are performed; if it does not support the operation, the process ends, step 120 is not entered, and an operation failure response is returned to the host.

[0068] In one embodiment, matching the first target logic block based on the operation start position and operation quantity to obtain the matching result means determining whether the logic block involved in the data being operated on can cover the first target logic block based on the operation start position and operation quantity of the logic block, and using the determination result as the matching result. It should be noted that this determination process is actually indirectly related to the data. Specifically, the operation start position and operation quantity of the logic block represent the data being operated on, and the first target logic block represents historical data. Based on this, the matching result can indicate whether the data being operated on can cover historical data.

[0069] In one embodiment, before matching the first target logic block according to the operation start position and the number of operations to obtain the matching result, a Message Authentication Code (MAC) can be calculated according to the operation start position and the number of operations to obtain the MAC to be verified. Then, the verification MAC issued by the host is obtained. Then, the MAC to be verified is compared with the verification MAC. If the MAC to be verified and the verification MAC are different, the data operation ends and an operation failure response is returned to the host. If the MAC to be verified and the verification MAC are the same, data matching is performed.

[0070] In one embodiment, an incomplete match refers to a situation where some of the data being operated on involves the same logical blocks as the target logical block, while other data involves different logical blocks. For example, suppose the target cache stores data in logical blocks A32 and A33 of the RPMB (i.e., historical data), and the data to be operated on involves logical blocks A31 to A33. In this case, the data involving logical blocks A32 and A33 matches the historical data, while the data involving logical block A31 does not match the historical data; this is an incomplete match.

[0071] In one embodiment, compared to an incomplete match, the matching result can also indicate that the data operated on this time completely matches the historical data. A complete match includes one of the following situations: a complete match with all first target logic blocks; or a complete match with a portion of the logic blocks in the first target logic blocks. Specifically, a complete match with the first target logic block means that the logic blocks involved in the data operated on this time are exactly the same as the target logic blocks to which the historical data belongs. For example, assuming the target cache stores data from logic blocks A32 and A33 in the RPMB, and the logic blocks involved in the data to be operated on are A32 to A33, then the data operated on this time completely matches the first target logic block. Conversely, a complete match with a portion of the logic blocks in the first target logic block means that the logic blocks involved in the data operated on this time are exactly the same as the target logic blocks to which a portion of the historical data belongs. For example, assuming the target cache stores data from logic blocks A31 to A33 in the RPMB, and the logic blocks involved in the data to be operated on are A32 to A33, then the data to be operated on completely matches a portion of the first target logic blocks.

[0072] In one embodiment, in addition to an incomplete match, the matching result can also indicate that the data being operated on this time is completely mismatched with the first target logic block. A complete mismatch means that the logic block involved in the data being operated on this time is completely different from the target logic block to which the historical data belongs. All the logic blocks involved in the data being operated on this time belong to logic blocks other than the target logic block to which the historical data belongs. For example, suppose the historical data is the data in logic blocks A32 to A33 in RPMB, and the logic blocks involved in the data to be operated on are A30 to A31, then the data being operated on this time is completely mismatched with the first target logic block.

[0073] In one embodiment, when the data being operated on is completely mismatched with the first target logical block, regardless of whether the data operation is reading or writing data, the data needs to be directly copied from the logical block corresponding to the RPMB to the first operation buffer based on the operation start position and the number of operations. For the case of reading data, a data return response is sent to the host using the data in the first operation buffer. For the case of writing data, the data in the first operation buffer is directly replaced with the data to be written, and then the data is written using the current data in the first operation buffer. After this, regardless of whether the data operation is reading or writing data, the current data in the first operation buffer is written as new historical data to the target buffer.

[0074] In one embodiment, determining the second target logic block based on the operation start position, the number of operations, and the first target logic block means first determining the logic block corresponding to the data being operated on based on the operation start position and the number of operations, and then determining the logic blocks other than the first target logic block among the logic blocks corresponding to the data being operated on as the second logic block.

[0075] For example, assuming the operation starts at position A31, the number of operations is 3, and the first target logic blocks are A31 to A32, then the logic blocks involved in this data operation are A31 to A34. Through logic blocks A31 to A34 and target logic blocks A31 and A32, logic blocks A33 and A34 can be determined as the second target logic blocks.

[0076] In one embodiment, the second target logic block is the logic block in the RPMB corresponding to the target data in the data being operated on that does not match the first target logic block. Specifically, it refers to the situation where the data operations involving the target data in the data being operated on that does not match the first target logic block involve logic blocks in the RPMB. Continuing with the example from the previous paragraph, the data in the data being operated on that involves operation target logic blocks A31 and A32 corresponds to historical data, and the target data that does not match the first target logic block corresponds to the data in the second target logic blocks A33 and A34.

[0077] In one embodiment, copying historical data to the first operation cache and copying the data of the second target logical block to the second operation cache refers to the operations of copying historical data from the target cache to the first operation cache and copying the data of the second target logical block of the RPMB to the second operation cache. The order of these two operations, "copying historical data to the first operation cache" and "copying the data of the second target logical block to the second operation cache," is variable and not specifically limited here.

[0078] In one embodiment, when the data operation is reading data, performing the data operation through the first operation buffer and the second operation buffer means returning a data response to the host that sent the data operation request using the current data in the first and second operation buffers. When the data operation is reading data, the data read response is performed using the current data in the first and second operation buffers. This eliminates the need to read historical data during the response process; only the target data needs to be read from the RPMB. This reduces the need to repeatedly read historical data from previous operations, thereby reducing the frequency of RPMB reads and improving read performance.

[0079] In one embodiment, when the data operation is writing data, performing data operation through the first operation buffer and the second operation buffer means first replacing the corresponding data in the first operation buffer and the second operation buffer according to the data to be written, and then performing the data writing operation according to the current data in the first operation buffer and the second operation buffer.

[0080] In RPMB-related technologies, writing data must follow a read-then-write mechanism. This means that when writing data, it is necessary to read data from the corresponding logical block, replace the read data with the data to be written, and then write it. When the data operation is to write data, the data write response is performed using the current data in the first operation buffer and the second operation buffer. In this way, there is no need to read historical data during the response process. Instead, only the target data needs to be read from the RPMB, which can reduce the repeated reading of historical data that has been operated on before. This reduces the reading frequency of the RPMB and helps to improve write performance.

[0081] It is important to note that during data operations, the order of operations in the first operation buffer and the second operation buffer is fixed: data in the first operation buffer is operated on first, followed by data in the second operation buffer.

[0082] In one embodiment, during the data operation through the first operation buffer and the second operation buffer, it can be specifically determined whether the data in the first operation buffer and the second operation buffer conforms to the position order of the logic block based on the operation start position, the number of operations, and the target logic block. If they conform, the data operation is performed. If they do not conform, the data in the first operation buffer and the second operation buffer are swapped based on the position order of the logic block, and then the data operation is performed.

[0083] For example, suppose the historical data is the data of logical blocks A32 and A33 in RPMB, and the data involved in this operation involves logical blocks A31 to A34. Then, the historical data is first copied to the first operation buffer, and the data of logical blocks A31 and A34 (that is, the data that does not match the historical data in logical blocks A32 and A33) is copied to the second operation buffer. At this time, the data in the first operation buffer and the second operation buffer do not conform to the position order of the logical blocks. Therefore, the data corresponding to logical block A33 in the historical data can be swapped to the second operation buffer, and then the data involving logical block A31 can be swapped to the first operation buffer. At this time, the data in the first operation buffer is the data involving logical block A31 and the data corresponding to logical block A32 in the historical data, and the data in the second operation buffer is the data corresponding to logical block A33 in the historical data and the data involving logical block A34.

[0084] For example, suppose the historical data is data in logical blocks A32 and A33 of the RPMB, and the data to be operated on this time involves logical blocks A31 to A33. Then, the historical data is first copied to the first operation buffer, which contains data in logical block A31. At this time, the data in the first operation buffer and the second operation buffer conform to the positional order of the logical blocks. Therefore, there is no need to swap the operation buffer data in the first operation buffer and the second operation buffer based on the positional order of the logical blocks.

[0085] In one embodiment, when the data operation is to read data, during the data operation through the first operation buffer and the second operation buffer, no data replacement operation may be performed in the first operation buffer and the second operation buffer. Instead, the host may be sent a data return response using the current data in the first operation buffer and the second operation buffer.

[0086] In one embodiment, when the data operation is to write data, during the data operation through the first operation buffer and the second operation buffer, the data to be written can first replace the corresponding data in the first operation buffer and the second operation buffer. Then, the current data in the first operation buffer and the second operation buffer is written into the first target logic block and the second target logic block.

[0087] In one embodiment, copying the data corresponding to the second target logic block in the current data of the second operation cache as new historical data to the target cache means first releasing the historical data currently stored in the target cache, and then copying all the current data of the second operation cache as new historical data to the target cache.

[0088] For example, assuming the historical data is data from logical blocks A32 and A33 in the RPMB (these two logical blocks are the first target logical block), and the second operation buffer contains data from logical blocks A33 and A34, then logical block A34 is the second target logical block. When the data operation is reading data, the data corresponding to logical block A34 in the second operation buffer is the data originally stored in the RPMB partition for logical block A34 (i.e., the target data). Based on this, the target buffer will store the data from logical blocks A33 and A34.

[0089] For example, assuming the historical data is data from logical blocks A32 and A33 in the RPMB (the two logical blocks are the so-called first target logical block), and the second operation buffer contains data from logical blocks A33 and A34, then logical block A34 is the second target logical block. When the data operation is writing data, the data corresponding to logical block A34 in the second buffer is the data that logical block A34 originally stored in the RPMB partition (i.e., the target data) after being replaced by the written data. The target buffer will store the data currently written to logical block A34 and the data of logical block A33.

[0090] See Figure 2 , Figure 2 The flowchart illustrates a sub-step embodiment of step 150 when the data operation is writing data. In one embodiment, the data operation request further includes data to be written, and step 150 may include the following steps.

[0091] Step 210: Perform data replacement on the data in the first operation buffer and the second operation buffer based on the data to be written;

[0092] Step 220: Write data using the current data in the first operation buffer and the second operation buffer.

[0093] In one embodiment, performing data replacement based on the data to be written in the first operation buffer and the second operation buffer means first determining the data in the first operation buffer and the second operation buffer that corresponds to the data to be written, and then replacing the corresponding data with the data to be written to obtain the combined data based on the original data of RPMB and the data to be written.

[0094] For example, suppose the first target logical blocks are A31 and A32, and the second target logical blocks are A33 and A34. Data A, B, and C, each corresponding to a logical block size, are to be written to logical blocks A32, A33, and A34, respectively. Then, data A will replace the data in the first target logical block A32 in the first operation buffer, data B will replace the data in the second target logical block A33 in the second operation buffer, and data C will replace the data in the second target logical block A34 in the second operation buffer. Ultimately, the data in the first operation buffer will be A31 and A, and the data in the second operation buffer will be B and C.

[0095] When the data operation is to write data, by replacing the data in the first operation buffer and the second operation buffer with data based on the data to be written, the data to be written can be replaced in multiple logical block sizes. Then, data can be written using the current data in the first operation buffer and the second operation buffer. Thus, the data to be written can be written by announcing the amount of data to be written, thereby improving the read and write performance of RPMB.

[0096] See Figure 3 , Figure 3 The flowchart of a data manipulation method provided in another embodiment of this application is shown. In one embodiment, after step 160, the data manipulation method may further include the following steps.

[0097] Step 310: Increment the write count of RPMB;

[0098] Step 320: Perform redundant data writing based on the number of update writes on the flash media with RPMB configured.

[0099] In one embodiment, incrementing the RPMB write count means incrementing the current RPMB write count by one. For example, if the previous operation had an RPMB write count of X, and the data operation involves writing data, after writing data through the first operation buffer and the second operation buffer, the RPMB write count is updated to X+1.

[0100] In one embodiment, performing redundant data writing based on the number of update writes on a flash memory medium configured with RPMB refers to the operation of writing the updated write count as redundant data of the RPMB partition data into the Nand Flash flash memory medium.

[0101] After a successful write operation to the RPMB partition, the update write count requires the time it takes for two flash media write operations: the first for the RPMB data to be written, and the second for the update write count. By writing the update write count as redundant data, the time only required for the RPMB data to be written to the flash media is eliminated, thus improving write efficiency. Furthermore, it reduces the need for separate page writes of the update write count to the flash media, further enhancing data write performance. Additionally, because the update write count is written as redundant data, the latest write count can be recovered through device reconstruction in the event of a power outage, improving the safety redundancy of the recorded write count.

[0102] See Figure 4 , Figure 4 The flowchart of a data manipulation method provided in another embodiment of this application is shown. In one embodiment, after step 310, the data manipulation method may further include the following steps.

[0103] Step 410: After a data write failure, the current write count is decremented.

[0104] Step 420: Perform redundant data writing to the flash memory medium based on the number of update writes, and discard the data in the target cache.

[0105] In one embodiment, after a data write failure, the current write count is updated by decrementing. This means restoring the updated write count to the count corresponding to the previous write operation by decreasing it by one. For example, if the previous RPMB write count was X, and the data operation was writing data, after writing data through the first and second operation buffers, the RPMB write count was updated to X+1. However, if this data write fails, the RPMB write count will be updated back to X.

[0106] When a data write fails, the write count can be restored to the original count by decrementing the update, and the restored write count is written as redundant data to the flash memory medium. This maintains the correctness of the write count. Since the data write failed, the data in the first and second operation buffers is no longer "historical data" relative to the data of the next operation. By discarding data in the target buffer, the possibility of using erroneous historical data from the failed data operation in the next data operation can be reduced, thereby improving the accuracy of the next data operation.

[0107] See Figure 5 , Figure 5 The flowchart of a data operation method provided in another embodiment of this application is shown. In one embodiment, when the data operation is to write data, the data operation request may further include the data to be written. After step 130, the data operation method may further include the following steps.

[0108] Step 510: When the matching result indicates that the data operated on this time completely matches the first target logic block, copy the historical data to the first operation buffer;

[0109] Step 520: Perform data replacement on the data to be written in the first operation buffer;

[0110] Step 530: Write data using the current data in the first operation buffer;

[0111] Step 540: Copy the current data in the first operation buffer as new historical data to the target buffer.

[0112] In one embodiment, when the data operated on in this operation is a complete match with the first target logic block, which is a complete match with all first target logic blocks, performing data replacement based on the data to be written on the data in the first operation buffer means replacing all historical data in the first operation buffer with the data to be written.

[0113] In one embodiment, when the complete match between the data operated on and the first target logic block is a complete match between the data operated on and a portion of the logic blocks in the first target logic block, the data replacement based on the data to be written in the first operation buffer refers to first determining the first target logic block corresponding to the data to be written in all the first target logic blocks, and then replacing the data of the first target logic block corresponding to the data to be written in the historical data of the first operation buffer with the data to be written.

[0114] In one embodiment, if the data operated on in this operation is a complete match with the first target logic block, which is a complete match with all first target logic blocks, the current data in the first operation buffer refers to the data to be written.

[0115] In one embodiment, when the complete match between the data operated on and the first target logic block is a complete match between the data operated on and a portion of the logic blocks in the first target logic block, the current data in the first operation buffer refers to the combined data consisting of historical data that has not been replaced by the data to be written and the data to be written.

[0116] When the data operation is to write data, by replacing the data to be written in the first operation buffer based on the data to be written, the data to be written can be replaced in multiple logical block sizes. Then, the data can be written using the current data in the first operation buffer. Thus, the data to be written can be written by announcing the amount of data to be written, thereby improving the read and write performance of RPMB.

[0117] For example, if the data being operated on completely matches some of the logic blocks in the first target logic block, assuming the first target logic blocks are A31 to A34, and the data to be written, A and B, are of the same size as the logic blocks to be written, correspond to logic blocks A33 and A34 respectively, then the data corresponding to logic blocks A33 and A34 in the first operation buffer will be replaced with data A and data B respectively. Then, the data written to RPMB through the first operation buffer will become the original data of logic block A31, the original data of logic block A32, data A, and data B.

[0118] For example, if the data being operated on matches all the data in the first target logic block exactly, assuming the first target logic block is A31 to A32, and the data to be written, A and B, are of the same size as the logic block, correspond to the logic blocks A31 and A32 respectively, then the data corresponding to logic blocks A31 and A32 in the first operation buffer will be replaced with data A and data B respectively. Then, the data written to the RPMB through the first operation buffer will become data A and data B.

[0119] In one embodiment, when the data operation is reading data, the data operation method may further include the following steps after step 130.

[0120] Step 610: When the matching result indicates that the data operated on this time completely matches the first target logic block, copy the historical data to the first operation buffer;

[0121] Step 620: Return a data response to the host that sent the data operation request using the current data in the first operation buffer.

[0122] When the data operation is to read data, the data read response is performed using the current data in the first operation buffer and the second operation buffer. Regardless of whether the data operated on this time completely matches all of the first target logical blocks or completely matches some of the logical blocks in the first target logical blocks, there is no need to read historical data during the response process. This can reduce the repeated reading of historical data that has been operated on in the previous operation, thereby reducing the reading frequency of RPMB and helping to improve read performance.

[0123] For example, if the data being operated on completely matches some of the logic blocks in the first target logic block, assuming the first target logic blocks are A31 to A34, and the data of logic blocks A33 and A34 needs to be read, then the data of logic blocks A33 and A34 are returned to the host through the first operation buffer.

[0124] For example, if the data being operated on matches exactly with all the data in the first target logic blocks, assuming the first target logic blocks are A31 to A32, and we want to read the data from logic blocks A31 and A32, then all the historical data is returned to the host through the first operation buffer.

[0125] In one embodiment, the target cache, the first operation cache, and the second operation cache are all configured to store 32 logical blocks of data (i.e., 4K storage size). The amount of historical data and data copied to the second operation cache is also 32 logical blocks. Since data copying, reading, and writing are all performed in units of 32 logical blocks, the historical data and data copied to the second operation cache can all meet the 4K alignment requirement. Thus, regardless of whether the data being operated on in the current operation meets the exact alignment requirement, the specific data operation of reading or writing data can handle more than 4K of read / write data, thereby improving the performance of reading and writing data from the RPMB partition of the flash memory medium.

[0126] In one embodiment, when the data operation is a data write operation, after step 120, a 4K alignment determination can be performed based on the operation start position and the number of operations. If both the operation start position and the number of operations meet the 4K alignment requirement, historical data is copied to the first operation buffer. Then, the data to be written replaces all data in the first operation buffer. Data operations are then performed through the first operation buffer, and the current data in the first operation buffer is copied as new historical data to the target buffer. If at least one of the operation start position or the number of operations does not meet the 4K alignment requirement, steps 130 to 160 are then performed.

[0127] In one embodiment, during the 4K alignment determination based on the operation start position and the number of operations, it can be specifically determined whether the operation start position and the number of logic blocks are modulo 32. If both are 0, then 4K alignment is satisfied; if the modulo result of one of them is not 0, then 4K alignment is not satisfied.

[0128] See Figure 6 This application also provides a data manipulation device that can implement the above method. The data manipulation device 700 includes:

[0129] The data operation request acquisition module 710 can be used to acquire data operation requests, wherein the data operation request includes the start position and number of operations of the logic block;

[0130] The first target logic block determination module 720 can be used to determine the first target logic block to which the historical data stored in the target cache belongs in the replay protection memory block RPMB, wherein the historical data is the data from the previous operation;

[0131] The matching module 730 can be used to match the first target logic block according to the operation start position and the number of operations to obtain the matching result;

[0132] The second target logic block determination module 740 can be used to determine the second target logic block based on the operation start position, operation quantity and the first target logic block when the matching result indicates that the data operated in this operation does not completely match the first target logic block. The second target logic block is the logic block in RPMB corresponding to the target data in the data operated in this operation that does not match the first target logic block.

[0133] The data operation module 750 can be used to copy historical data to the first operation buffer and data of the second target logic block to the second operation buffer, and perform data operations through the first operation buffer and the second operation buffer.

[0134] The target cache data update module 760 can be used to copy the current data of the second operation cache as new historical data to the target cache.

[0135] The specific implementation of this data operation device is basically the same as the specific embodiment of the data operation method described above, and will not be repeated here.

[0136] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described data operation method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0137] Please see Figure 7 , Figure 7 The hardware structure of an electronic device 800, according to another embodiment, is illustrated. The electronic device 800 includes:

[0138] The processor 801 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0139] The memory 802 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 802 and is called and executed by the processor 801 using the data operation methods of the embodiments of this application.

[0140] The 803 input / output interface is used to implement information input and output.

[0141] The communication interface 804 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0142] Bus 805 transmits information between various components of the device (e.g., processor 801, memory 802, input / output interface 803, and communication interface 804);

[0143] The processor 801, memory 802, input / output interface 803, and communication interface 804 are connected to each other within the device via bus 805.

[0144] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described data manipulation method.

[0145] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0146] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of this application, and do not constitute a limitation on the technical solutions provided in this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in this application are also applicable to similar technical problems.

[0147] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0148] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0149] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0150] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0151] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0152] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0153] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0154] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0155] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0156] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A data manipulation method, characterized in that, include: Obtain a data operation request, wherein the data operation request includes the start position and number of operations of the logic block; Determine the first target logical block in the Replay Protection Memory Block (RPMB) to which the historical data stored in the target cache belongs, wherein the historical data is the data from the previous operation; The first target logic block is matched according to the operation start position and the operation number to obtain the matching result; If the matching result indicates that the data operated on this time does not completely match the first target logic block, a second target logic block is determined based on the operation start position, the number of operations, and the first target logic block. The second target logic block is the logic block in the RPMB corresponding to the target data in the data operated on this time that does not match the first target logic block. The historical data is copied to the first operation cache and the data of the second target logic block is copied to the second operation cache, and data operations are performed through the first operation cache and the second operation cache. Copy the current data in the second operation cache as new historical data to the target cache. The data operations performed through the first operation buffer and the second operation buffer include one of the following: When the data operation is to read data, a data return response is sent to the host that sent the data operation request using the current data in the first operation buffer and the second operation buffer; or, When the data operation is to write data, the data operation request also includes data to be written; the data in the first operation buffer and the second operation buffer are replaced based on the data to be written, and the data is written using the current data in the first operation buffer and the second operation buffer.

2. The method according to claim 1, characterized in that, After copying the current data of the second operation buffer as new historical data to the target buffer, the method further includes: The write count of the RPMB is updated incrementally; Redundant data writing is performed on the flash media with the RPMB configured, based on the number of writes to be updated.

3. The method according to claim 2, characterized in that, After updating the write count of the RPMB, the method further includes: If a data write fails, the current write count is decremented. Redundant data is written to the flash memory medium based on the number of updates, and data is discarded from the target cache.

4. The method according to claim 1, characterized in that, When the data operation is to write data, the data operation request also includes the data to be written; After obtaining the matching result, the method further includes: When the matching result indicates that the data operated on this time completely matches the first target logic block, the historical data is copied to the first operation cache area; The data in the first operation buffer is replaced based on the data to be written; Data is written to the current data in the first operation buffer; The current data in the first operation cache is copied as new historical data to the target cache.

5. The method according to claim 1, characterized in that, The target cache, the first operation cache, and the second operation cache are all configured to store 32 logical blocks of data, and the amount of historical data and data copied to the second operation cache is also 32 logical blocks.

6. A data manipulation device, characterized in that, The device includes: A data operation request acquisition module is used to acquire data operation requests, wherein the data operation request includes the start position and number of operations of the logic block; The first target logical block determination module is used to determine the first target logical block to which the historical data stored in the target cache belongs in the replay protection memory block RPMB, wherein the historical data is the data from the previous operation; The matching module is used to match the first target logic block according to the operation start position and the number of operations to obtain a matching result; The second target logic block determination module is used to determine a second target logic block based on the operation start position, the number of operations, and the first target logic block when the matching result indicates that the data operated on this time does not completely match the first target logic block. The second target logic block is the logic block in the RPMB corresponding to the target data in the data operated on this time that does not match the first target logic block. The data operation module is used to copy the historical data to the first operation cache and the data of the second target logic block to the second operation cache, and to perform data operations through the first operation cache and the second operation cache. The target cache data update module is used to copy the current data of the second operation cache as new historical data to the target cache. The data operations performed through the first operation buffer and the second operation buffer include one of the following: When the data operation is to read data, a data return response is sent to the host that sent the data operation request using the current data in the first operation buffer and the second operation buffer; or, When the data operation is to write data, the data operation request also includes data to be written; the data in the first operation buffer and the second operation buffer are replaced based on the data to be written, and the data is written using the current data in the first operation buffer and the second operation buffer.

7. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method according to any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 5.

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