Cache device of PSRAM controller and processing method thereof

Abstract

The invention discloses a cache device of a PSRAM controller and a processing method of the cache device, and relates to the cache device of the PSRAM controller, which comprises a plurality of random access main body caches, a plurality of continuous access main body caches and a write queue, each random access main body cache in the plurality of random access main body caches is used for temporarily storing data transmitted when the random access main body accesses the PSRAM; each continuous access main body cache in the plurality of continuous access main body caches is used for temporarily storing data transmitted by the continuous access main body access PSRAM; and the write queue is used for temporarily storing data written into the PSRAM by the random access main body and the continuous access main body, and further storing write data commands of different access main bodies or different lengths of the same access main body.

Description

Technical Field

[0001] The present invention relates to the technical field of controllers, and particularly to a cache device of a PSRAM controller and a processing method thereof. Background Art

[0002] PSRAM is called pseudo-static random access memory, which adopts the process and technology of DRAM, but does not require a complex control and refresh mechanism like DRAM. It realizes a RAM device similar to SRAM and has the characteristics of large capacity and simple interface. For example, a PSRAM with an 8-bit data width has only 11 signal lines and is very suitable for stacking and using in a microprocessor. Since the PSRAM interface is simple and the number of signal lines is small, the command, address, and data signals for PSRAM access must be transmitted from the data bus. Theoretically, for a 133MHz PSRAM access with a latency of 5 cycles, its additional overhead is 10 cycles, and the higher the PSRAM access clock frequency, the more additional overhead cycles. Therefore, when accessing PSRAM, it is necessary to increase the length of the accessed data as much as possible. For example, when the access length is 16 bytes, the bus efficiency is (16 / 2) / ((16 / 2)+10)=44.4%, and when the access length is increased to 256 bytes, the bus efficiency can be increased to (256 / 2) / ((256 / 2)+10)=92.8%. The PSRAM controller is a hardware component dedicated to managing and controlling PSRAM, which is connected to the CPU bus matrix to realize the main body of the CPU or DMA to read and write PSRAM data, and controls the read and write operations of PSRAM according to the read and write instructions of the bus matrix. When reading data, the controller issues a read instruction and waits to read after the data is stable; when writing data, the controller issues a write instruction and writes the data into the specified storage unit.

[0003] In the prior art, the cache management method of the PSRAM controller mainly adopts the traditional data cache mechanism. However, the data cache is a fixed-length access mechanism, and its length is the cache line length. Regardless of the length of the data accessed by the main body, the cache reads and writes according to the length of its line, and the address of the line must be aligned with the line length. When accessing, the data cannot be concatenated into a larger PSRAM access length, especially not suitable for continuous access scenarios. For accesses with a length less than the cache line length, due to the fixed-length access mechanism, only fixed-length data can be read, resulting in additional overhead and a great loss of efficiency.

[0004] In view of the above technical problems, the present invention proposes a cache device of a PSRAM controller and a processing method thereof. Summary of the Invention

[0005] The object of the present invention is to provide a cache device for a PSRAM controller and a processing method thereof in view of the defects of the prior art.

[0006] To achieve the above object, the present invention adopts the following technical solutions: A cache device for a PSRAM controller includes a plurality of random access body caches, a plurality of sequential access body caches, and a write queue; Each of the plurality of random access body caches is used to temporarily store data transmitted by a random access body accessing the PSRAM; Each of the plurality of sequential access body caches is used to temporarily store data transmitted by a sequential access body accessing the PSRAM; The write queue is used to temporarily store data written by the random access body and the sequential access body to the PSRAM, and further store write data commands of different access bodies or different lengths of the same access body.

[0007] Further, each of the random access body caches includes a first read cache, a first primary write cache, and a first secondary write cache; wherein the first read cache, the first primary write cache, and the first secondary write cache all include a first data memory and a first Tag memory; The first data memory of the first read cache is used to temporarily store data read or pre-read by the random access body; The first data memories of the first primary write cache and the first secondary write cache are both used to temporarily store data written by the random access body; The first Tag memories of the first read cache, the first primary write cache, and the first secondary write cache are all used to mark the status of the data in the corresponding first data memory, and the status includes the PSRAM address aligned with the length of the corresponding first data memory, and a byte status flag used to record whether each byte in the corresponding first data memory is valid.

[0008] Further, each of the sequential access body caches includes a second read cache, a second primary write cache, and a second secondary write cache; wherein the second read cache, the second primary write cache, and the second secondary write cache all include a second data memory and a second Tag memory; The second data memory of the second read cache is used to temporarily store data read or pre-read by the sequential access body; The second data memories of the second primary write cache and the second secondary write cache are both used to temporarily store data written by the sequential access body; The second Tag memories of the second read cache, the second first-level write cache, and the second second-level write cache are all used to mark the status of the data stored in the corresponding second data memories. The status includes a 1-bit valid flag, the starting address of the data stored in the corresponding second data memory mapped to the PSRAM, and the length of the valid data stored in the corresponding second data memory.

[0009] Further, the write queue includes a command queue and a third data memory; wherein the command queue consists of several third Tag memories; The third data memory is used to temporarily store all the data to be written to the PSRAM; The third Tag memory includes a 1-bit valid flag, the starting address of the PSRAM where the data in the third data memory is written, the length of the data written to the PSRAM, and the storage address of the data written to the PSRAM in the third data memory.

[0010] Correspondingly, a processing method for the cache device of the PSRAM controller is also provided, including: Main body cache write data: The access main body sends a write data command to the PSRAM. After the PSRAM receives the write data command, it judges whether the first-level write cache is in a valid state and whether the address matches; if so, it writes the write data into the first-level write cache and marks it as valid data, and at the same time judges whether the address in the read cache matches. If so, it writes the data into the data memory of the read cache; after all the data is written into the first-level write cache, it updates the PSRAM address in the Tag memory of the first-level write cache; Main body cache read data: The access main body sends a read data command to the PSRAM. The PSRAM determines the address and length of the read data, and judges whether the read cache contains all the required data. If so, it directly reads the data from the read cache and returns it to the access main body; if not, it marks the missing data part, and queries the data in the first-level write cache, the second-level write cache, and the write queue in the main body cache, and judges whether the required data exists according to the preset policy. If so, it reads the data into the read cache and marks it as valid data, and judges again whether the read cache contains all the required data. If there is a shortage, it reads the missing data from the PSRAM and writes it into the read cache, and finally returns the data to the access main body; Writing to the write queue: The PSRAM detects the secondary write cache that caches all access subjects. When any secondary write cache is in a valid state, it generates the address and data length for continuous writing to the PSRAM. It determines whether the command queue is not full and the data memory has sufficient storage space. If so, it writes the data to the third data memory, and writes the PSRAM address, data length, and the position information of the data in the third data memory to the third Tag memory in the command queue, and marks it as valid data. It clears the valid state flag of the corresponding data in the secondary write cache until the secondary write cache is in an invalid state. Reading from the write queue: The PSRAM checks whether the command queue is non-empty. If it is non-empty, it reads the PSRAM address, data length, and the position information of the data in the third data memory in the third Tag memory at the head of the command queue, sends a write command to the PSRAM memory, writes the data stored in the third data memory identified by the third Tag memory to the PSRAM memory, and clears the valid flag of the Tag at the head of the command queue, releasing the resources of the third Tag memory and the third data memory.

[0011] Furthermore, in the main cache write data, for the random access main cache, it determines whether the first-level write cache is valid by the byte status flag bit in the first Tag memory, and determines whether the address matches by judging that the PSRAM address in the first Tag memory is the same as the address of the write data after being aligned according to the length of the corresponding first data memory. The data is written to the offset address position of the first data memory in the first-level write cache. The offset address is obtained by subtracting the PSRAM address in the first Tag memory from the write data address, and marking it as valid by setting the byte status flag bit of the corresponding byte data in the first Tag memory to valid.

[0012] Furthermore, in the main cache write data, for the sequential access main cache, it directly determines whether the second-level write cache is valid by judging the 1-bit valid flag in the second Tag memory, and determines whether the address matches by judging that the PSRAM start address in the second Tag memory and the valid data length recorded in the second Tag memory are the same as the address of the write data, and the result of the valid data length recorded in the second Tag memory and the length of the write data does not exceed the length of the second-level write cache data memory. The data is written to the offset address position of the second data memory in the second-level cache. The offset address is the valid data length recorded in the second Tag memory, and marking it as valid by updating the result of the valid data length recorded in the second Tag memory and the length of the write data to the second Tag memory.

[0013] Further, in the main cache read data, for random access to the main cache, the corresponding byte status identification bits in the first Tag memory are determined according to the address and length of the read data, and logical operations are performed to obtain a result to determine whether the data is all in the first read cache.

[0014] Further, in the main cache read data, for sequential access to the main cache, it is judged whether the data is all in the second read cache by accessing the address.

[0015] Further, in the write to the write queue, for random access to the main cache, the data in the first and second-level write cache is not continuous. According to the information in the first Tag memory, a set of addresses and data lengths for continuous writing to the PSRAM memory are generated; For sequential access to the main cache, the data in the second and second-level write cache is continuous, and the addresses and data lengths for writing to the PSRAM memory are directly obtained.

[0016] Compared with the prior art, the beneficial effects of the present invention are: 1. Improve the PSRAM access efficiency: By optimizing the cache structure, according to the access characteristics of different access entities (such as CPU, DMA, etc.), the access data is concatenated into a larger PSRAM read / write length, thereby reducing unnecessary access times and significantly improving the single access efficiency of the PSRAM. In dealing with sequential access scenarios, the characteristics of the PSRAM can be better utilized to further improve the bus efficiency.

[0017] 2. Reduce the waiting time of the access entity: Optimize the write queue design, making data access faster and more accurate, reducing the waiting time of the access entity (such as CPU or DMA) during the write operation, and improving the overall response speed of the system.

[0018] 3. Flexibly adapt to different access entities: For the different characteristics of random access entities (such as CPU) and sequential access entities (such as DMA), a random access main cache and a sequential access main cache are respectively designed, enabling the cache structure to better adapt to the access requirements of different entities and improving the versatility and adaptability of the system.

[0019] 4. Reduce data transmission overhead: Through the cache mechanism and data prefetching strategy, the frequent access to the PSRAM is reduced, avoiding the additional overhead caused by insufficient access length, and improving the overall efficiency of data transmission.

[0020] 5. Improve the system performance and stability: The design of the cache device and processing method can effectively reduce the direct access pressure on the PSRAM memory, reduce the system latency and error rate caused by frequent access, and improve the overall performance and stability of the system.

[0021] 6. Enhance data consistency: In write operations, through the collaborative work of multi-level caches (such as the first-level write cache and the second-level write cache) and the write queue, the synchronization and consistency of data between different caches and memories are ensured, avoiding data loss or errors.

[0022] 7. Optimize resource utilization: The write queue can receive write data of indefinite length from all access subject caches, and reasonably arrange the order and length of writing to the PSRAM, improving the utilization rate of storage resources and reducing performance bottlenecks caused by resource waste. Brief Description of the Drawings

[0023] In Figure 1 is a structural diagram of the cache device of a PSRAM controller provided in the first embodiment; Figure 2 is a structural diagram of the random access subject read / write cache provided in the first embodiment; Figure 3 is a structural diagram of the sequential access subject read / write cache provided in the first embodiment; Figure 4 is a structural diagram of the write queue provided in the first embodiment; Figure 5 is a flowchart of the main body cache write data provided in the second embodiment; Figure 6 is a flowchart of the main body cache read data provided in the second embodiment; Figure 7 is a flowchart of writing to the write queue provided in the second embodiment; Figure 8 is a flowchart of reading from the write queue provided in the second embodiment. Detailed Embodiments

[0024] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0025] The purpose of the present invention is to provide a cache device of a PSRAM controller and its processing method in view of the defects of the prior art.

[0026] First Embodiment

[0027] This embodiment provides a caching device for a PSRAM controller. The caching device is a part of the PSRAM memory and is used to temporarily store the data written to or read from the PSRAM memory by each main body accessing the PSRAM memory on the bus matrix.

[0028] Each access main body corresponds to a cache, effectively avoiding the excessive dispersion of data caused by different access addresses among different main bodies, which is beneficial to connecting the access data into a larger PSRAM read / write length. According to the random and continuous access characteristics of the access main body, the access main body caches are divided into two different types: the random access main body cache 1 and the continuous access main body cache 2. The cache lengths between different access main bodies do not need to be the same to adapt to the access characteristics of different main bodies. All the access main body caches are connected to the same write queue 3. As Figure 1 shown, Figure 1 the arrows in it indicate the data flow direction.

[0029] The random access main body cache 1 is used to temporarily store the data transmitted by the random access main body (such as the CPU) accessing the PSRAM, and is composed of a first read cache 11, a first primary write cache 12, and a first secondary write cache 13.

[0030] The first read cache 11, the first primary write cache 12, and the first secondary write cache 13 of the random access main body cache 1 all contain a first data memory and a first Tag memory, as Figure 2 shown.

[0031] The first data memory of the first read cache 11 is used to temporarily store the data read or pre-read by the random access main body.

[0032] The first data memory of the first primary write cache 12 is used to temporarily store the data written by the random access main body.

[0033] The first data memory of the first secondary write cache 13 is used to temporarily store the data written by the random access main body.

[0034] The first secondary write cache 13 is also used to temporarily store the Tag and data written to the write queue 3. Because when there is a large amount of data written to the write queue 3, it takes multiple cycles to complete, which ensures that the first primary write cache 12 can continue to receive the written data.

[0035] The lengths of the first data memories corresponding to the first read cache 11, the first primary write cache 12, and the first secondary write cache 13 do not need to be the same.

[0036] The first Tag memory of the first read cache 11 is used to mark the status of the data stored in the first data memory corresponding to the first read cache 11; the first Tag memory of the first primary write cache 12 is used to mark the status of the data stored in the first data memory corresponding to the first primary write cache 12; the first Tag memory of the first secondary write cache 13 is used to mark the status of the data stored in the first data memory corresponding to the first secondary write cache 13; the status of the stored data all includes a PSRAM address aligned with the length of the corresponding first data memory and a byte status identifier for recording whether each byte in the corresponding first data memory is valid, and the number of bits of the byte status identifier is 1 / 8 of the number of bits of the corresponding first data memory.

[0037] The continuous access main cache 2 is used to temporarily store the data transmitted by the continuous access main body (such as a DMA channel) when accessing the PSRAM, and is composed of a second read cache 21, a second primary write cache 22 and a second secondary write cache 23.

[0038] The second read cache 21, the second primary write cache 22 and the second secondary write cache 23 of the continuous access main cache 2 all include a second data memory and a second Tag memory, as Figure 3 shown.

[0039] The second data memory of the second read cache 21 is used to temporarily store the data read or pre-read by the continuous access main body.

[0040] The second data memory of the second primary write cache 22 is used to temporarily store the data written by the continuous access main body.

[0041] The second data memory of the second secondary write cache 23 is used to temporarily store the data written by the continuous access main body.

[0042] The second secondary write cache 23 is also used to temporarily store the Tag and data written to the write queue 3.

[0043] The lengths of the second data memories corresponding to the second read cache 21, the second primary write cache 22 and the second secondary write cache 23 do not need to be the same.

[0044] The second Tag memory of the second read cache 21 is used to mark the status of the data stored in the second data memory corresponding to the second read cache 21; the second Tag memory of the second first-level write cache 22 is used to mark the status of the data stored in the second data memory corresponding to the second first-level write cache 22; the second Tag memory of the second second-level write cache 23 is used to mark the status of the data stored in the second data memory corresponding to the second second-level write cache 23; wherein the status of the stored data all includes a 1-bit valid flag, a starting address that records the mapping of the data stored in the corresponding second data memory to the PSRAM, and a length of the valid data stored in the corresponding second data memory.

[0045] The write queue 3 is used to temporarily store the data that all access entities (all random access entities, all sequential access entities) need to write to the PSRAM. The write queue 3 consists of a command queue 31 and a third data memory 32. The write queue 3 is used to store write data commands of different access entities or different lengths of the same access entity, as Figure 4 shown.

[0046] The command queue 31 consists of several third Tag memories. The third Tag memory includes a 1-bit valid flag, a starting address of the PSRAM where the data is written, a length of the data written to the PSRAM, and a storage address of the data written to the PSRAM in the third data memory 32. The third data memory 32 is used to temporarily store all the data that needs to be written to the PSRAM.

[0047] It should be noted that the data memory and Tag memory involved in this embodiment are generally implemented in the form of logical registers, but are not limited to the register form, and can also be implemented using directly accessible storage media such as SRAM.

[0048] When the length of the command queue in the write queue and the capacity of the third data memory are larger, more data can be cached and the efficiency is higher, but more resources are consumed. Therefore, it needs to be determined according to the actual access situation of the system. The length of the command queue should be greater than or equal to the quotient of the capacity of the third data memory divided by the maximum length of the first-level write cache. For example, if the system consists of three access entities, the lengths of the first-level write caches are 32 bytes, 64 bytes, and 128 bytes respectively, and the capacity of the third data memory is 1024 bytes, then the queue length should be designed to be greater than or equal to 8 (1024 / 128), and a more appropriate value is to perform a weighted average according to the write access frequencies of each access entity.

[0049] The cache device of this embodiment has the following beneficial effects: 1. Improve the access efficiency of the PSRAM controller: By optimizing the cache structure according to the characteristics of different access entities, effectively increase the single access length of the PSRAM controller, reduce unnecessary access times, and thus improve the access efficiency of the PSRAM controller.

[0050] 2. Reduce the write waiting time: By optimizing the write queue, make data access faster and more accurate, and reduce the write waiting time of the access entity.

[0051] 3. Adapt to different access entities: The cache device is divided into a random access entity cache and a sequential access entity cache, which can adapt to the access characteristics of different access entities (such as CPU and DMA), avoid excessive data fragmentation, and is conducive to connecting the accessed data into a larger PSRAM read / write length.

[0052] 4. Data prefetching and integration: During the read operation, extend the length of the read data to the size of the read cache, pre-store more data in the read cache, and reduce the overhead of multiple read operations.

[0053] 5. Improve data consistency: By synchronously updating the data in the read cache during the write operation, ensure the consistency of the cached data.

[0054] 6. Reduce the access pressure on the PSRAM controller: By temporarily storing data, reduce the frequent direct access to the PSRAM controller, reduce the access pressure on the PSRAM controller, and improve the overall performance of the system.

[0055] 7. Flexible data processing: It can process write data of uncertain length, integrate write data commands of different access entities or different lengths of the same access entity through the write queue, and improve the efficiency of data writing.

[0056] Embodiment 2

[0057] This embodiment provides a processing method for a cache device of a PSRAM controller, and this processing method is based on a cache device of a PSRAM controller in Embodiment 1.

[0058] The processing method refers to the data transfer control method and strategy in the cache device. When the access entity performs a write operation, the written data is first temporarily stored in the entity write cache, and multiple write operations are concatenated until the written data cannot be temporarily stored in the write cache, and then written into the write queue, and finally read from the write queue and written into the PSRAM memory; when the access entity performs a read operation, extend the length of the read data to the size of the read cache, and the data is read and aggregated from the secondary write cache, write queue, and PSRAM memory of the access entity cache, pre-store more data in the read cache, and finally return the data required by the access entity. It mainly includes writing data to the entity cache, reading data from the entity cache, writing to the write queue, and reading from the write queue.

[0059] Main body cache writes data: The access main body sends a write data command to the PSRAM controller. After receiving the write command, the PSRAM controller starts to process the data, such as Figure 5 shown.

[0060] S101. The access main body sends a write data command to the PSRAM. After the PSRAM receives the write data command sent by the main body, it starts to process the data; S102. Determine whether the first-level write cache is valid. If so, execute step S103; Specifically: If the access main body is a random access main body, it is processed through the random access main body cache, and then judged by the byte status flag bit in the first Tag memory corresponding to the first-level write cache.

[0061] If the access main body is a sequential access main body, it is processed through the sequential access main body cache, and then directly judged by the 1-bit valid flag in the second Tag memory corresponding to the second-level write cache.

[0062] S103. Determine whether the first-level write cache address matches the address of the write data. If so, execute step S104; Specifically: For the random access main body cache, when it is judged that the PSRAM address in the first Tag memory corresponding to the first-level write cache is the same as the address of the write data after being aligned according to the length of the first data memory of the first-level write cache, it is considered that the address matches.

[0063] For the sequential access main body cache, when it is judged that the PSRAM start address in the second Tag memory corresponding to the second-level write cache and the valid data length recorded in the second Tag memory are the same as the address of the write data, and the result of the valid data length box write data length recorded in the second Tag memory does not exceed the length of the second data memory of the second-level write cache, it is considered that the address matches.

[0064] S104. Receive the write data, write it into the first-level write cache, and mark it as valid.

[0065] For the random access main body cache, the data is written to the offset address position of the first data memory of the first-level write cache. The offset address is calculated by subtracting the PSRAM address in the first Tag memory of the first-level write cache from the write data address. Marking as valid means setting the byte status flag bit of the corresponding byte data in the first Tag memory to valid.

[0066] For continuous access to the main cache, data is written to the offset address position of the second data memory of the second level write cache. The offset address is the effective data length recorded in the second Tag memory of the second level write cache. Marking valid means updating the result of the effective data length and the write data length recorded in the second Tag memory to the second Tag memory.

[0067] S105. Determine whether the address in the read cache is valid and whether the addresses match. If so, execute step S106; if not, execute step S107.

[0068] The determination of whether the address in the read cache is valid is specifically as follows: For random access to the main cache, it is determined by the byte status flag bit in the first Tag memory corresponding to the first read cache.

[0069] For continuous access to the main cache, it is directly determined by the 1-bit valid flag in the second Tag memory corresponding to the second read cache.

[0070] The determination of whether the addresses match is specifically as follows: For random access to the main cache, when the PSRAM address in the first Tag memory corresponding to the first read cache is the same as the address of the write data aligned with the length of the first data memory of the first read cache, it is considered that the addresses match.

[0071] For continuous access to the main cache, when the PSRAM start address in the second Tag memory corresponding to the second read cache and the effective data length recorded in the second Tag memory are the same as the address of the write data, and the result of the effective data length and the write data length recorded in the second Tag memory does not exceed the length of the second data memory of the second read cache, it is considered that the addresses match.

[0072] S106. Write the data to the data memory of the read cache and synchronize the latest data to the read cache, which is the processing for cache data consistency.

[0073] For random access to the main cache, write the data to the first data memory corresponding to the first read cache and synchronize the latest data to the first read cache.

[0074] For continuous access to the main cache, write the data to the second data memory corresponding to the second read cache and synchronize the latest data to the second read cache.

[0075] S107. Update the write data address; increase the address of the write data by the byte length of the data written this time as the address for the next write data.

[0076] S108. Determine whether all data of the current write command have been written into the first-level write cache. If so, execute step S109; if not, execute step S103.

[0077] For the random access main cache, the length of the write data in the write command sent by the random access main body is uncertain. Therefore, it is necessary to judge according to the type of the write command and write all data into the first first-level write cache.

[0078] For the sequential access main cache, the length of the write data in the write command sent by the sequential access main body is uncertain. Therefore, it is necessary to judge according to the type of the write command and write all data into the second first-level write cache.

[0079] S109. After all data are written into the first-level write cache, the access main body write command processing is completed.

[0080] In this embodiment, in step S102, determine whether the first-level write cache is valid. If not, execute step S110; S110. Update the PSRAM address in the first-level write cache Tag memory and execute step S104.

[0081] For the random access main cache, write the address of the write data aligned according to the length of the corresponding first data memory of the corresponding first-level write cache into the PSRAM address in the corresponding first Tag memory; For the sequential access main cache, write the address of the write data into the PSRAM address in the second Tag memory corresponding to the second first-level write cache, and clear the valid data length recorded in the second Tag memory.

[0082] In this embodiment, in step S103, determine whether the first-level write cache address matches the write data address. If not, execute step S111; S111. Determine whether the second-level write cache is valid. If so, execute step S112.

[0083] Regarding the random access main cache, judge through the byte status flag bit in the first Tag memory corresponding to the first second-level write cache.

[0084] Regarding the sequential access main cache, directly judge through the 1-bit valid flag in the second Tag memory corresponding to the second second-level write cache.

[0085] S112. Write all contents of the first-level write cache into the second-level write cache, invalidate the first-level write cache, and then continue to process the data in the second-level write cache and write it into the write queue for final writing into the PSRAM memory.

[0086] Regarding the random access main cache, write all the contents of the first - level write cache to the second - level write cache, and invalidate the first - level write cache.

[0087] Regarding the sequential access main cache, write all the contents of the second - level write cache to the second - level write cache, and invalidate the second - level write cache.

[0088] In this embodiment, in step S111, determine whether the second - level write cache is valid. If not, it means there is no valid data in the second - level write cache. At this time, it is not necessary to write the data in the first - level write cache to the second - level write cache, and step S104 can be continued. Specifically: Continue to process the current write command: If there is still data in the first - level write cache that has not been written, continue to write the data to the first - level write cache.

[0089] Update the write data address: Increase the address of the write data by the length of the data written this time as the address for the next write data.

[0090] Determine whether all the data of the current write command has been written to the first - level write cache: If all the data has been written to the first - level write cache, the processing of the main cache write command is completed.

[0091] Main cache read data: The access main body sends a read data command to the PSRAM controller. After receiving the read command, the PSRAM controller starts data processing, as Figure 6 shown.

[0092] S201. After the PSRAM controller receives the read command, it starts data processing and determines the address and length of the read data. To increase the single - access length of the PSRAM, the length read is determined as the length of the read cache (the first read cache or the second read cache).

[0093] S202. Determine whether the read cache (the first read cache or the second read cache) is valid. If so, execute step S203.

[0094] S203. Determine whether all the data is in the read cache. If so, execute step S204.

[0095] For the random access main cache, determine the corresponding byte status flag bits in the first Tag memory corresponding to the first read cache according to the address and length of the read data, and perform logical operations to obtain the result; For the sequential access main cache, make a judgment by accessing the address.

[0096] S204. Read the data from the read cache (the first read cache or the second read cache).

[0097] S205. Return the data to the access main body (random access main body or sequential access main body), and end the read command.

[0098] In this embodiment, in step S202, it is determined whether the read cache (the first read cache or the second read cache) is valid. If not, step S206 is executed.

[0099] In step S203, it is determined whether all data is in the read cache. If not, step S206 is executed.

[0100] S206. Mark the missing data.

[0101] When the read cache (the first read cache or the second read cache) is invalid, all data required by the main body is marked as missing data.

[0102] When the read cache (the first read cache or the second read cache) is valid but some data is missing, the corresponding byte status identification bit in the Tag memory of the read cache marks the missing data.

[0103] For the random access main body cache, the corresponding byte status identification bit in the first Tag memory corresponding to the first read cache marks the missing data.

[0104] For the sequential access main body cache, the corresponding byte status identification bit in the second Tag memory corresponding to the second read cache marks the missing data.

[0105] S207. Query the data in the first-level write cache, second-level write cache, and write queue in the access main body cache.

[0106] For the random access main body cache, compare the address of the missing data with the data addresses recorded in the first first-level write cache, first second-level write cache, and write queue, and perform the query according to the strategy that the first first-level write cache takes precedence over the first second-level write cache, the first second-level write cache takes precedence over the write queue, and the tail in the write queue takes precedence over the head.

[0107] For the sequential access main body cache, compare the address of the missing data with the data addresses recorded in the second first-level write cache, second second-level write cache, and write queue, and perform the query according to the strategy that the second first-level write cache takes precedence over the second second-level write cache, the second second-level write cache takes precedence over the write queue, and the tail in the write queue takes precedence over the head.

[0108] S208. Determine whether the required data exists. If so, execute step S209. If not, execute step S212.

[0109] For the random access main body cache, when the address of the missing data exists within the address range of the data recorded in the first first-level write cache, first second-level write cache, and write queue, it indicates that the data exists.

[0110] For consecutive access to the main cache, when the address of the missing data is within the address range of the data recorded in the second-level write cache, the second-level write cache, and the write queue, it indicates that the data exists.

[0111] S209. Read the existing data into the read cache and mark it as valid.

[0112] For random access to the main cache, the data is written to the position corresponding to the address offset of the first data memory in the first read cache, and the byte status flag bit in the corresponding first Tag memory is identified.

[0113] For consecutive access to the main cache, the data is written to the position corresponding to the address offset of the second data memory in the second read cache, and the byte status flag bit in the corresponding second Tag memory is identified.

[0114] S210. Determine whether all the data is in the read cache. If not, execute step S211; if so, execute step S204.

[0115] For random access to the main cache, determine the corresponding byte status flag bits in the first Tag memory corresponding to the first read cache according to the address and length of the read data, and perform a logical operation to obtain the result; For consecutive access to the main cache, make a judgment by accessing the address.

[0116] S211. Mark the missing data.

[0117] When the read cache (the first read cache or the second read cache) is invalid, mark all the data required by the main body as missing data.

[0118] When the read cache (the first read cache or the second read cache) is valid, but some data is missing, the data marked as missing is marked by the corresponding byte status flag bits in the Tag memory of the read cache.

[0119] For random access to the main cache, the data marked as missing is marked by the corresponding byte status flag bits in the first Tag memory corresponding to the first read cache.

[0120] For consecutive access to the main cache, the data marked as missing is marked by the corresponding byte status flag bits in the second Tag memory corresponding to the second read cache.

[0121] S212. Read the missing data from the PSRAM.

[0122] Organize the missing data into the interface commands for the PSRAM controller to read the PSRAM memory, and read all the missing data.

[0123] S213. Write the data to the read cache and mark it as valid.

[0124] The PSRAM controller writes the data read from the PSRAM memory into the read cache and identifies the byte status identification bits in the Tag memory.

[0125] Writing to the write queue: The PSRAM controller detects all the secondary write caches that access the main body cache. When any of the secondary write caches for accessing the main body cache is valid, the process of writing to the write queue will start, as Figure 7 shown.

[0126] S301. Generate the addresses and data lengths for continuous writing to the PSRAM.

[0127] For the random access main body cache, the data in the first secondary write cache may not be completely continuous. According to the information in the first Tag memory corresponding to the first secondary write cache, a set of addresses and data lengths for continuous writing to the PSRAM memory are generated; For the continuous access main body cache, the data in the second secondary write cache is continuous, and the addresses and data lengths for writing to the PSARM memory can be directly obtained.

[0128] S302. Determine whether the command queue is not full. If so, execute step S303; if not, wait for the queue to have free space or optimize the writing strategy.

[0129] S303. Determine whether the space in the third data memory is sufficient. If so, execute step S303; if not, wait for the third data memory to have sufficient space or optimize the writing strategy.

[0130] S304. Write the data into the third data memory.

[0131] S305. Write the PSRAM address, data length, and the position where the data is stored in the third data memory into the third Tag memory in the command queue and mark it as valid.

[0132] S306. Clear the valid status of the corresponding data in the secondary write cache.

[0133] For the random access main body cache, mark the byte status identification bits of the corresponding bytes in the first Tag memory of the first secondary write cache that have been written to the write queue as invalid; For the continuous access main body cache, clear the valid bit of the second Tag memory in the second secondary write cache.

[0134] S307. Determine whether the secondary write cache (the first secondary write cache or the second secondary write cache) is invalid. If so, end the process; if not, continue to execute S301.

[0135] Reading the write queue: When the PSRAM bus is idle, the PSRAM controller reads the data in the write queue and writes it into the PSRAM memory, asFigure 8 as shown

[0136] S401. Check whether the command queue is non-empty. If it is, execute step S402; if not, end.

[0137] S402. Read the PSRAM address, data length, and the position where the data is stored in the third data memory in the third Tag memory at the head of the command queue.

[0138] S403. Send a write command to the PSRAM memory to write the data stored in the third data memory identified by this third Tag memory into the PSRAM memory.

[0139] S404. Clear the valid flag of the Tag at the head of the command queue, release the resources of the third Tag memory and the third data memory, and end.

[0140] The beneficial effects of this embodiment are as follows: 1. Improve the PSRAM access efficiency: By optimizing the cache structure, according to the access characteristics of different access entities (such as CPU, DMA, etc.), the accessed data is connected into a larger PSRAM read / write length, thereby reducing unnecessary access times and significantly improving the single access efficiency of the PSRAM. In the case of handling continuous access scenarios, it can better utilize the characteristics of the PSRAM and further improve the bus efficiency.

[0141] 2. Reduce the waiting time of the access entity: Optimize the write queue design to make data access faster and more accurate, reduce the waiting time of the access entity (such as CPU or DMA) during the write operation, and improve the overall response speed of the system.

[0142] 3. Flexibly adapt to different access entities: For the different characteristics of random access entities (such as CPU) and continuous access entities (such as DMA), a random access entity cache and a continuous access entity cache are designed respectively, so that the cache structure can better adapt to the access requirements of different entities and improve the versatility and adaptability of the system.

[0143] 4. Reduce the data transmission overhead: Through the cache mechanism and data prefetching strategy, reduce the frequent access to the PSRAM, avoid the additional overhead caused by insufficient access length, and improve the overall efficiency of data transmission.

[0144] 5. Improve the system performance and stability: The design of the cache device and the processing method can effectively reduce the direct access pressure on the PSRAM memory, reduce the system latency and error rate caused by frequent access, and improve the overall performance and stability of the system.

[0145] 6. Enhance data consistency: In write operations, through the collaborative work of multi-level caches (such as the first-level write cache and the second-level write cache) and the write queue, the synchronization and consistency of data among different caches and memories are ensured, avoiding data loss or errors.

[0146] 7. Optimize resource utilization: The write queue can receive write data of uncertain length from all access subject caches, and reasonably arrange the order and length of writing to the PSRAM, improving the utilization rate of storage resources and reducing performance bottlenecks caused by resource waste.

[0147] Note that the above is only the preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A cache device for a PSRAM controller, characterized in that, It includes several random access entity caches, several sequential access entity caches, and a write queue; Each of the several random access entity caches is used to temporarily store the data transmitted by the random access entity accessing the PSRAM; Each of the several sequential access entity caches is used to temporarily store the data transmitted by the sequential access entity accessing the PSRAM; The write queue is used to temporarily store the data written by the random access entity and the sequential access entity to the PSRAM, and further store the write data commands of different access entities or different lengths of the same access entity.

2. The cache device of a PSRAM controller according to claim 1, wherein Each of the random access entity caches includes a first read cache, a first primary write cache, and a first secondary write cache; wherein the first read cache, the first primary write cache, and the first secondary write cache all include a first data memory and a first Tag memory; The first data memory of the first read cache is used to temporarily store the data read or pre-read by the random access entity; The first data memories of the first primary write cache and the first secondary write cache are both used to temporarily store the data written by the random access entity; The first Tag memories of the first read cache, the first primary write cache, and the first secondary write cache are all used to mark the status of the data in the corresponding first data memory. The status includes the PSRAM address aligned with the length of the corresponding first data memory, and the byte status flag used to record whether each byte in the corresponding first data memory is valid.

3. The cache device of a PSRAM controller according to claim 1, characterized in that Each of the sequential access entity caches includes a second read cache, a second primary write cache, and a second secondary write cache; wherein the second read cache, the second primary write cache, and the second secondary write cache all include a second data memory and a second Tag memory; The second data memory of the second read cache is used to temporarily store the data read or pre-read by the sequential access entity; The second data memories of the second primary write cache and the second secondary write cache are both used to temporarily store the data written by the sequential access entity; The second Tag memories of the second read cache, the second primary write cache, and the second secondary write cache are all used to mark the status of the data stored in the corresponding second data memory. The status includes a 1-bit valid flag, the start address of the data stored in the corresponding second data memory mapped to the PSRAM, and the length of the valid data stored in the corresponding second data memory.

4. The cache device of a PSRAM controller according to claim 1, wherein: The write queue includes a command queue and a third data memory; wherein the command queue consists of several third Tag memories; The third data memory is used to temporarily store all the data that needs to be written to the PSRAM; The third Tag memory includes a 1-bit valid flag, the start address of the PSRAM memory where the data in the third data memory is written, the length of the data written to the PSRAM, and the storage address of the data written to the PSRAM in the third data memory.

5. A processing method for a cache device of a PSRAM controller according to any one of claims 1-4, characterized in that, It includes: Entity cache write data: The access entity sends a write data command to the PSRAM, and the PSRAM processes the received write data command; Entity cache read data: The access entity sends a read data command to the PSRAM, and the PSRAM processes the received read command; Writing to the Write Queue: The PSRAM detects the secondary write cache that caches all access subjects. When any secondary write cache is in the valid state, it enters the writing to the write queue process; Reading from the Write Queue: When the PSRAM bus is idle, the PSRAM reads the data in the write queue and writes it into the PSRAM memory.

6. The processing method of a PSRAM controller cache device according to claim 5, characterized in that In the main cache write data, the specific processing of the write data command received by the PSRAM is as follows: Judge whether the primary write cache is in the valid state and whether the address matches; if so, write the write data into the primary write cache and mark it as valid data. At the same time, judge whether the address in the read cache matches. If so, write the data into the data memory of the read cache; after all data are written into the primary write cache, update the PSRAM address in the Tag memory of the primary write cache.

7. The processing method of a PSRAM controller cache device according to claim 6, characterized in that, In the main cache write data: For the random access main cache, judge whether the first primary write cache is valid by the byte status flag bit in the first Tag memory, and judge whether the address matches by judging that the PSRAM address in the first Tag memory is the same as the address of the write data aligned according to the corresponding first data memory length. The data is written to the offset address position of the first data memory of the first primary write cache. The offset address is obtained by subtracting the PSRAM address in the first Tag memory from the write data address. Mark it as valid by setting the byte status flag bit of the corresponding byte data in the first Tag memory to valid; For the sequential access main cache, directly judge whether the second primary write cache is valid by judging the 1-bit valid flag in the second Tag memory. Judge whether the address matches by judging that the PSRAM start address in the second Tag memory and the valid data length recorded in the second Tag memory are the same as the address of the write data, and the result of the valid data length recorded in the second Tag memory and the length of the write data does not exceed the length of the second data memory of the second primary write cache. The data is written to the offset address position of the second data memory of the second primary cache. The offset address is the valid data length recorded in the second Tag memory. Mark it as valid by updating the result of the valid data length recorded in the second Tag memory and the length of the write data to the second Tag memory.

8. The processing method of a PSRAM controller cache device according to claim 5, characterized in that, In the main cache read data, the specific processing of the read command received by the PSRAM is as follows: Determine the address and length of the read data, and judge whether the read cache contains all the required data. If so, directly read the data from the read cache and return it to the access subject; if not, mark the missing data part, and query the data in the primary write cache, secondary write cache and write queue in the main cache. Judge whether the required data exists according to the preset policy. If so, read the data into the read cache and mark it as valid data. Judge again whether the read cache contains all the required data. If there is a shortage, read the missing data from the PSRAM and write it into the read cache, and finally return the data to the access subject.

9. The processing method of a PSRAM controller cache device according to claim 8, characterized in that, In the main cache read data: For the random access main cache, the corresponding byte status identification bits in the first Tag memory are determined according to the address and length of the read data, and a logical operation is performed to obtain a result to judge whether the data is all in the first read cache; For the sequential access main cache, it is judged whether the data is all in the second read cache by accessing the address.

10. The processing method of a PSRAM controller cache device according to claim 5, characterized in that The specific process of entering the write queue in the write queue is as follows: Generate the address and data length for continuous writing to the PSRAM; judge whether the command queue is not full and the data memory has sufficient storage space. If so, write the data into the third data memory, and write the PSRAM address, data length, and the position information of the data in the third data memory into the third Tag memory in the command queue, and mark it as valid data; clear the valid status flag of the corresponding data in the secondary write cache until the secondary write cache is in an invalid state; When the PSRAM in the read write queue is idle on the PSRAM bus, the data in the write queue is read and written into the PSRAM memory. Specifically: The PSRAM checks whether the command queue is non-empty. If it is non-empty, it reads the PSRAM address, data length, and the position information of the data in the third data memory in the third Tag memory at the head of the command queue, sends a write command to the PSRAM memory, writes the data stored in the third data memory identified by the third Tag memory into the PSRAM memory, and clears the valid flag of the Tag at the head of the command queue, releasing the resources of the third Tag memory and the third data memory.

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