Design method and device of many-core processor architecture, equipment and storage medium

Abstract

The invention discloses a design method, device and equipment of a many-core processor architecture and a storage medium, and relates to the technical field of distributed computing. Comprising the steps of 1, dividing all cores into groups, 2, integrating a CPU assembly line, an intra-core private memory, a hardware FIFO queue and a DMA engine in each core, 3, labeling the cores in each group according to coordinates, storing shared data of processors in the group by using an intra-group shared memory, and storing the shared data of the processors in the group. The method comprises the following steps: step 1, transmitting and receiving an NoC data packet through an intra-group main core control inter-group communication interface for intra-group communication, and step 4, planning an inter-group optimal transmission path for inter-group communication according to the transmitted core coordinates of a source processor group and a target processor group. According to the method, the shortest path between the groups is automatically calculated, and NoC transmission is dynamically optimized; hardware FIFO and a DMA engine are adopted to realize low-delay data transmission, and a main core efficiently exchanges data among groups through an NoC to realize response.

Description

Technical Field

[0001] The present invention discloses a design method, device, equipment and storage medium for a multi-core processor architecture, which relates to the technical field of distributed computing. Background Art

[0002] A many-core processor is a processor architecture that integrates a large number of simple computing cores. By means of parallel computing, the overall performance is improved, and it is widely used in the fields of high-performance computing, artificial intelligence, big data processing, etc. With the expansion of the scale of many-core processors, the existing architectures face problems such as poor scalability, high latency and congestion in inter-core communication. Especially in the design of intra-group shared memory and fixed master cores, the communication bottleneck and load imbalance problems are prominent, which limit the improvement of the overall performance. Summary of the Invention

[0003] Aiming at the problems of the existing technology, the present invention provides a design method, device, equipment and storage medium for a multi-core processor architecture. By automatically calculating the shortest path between groups and dynamically optimizing the NoC transmission; inside the group, a hardware FIFO and a DMA engine are used to achieve low-latency data transmission, and between groups, the master core efficiently exchanges data through the NoC to achieve interrupt / polling response.

[0004] The specific solution proposed by the present invention is as follows: The present invention provides a design method for a multi-core processor architecture, based on a multi-core processor, including: Step 1: Divide all cores into groups, with a fixed number of cores in each group, specify the master core and ordinary cores in each group, and the master cores between groups are connected through the NoC and are responsible for inter-group communication. Step 2: Inside each core, integrate a CPU pipeline, an intra-core private memory, a hardware FIFO queue and a DMA engine. Use the CPU pipeline to perform calculations and logical task processing; use the intra-core private memory to store the data required for calculations; use the hardware FIFO queue to store requests from ordinary cores or responses from the master core; use the DMA engine to transfer operation or status data between the master core and the ordinary core. Step 3: Number the cores within each group according to coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. Use the intra-group shared memory to store the shared data of the processors within the group, and control the inter-group communication interface through the intra-group master core to send and receive NoC data packets for intra-group communication. Step 4: Plan the optimal inter-group transmission path according to the coordinates of the cores in the source processor group and the target processor group for inter-group communication.

[0005] Further, in the Step 3 of the design method for a multi-core processor architecture, the data transmission process between the cores within the group is as follows: Step 31: Submit a request from the general core to the master core: The general core writes the request into the local hardware FIFO and marks the target as the master core. After detecting the request through an interrupt or polling, the master core reads the message from the hardware FIFO. The master core executes the request. Step 32: Return the operation result from the master core to the general core: After completing the operation, the master core determines whether the operation result is a response or data. If the operation result is a response, write the result into the local hardware FIFO of the master core and mark the target as the general core that sent the request. If the operation result is data, directly transfer the result data to the private memory of the target core through the DMA engine. The general core obtains the result through interrupt or polling.

[0006] Furthermore, in step 4 of the design method of the many-core processor architecture, communication between groups is performed by the master core through the NoC, and the process is as follows: Step 41: The master core of the source processor group encapsulates the inter-group communication information into a message and sends it to the master core of the target processor group through the NoC network, and determines the transmission path of the NoC according to the optimal path planning. Step 42: After processing the request, the master core of the target processor group returns a response.

[0007] The present invention also provides a design device for a many-core processor architecture, based on a many-core processor, including a master core and general cores. All cores are divided into groups, with a fixed number of cores in each group. The master core and general cores of each group are specified, and the master cores between groups are connected through the NoC and are responsible for inter-group communication. Inside each core, a CPU pipeline, an intra-core private memory, a hardware FIFO queue, and a DMA engine are integrated. The CPU pipeline is used for computing and logical task processing; the intra-core private memory is used to store the data required for computing; the hardware FIFO queue is used to store the requests from general cores or the responses from the master core; the DMA engine is used to transfer operation or status data between the master core and general cores. The cores within each group are numbered according to coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. The intra-group shared memory is used to store the shared data of the processors within the group, and the intra-group master core controls the inter-group communication interface to send and receive NoC data packets for intra-group communication. According to the coordinates of the cores in the source and target processor groups for transmission, plan the optimal inter-group transmission path for inter-group communication.

[0008] Furthermore, the data transmission process between cores within a group of the design device for a many-core processor architecture is as follows: Step 31: Submit a request from a general core to the master core: The general core writes the request into the local hardware FIFO and marks the target as the master core. After detecting the request through an interrupt or polling, the master core reads the message from the hardware FIFO. The master core executes the request. Step 32: Return the operation result from the master core to the general core: After completing the operation, the master core determines whether the operation result is a response or data. If the operation result is a response, the result is written into the local hardware FIFO of the master core, and the target is marked as the general core that issued the request. If the operation result is data, the result data is directly transmitted into the private memory of the target core through the DMA engine. The general core obtains the result through interrupt or polling.

[0009] Furthermore, the master core of the design device for a many-core processor architecture communicates between groups through the NoC, and the process is as follows: The master core of the source processor group encapsulates the inter-group communication information into a message and sends it to the master core of the target processor group through the NoC network, and determines the transmission path of the NoC according to the optimal path planning. After processing the request, the master core of the target processor group returns a response.

[0010] The present invention also provides a design device for a many-core processor architecture, including: at least one memory and at least one processor; The at least one memory is used to store machine-readable programs; The at least one processor is used to call the machine-readable program and execute the design method for a many-core processor architecture as described above.

[0011] The present invention also provides a storage medium, on which computer instructions are stored. When the computer instructions are executed by a processor, the processor executes the design method for a many-core processor architecture as described above.

[0012] The beneficial effects of the present invention are: Achieve optimal path planning at the hardware level: automatically calculate the shortest path between groups and dynamically optimize NoC transmission; Achieve an efficient communication mechanism: within a group, use a hardware FIFO and a DMA engine to achieve low-latency data transmission, and between groups, the master core efficiently exchanges data through the NoC, supporting interrupt / polling response; The architecture of the present invention is applicable to scenarios such as high-performance computing and AI training, significantly improving the communication efficiency and parallel computing ability of many-core processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the inter-group hardware interconnection of the hierarchical many-core processor architecture.

[0014] Figure 2 It is a schematic diagram of the intra-group structure of the hierarchical many-core processor architecture.

[0015] Figure 3 It is a schematic diagram of the intra-core structure of the hierarchical many-core processor architecture. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] NoC (Network on Chip), the network on chip, and NoC transmission is a network-based communication interconnection method within a system on chip (SoC).

[0017] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments given are not intended to limit the present invention.

[0018] Embodiment 1; The present invention provides a design method for a many-core processor architecture, based on a many-core processor, including: Step 1: Divide all cores into groups, with a fixed number of cores in each group, specify the master core and ordinary cores in each group, and the master cores between groups are connected through NoC to be responsible for inter-group communication.

[0019] Step 2: Inside each core, integrate a CPU pipeline, intra-core private memory, a hardware FIFO queue, and a DMA engine. Use the CPU pipeline to perform calculations and logical task processing; use the intra-core private memory to store the data required for calculations; use the hardware FIFO queue to store requests from ordinary cores or responses from the master core; use the DMA engine to transfer operation or status data between the master core and ordinary cores.

[0020] Step 3: Number the cores within each group according to coordinates, and integrate an intra-group shared memory and an inter-group communication interface in each group. Use the intra-group shared memory to store the shared data of the processors within the group, and control the inter-group communication interface through the intra-group master core to send and receive NoC data packets for intra-group communication.

[0021] Among them, the data transfer process between the cores within the group is as follows: Step 31: Submit a request from an ordinary core to the master core: The ordinary core writes the request into the local hardware FIFO and marks the target as the master core. After the main core detects a request through interruption or polling, it reads the message from the hardware FIFO. The main core executes the request; Step 32: Return the operation result to the general core through the main core: After the main core completes the operation, it determines whether the operation result is a response or data. If the operation result is a response, the result is written into the local hardware FIFO of the main core, and the target is marked as the general core that issued the request; If the operation result is data, the result data is directly transmitted into the private memory of the target core through the DMA engine. The general core obtains the result through interruption or polling.

[0022] Step 4: Plan the optimal inter-group transmission path according to the coordinates of the cores in the source processor group and the target processor group for inter-group communication.

[0023] Among them, the main core communicates between each group through the NoC, and the process is as follows: Step 41: The main core of the source processor group encapsulates the inter-group communication information into a message and sends it to the main core of the target processor group through the NoC network, and determines the transmission path of the NoC according to the optimal path planning; Step 42: After the main core of the target processor group processes the request, it returns a response.

[0024] The main core can be dynamically adjusted according to the inter-group communication direction. For example, the right core is selected for horizontal communication, and the lower core is selected for vertical communication to reduce the number of hops and balance the load.

[0025] For example, as Figure 1 shown, according to the different positions of two adjacent core groups, the main core will also change. For example, when transmitting from Group 0_0 to Group 1_1, the main cores are Core 2_2 of Group 0_0 and Core 0_0 of Group 1_1; when transmitting from Group 0_1 to Group 0_2, the main cores are Core 1_2 of Group 0_1 and Core 1_0 of Group 0_2, etc.

[0026] When planning the optimal transmission path according to the coordinates of the source processor group and the target processor group for transmission, for example, when transmitting from Group 0_0 to Group 1_2, the optimal transmission path is from Group 0_0 to Group 1_1 to Group 1_2.

[0027] When specifically transmitting data, taking the scenario that Core 1_1 of Group 0_0 needs to access the shared memory data of Group 1_2 as an example, the execution steps can be: S1: Optimal path planning: Query the optimal path planning and obtain the path: Group (0,0) → Group (1,1) → Group (1,2), S2: Perform the first-hop transmission Group (0,0) → Group (1,1): S21: Initiate an in-group request: The Core(1,1) of Group(0,0) writes the request packet into the local FIFO, Perform target marking: Master_Core(2,2), Specify the operation type: Remote_Read(Group 1_2, 0x1234), S22: Master core processing: The Master_Core(2,2) of Group(0,0) detects that the FIFO is not empty, Parse the request and find that cross-group communication is required; Encapsulate the NoC packet header: src=(0,0), dst=(1,1); Select the interface: According to the relative position of (1,1), use the southeast direction interface; Send it to the Master_Core(0,0) of Group(1,1).

[0028] S3: Perform the second-hop transmission Group 1_1 → Group 1_2: Core 0_0 parses the request and finds that cross-group communication is required; Transmit the request to Core 1_2 through the hardware FIFO of Group 1_1; Encapsulate the NoC packet header: src=(1,1), dst=(1,2), Select the eastward interface and send it to Core 1_0 of Group 1_2, S4: Target group processing: Core 1_0 of Group 1_2 accesses the local shared memory 0x1234 and transmits the data and ACK response back to Core 2_2 of Group 0_0 through the original path; S5: Result return: After receiving the ACK, Core 2_2 of Group 0_0 updates the status and triggers the DMA to transfer the returned data to the private memory of Core 1_1.

[0029] Embodiment 2: The present invention further provides a design device for a many-core processor architecture. Based on the many-core processor, it includes a main core and ordinary cores. All cores are divided into groups, with a fixed number of cores in each group. The main core and ordinary cores of each group are specified. The main cores between groups are connected through the NoC and are responsible for inter-group communication. Inside each core, a CPU pipeline, on-chip private memory, a hardware FIFO queue, and a DMA engine are integrated. The CPU pipeline is used for computing and logical task processing; the on-chip private memory is used to store the data required for computing; the hardware FIFO queue is used to store the requests of ordinary cores or the responses of the main core; the DMA engine is used to transfer operation or status data between the main core and ordinary cores. The cores within each group are numbered according to coordinates. Each group integrates an intra-group shared memory and an inter-group communication interface. The intra-group shared memory is used to store the shared data of the processors within the group, and the intra-group main core controls the inter-group communication interface to send and receive NoC data packets for intra-group communication. According to the coordinates of the cores in the source processor group and the target processor group for transmission, the optimal inter-group transmission path is planned for inter-group communication.

[0030] Regarding the information interaction and execution process between the above-mentioned modules in the device, since they are based on the same concept as the method embodiment of the present invention, the specific content can be referred to the description in the method embodiment of the present invention and will not be elaborated here.

[0031] Similarly, the device of the present invention can achieve optimal path planning at the hardware level: automatically calculate the shortest inter-group path and dynamically optimize NoC transmission; achieve an efficient communication mechanism: use hardware FIFO and DMA engines within the group to achieve low-latency data transmission, and the main core between groups exchanges data efficiently through the NoC, supporting interrupt / polling response. The architecture of the present invention is applicable to scenarios such as high-performance computing and AI training, significantly improving the communication efficiency and parallel computing ability of the many-core processor.

[0032] It should be noted that not all steps and modules in the above-mentioned processes and device structures are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted according to needs. The system structures described in the above-mentioned embodiments can be physical structures or logical structures, that is, some modules may be implemented by the same physical entity, or some modules may be implemented by multiple physical entities respectively, or some components in multiple independent devices can be jointly implemented.

[0033] Embodiment 3: The present invention further provides a design device for a many-core processor architecture, including: at least one memory and at least one processor; The at least one memory is configured to store machine-readable programs; The at least one processor is configured to call the machine-readable programs to execute the design method of a many-core processor architecture as described above.

[0034] Regarding the content such as the information interaction of the processor and the process of executing the readable program in the above device, since it is based on the same concept as the method embodiment of the present invention, the specific content can be referred to the description in the method embodiment of the present invention and will not be elaborated here.

[0035] Similarly, the device of the present invention can achieve optimal path planning at the hardware level: automatically calculate the shortest path between groups and dynamically optimize NoC transmission; implement an efficient communication mechanism: guide the use of hardware FIFOs and DMA engines within the group to achieve low-latency data transmission, and the main core efficiently exchanges data between groups through the NoC, supporting interrupt / polling responses.

[0036] Embodiment 4: The present invention further provides a storage medium having computer instructions stored thereon, and when the computer instructions are executed by a processor, the processor is caused to execute the design method of a many-core processor architecture as described above. Specifically, a system or device equipped with the storage medium can be provided, and software program codes for implementing the functions of any one of the above embodiments are stored on the storage medium, and the computer (or CPU or MPU) of the system or device is caused to read and execute the program codes stored in the storage medium.

[0037] In this case, the program code read from the storage medium itself can implement the functions of any one of the above embodiments, so the program code and the storage medium storing the program code constitute a part of the present invention.

[0038] Embodiments of the storage medium for providing the program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program code can be downloaded from a server computer via a communication network.

[0039] In addition, it should be clear that not only can the functions of any one of the above embodiments be realized by executing the program code read by the computer, but also some or all of the actual operations can be completed by an operating system or the like operating on the computer based on the instructions of the program code.

[0040] In addition, it can be understood that the program code read from the storage medium is written into the memory provided in the expansion board inserted into the computer or into the memory provided in the expansion unit connected to the computer, and then based on the instructions of the program code, the CPU or the like installed on the expansion board or the expansion unit is made to execute part or all of the actual operations, thereby realizing the functions of any one of the above embodiments.

[0041] The above-described embodiments are merely preferred embodiments cited to fully illustrate the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or transformations made by those skilled in the art on the basis of the present invention are within the protection scope of the present invention. The protection scope of the present invention is subject to the claims.

Claims

1. A design method for a many-core processor architecture, characterized in that Based on a many-core processor, including: Step 1: Divide all cores into groups, with a fixed number of cores in each group. Designate the master core and ordinary cores in each group. The master cores between groups are connected through the NoC and are responsible for inter-group communication. Step 2: Inside each core, integrate a CPU pipeline, on-core private memory, a hardware FIFO queue, and a DMA engine. Use the CPU pipeline to perform calculations and logical task processing; use the on-core private memory to store the data required for calculations; use the hardware FIFO queue to store requests from ordinary cores or responses from master cores; use the DMA engine to transfer operation or status data between the master core and ordinary cores. Step 3: Number the cores within each group according to coordinates. Integrate intra-group shared memory and inter-group communication interfaces in each group. Use the intra-group shared memory to store the shared data of the processors within the group, and control the inter-group communication interface through the intra-group master core to send and receive NoC data packets for intra-group communication. Step 4: Plan the optimal inter-group transmission path according to the coordinates of the cores in the source processor group and the target processor group for inter-group communication.

2. The design method of a many-core processor architecture according to claim 1, characterized in that In Step 3, the data transfer process between the cores within the group is as follows: Step 31: Submit a request from an ordinary core to the master core: The ordinary core writes the request into the local hardware FIFO and marks the target as the master core. After detecting the request through an interrupt or polling, the master core reads the message from the hardware FIFO. The master core executes the request. Step 32: Return the operation result from the master core to the ordinary core: After the master core completes the operation, it determines whether the operation result is a response or data. If the operation result is a response, write the result into the local hardware FIFO of the master core and mark the target as the ordinary core that sent the request. If the operation result is data, directly transfer the result data to the private memory of the target core through the DMA engine. The ordinary core obtains the result through an interrupt or polling.

3. A design method for a many-core processor architecture according to claim 1, The feature is that in Step 4, the master core communicates between groups through the NoC, and the process is as follows: Step 41: The master core of the source processor group encapsulates the inter-group communication information into a message and sends it to the master core of the target processor group through the NoC network, and determines the transmission path of the NoC according to the optimal path planning. Step 42: After processing the request, the master core of the target processor group returns a response.

4. A design device for a many-core processor architecture, characterized in that Based on a many-core processor, including a master core and ordinary cores, wherein all cores are divided into groups, with a fixed number of cores in each group. Designate the master core and ordinary cores in each group. The master cores between groups are connected through the NoC and are responsible for inter-group communication. Inside each core, integrate a CPU pipeline, on-core private memory, a hardware FIFO queue, and a DMA engine. Use the CPU pipeline to perform calculations and logical task processing; Use the on-core private memory to store the data required for calculations; Use the hardware FIFO queue to store requests from ordinary cores or responses from master cores; use the DMA engine to transfer operation or status data between the master core and ordinary cores. Label the cores within each group according to their coordinates. Integrate shared memory within the group and an inter-group communication interface in each group. Use the shared memory within the group to store the shared data of the processors within the group. The main core within the group controls the inter-group communication interface to send and receive NoC data packets for inter-group communication. Plan the optimal inter-group transmission path according to the coordinates of the cores in the source processor group and the destination processor group for inter-group communication.

5. A design device for a many-core processor architecture according to claim 4, It is characterized in that the data transmission process between the cores within the group is as follows: Step 31: Submit a request from a general core to the main core: The general core writes the request into the local hardware FIFO and marks the destination as the main core. After detecting the request through an interrupt or polling, the main core reads the message from the hardware FIFO. The main core executes the request. Step 32: Return the operation result from the main core to the general core: After the main core completes the operation, it determines whether the operation result is a response or data. If the operation result is a response, write the result into the local hardware FIFO of the main core and mark the destination as the general core that issued the request. If the operation result is data, directly transfer the result data to the private memory of the destination core through the DMA engine. The general core obtains the result through interrupt or polling.

6. The design device of a many-core processor architecture according to claim 4, characterized in that the main The cores communicate between groups through the NoC, and the process is as follows: The main core of the source processor group encapsulates the inter-group communication information into a message and sends it to the main core of the destination processor group through the NoC network, and determines the transmission path of the NoC according to the optimal path planning. After processing the request, the main core of the destination processor group returns a response.

7. A design device for a many-core processor architecture, characterized in that It includes: At least one memory and at least one processor; The at least one memory is used to store machine-readable programs. The at least one processor is used to call the machine-readable program and execute a design method of a many-core processor architecture according to any one of claims 1 to 3.

8. A storage medium, characterized in that Computer instructions are stored on the storage medium, and when the computer instructions are executed by the processor, the processor executes a design method of a many-core processor architecture according to any one of claims 1 to 3.

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