Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises an array substrate, the array substrate comprises a display area and a non-display area, the display area comprises data lines, scanning lines and pixel units, the data lines and the scanning lines are arranged on different layers, and the pixel units are correspondingly connected with the data lines and the scanning lines. A first jump signal of a row scanning signal is coupled on a data line to generate a first coupling voltage, the non-display area is provided with a connecting line and an anti-coupling line which are connected with the data line, a second jump signal of a clock pulse signal on the anti-coupling line is coupled on the connecting line to generate a second coupling voltage, and the first coupling voltage and the second coupling voltage offset each other. Therefore, no voltage change of the data signal within the charging time is ensured, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of display devices, and particularly relates to a display panel and a display device. Background Art

[0002] A display panel generally consists of a color filter substrate, a liquid crystal layer, and an array substrate. Among them, the array substrate is provided with a display area and a non-display area. The display area is provided with corresponding data lines, scan lines, and a pixel array. The pixel array is composed of pixel units arranged in an array. The pixel units are correspondingly connected to the data lines and the scan lines. The scan lines are used to input row scan signals row by row, the data lines are used to input data signals, and the pixel units display correspondingly according to the received row scan signals and data signals.

[0003] Due to the overlap between the scan lines and the data lines in the array substrate, there is a coupling effect. As Figure 1 shown, TP is a data output control signal. When TP is at the rising edge, the data signal input to the source driver circuit is latched. When it is at the falling edge, the source driver circuit is controlled to output the latched data signals of each path to the data lines of the display panel. When the row scan signal on the scan line jumps, it will couple the data signal on the data line, causing the data signal to jump. If the data signal jump occurs at time t1 during the charging time, it will cause the storage voltage of the pixel unit to change or the charging to be insufficient, ultimately affecting the display effect of the display panel. Summary of the Invention

[0004] The purpose of the present invention is to provide a display panel, aiming to solve the problem that the traditional display panel has the jump of the row scan signal coupling causing the jump of the data signal, which affects the display effect of the display panel.

[0005] In a first aspect of an embodiment of the present invention, a display panel is proposed, including an array substrate, and the array substrate includes: A display area, which includes multiple columns of data lines and multiple rows of scan lines arranged in different layers, and pixel units correspondingly connected to the data lines and the scan lines. The multiple rows of scan lines are used to input row scan signals row by row, the multiple columns of data lines are used to input data signals respectively, and the first jump signal of the row scan signal generates a first coupling voltage on the data lines; A non-display area, which includes multiple connection lines connecting the source driver circuit and multiple columns of the data lines. The connection lines are arranged in the same layer as the data lines and are used to transmit the data signals to the data lines; The non-display area further includes an anti-coupling line disposed in a different layer from the connection line. The anti-coupling line is disposed parallel to the scan line and is used to input a clock pulse signal. Each second transition signal of the clock pulse signal is phase-aligned with the first transition signal of a row scan signal. The second transition signal generates a second coupling voltage on the connection line, and the first coupling voltage and the second coupling voltage cancel each other out. The first transition signal and the second transition signal are corresponding ones of the rising edge signal and the falling edge signal.

[0006] Optionally, the display area is symmetrically divided into a first display area and a second display area along a second direction. The first display area has a first refresh rate, and the second display area has a second refresh rate. Each scan line includes separate first sub-scan lines and second sub-scan lines. A plurality of the first sub-scan lines are located in the first display area and are used to input first row scan signals row by row, and a plurality of the second sub-scan lines are located in the second display area and are used to input second row scan signals row by row. The anti-coupling line includes a first anti-coupling line and a second anti-coupling line. The first anti-coupling line is disposed parallel to the first sub-scan line, and the second anti-coupling line is disposed parallel to the second sub-scan line. The clock pulse signal includes a first clock pulse signal and a second clock pulse signal. The first anti-coupling line is used to input the first clock pulse signal, and the second anti-coupling line is used to input the second clock pulse signal. Each second transition signal of the first clock pulse signal is phase-aligned with the first transition signal of a first row scan signal, and each second transition signal of the second clock pulse signal is phase-aligned with the first transition signal of a second row scan signal.

[0007] Optionally, along a first direction, the width of the corresponding scan line is equal to the width of the anti-coupling line disposed in parallel therewith. The first direction is the arrangement direction of the corresponding scan line.

[0008] Optionally, the anti-coupling line is disposed in the same layer as the scan line. The voltage of the high level of the clock pulse signal is the negative value of the voltage of the row-off signal of the row scan signal, and the voltage of the low level of the clock pulse signal is the negative value of the voltage of the row-on signal of the row scan signal.

[0009] Optionally, the anti-coupling line is disposed in a different layer from the scan line and is simultaneously located above or below the data line. The interlayer distance between the anti-coupling line and the connection line is less than the interlayer distance between the scanning line and the data line, the negative voltage value of the low level of the clock pulse signal is less than the voltage of the line turn-on signal of the line scanning signal, and the negative voltage value of the high level of the clock pulse signal is less than the voltage of the line turn-on signal of the line scanning signal; Alternatively, the interlayer distance between the anti-coupling line and the connection line is greater than the interlayer distance between the scanning line and the data line, the negative voltage value of the low level of the clock pulse signal is greater than the voltage of the line turn-on signal of the line scanning signal, and the negative voltage value of the high level of the clock pulse signal is greater than the voltage of the line turn-on signal of the line scanning signal.

[0010] Optionally, the anti-coupling line and the scanning line are arranged in different layers and symmetrically located above and below the data line; The voltage of the high level of the clock pulse signal is equal to the voltage of the line turn-on signal of the line scanning signal, and the voltage of the low level of the clock pulse signal is equal to the line turn-off signal of the line scanning signal.

[0011] Optionally, the anti-coupling line and the scanning line are arranged in different layers and are respectively located above and below the data line; The interlayer distance between the scanning line and the data line is greater than the interlayer distance between the anti-coupling line and the connection line; The voltage of the high level of the clock pulse signal is less than the voltage of the line turn-on signal of the line scanning signal, and the voltage of the low level of the clock pulse signal is less than the line turn-off signal of the line scanning signal; Alternatively, the interlayer distance between the scanning line and the data line is less than the interlayer distance between the anti-coupling line and the connection line; The voltage of the high level of the clock pulse signal is greater than the voltage of the line turn-on signal of the line scanning signal, and the voltage of the low level of the clock pulse signal is greater than the line turn-off signal of the line scanning signal.

[0012] A second aspect of the embodiments of the present invention provides a display device, including a driving circuit of a display panel and the display panel as described above. The scanning line, the connection line, and the anti-coupling line of the display panel are connected to the driving circuit of the display panel, and the driving circuit of the display panel is configured to respectively output a line scanning signal, a data signal, and a clock pulse signal to the scanning line, the data line, and the anti-coupling line.

[0013] Optionally, the driving circuit of the display panel includes: A source driving circuit, connected to a plurality of the connection lines, for outputting a plurality of the data signals according to a first control signal; A gate driving circuit, connected to a plurality of rows of the scanning lines, for outputting a plurality of the line scanning signals row by row according to a second control signal; A pulse output circuit, connected to the anti-coupling line, for outputting the clock pulse signal according to a third control signal; A timing controller, respectively connected to the source driver circuit, the gate driver circuit and the pulse output circuit, for respectively outputting the first control signal, the second control signal and the third control signal.

[0014] Optionally, the pulse output circuit includes differential traces, a comparator, a first electronic switch tube and a second electronic switch tube; The input end of the differential trace is used for inputting a differential signal. The differential trace is respectively connected to the positive-phase input end and the negative-phase input end of the comparator. The output end of the comparator is respectively connected to the control ends of the first electronic switch tube and the second electronic switch tube. The first end of the first electronic switch tube is used for inputting a first voltage signal, and the first end of the second electronic switch tube is used for inputting a second voltage signal. The second ends of the first electronic switch tube and the second electronic switch tube are connected to form the output end of the pulse output circuit. The first voltage signal and the second voltage signal are alternately output to form the corresponding clock pulse signal.

[0015] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above display panel includes an array substrate. The array substrate includes a display area and a non-display area. The display area includes data lines and scan lines arranged in different layers and pixel units correspondingly connected to the data lines and the scan lines. The first jump signal of the row scan signal generates a first coupling voltage by coupling on the data line. The non-display area is provided with a connection line connected to the data line and an anti-coupling line. The second jump signal of the clock pulse signal on the anti-coupling line generates a second coupling voltage by coupling on the connection line. The first coupling voltage and the second coupling voltage cancel each other out, so as to ensure that there is no voltage change in the data signal during the charging time, and improve the display effect of the display panel. Description of the Drawings

[0016] Figure 1 It is a schematic diagram of signal coupling between scan lines and data lines in a traditional array substrate; Figure 2 It is a schematic structural diagram of an array substrate provided in Embodiment 1 of the present invention; Figure 3 It is a schematic diagram of signal coupling between scan lines, data lines and anti-coupling lines in an array substrate provided in Embodiment 1 of the present invention; Figure 4 It is a waveform schematic diagram of scan lines and anti-coupling lines in an array substrate provided in Embodiment 1 of the present invention; Figure 5 It is a schematic structural diagram of an array substrate provided in Embodiment 2 of the present invention; Figure 6Schematic diagram of the array substrate provided in Embodiment III of the present invention; Figure 7 Schematic diagram of the array substrate provided in Embodiment IV of the present invention; Figure 8 Schematic diagram of the array substrate provided in Embodiment V of the present invention; Figure 9 Schematic diagram of the array substrate provided in Embodiment VI of the present invention; Figure 10 Waveform diagram of the scanning line and the anti-coupling line in the array substrate provided in Embodiment VI of the present invention; Figure 11 First schematic diagram of the display device provided in Embodiment VII of the present invention; Figure 12 Second schematic diagram of the display device provided in Embodiment VII of the present invention; Figure 13 Circuit schematic diagram of the pulse output circuit provided in Embodiment VII of the present invention; Figure 14 Waveform diagram of the differential signal and the clock pulse signal provided in Embodiment VII of the present invention.

[0017] Among them, the reference numerals in the figure are as follows: 100, array substrate; 200, driving circuit of the display panel; 210, gate driving circuit; 220, source driving circuit; 230, pulse output circuit; 240, timing controller; 110, display area; 120, non-display area; 111, data line; 112, scanning line; 121, connection line; 122, anti-coupling line; 1121, first sub-scanning line; 1122, second sub-scanning line; 1221, first anti-coupling line; 1222, second anti-coupling line; 231, differential trace; U1, comparator; U2, first operational amplifier; U3, second operational amplifier; M1, first electronic switch tube; M2, second electronic switch tube; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; TP, control signal for data transmission; VGH, row enable signal; VGL, row disable signal; CLK, clock pulse signal; t1, transition moment of the data signal; H1, layer distance between the scanning line and the data line; H2, layer distance between the anti-coupling line and the connection line. Detailed implementation manners

[0018] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0020] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0021] Embodiment 1 A first aspect of the embodiment of the present invention provides a display panel, including an array substrate 100. The display panel further includes a color filter substrate and a liquid crystal layer. The color filter substrate and the array substrate 100 are disposed opposite to each other, and the liquid crystal layer is located between the color filter substrate and the array substrate 100. The color filter substrate includes an upper polarizer, a color filter, a common electrode layer, and an upper alignment layer. The array substrate 100 includes a lower alignment layer, a driving layer, and a lower polarizer. Among them, the driving layer is a thin film transistor driving layer, and the driving layer is used to cooperate with the common electrode layer to drive the liquid crystal molecules of the liquid crystal layer.

[0022] Among them, as Figure 2 shown, in this embodiment, the array substrate 100 includes: A display area 110, the display area 110 includes multiple columns of data lines 111 and multiple rows of scan lines 112 arranged in different layers, and pixel units corresponding to and connected to the data lines 111 and the scan lines 112. The multiple rows of scan lines 112 are used to input row scan signals row by row, and the multiple columns of data lines 111 are used to input data signals respectively. The first jump signal of the row scan signal generates a first coupling voltage on the data lines 111; A non-display area 120, the non-display area 120 includes multiple connection lines 121 connecting the source driver circuit 220 and multiple columns of data lines 111. The connection lines 121 are arranged in the same layer as the data lines 111 and are used to transmit data signals to the data lines 111; The non-display area 120 further includes an anti-coupling line 122 disposed in a different layer from the connection line 121. The anti-coupling line 122 is arranged in parallel with the scanning line 112. The anti-coupling line 122 is used to input a clock pulse signal CLK. Each second transition signal of the clock pulse signal CLK is phase-aligned with the first transition signal of a row of scanning signals. The second transition signal generates a second coupling voltage on the connection line 121. The first coupling voltage and the second coupling voltage cancel each other out. The first transition signal and the second transition signal are corresponding ones of the rising edge signal and the falling edge signal.

[0023] In this embodiment, the display area 110 includes data lines 111, scanning lines 112, and a pixel array. The pixel array is composed of pixel units arranged in an array. The pixel units are correspondingly connected to a scanning line 112 and a data line 111, and are turned on when receiving a row scanning signal and receive a data signal to achieve charging, and form a driving voltage with a common electrode layer on the color filter substrate to drive the liquid crystal to deflect, and cooperate with the color filter on the color filter substrate to display corresponding image information.

[0024] Among them, when the scanning line 112 inputs multiple row scanning signals row by row, the rising edge signal or the falling edge signal of the row scanning signal will generate coupling on the data line 111, causing the data signal to rise or fall during the charging time. The change voltage of the data signal is the first coupling voltage. The first coupling voltage will change the magnitude of the driving voltage, and finally cause the display panel to be unable to display the normal gray-scale voltage, resulting in abnormal display.

[0025] To solve this problem, in this embodiment, an anti-coupling line 122 is provided in the non-display area 120 on the array substrate 100. The non-display area 120 is further provided with a plurality of connection lines 121. The plurality of connection lines 121 are connected to the plurality of data lines 111 one by one. The plurality of connection lines 121 are also connected to the signal terminals of the source driver circuit 220. The source driver circuit 220 is used to output multiple data signals. The connection line 121 is used to transfer the received data signal to the data line 111.

[0026] The anti-coupling line 122 can be connected to the driving circuit 200 of the display panel, for example, connected to the timing controller 240 or connected to one of the signal terminals of the source driver circuit 220. The specific connection method is not limited.

[0027] The anti-coupling line 122 is arranged in parallel with the scanning line 112, and can be arranged in the same layer or an abnormal layer as the scanning line 112. The anti-coupling line 122 partially overlaps with the plurality of data lines 111 respectively, such as Figure 3As shown, the anti-coupling line 122 receives the clock pulse signal CLK output by the driving circuit. The clock pulse signal CLK consists of alternating high and low levels. The i-th second transition signal of the clock pulse signal CLK is phase-aligned with the first transition signal of the (i + 1)-th row scanning signal input to the (i + 1)-th scanning line 112. The second transition signal of the clock pulse signal CLK generates a second coupling voltage on the connection line 121. Since the data line 111 is connected to the connection line 121, it is equivalent to the second transition signal generating a second coupling voltage on the data line 111. The absolute values of the second coupling voltage and the first coupling voltage are equal, one is a positive voltage and the other is a negative voltage, and the first coupling voltage and the second coupling voltage cancel each other out, thereby ensuring that there is no voltage change in the data signal during the charging time and improving the display effect of the display panel.

[0028] For example Figure 3 As shown, it is assumed that the anti-coupling line 122 and the scanning line 112 are arranged on the same layer. The rising edge signal on the scanning line 112 causes a jump in the data signal, then the second transition signal is a falling edge signal, that is, the falling edge signal of the clock pulse signal CLK is phase-aligned with the row scanning signals in sequence. When the rising edge signal of the second row scanning signal starts to change, the clock pulse signal CLK synchronously changes to a falling edge signal. The rising edge signal and the falling edge signal respectively generate an upward first coupling voltage and a downward second coupling voltage on the data line 111. The first coupling voltage and the second coupling voltage cancel each other out. Similarly, when the rising edge signal of the third row scanning signal starts to change, the clock pulse signal CLK synchronously changes to a falling edge signal. The rising edge signal and the falling edge signal respectively generate an upward first coupling voltage and a downward second coupling voltage on the data line 111. The first coupling voltage and the second coupling voltage cancel each other out. Finally, it realizes the compensation for the changing voltage of the data signal caused by the first transition signal of each row scanning signal, ensures that there is no voltage change in the data signal during the charging time, and improves the display effect of the display panel.

[0029] Or as Figure 4 As shown, in an alternative embodiment, the first transition signal of the row scanning signal is a falling edge signal, and the falling edge signal generates a downward first coupling voltage on the data signal. It is assumed that the anti-coupling line 122 and the scanning line 112 are arranged on the same layer. The rising edge signal of the clock pulse signal CLK is phase-aligned with the falling edge signal of the row scanning signal. The rising edge signal of the clock pulse signal CLK generates an upward second coupling voltage on the connection line 121. The first coupling voltage and the second coupling voltage cancel each other out. Finally, it realizes the compensation for the changing voltage of the data signal caused by the first transition signal of each row scanning signal, ensures that there is no voltage change in the data signal during the charging time, and improves the display effect of the display panel.

[0030] Among them, the voltage magnitude of the high level of the clock pulse signal CLK can be specifically set according to the voltage magnitude of the line scan signal, the distance between the data line 111 and the scan line 112, and the interlayer distance from the connection line 121.

[0031] The type of the second transition signal of the clock pulse signal CLK can be specifically set according to the type of the first transition signal and the interlayer position of the scan line 112 and the anti-coupling line 122. For example, when the anti-coupling line 122 and the scan line 112 are arranged in different layers and symmetrically located on both sides of the data line 111, and when the rising edge signal of the line scan signal causes the data signal to transition, the rising edge signal of the clock pulse signal CLK can be phase-aligned with the rising edge signal of the line scan signal, and the voltage of the high level signal of the clock pulse signal CLK can be equal to the voltage of the line turn-on signal VGH, and the voltage of the low level signal of the clock pulse signal CLK can be equal to the line turn-off signal VGL. The line turn-on signal VGH and the line turn-off signal VGL form the line scan signal, and the voltage of the line turn-on signal VGH is greater than the voltage of the line turn-off signal VGL.

[0032] Among them, in order to facilitate the adjustment of the voltage magnitude of the clock pulse signal CLK, in an optional embodiment, along the first direction, the widths of the corresponding scan line 112 and the corresponding anti-coupling line 122 arranged in parallel are equal. The first direction is the arrangement direction of the corresponding scan line 112. Among them, the connection line 121 is an extension line of the data line 111, and the two have the same size. For example Figure 6 As shown, in order to achieve the overlapping area between the anti-coupling line 122 and each connection line 121 and the overlapping area between the scan line 112 and the data line 111, the widths of the scan line 112 and the anti-coupling line 122 are equal. Therefore, when the corresponding level signal of the clock pulse signal CLK is equal to the corresponding level signal of the scan line 112, the second coupling voltage generated by the clock pulse signal CLK coupling on the connection line 121 will have the same magnitude and opposite polarity as the first coupling voltage generated by the scan line 112 coupling on the connection line 121, so as to achieve the cancellation of the coupling voltage and improve the display effect.

[0033] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above display panel includes an array substrate 100. The array substrate 100 includes a display area 110 and a non-display area 120. The display area 110 includes a data line 111 and a scan line 112 arranged in different layers, and pixel units correspondingly connected to the data line 111 and the scan line 112. The first jump signal of the row scan signal generates a first coupling voltage by coupling on the data line 111. The non-display area 120 is provided with a connection line 121 connecting the data line 111 and an anti-coupling line 122. The second jump signal of the clock pulse signal CLK on the anti-coupling line 122 generates a second coupling voltage by coupling on the connection line 121. The first coupling voltage and the second coupling voltage cancel each other out, thereby ensuring that there is no voltage change in the data signal during the charging time and improving the display effect of the display panel.

[0034] Embodiment 2 In another alternative embodiment, as Figure 5 shown, the display area 110 is symmetrically divided into a first display area 1101 and a second display area 1102 along the second direction. The first display area 1101 has a first refresh rate, and the second display area 1102 has a second refresh rate. Each scan line 112 includes a separated first sub-scan line 1121 and a second sub-scan line 1122. A plurality of first sub-scan lines 1121 are located in the first display area 1101 and are used to input the first row scan signal row by row. A plurality of second sub-scan lines 1122 are located in the second display area 1102 and are used to input the second row scan signal row by row; The anti-coupling line 122 includes a first anti-coupling line 1221 and a second anti-coupling line 1222. The first anti-coupling line 1221 is arranged in parallel with the first sub-scan line 1121, and the second anti-coupling line 1222 is arranged in parallel with the second sub-scan line 1122; The clock pulse signal CLK includes a first clock pulse signal and a second clock pulse signal. The first anti-coupling line 1221 is used to input the first clock pulse signal, and the second anti-coupling line 1222 is used to input the second clock pulse signal; Each second jump signal of the first clock pulse signal is phase-aligned with the first jump signal of a first row scan signal, and each second jump signal of the second clock pulse signal is phase-aligned with the first jump signal of a second row scan signal.

[0035] In this embodiment, the display area 110 can be partitioned, and different display areas 110 can have different refresh rates. The non-display area 120 includes a first non-display area 120 corresponding to the first display area 1101 and a second non-display area 120 corresponding to the second display area 1102. The first non-display area 120 is provided with a plurality of connection lines 121 and a first anti-coupling line 1221, and the second non-display area 120 is provided with a plurality of connection lines 121 and a second anti-coupling line 1222.

[0036] Each second transition signal of the first clock pulse signal is phase-aligned with the first transition signal of a first row scanning signal. The first row scanning signal input to the first display area 1101 and the data line 111 can correspondingly generate a first coupling voltage. The first clock pulse signal on the first anti-coupling line 1221 of the first non-display area 120 and the connection line 121 can correspondingly generate a second coupling voltage. The first coupling voltage and the second coupling voltage are equal in magnitude and opposite in polarity, and the voltages cancel each other out.

[0037] Similarly, each second transition signal of the second clock pulse signal is phase-aligned with the first transition signal of a second row scanning signal. The second row scanning signal input to the second display area 1102 and the data line 111 can correspondingly generate a first coupling voltage. The second clock pulse signal on the second anti-coupling line 1222 of the second non-display area 120 and the connection line 121 can correspondingly generate a second coupling voltage. The first coupling voltage and the second coupling voltage are equal in magnitude and opposite in polarity, and the voltages cancel each other out.

[0038] The frequency of the first clock pulse signal is correspondingly set relative to the refresh rate of the first display area 1101, and the frequency of the second clock pulse signal is correspondingly set relative to the refresh rate of the second display area 1102.

[0039] Wherein, for the convenience of adjusting the voltage magnitude of the clock pulse signal CLK, in an optional embodiment, along the first direction, the width of the first sub-scanning line 1121 corresponding to the first anti-coupling line 1221 arranged in parallel therewith is equal, and the width of the second sub-scanning line 1122 corresponding to the second anti-coupling line 1222 arranged in parallel therewith is equal. Therefore, when the corresponding level signal of the clock pulse signal CLK and the corresponding level signal of the corresponding scanning line 112 are equal, the second coupling voltage coupled by the clock pulse signal CLK on the connection line 121 will have the same numerical value and opposite polarity as the first coupling voltage coupled by the scanning line 112 on the connection line 121, thereby realizing the cancellation of the coupling voltage and improving the display effect.

[0040] Embodiment Three As Figure 6 shown, in an optional embodiment, the anti-coupling line 122 and the scanning line 112 are arranged on the same layer; The voltage of the high level of the clock pulse signal CLK is the negative value of the voltage of the row off signal VGL of the row scanning signal, and the voltage of the low level of the clock pulse signal CLK is the negative value of the voltage of the row on signal VGH of the row scanning signal.

[0041] In this embodiment, as Figure 3As shown, it is assumed that when the rising edge signal of the row scanning signal causes the data signal to jump, since the width of the anti-coupling line 122 is equal to that of the scanning line 112, and the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is equal to the interlayer distance H1 between the scanning line 112 and the data line 111, the low-level signal of the clock pulse signal CLK is the negative voltage of the row turn-on signal VGH, and the first coupling voltage generated by the rising edge signal of the row scanning signal and the second coupling voltage generated by the falling edge signal of the clock pulse signal CLK cancel each other out, improving the display effect.

[0042] Or, as Figure 4 shown, when the falling edge signal of the row scanning signal causes the data signal to jump, since the width of the anti-coupling line 122 is equal to that of the scanning line 112, and the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is equal to the interlayer distance H1 between the scanning line 112 and the data line 111, the voltage of the high level of the clock pulse signal CLK is the negative voltage of the row turn-off signal VGL of the row scanning signal, and the first coupling voltage generated by the falling edge signal of the row scanning signal and the second coupling voltage generated by the rising edge signal of the clock pulse signal CLK cancel each other out, improving the display effect.

[0043] Embodiment 4 In an alternative embodiment, as Figure 7 shown, the anti-coupling line 122 and the scanning line 112 are arranged in different layers and are both located above or below the data line 111; the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is less than the interlayer distance H1 between the scanning line 112 and the data line 111, the negative voltage of the low level of the clock pulse signal CLK is less than the voltage of the row turn-on signal VGH of the row scanning signal, and the negative voltage of the high level of the clock pulse signal CLK is less than the voltage of the row turn-on signal VGH of the row scanning signal; Or, the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is greater than the interlayer distance H1 between the scanning line 112 and the data line 111, the negative voltage of the low level of the clock pulse signal CLK is greater than the voltage of the row turn-on signal VGH of the row scanning signal, and the negative voltage of the high level of the clock pulse signal CLK is greater than the voltage of the row turn-on signal VGH of the row scanning signal.

[0044] Taking Figure 7 as an example, it is assumed that both the anti-coupling line 122 and the scanning line 112 are located below the data line 111. When the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is less than the interlayer distance H1 between the scanning line 112 and the data line 111, as Figure 3As shown, assuming that when the rising edge signal of the row scan signal causes the data signal to jump, since the width of the anti-coupling line 122 is equal to that of the scan line 112, the absolute value of the low-level signal of the clock pulse signal CLK needs to be less than the negative value of the voltage of the row enable signal VGH. The absolute values of the first coupling voltage generated by the rising edge signal of the row scan signal and the second coupling voltage generated by the falling edge signal of the clock pulse signal CLK are equal, with opposite polarities, and the voltages cancel each other out, improving the display effect.

[0045] Alternatively, when the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is greater than the interlayer distance H1 between the scan line 112 and the data line 111, as Figure 4 shown, when the falling edge signal of the row scan signal causes the data signal to jump, since the width of the anti-coupling line 122 is equal to that of the scan line 112, the voltage of the high level of the clock pulse signal CLK needs to be greater than the negative value of the voltage of the row off signal VGL of the row scan signal. The absolute values of the first coupling voltage generated by the falling edge signal of the row scan signal and the second coupling voltage generated by the falling edge signal of the clock pulse signal CLK are equal, with opposite polarities, and the voltages cancel each other out, improving the display effect.

[0046] Embodiment Five In an alternative embodiment, as Figure 8 shown, the anti-coupling line 122 and the scan line 112 are arranged in different layers and symmetrically located in the upper and lower layers of the data line 111; The voltage of the high level of the clock pulse signal CLK is equal to the voltage of the row enable signal VGH of the row scan signal, and the voltage of the low level of the clock pulse signal CLK is equal to the row off signal VGL of the row scan signal.

[0047] When the anti-coupling line 122 and the scan line 112 are respectively located in the upper and lower layers of the data line 111, for example, the anti-coupling line 122 is located in the upper layer of the data line 111 and the scan line 112 is located in the lower layer of the data line 111. At this time, the rising edge signal of the clock pulse signal CLK and the rising edge signal of the row scan signal need to be phase-aligned, or the falling edge signal of the clock pulse signal CLK and the falling edge signal of the scan signal need to be phase-aligned.

[0048] When the anti-coupling line 122 and the scan line 112 are arranged in different layers and symmetrically located in the upper and lower layers of the data line 111, the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is equal to the interlayer distance H1 between the scan line 112 and the data line 111. Assuming that when the rising edge signal of the row scan signal causes the data signal to jump, as Figure 10As shown, it is necessary to align the rising edge signals of the clock pulse signal CLK and the line scan signal in phase, and the high-level signal of the clock pulse signal CLK is equal to the voltage of the line enable signal VGH. The absolute values of the first coupling voltage generated by the rising edge signal of the line scan signal and the second coupling voltage generated by the rising edge signal of the clock pulse signal CLK are equal, with opposite polarities, and the voltages cancel each other out, improving the display effect.

[0049] Alternatively, assuming that the falling edge signal of the line scan signal causes the data signal to jump, it is necessary to align the falling edge signals of the clock pulse signal CLK and the line scan signal in phase, and the low-level signal of the clock pulse signal CLK is equal to the voltage of the line disable signal VGL. The absolute values of the first coupling voltage generated by the falling edge signal of the line scan signal and the second coupling voltage generated by the falling edge signal of the clock pulse signal CLK are equal, with opposite polarities, and the voltages cancel each other out, improving the display effect.

[0050] Embodiment Six In an alternative embodiment, as Figure 9 shown, the anti-coupling line 122 is arranged in a different layer from the scan line 112 and is located above and below the data line 111 respectively; The interlayer distance H1 between the scan line 112 and the data line 111 is greater than the interlayer distance H2 between the anti-coupling line 122 and the connection line 121; The voltage of the high level of the clock pulse signal CLK is less than the voltage of the line enable signal VGH of the line scan signal, and the voltage of the low level of the clock pulse signal CLK is less than the line disable signal VGL of the line scan signal; Alternatively, the interlayer distance H1 between the scan line 112 and the data line 111 is less than the interlayer distance H2 between the anti-coupling line 122 and the connection line 121; The voltage of the high level of the clock pulse signal CLK is greater than the voltage of the line enable signal VGH of the line scan signal, and the voltage of the low level of the clock pulse signal CLK is greater than the line disable signal VGL of the line scan signal.

[0051] In this embodiment, when the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is less than the interlayer distance H1 between the scan line 112 and the data line 111, as Figure 10 shown, assuming that the rising edge signal of the line scan signal causes the data signal to jump, since the widths of the anti-coupling line 122 and the scan line 112 are equal, the high-level signal of the clock pulse signal CLK needs to be less than the voltage of the line enable signal VGH. The absolute values of the first coupling voltage generated by the rising edge signal of the line scan signal and the second coupling voltage generated by the rising edge signal of the clock pulse signal CLK are equal, with opposite polarities, and the voltages cancel each other out, improving the display effect.

[0052] Alternatively, when the interlayer distance H2 between the anti-coupling line 122 and the connection line 121 is greater than the interlayer distance H1 between the scan line 112 and the data line 111, as Figure 10 shown, when the falling edge signal of the row scan signal causes the data signal to jump, since the widths of the anti-coupling line 122 and the scan line 112 are equal, the voltage of the low-level signal of the clock pulse signal CLK needs to be greater than the voltage of the row blanking signal VGL of the row scan signal. The absolute values of the first coupling voltage generated by the falling edge signal of the row scan signal and the second coupling voltage generated by the falling edge signal of the clock pulse signal CLK are equal, and the polarities are opposite, so the voltages cancel each other out, improving the display effect.

[0053] Embodiment Seven A second aspect of the embodiments of the present invention provides a display device, as Figure 11 shown, the display device includes a driving circuit 200 of the display panel and the display panel. The specific structure of the display panel refers to the above embodiments. Since the present display device adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one. Among them, the scan line 112, the connection line 121, and the anti-coupling line 122 of the display panel are connected to the driving circuit 200 of the display panel, and the driving circuit 200 of the display panel is used to output a row scan signal, a data signal, and a clock pulse signal CLK to the scan line 112, the data line 111, and the anti-coupling line 122 respectively.

[0054] In this embodiment, the driving circuit 200 of the display panel is used to output multiple paths of row scan signals and multiple paths of data signals to sequentially turn on the pixel units. The pixel units are correspondingly connected to a scan line 112 and a data line 111, and are turned on when receiving the row scan signal and receive the data signal to charge, and form a driving voltage with the common electrode layer on the color filter substrate to drive the liquid crystal to deflect, and cooperate with the color filter on the color filter substrate to display corresponding image information.

[0055] The driving circuit 200 of the display panel also outputs a correspondingly changing clock pulse signal CLK according to the row scan signal. The first coupling voltage generated by the first jump signal of the row scan signal and the second coupling voltage generated by the second jump signal of the clock pulse signal CLK cancel each other out, improving the display effect.

[0056] According to the signal output type, in an alternative embodiment, as Figure 12 shown, the driving circuit 200 of the display panel includes: A source driving circuit 220, connected to multiple connection lines 121, for outputting multiple paths of data signals according to the first control signal; A gate driving circuit 210, connected to multiple rows of scan lines 112, for sequentially outputting multiple paths of row scan signals according to the second control signal; A pulse output circuit 230 is connected to the anti-coupling line 122 and is configured to output a clock pulse signal CLK according to a third control signal. A timing controller 240 is respectively connected to the source driver circuit 220, the gate driver circuit 210, and the pulse output circuit 230, and is configured to output a first control signal, a second control signal, and a third control signal respectively.

[0057] In this embodiment, the timing controller 240 serves as a master controller and outputs a first control signal, a second control signal, and a third control signal respectively, so as to control the source driver circuit 220 to output multiple data signals to multiple connection lines 121, control the gate driver circuit 210 to output multiple row scanning signals to multiple scanning lines 112, and control the pulse output circuit 230 to output a clock pulse signal CLK to the anti-coupling line 122, and finally achieve that the first coupling voltage generated by the first jump signal of the row scanning signal and the second coupling voltage generated by the second jump signal of the clock pulse signal CLK cancel each other out, improving the display effect.

[0058] Among them, the pulse output circuit 230 can adopt structures such as a clock generator and a signal amplifier. To prevent electromagnetic interference, in an alternative embodiment, as Figure 13 shown, the pulse output circuit 230 includes a differential trace 231, a comparator U1, a first electronic switch tube M1, and a second electronic switch tube M2; The input end of the differential trace 231 is configured to input a differential signal. The differential trace 231 is respectively connected to the positive-phase input end and the anti-phase input end of the comparator U1. The output end of the comparator U1 is respectively connected to the control ends of the first electronic switch tube M1 and the second electronic switch tube M2. The first end of the first electronic switch tube M1 is configured to input a first voltage signal, the first end of the second electronic switch tube M2 is configured to input a second voltage signal, the second ends of the first electronic switch tube M1 and the second electronic switch tube M2 are connected to form the output end of the pulse output circuit 230, and the first voltage signal and the second voltage signal are alternately output to form the corresponding clock pulse signal CLK.

[0059] In this embodiment, the pulse output circuit 230 adopts a differential trace 231 to utilize the symmetry of the differential trace 231 to cancel electromagnetic radiation, improve electromagnetic interference and conduction. The timing controller 240 is configured to output a differential signal, as Figure 14As shown, the differential signal is an alternating positive voltage and negative voltage, such as 1V and -1V. The alternating differential signal is output to the comparator U1. A first resistor R1 is also connected between the positive input terminal and the negative input terminal of the comparator U1. The comparator U1 compares the voltage difference between the positive input terminal and the negative input terminal and outputs a comparison signal with high and low level changes. The comparison signal alternately controls the first electronic switch tube M1 and the second electronic switch tube M2 to conduct, and outputs a clock pulse signal CLK composed of an alternating first voltage signal and second voltage signal.

[0060] The first voltage signal and the second voltage signal can be output by corresponding amplifiers or signal sources. For example, as Figure 13 shown, the first voltage signal is output by the first inverting amplifier. The first inverting amplifier is composed of the first operational amplifier U2, the second resistor R2, and the third resistor R3. The second voltage signal is output by the second inverting amplifier. The second inverting amplifier is composed of the fourth resistor R4, the fifth resistor R5, and the second operational amplifier U3. For example, the first voltage signal is the negative value -VGH of the row start signal VGH, and the second voltage signal is the negative value -VGL of the row end signal VGL. The row start signal VGH is input to the inverting input terminal of the first operational amplifier U2, and the row end signal VGL is input to the inverting input terminal of the second operational amplifier U3. Through amplification by an inverting amplifier with an amplification factor of -1, -VGH and -VGL are output.

[0061] The above-described embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention and should all be included within the protection scope of the present invention.

Claims

1. A display panel, comprising an array substrate, characterized in that, The array substrate includes: A display area, which includes multiple columns of data lines and multiple rows of scan lines arranged in different layers, and pixel units corresponding to and connected to the data lines and the scan lines. The multiple rows of scan lines are used to input row scan signals row by row, and the multiple columns of data lines are used to input data signals respectively. The first transition signal of the row scan signal generates a first coupling voltage on the data lines. A non-display area, which includes multiple connection lines connecting the source driver circuit and the multiple columns of data lines. The connection lines are arranged in the same layer as the data lines and are used to transmit the data signals to the data lines. The non-display area further includes an anti-coupling line arranged in a different layer from the connection lines. The anti-coupling line is arranged parallel to the scan line and is used to input a clock pulse signal. Each second transition signal of the clock pulse signal is phase-aligned with the first transition signal of a row scan signal. The second transition signal generates a second coupling voltage on the connection line. The first coupling voltage and the second coupling voltage cancel each other out. The first transition signal and the second transition signal are corresponding ones of the rising edge signal and the falling edge signal.

2. The display panel according to claim 1, characterized in that The display area is symmetrically divided into a first display area and a second display area along a second direction. The first display area has a first refresh rate, and the second display area has a second refresh rate. Each scan line includes a separated first sub-scan line and a second sub-scan line. The multiple first sub-scan lines are located in the first display area and are used to input first row scan signals row by row. The multiple second sub-scan lines are located in the second display area and are used to input second row scan signals row by row. The anti-coupling line includes a first anti-coupling line and a second anti-coupling line. The first anti-coupling line is arranged parallel to the first sub-scan line, and the second anti-coupling line is arranged parallel to the second sub-scan line. The clock pulse signal includes a first clock pulse signal and a second clock pulse signal. The first anti-coupling line is used to input the first clock pulse signal, and the second anti-coupling line is used to input the second clock pulse signal. Each second transition signal of the first clock pulse signal is phase-aligned with the first transition signal of a first row scan signal, and each second transition signal of the second clock pulse signal is phase-aligned with the first transition signal of a second row scan signal.

3. The display panel according to claim 1 or 2, characterized in that, Along a first direction, the width of the corresponding scan line is equal to the width of the anti-coupling line arranged parallel to it. The first direction is the arrangement direction of the corresponding scan line.

4. The display panel according to claim 3, wherein The anti-coupling line is arranged in the same layer as the scan line. The voltage of the high level of the clock pulse signal is the negative value of the voltage of the row off signal of the row scan signal, and the voltage of the low level of the clock pulse signal is the negative value of the voltage of the row on signal of the row scan signal.

5. The display panel according to claim 3, characterized in that, The anti-coupling line is arranged in a different layer from the scan line and is located above or below the data lines at the same time. The interlayer distance between the anti-coupling line and the connection line is less than the interlayer distance between the scanning line and the data line, the negative voltage value of the low level of the clock pulse signal is less than the voltage of the line start signal of the line scanning signal, and the negative voltage value of the high level of the clock pulse signal is less than the voltage of the line start signal of the line scanning signal; Alternatively, the interlayer distance between the anti-coupling line and the connection line is greater than the interlayer distance between the scanning line and the data line, the negative voltage value of the low level of the clock pulse signal is greater than the voltage of the line start signal of the line scanning signal, and the negative voltage value of the high level of the clock pulse signal is greater than the voltage of the line start signal of the line scanning signal.

6. The display panel according to claim 3, wherein The anti-coupling line and the scanning line are arranged on different layers and symmetrically located above and below the data line; The voltage of the high level of the clock pulse signal is equal to the voltage of the line start signal of the line scanning signal, and the voltage of the low level of the clock pulse signal is equal to the line shutdown signal of the line scanning signal.

7. The display panel according to claim 3, characterized in that, The anti-coupling line and the scanning line are arranged on different layers and are respectively located above and below the data line; The interlayer distance between the scanning line and the data line is greater than the interlayer distance between the anti-coupling line and the connection line; The voltage of the high level of the clock pulse signal is less than the voltage of the line start signal of the line scanning signal, and the voltage of the low level of the clock pulse signal is less than the line shutdown signal of the line scanning signal; Alternatively, the interlayer distance between the scanning line and the data line is less than the interlayer distance between the anti-coupling line and the connection line; The voltage of the high level of the clock pulse signal is greater than the voltage of the line start signal of the line scanning signal, and the voltage of the low level of the clock pulse signal is greater than the line shutdown signal of the line scanning signal.

8. A display device, characterized in that, It includes a driving circuit of a display panel and the display panel according to any one of claims 1 to 7, wherein the scanning line, the connection line and the anti-coupling line of the display panel are connected to the driving circuit of the display panel, and the driving circuit of the display panel is configured to respectively output a line scanning signal, a data signal and a clock pulse signal to the scanning line, the data line and the anti-coupling line.

9. The display device according to claim 8, wherein The driving circuit of the display panel includes: A source driving circuit, connected to a plurality of the connection lines, for outputting a plurality of the data signals according to a first control signal; A gate driving circuit, connected to a plurality of rows of the scanning lines, for outputting a plurality of the line scanning signals row by row according to a second control signal; A pulse output circuit, connected to the anti-coupling line, for outputting the clock pulse signal according to a third control signal; A timing controller, respectively connected to the source driving circuit, the gate driving circuit and the pulse output circuit, for respectively outputting the first control signal, the second control signal and the third control signal.

10. The display device according to claim 9, characterized in that, The pulse output circuit includes differential traces, a comparator, a first electronic switch tube and a second electronic switch tube; The input end of the differential trace is used to input a differential signal. The differential trace is respectively connected to the positive-phase input end and the negative-phase input end of the comparator. The output end of the comparator is respectively connected to the control end of the first electronic switch tube and the control end of the second electronic switch tube. The first end of the first electronic switch tube is used to input a first voltage signal, and the first end of the second electronic switch tube is used to input a second voltage signal. The second end of the first electronic switch tube and the second end of the second electronic switch tube are connected to form the output end of the pulse output circuit. The first voltage signal and the second voltage signal are alternately output to form the clock pulse signal corresponding thereto.

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