Display device and control method of display device

Abstract

The invention provides a display device and a control method of the display device. The display device comprises a display panel and a driving circuit. The display panel comprises a plurality of pixel rows, a plurality of data line groups and a plurality of scanning line groups. The first data lines in each data line group are electrically connected with one column of first sub-pixels and are arranged close to the first sub-pixels in the corresponding column; the second data line in each data line group is electrically connected with the first data line through the switch module and is electrically connected with one column of second sub-pixels; the driving circuit is electrically connected with a plurality of scanning line groups in the display panel and first data lines in a plurality of data line groups, and the driving circuit is used for controlling the switch module to be switched off at a first moment in a blanking period of a current frame and increasing data voltage provided for the data line groups at a second moment in the blanking period of the current frame; the first moment is earlier than or equal to the second moment. By means of the display device, the problem of vertical stripes of an existing display panel of a U-Type pixel framework can be solved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display device and a control method thereof. Background Art

[0002] Currently, in order to reduce the cost of displays, a U-Type pixel architecture has been developed in the field of display technologies. The U-Type pixel architecture controls one row of pixels through two rows of scan lines, thus halving the number of data lines and doubling the number of scan lines. The additional scan lines can be implemented by designing a GOA (Gate Driven on Array) circuit on the side through a gate less mechanism, thereby saving the cost of the Source IC (source chip).

[0003] However, in practical applications, there are vertical stripe problems in the display panel with the U-Type pixel architecture. When the screen displays an image, the vertical stripes appear randomly or regularly, destroying the integrity of the picture, interfering with image details, making the color transition unnatural, and seriously affecting the display effect and user experience. Summary of the Invention

[0004] In view of this, the main purpose of this application is to propose a display device and a control method thereof, aiming to solve the vertical stripe problem of the display panel with the existing U-Type pixel architecture.

[0005] To achieve the above object, a first aspect of the present application provides a display device, the display device includes a display panel and a driving circuit; the display panel includes a plurality of pixel rows, a plurality of data line groups, and a plurality of scan line groups. The plurality of pixel rows are arranged in a column direction, each pixel row includes a plurality of sub-pixels arranged in a row direction, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel; each data line group includes a first data line, a second data line, and a switching module; wherein, the first data line in each data line group is electrically connected to a column of the first sub-pixels and is disposed close to the first sub-pixels in the corresponding column; the second data line in each data line group is electrically connected to the first data line through the switching module and is electrically connected to a column of the second sub-pixels; each scan line group includes a first scan line and a second scan line, the first scan line and the second scan line in each scan line group are spaced apart on one side of the corresponding pixel row, and the first scan line in each scan line group is located between the second scan line and the corresponding pixel row, the first scan line in each scan line group is electrically connected to all the first sub-pixels in the corresponding pixel row, the second scan line in each scan line group is electrically connected to all the second sub-pixels in the corresponding pixel row; the driving circuit is electrically connected to the plurality of scan line groups and the first data lines in the plurality of data line groups in the display panel respectively, and the driving circuit is configured to control the switching module to turn off at a first moment during the blanking period of the current frame, and to increase the data voltage provided to the data line group at a second moment during the blanking period of the current frame; wherein, the first moment is earlier than or equal to the second moment.

[0006] In the display device provided by the embodiment of the present application, by providing a switching module between the first data line and the corresponding second data line, and by the driving circuit controlling the switching module to turn off at a first moment during the blanking period of the current frame, and increasing the data voltage provided to the data line group at a second moment during the blanking period of the current frame, it can make the voltage jump generated by the pixel electrode in the first sub-pixel during the blanking period at least partially offset the voltage attenuation amount during the display period, thereby being able to reduce the difference between the voltage attenuation amount of the second sub-pixel and the voltage attenuation amount of the first sub-pixel, and further being able to improve the vertical stripe problem of the display panel with the existing U-Type pixel structure.

[0007] In some embodiments, the driving circuit is specifically configured to jump from providing a first data voltage Vdata1 to providing a second data voltage Vdata2 at a second moment during the blanking period of the current frame; wherein, the first data voltage Vdata1 is the data voltage provided by the driving circuit to the data line group at the last moment of the display period of the current frame, and the second data voltage Vdata2 is the sum of the first data voltage Vdata1 and a compensation voltage ΔV; wherein, the compensation voltage ΔV is positively correlated with ΔV1 - ΔV2, ΔV1 is the first voltage change amount of the first array common electrode in the first sub-pixel electrically connected to the data line group, the first voltage change amount is caused by the scanning signal in the first scanning line corresponding to the first array common electrode jumping from a high level to a low level, and ΔV2 is the second voltage change amount of the second array common electrode in the second sub-pixel electrically connected to the data line group, the second voltage change amount is caused by the scanning signal in the second scanning line corresponding to the second array common electrode jumping from a high level to a low level.

[0008] In some embodiments, the driving circuit further includes a first detection circuit, a second detection circuit, and a timing controller. The first detection circuit is electrically connected to the first array common electrode in one of the first sub-pixels, and is configured to receive the first actual common voltage of the first array common electrode and output a first detection voltage based on the first actual common voltage; wherein, during the process of the first actual common voltage decreasing caused by the scanning signal in the first scanning line corresponding to the first array common electrode jumping from a high level to a low level, the first detection voltage decreases following the decrease of the first actual common voltage; the second detection circuit is electrically connected to the second array common electrode in one of the second sub-pixels, and is configured to receive the second actual common voltage of the second array common electrode and output a second detection voltage based on the second actual common voltage; wherein, during the process of the second actual common voltage decreasing caused by the scanning signal in the second scanning line corresponding to the second array common electrode jumping from a high level to a low level, the second detection voltage decreases following the decrease of the second actual common voltage; the timing controller is electrically connected to both the first detection circuit and the second detection circuit, and is configured to obtain the first detection voltage from the first detection circuit, obtain the second detection voltage from the second detection circuit, and determine the compensation voltage ΔV according to the first detection voltage and the second detection voltage.

[0009] In some embodiments, the timing controller is configured to determine the voltage value of the compensation voltage ΔV according to the difference obtained by subtracting the first minimum voltage value from the second minimum voltage value; wherein, the first minimum voltage value is the minimum value of the first detection voltage, and the second minimum voltage value is the minimum value of the second detection voltage.

[0010] In some embodiments, the first voltage change amount is the difference obtained by subtracting the first minimum voltage value from the voltage value of the initial common voltage, and the second voltage change amount is the difference obtained by subtracting the second minimum voltage value from the voltage value of the initial common voltage.

[0011] In some embodiments, the first detection circuit includes: a first diode, a first switching transistor, and a first capacitor. The cathode of the first diode is electrically connected to the first array common electrode in one of the first sub-pixels; the first switching transistor includes a first connection end and a second connection end. The first connection end of the first switching transistor is used to receive the initial common voltage, and the second connection end of the first switching transistor is electrically connected to the anode of the first diode; the first end of the first capacitor is electrically connected to both the anode of the first diode and the timing controller, and the second end of the first capacitor is grounded; wherein, the first detection voltage output by the first detection circuit is the voltage at the first end of the first capacitor. During at least a part of the period when the scan signal in the corresponding first scan line is at a high level, the first switching transistor is turned on to charge the first capacitor, so that the first end of the first capacitor is charged to the initial common voltage; before the scan signal in the corresponding first scan line jumps from a high level to a low level, the first switching transistor is turned off, so that the first capacitor discharges to the first array common electrode through the first diode, so that the voltage value at the first end of the first capacitor discharges to the first minimum voltage value.

[0012] In some embodiments, the first detection circuit further includes: a first voltage follower and a first analog-to-digital conversion circuit. The input end of the first voltage follower is electrically connected to the anode of the first diode; the first analog-to-digital conversion circuit is electrically connected between the output end of the first voltage follower and the timing controller, and is used to receive the first detection voltage output by the first voltage follower, perform analog-to-digital conversion on the first detection voltage, and then output it to the timing controller.

[0013] In some embodiments, a first parasitic capacitor is formed between the first data line in each data line group and the corresponding column of the first sub-pixels. At the second moment during the blanking period of the current frame, when the data voltage in the first data line of the data line group jumps, under the coupling action of the first parasitic capacitor, a corresponding voltage jump occurs in the first pixel electrode of the first sub-pixel corresponding to the first data line in the data line group.

[0014] In some embodiments, the driving circuit is further configured to control the switch module to turn on at the start moment or before the start moment of the display period of the next frame after controlling the switch module to turn off.

[0015] The second aspect of the present application further provides a control method for a display device. The control method is used to control the display device described in the first aspect above for display. The control method includes: at a first moment in the blanking period of the current frame, controlling the switch module to turn off; and at a second moment in the blanking period of the current frame, increasing the data voltage provided to the data line group; wherein, the first moment is earlier than or equal to the second moment.

[0016] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. Brief Description of the Drawings

[0017] Figure 1 It is a schematic diagram of a display panel with a U-Type pixel architecture provided by an embodiment of the present application; Figure 2 For Figure 1 Partial wiring schematic diagram of the first pixel row in Figure 3 For Figure 1 Partial pixel circuit schematic diagram of the first pixel row in Figure 4 It is a schematic diagram of the structure of a display device provided by an embodiment of the present application; Figure 5 For Figure 4 Partial wiring schematic diagram of the first pixel row in Figure 6 For Figure 4 Partial pixel circuit schematic diagram of the first pixel row in Figure 7 For Figure 4 Drive signal timing diagram of the display device shown; Figure 8 It is a schematic diagram of the circuit structure of a drive circuit provided by an embodiment of the present application; Figure 9 It is a voltage waveform diagram of the first actual common voltage and the second actual common voltage provided by an embodiment of the present application; Figure 10 It is a timing diagram of the first control signal and the first detection voltage provided by an embodiment of the present application; Figure 11 It is a flowchart of a control method for a display device provided by an embodiment of the present application.

[0018] The description of the reference numerals is as follows: 100 - Display device; 10 - Display panel; 10' - Display panel; 20 - Driving circuit; 101 - Pixel row; 11 - Data line group; 12 - Scan line group; P1 - First sub - pixel; P2 - Second sub - pixel; 111 - First data line; 112 - Second data line; 121 - First scan line; 122 - Second scan line; TFT1 - First scan transistor; ACOM1 - First array common electrode; S - Source; D - Drain; G - Gate; Cgs1 - Second parasitic capacitance; Cgs2 - Third parasitic capacitance; CFCOM - Color filter common electrode; Clc1 - First liquid crystal capacitance; Clc2 - Second liquid crystal capacitance; Cst1 - First storage capacitance; Cst2 - Second storage capacitance; Cp1 - Fourth parasitic capacitance; Cp2 - Fifth parasitic capacitance; TFT2 - Second scan transistor; ACOM2 - Second array common electrode; T1 - Switch module; Cpd - First parasitic capacitance; 23 - Timing controller; 24 - Gate driver; 25 - Source driver; CLK - First clock signal; Gn - nth row scan signal; G2 - Second row scan signal; G1 - First row scan signal; Dm - Data voltage; ΔV - Compensation voltage; V_FB1 - First actual common voltage; V_FB2 - Second actual common voltage; V1 - First detection voltage; V10 - First minimum voltage value; V20 - Second minimum voltage value; 21 - First detection circuit; 22 - Second detection circuit; D1 - First diode; Q1 - First switch tube; C1 - First capacitor; ADC1 - First analog - to - digital conversion circuit; U1 - First voltage follower; D2 - Second diode; Q2 - Second switch tube; C2 - Second capacitor; U2 - Second voltage follower; ADC2 - Second analog - to - digital conversion circuit; Ctrl1 - First control signal; Ctrl2 - Second control signal; VACOM - Initial common voltage; ACOM - Common voltage source.

[0019] The following specific embodiments will further illustrate the present application in conjunction with the above - mentioned drawings. Specific embodiments

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0021] In addition, the terms "first", "second", etc. in the specification of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0022] It should be noted that, without conflict, the features in the embodiments of the present application can be combined with each other.

[0023] Please refer to Figure 1 , Figure 1 which is a schematic diagram of a display panel with a U-Type pixel architecture provided by an embodiment of the present application.

[0024] As Figure 1 shown, an existing display panel 10' with a U-Type pixel architecture includes a plurality of pixel rows 101, a plurality of data line groups 11, and a plurality of scan line groups 12.

[0025] Among them, the plurality of pixel rows 101 are arranged in the column direction, and each pixel row 101 includes a plurality of sub-pixels arranged in the row direction. The plurality of sub-pixels include a first sub-pixel P1 and a second sub-pixel P2. Exemplarily, as Figure 1 shown, the sub-pixels in columns 1 to 6 are the first sub-pixels P1, and the sub-pixels in columns 7 to 12 are the second sub-pixels P2.

[0026] Each data line group 11 includes a first data line 111 and a second data line 112. Each first data line 111 corresponds to a column of the first sub-pixels P1, and each second data line 112 corresponds to a column of the second sub-pixels P2. Among them, the first data line 111 in each data line group 11 is electrically connected to a column of the first sub-pixels P1 and is disposed close to the corresponding column of the first sub-pixels P1. The second data line 112 in each data line group 11 is electrically connected to the first data line 111 in this data line group 11, is electrically connected to a column of the second sub-pixels P2, and is disposed close to the corresponding column of the second sub-pixels P2.

[0027] Exemplarily, as Figure 1As shown, the data lines in the 1st to 6th columns are the first data lines 111, the data lines in the 7th to 12th columns are the second data lines 112. The data line in the 1st column and the data line in the 6th column form the 1st data line group 11, the data line in the 2nd column and the data line in the 7th column form the 2nd data line group 11, and so on.

[0028] Each scanning line group 12 includes a first scanning line 121 and a second scanning line 122, and each scanning line group 12 corresponds to a pixel row 101. The first scanning line 121 and the second scanning line 122 in each scanning line group 12 are arranged at intervals on one side of the corresponding pixel row 101, and the first scanning line 121 in each scanning line group 12 is located between the second scanning line 122 in this scanning line group 12 and the corresponding pixel row 101. Exemplarily, as Figure 1 shown, the scanning lines of odd rows are the first scanning lines 121, the scanning lines of even rows are the second scanning lines 122. The 1st to 2nd scanning lines form the 1st scanning line group 12, corresponding to the 1st pixel row 101. The 1st scanning line is located below the 1st pixel row 101, and the 2nd scanning line is located below the 1st scanning line, and so on.

[0029] It is not difficult to see that the U-Type pixel architecture controls one row of pixels through two rows of scanning lines, so that the number of data lines is halved and the number of scanning lines is doubled. The increased scanning lines can be implemented by designing a GOA circuit on the side through the gate less mechanism, thus saving the cost of the Source IC.

[0030] However, in practical applications, there is a vertical stripe problem in the display panel of the U-Type pixel architecture. Specifically, please refer to Figures 2 - 3 , Figure 2 for Figure 1 a partial wiring schematic diagram of the 1st pixel row in Figure 3 and Figure 1 a partial pixel circuit schematic diagram of the 1st pixel row in

[0031] As Figures 2 - 3As shown, the first sub-pixel P1 includes a first scanning transistor TFT1, a first pixel electrode (not labeled in the figure), and a first array common electrode ACOM1. The source S of the first scanning transistor TFT1 is electrically connected to the first pixel electrode. The drain D of the first scanning transistor TFT1 is electrically connected to the corresponding first data line 111. The gate G of the first scanning transistor TFT1 is electrically connected to the corresponding first scanning line 121. A second parasitic capacitance Cgs1 is formed between the source S of the first scanning transistor TFT1 and the corresponding first scanning line 121. A first liquid crystal capacitance Clc1 is formed between the source S of the first scanning transistor TFT1 and the color filter common electrode CFCOM. A first storage capacitance Cst1 is formed between the source S of the first scanning transistor TFT1 and the first array common electrode ACOM1. A fourth parasitic capacitance Cp1 is formed between the first array common electrode ACOM1 and the corresponding first scanning line 121.

[0032] Then, when the scanning of the first scanning line 121 corresponding to the first sub-pixel P1 ends, that is, when the scanning signal in the first scanning line 121 corresponding to the first sub-pixel P1 jumps from the high level VGH to the low level VGL, this voltage jump will be coupled to the source S of the first scanning transistor TFT1 through the second parasitic capacitance Cgs1 and the fourth parasitic capacitance Cp1, thereby causing a voltage attenuation at the source S of the first scanning transistor TFT1. Specifically, the voltage attenuation amount ΔVS1 at the source S of the first scanning transistor TFT1, the high level VGH, and the low level VGL satisfy the relational expression (1): (1) The second sub-pixel P2 includes a second scanning transistor TFT2, a second pixel electrode (not labeled in the figure), and a second array common electrode ACOM2. The source S of the second scanning transistor TFT2 is electrically connected to the second pixel electrode. The drain D of the second scanning transistor TFT2 is electrically connected to the corresponding second data line 112. The gate G of the second scanning transistor TFT2 is electrically connected to the corresponding second scanning line 122. A third parasitic capacitance Cgs2 is formed between the source S of the second scanning transistor TFT2 and the corresponding second scanning line 122. A second liquid crystal capacitance Clc2 is formed between the source S of the second scanning transistor TFT2 and the color filter common electrode CFCOM. A second storage capacitance Cst2 is formed between the source S of the second scanning transistor TFT2 and the second array common electrode ACOM2. A fifth parasitic capacitance Cp2 is formed between the corresponding second scanning line 122 and the corresponding first scanning line 121. Among them, since the first scanning line 121 corresponding to the second sub-pixel P2 is located between the source S of the second scanning transistor TFT2 and the second array common electrode ACOM2, the source S of the second scanning transistor TFT2 and the second array common electrode ACOM2 are isolated from each other, so there is no parasitic capacitance between the source S of the second scanning transistor TFT2 and the second array common electrode ACOM2.

[0033] Then, when the scanning of the second scanning line 122 corresponding to the second sub-pixel P2 ends, that is, when the scanning signal in the second scanning line 122 corresponding to the second sub-pixel P2 jumps from the high level VGH to the low level VGL, this voltage jump will be coupled to the source S of the second scanning transistor TFT2 through the third parasitic capacitance Cgs2, thereby causing the voltage attenuation of the source S of the second scanning transistor TFT2. Specifically, the voltage attenuation amount ΔVS2 of the source S of the second scanning transistor TFT2 and the high level VGH and the low level VGL satisfy the relational expression (2): (2) According to the relational expressions (1)-(2), it can be known that Cst1≈Cst2, Clc1≈Clc2, Cgs1≈Cgs2, and Cgs1 + Cst in the first sub-pixel P1 must be greater than Cgs2 in the second sub-pixel P2. Therefore, the voltage attenuation amount ΔVS2 of the pixel electrode in the second sub-pixel P2 will be significantly smaller than the voltage attenuation amount ΔVS1 of the pixel electrode in the first sub-pixel P1. This difference in voltage attenuation amount will cause the display panel 10' of the existing U-Type pixel architecture to have a vertical stripe phenomenon of alternating light and dark.

[0034] In view of this, an embodiment of the present application provides a display device 100. Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the display device provided by the embodiment of the present application.

[0035] As shown Figure 4 in the figure, the display device 100 includes a display panel 10 and a driving circuit 20. The display panel 10 includes a plurality of pixel rows 101, a plurality of data line groups 11, and a plurality of scan line groups 12.

[0036] Among them, the plurality of pixel rows 101 are arranged in the column direction, and each pixel row 101 includes a plurality of sub-pixels arranged in the row direction. The plurality of sub-pixels include a first sub-pixel P1 and a second sub-pixel P2.

[0037] In the column direction, the types of sub-pixels in each pixel column are the same, that is, the sub-pixels in any pixel column are either all the first sub-pixels P1 or all the second sub-pixels P2. Exemplarily, the sub-pixels in columns 2×x×b + 1 to (2×x + 1)×b are the first sub-pixels P1, and the sub-pixels in columns (2×x + 1)×b + 1 to (2×x + 2)×b are the second sub-pixels P2, where 0 ≤ x and 1 < b.

[0038] Each data line group 11 includes a first data line 111, a second data line 112, and a switch module T1. Each first data line 111 corresponds to a column of the first sub-pixels P1, and each second data line 112 corresponds to a column of the second sub-pixels P2. Among them, the first data line 111 in each data line group 11 is electrically connected to the first sub-pixels P1 in the corresponding column and is disposed close to the first sub-pixels P1 in the corresponding column. The second data line 112 in each data line group 11 is electrically connected to the first data line 111 in the same data line group 11 through the switch module T1 in this data line group 11, is electrically connected to the second sub-pixels P2 in the corresponding column, and is disposed close to the second sub-pixels P2 in the corresponding column.

[0039] Each scan line group 12 includes a first scan line 121 and a second scan line 122. Each scan line group 12 corresponds to a pixel row 101. The first scan line 121 and the second scan line 122 in each scan line group 12 are spaced apart on one side of the corresponding pixel row 101 in the column direction. In the column direction, the first scan line 121 in each scan line group 12 is located between the second scan line 122 in this scan line group 12 and the corresponding pixel row 101. The first scan line 121 in each scan line group 12 is electrically connected to all the first sub-pixels P1 in the corresponding pixel row 101, and the second scan line 122 in each scan line group 12 is electrically connected to all the second sub-pixels P2 in the corresponding pixel row 101.

[0040] Exemplarily, as Figure 4As shown, the odd-numbered scan lines are the first scan lines 121, and the even-numbered scan lines are the second scan lines 122. For example, the first and second scan lines form the first scan line group 12, corresponding to the first pixel row 101. The first scan line is electrically connected to all the first sub-pixels P1 in the first pixel row 101, and the second scan line is electrically connected to all the second sub-pixels P2 in the first pixel row 101, and so on.

[0041] The driving circuit 20 is electrically connected to the first scan lines 121 and the second scan lines 122 in the multiple scan line groups 12 and the first data lines 111 in the multiple data line groups 11 in the display panel 10 respectively. The driving circuit 20 is configured to control the switch module T1 to turn off at a first moment during the blanking period (Blanking Time) of the current frame, and to increase the data voltage provided to the data line groups 11 at a second moment during the blanking period of the current frame. Wherein, the first moment is earlier than or equal to the second moment.

[0042] In some embodiments of the present application, the driving circuit 20 controlling the switch module T1 to turn off may refer to controlling all the switch modules T1 to turn off. The driving circuit 20 increasing the data voltage provided to the data line groups 11 may refer to increasing the data voltage provided to all the data line groups 11.

[0043] Exemplarily, as Figure 4 shown, b = 6. Each data line group 11 includes two switch modules T1. Opposite ends of each second data line 112 are electrically connected to the corresponding first data line 111 through the corresponding two switch modules T1 respectively. During the display period of each frame, each switch module T1 is turned on. At this time, the second data lines 112 in the same data line group 11 are in parallel with the first data line 111. Thus, each second data line 112 can receive the data voltage output by the driving circuit 20 through the corresponding switch module T1 and the corresponding first data line 111, which can ensure that all the second sub-pixels P2 can receive the data voltage normally through the corresponding second data lines 112 during the display period of each frame. When each switch module T1 is turned off, the electrical connection between each second data line 112 and the corresponding first data line 111 will be disconnected, so that each second data line 112 cannot receive the data voltage output by the driving circuit 20.

[0044] Please refer to and Figures 5 - 6 , Figure 5 is Figure 4 a partial wiring schematic diagram of the first pixel row in Figure 6 is Figure 4 a partial pixel circuit schematic diagram of the first pixel row in

[0045] As Figures 5 - 6 shown, a first parasitic capacitance Cpd is formed between the first data line 111 in each data line group 11 and the corresponding first sub-pixel P1 in the column. At the second moment during the blanking period of the current frame, when the data voltage in the data line group 11 jumps, under the coupling effect of the first parasitic capacitance Cpd, a corresponding voltage jump occurs in the pixel electrode in the first sub-pixel P1 corresponding to the first data line 111 in the data line group 11. At this time, since the switching module T1 has been turned off, each second data line 112 no longer receives the data voltage output by the driving circuit 20. Thus, the voltage in each second data line 112 will not jump, and further, the pixel electrodes in each second sub-pixel P2 corresponding to each second data line 112 will not generate voltage jumps.

[0046] Specifically, the voltage jump amount ΔVS of the first pixel electrode in the first sub-pixel P1 and the voltage jump of the corresponding data line group 11 at the second moment (i.e., the compensation voltage ΔV in the following text) satisfy the relational expression (3): (3) wherein, Cgs1, Cst1, and Clc1 have been introduced in detail above and will not be elaborated here.

[0047] In this way, by using the coupling effect of the first parasitic capacitance Cpd between the first data line 111 and the corresponding first sub-pixel P1, the voltage jump amount ΔVS generated by the pixel electrode in the first sub-pixel P1 can at least partially offset the voltage attenuation amount ΔVS1 of the pixel electrode in the first sub-pixel P1, so as to be able to reduce the difference between ΔVS2 and ΔVS1, and further be able to improve the vertical stripe problem of the display panel 10' of the existing U-Type pixel architecture.

[0048] In some embodiments of the present application, the driving circuit 20 boosting the data voltage provided to the data line group 11 means instantaneously boosting the data voltage provided to the data line group 11, that is, the data voltage received by the data line group 11 rises step by step. It is not difficult to understand that the faster the rising rate of the data voltage received by the first data line 111, the stronger the coupling effect of the first parasitic capacitance Cpd, and thus the larger the voltage jump amount ΔVS of the pixel electrode in the first sub-pixel P1 corresponding to the first data line 111 in the data line group 11, and the more obvious the improvement effect on the vertical stripe problem.

[0049] The display device 100 provided by the embodiment of the present application can, by setting a switching module T1 between the first data line 111 and the corresponding second data line 112, and controlling the switching module T1 to turn off at a first moment during the blanking period of the current frame by the driving circuit 20, and boosting the data voltage supplied to the data line group 11 at a second moment during the blanking period of the current frame, make the voltage jump generated by the pixel electrode in the first sub-pixel P1 during the blanking period at least partially offset the voltage attenuation amount ΔVS1 during the display period, so as to be able to reduce the difference between the voltage attenuation amount ΔVS2 of the second sub-pixel P2 and the voltage attenuation amount ΔVS1 of the first sub-pixel P1, and further improve the vertical stripe problem of the display panel 10' of the existing U-Type pixel architecture.

[0050] As Figure 4 shown, the driving circuit 20 includes a timing controller (TCON) 23, a gate driver 24, and a source driver 25. The gate driver 24 is electrically connected to each of the first scan lines 121 and each of the second scan lines 122 respectively. The source driver 25 is electrically connected to each of the first data lines 111 respectively. The timing controller 23 is electrically connected to the gate driver 24 and the source driver 25 respectively.

[0051] During operation, the timing controller 23 is configured to receive an image signal representing image information from an external signal source, and provide various voltage signals for driving the source driver 25 and the gate driver 24 to operate based on the image signal, and then transmit the signals to each of the first sub-pixels P1 and each of the second sub-pixels P2 by the source driver 25 and the gate driver 24, so as to drive the display panel 10 to display. Specifically, the timing controller 23 is configured to provide a data timing signal to the source driver 25, so that the source driver 25 outputs corresponding data voltages to the corresponding column of first sub-pixels P1 through each of the first data lines 111, and outputs corresponding data voltages to the corresponding column of second sub-pixels P2 through each of the second data lines 112 based on the data timing signal. The timing controller 23 is further configured to output a clock signal, etc. to the gate driver 24, so that the gate driver 24 outputs corresponding scan signals to the first sub-pixels P1 in the corresponding pixel row 101 through each of the first scan lines 121, and outputs corresponding scan signals to the second sub-pixels P2 in the corresponding pixel row 101 through each of the second scan lines 122 based on the clock signal.

[0052] The gate driver 24 is also electrically connected to the control terminals of the respective switch modules T1, and is configured to output a first clock signal CLK to the control terminals of the respective switch modules T1 to control the conduction / turn-off of the respective switch modules T1. Specifically, the gate driver 24 is configured to control the respective switch modules T1 to turn off at a first moment during the blanking period (Blanking Time) of the current frame. In other embodiments, the on / off state of the switch module T1 may also be controlled by other modules (such as the timing controller 23) in the driving circuit 20.

[0053] The source driver 25 is further configured to boost the data voltage provided to each of the data line groups 11 at a second moment during the blanking period of the current frame.

[0054] In some embodiments of the present application, the driving circuit 20 is further configured to control the switch module T1 to conduct at the start time or before the start time of the display period of the next frame after controlling the switch module T1 to turn off.

[0055] Please refer to Figure 7 , Figure 7 For Figure 4 the driving signal timing diagram of the display device shown. As Figure 7 shown, in some embodiments of the present application, both the first moment and the second moment are the start time of the blanking period of the current frame, and the gate driver 24 is further configured to control the switch module T1 to conduct at the start time of the display period of each frame of the switch module T1.

[0056] Wherein, G1 represents the first row scan signal output by the driving circuit 20 to the first row scan line, G2 represents the second row scan signal output by the driving circuit 20 to the second row scan line, Gn represents the nth row scan signal output by the driving circuit 20 to the nth row scan line, and Dm represents the data voltage output by the driving circuit 20 to the mth column data line. Wherein, when the first clock signal CLK is at a high level, the switch module T1 conducts, and when the first clock signal CLK is at a low level, the switch module T1 turns off.

[0057] In some embodiments of the present application, the source driver 25 is specifically configured to maintain providing a first data voltage Vdata1 to the data line group 11 before the second moment during the blanking period of the current frame, and at the second moment, jump from providing the first data voltage Vdata1 to the data line group 11 to providing a second data voltage Vdata2 to the data line group 11.

[0058] Among them, the first data voltage Vdata1 is the data voltage provided by the driving circuit 20 to the data line group 11 at the last moment of the display period of the current frame. The second data voltage Vdata2 is the sum of the first data voltage Vdata1 and the compensation voltage ΔV, that is, Vdata2 = Vdata1 + ΔV.

[0059] It should be noted that the statement that the first data voltage Vdata1 is the data voltage provided by the driving circuit 20 to the data line group 11 at the last moment of the display period of the current frame means that the first data voltage Vdata1 of each data line group 11 is the data voltage provided by the driving circuit 20 to this data line group 11 at the last moment of the display period of the current frame. That is to say, for different data line groups 11, the voltage values of their first data voltages Vdata1 may not be equal, and correspondingly, their second data voltages Vdata2 may also not be equal.

[0060] Among them, the compensation voltage ΔV is positively correlated with ΔV1 - ΔV2. That is to say, the larger ΔV1 - ΔV2 is, the larger ΔV is; the smaller ΔV1 - ΔV2 is, the smaller ΔV is. Among them, ΔV1 is the first voltage change amount of the first array common electrode ACOM1 in the first sub-pixel P1 electrically connected to the data line group 11. The first voltage change amount is caused by the scanning signal in the first scanning line 121 corresponding to the first array common electrode ACOM1 jumping from a high level to a low level. ΔV2 is the second voltage change amount of the second array common electrode ACOM2 in the second sub-pixel P2 electrically connected to the data line group 11. The second voltage change amount is caused by the scanning signal in the second scanning line 122 corresponding to the second array common electrode ACOM2 jumping from a high level to a low level.

[0061] It should be noted that as Figure 6As shown, since a first storage capacitor Cst1 is formed between the source S of the first scanning transistor TFT1 and the first array common electrode ACOM1, when the scanning signal in the first scanning line 121 jumps from a high level VGH to a low level VGL, the voltage attenuation ΔVS1 of the source S of the first scanning transistor TFT1 will be coupled to the first array common electrode ACOM1 through the first storage capacitor Cst1, that is, the voltage attenuation ΔVS1 of the source S of the first scanning transistor TFT1 is proportional to the first voltage change ΔV1 of the first array common electrode ACOM1 in its corresponding first sub-pixel P1. Similarly, the voltage attenuation ΔVS2 of the source S of the second scanning transistor TFT2 is also proportional to the second voltage change ΔV2 of the second array common electrode ACOM2 in its corresponding second sub-pixel P2. Therefore, the difference between the second voltage change ΔV2 and the first voltage change ΔV1 can reflect the difference between ΔVS2 and ΔVS1.

[0062] Please refer to Figure 8 , Figure 8 which is a schematic circuit diagram of the driving circuit provided by the embodiment of the present application. In some embodiments of the present application, the driving circuit 20 further includes a first detection circuit 21 and a second detection circuit 22.

[0063] Among them, the first detection circuit 21 is electrically connected to the first array common electrode ACOM1 in one of the first sub-pixels P1. The first detection circuit 21 is configured to receive the first actual common voltage V_FB1 of the first array common electrode ACOM1 and output a first detection voltage V1 based on the first actual common voltage V_FB1. Among them, during the process that the scanning signal in the first scanning line 121 corresponding to the first array common electrode ACOM1 jumps from a high level to a low level, causing the first actual common voltage V_FB1 to drop, the first detection voltage V1 drops following the drop of the first actual common voltage V_FB1.

[0064] The second detection circuit 22 is electrically connected to the second array common electrode ACOM2 in one of the second sub-pixels P2. The second detection circuit 22 is configured to receive the second actual common voltage V_FB2 of the second array common electrode ACOM2 and output a second detection voltage V2 based on the second actual common voltage V_FB2. Among them, during the process that the scanning signal in the second scanning line 122 corresponding to the second array common electrode ACOM2 jumps from a high level to a low level, causing the second actual common voltage V_FB2 to drop, the second detection voltage V2 drops following the drop of the second actual common voltage V_FB2.

[0065] The timing controller 23 is also electrically connected to the first detection circuit 21 and the second detection circuit 22. The timing controller 23 is used to obtain the first detection voltage V1 from the first detection circuit 21, obtain the second detection voltage V2 from the second detection circuit 22, and determine the compensation voltage ΔV based on the first detection voltage V1 and the second detection voltage V2.

[0066] After determining the compensation voltage ΔV, the timing controller 23 is further used to add the first data voltage Vdata1 provided by the data line group 11 and the compensation voltage ΔV to obtain the second data voltage Vdata2, and control the source driver 25 to jump from providing the first data voltage Vdata1 to the data line group 11 to providing the second data voltage Vdata2 to the data line group 11.

[0067] In this way, the timing controller 23 can determine the compensation voltage ΔV by detecting the first actual common voltage V_FB1 of the first array common electrode ACOM1 and the second actual common voltage V_FB2 of the first array common electrode ACOM1, so as to accurately control the voltage change of the first data line 111 at the second moment, and enable the compensation voltage ΔV to match the difference between ΔVS2 and ΔVS1, thereby achieving better compensation effect and better display effect.

[0068] It should be noted that, in the same display panel, since the capacitance values of the parasitic capacitances, liquid crystal capacitances, and storage capacitances of different sub-pixels are approximately equal, the first voltage change ΔV1 and the second voltage change ΔV2 corresponding to different data line groups 11 are also approximately equal. Therefore, in some embodiments of the present application, the compensation voltages ΔV corresponding to different data line groups 11 can be equal. In this case, the compensation voltages ΔV corresponding to all data line groups 11 can be determined by detecting the first voltage change ΔV1 and the second voltage change ΔV2 corresponding to one data line group 11. This simplifies the circuit structure.

[0069] Of course, in some other embodiments, the compensation voltages ΔV corresponding to different data line groups 11 may also be unequal. In this case, it is necessary to separately provide the first detection circuit 21 and the second detection circuit 22 for different data line groups 11 to detect the corresponding first detection voltage V1 and second detection voltage V2. In this way, the compensation effect is better.

[0070] In some embodiments of the present application, the timing controller 23 is configured to determine the voltage value of the compensation voltage ΔV according to the difference obtained by subtracting the first minimum voltage value V10 from the second minimum voltage value V20. Wherein, the first minimum voltage value V10 is the minimum value of the first detection voltage V1, and the second minimum voltage value V20 is the minimum value of the second detection voltage V2.

[0071] Exemplarily, ΔV, V20, and V10 satisfy the relational expression (4): ΔV = K × (V20 - V10) (4) Wherein, K is a preset compensation coefficient, which can be determined through experiments.

[0072] Exemplarily, the timing controller 23 is configured to determine the difference obtained by subtracting the first minimum voltage value V10 from the second minimum voltage value V20 as the voltage value of the compensation voltage ΔV, that is, ΔV = V20 - V10.

[0073] Wherein, the first voltage change amount ΔV1 is the difference obtained by subtracting the first minimum voltage value V10 from the voltage value of the initial common voltage VACOM, that is, ΔV1 = VACOM - V10. The second voltage change amount ΔV2 is the difference obtained by subtracting the second minimum voltage value V20 from the voltage value of the initial common voltage VACOM, that is, ΔV2 = VACOM - V20.

[0074] In some embodiments of the present application, the first detection circuit 21 includes a first diode D1, a first switching transistor Q1, and a first capacitor C1.

[0075] Wherein, the cathode of the first diode D1 is electrically connected to the first array common electrode ACOM1 in one of the first sub-pixels P1.

[0076] The first switching transistor Q1 includes a first connection end and a second connection end. The first connection end of the first switching transistor Q1 is configured to receive the initial common voltage VACOM from the common voltage source ACOM, and the second connection end of the first switching transistor Q1 is electrically connected to the anode of the first diode D1.

[0077] The first end of the first capacitor C1 is electrically connected to the anode of the first diode D1 and the timing controller 23, and the second end of the first capacitor C1 is grounded.

[0078] Among them, the first detection voltage V1 output by the first detection circuit 21 is the voltage at the first end of the first capacitor C1. During at least a part of the period when the scan signal in the corresponding first scan line 121 (i.e., the first scan line 121 electrically connected to the first sub-pixel P1 electrically connected to the cathode of the first diode D1) is at a high level, the first switching transistor Q1 is turned on to charge the first capacitor C1 with the initial common voltage VACOM received at its first connection end, so as to charge the first end of the first capacitor C1 to the initial common voltage VACOM. Before the scan signal in the corresponding first scan line 121 jumps from a high level to a low level (including when jumping and before jumping), the first switching transistor Q1 is turned off, so that the first capacitor C1 discharges to the first array common electrode ACOM1 through the first diode D1, so that the voltage value at the first end of the first capacitor C1 discharges to the first minimum voltage value V10.

[0079] In some embodiments of the present application, the first detection circuit 21 further includes a first voltage follower U1 and a first analog-to-digital conversion circuit ADC1.

[0080] The input end of the first voltage follower U1 is electrically connected to the anode of the first diode D1.

[0081] The first analog-to-digital conversion circuit ADC1 is electrically connected between the output end of the first voltage follower U1 and the timing controller 23. The first analog-to-digital conversion circuit ADC1 is configured to receive the first detection voltage V1 output by the first voltage follower U1, perform analog-to-digital conversion on the first detection voltage V1, and then output it to the timing controller 23.

[0082] Among them, the first voltage follower U1 performs a transformation from a high input impedance to a low output impedance, and can provide a stable sampling signal for the first analog-to-digital conversion circuit ADC1.

[0083] In some embodiments of the present application, the circuit structure of the second detection circuit 22 is the same as that of the first detection circuit 21. Specifically, the second detection circuit 22 includes a second diode D2, a second switching transistor Q2, and a second capacitor C2.

[0084] Among them, the cathode of the second diode D2 is electrically connected to the second array common electrode ACOM2 in one of the second sub-pixels P2.

[0085] The second switching transistor Q2 includes a first connection end and a second connection end. The first connection end of the second switching transistor Q2 is used to receive the initial common voltage VACOM from the common voltage source ACOM, and the second connection end of the second switching transistor Q2 is electrically connected to the anode of the second diode D2.

[0086] The first end of the second capacitor C2 is electrically connected to the anode of the second diode D2 and the timing controller 23, and the second end of the second capacitor C2 is grounded.

[0087] Wherein, the second detection voltage V2 output by the second detection circuit 22 is the voltage at the first end of the second capacitor C2. During at least a part of the period when the scan signal in the corresponding second scan line 122 (i.e., the second scan line 122 electrically connected to the second sub-pixel P2 electrically connected to the cathode of the second diode D2) is at a high level, the second switch transistor Q2 is turned on to charge the second capacitor C2 by using the initial common voltage VACOM received at its first connection end, so as to charge the first end of the second capacitor C2 to the initial common voltage VACOM. When the scan signal in the corresponding second scan line 122 jumps from a high level to a low level, the second switch transistor Q2 is turned off, so that the second capacitor C2 discharges to the second array common electrode ACOM2 through the second diode D2, so that the voltage value at the first end of the second capacitor C2 discharges to the second lowest voltage value V20.

[0088] In some embodiments of the present application, the second detection circuit 22 further includes a second voltage follower U2 and a second analog-to-digital conversion circuit ADC2.

[0089] The input end of the second voltage follower U2 is electrically connected to the anode of the second diode D2.

[0090] The second analog-to-digital conversion circuit ADC2 is electrically connected between the output end of the second voltage follower U2 and the timing controller 23. The second analog-to-digital conversion circuit ADC2 is used to receive the second detection voltage V2 output by the second voltage follower U2, and perform analog-to-digital conversion on the second detection voltage V2 and then output it to the timing controller 23.

[0091] Wherein, the on-off state of the first switch transistor Q1 is controlled by a first control signal Ctrl1, and the on-off state of the second switch transistor Q2 is controlled by a second control signal Ctrl2. Wherein, the first control signal Ctrl1 and the second control signal Ctrl2 can both be output by the timing controller 23, or can be output by the gate driver 24.

[0092] In some embodiments, both the first switch transistor Q1 and the second switch transistor Q2 are PMOS transistors.

[0093] The following Figures 9 - 10 will introduce the working principles of the first detection circuit 21 and the second detection circuit 22 in detail. Figure 9Voltage waveform diagrams of the first actual common voltage and the second actual common voltage provided by the embodiments of the present application; Figure 10 Timing diagrams of the first control signal and the first detection voltage provided by the embodiments of the present application.

[0094] As Figure 9 shown, in the same scan line group 12, when the first scan line 121 jumps from a high level to a low level, affected by the level jump of the first scan line 121, the first actual common voltage V_FB1 of the first array common electrode ACOM1 in the first sub-pixel P1 of the pixel row 101 corresponding to the scan line group 12 will generate a corresponding jump. Specifically, it jumps from the initial common voltage VACOM to the first lowest voltage value V10 and then returns to the initial common voltage VACOM after a certain period of time; when the second scan line 122 jumps from a high level to a low level, affected by the level jump of the second scan line 122, the second actual common voltage V_FB2 of the second array common electrode ACOM2 in the second sub-pixel P2 of the pixel row 101 corresponding to the scan line group 12 will generate a corresponding jump. Specifically, it jumps from the initial common voltage VACOM to the second lowest voltage value V20 and then returns to the initial common voltage VACOM after a certain period of time. Obviously, the first lowest voltage value V10 is less than the second lowest voltage value V20, and the first voltage change amount ΔV1 of the first actual common voltage V_FB1 is greater than the second voltage change amount ΔV2 of the second actual common voltage V_FB2.

[0095] As Figure 10 shown, taking the first scan line group 12 as an example, the first detection circuit 21 is electrically connected to the first sub-pixel (the first sub-pixel P1) in the first pixel row 101, and the second detection circuit 22 is electrically connected to the seventh sub-pixel (the second sub-pixel P2) in the first pixel row 101.

[0096] During at least a part of the period when the scanning signal in the first row of scanning lines is at a high level, the first control signal Ctrl1 is pulled low to control the conduction of the first switching transistor Q1, so that the first end of the first capacitor C1 is charged to the initial common voltage VACOM, that is, the first detection voltage V1 is stabilized at the initial common voltage VACOM. When the scanning signal in the first row of scanning lines switches from a high level to a low level, the source S of the first scanning transistor TFT1 in the sub-pixels from the first column to the sixth column will have a voltage decay, and at the same time, the corresponding first array common electrode ACOM1 will have a voltage jump. At the same time, the first control signal Ctrl1 is pulled high to control the first switching transistor Q1 to turn off. At this time, along with the decrease of the first actual common voltage V_FB1 of the first array common electrode ACOM1, the first diode D1 is forward-biased and conducts, causing the charged first capacitor C1 to start discharging until the voltage at the first end of the first capacitor C1 drops to the first minimum voltage value V10 of the first actual common voltage V_FB1. After that, the first actual common voltage V_FB1 rises, and the second diode D2 is reverse cut-off, thereby clamping the voltage at the first end of the first capacitor C1 at the first minimum voltage value V10, that is, the first detection voltage V1 remains at the first minimum voltage value V10. In this way, the detection of the valley voltage data of the first actual common voltage V_FB1 can be realized, that is, the detection of the first voltage change amount ΔV1 of the first actual common voltage V_FB1 can be realized.

[0097] Similarly, when the scanning signal in the second row of scanning lines switches from a high level to a low level, the source S of the first scanning transistor TFT1 in the sub-pixels from the seventh column to the twelfth column will have a voltage decay, and the detection of the valley voltage data of the second actual common voltage V_FB2 can be realized by using the same circuit mechanism.

[0098] Please refer to Figure 11 , Figure 11 which is a flowchart of the control method for the display device provided by the embodiment of the present application. Based on the same concept, the embodiment of the present application also provides a control method for a display device. The control method is used to control the display device 100 as described in any of the above embodiments to perform display. The control method includes: Step S1, at a first moment in the blanking period of the current frame, control the switch module T1 to turn off.

[0099] Step S2, at a second moment in the blanking period of the current frame, increase the data voltage provided to the data line group 11.

[0100] Wherein, the first moment is earlier than or equal to the second moment.

[0101] It should be noted that the control method of the display device corresponds to the solution of the display device 100 in the foregoing text. For a more detailed description, reference can be made to the content of each embodiment of the foregoing display device 100, which will not be elaborated herein.

[0102] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A display device, the display device comprising a display panel and a driving circuit; characterized in that, The display panel includes: A plurality of pixel rows arranged in a column direction, each of the pixel rows including a plurality of sub-pixels arranged in a row direction, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel; A plurality of data line groups, each of the data line groups including a first data line, a second data line, and a switching module; wherein, the first data line in each of the data line groups is electrically connected to a column of the first sub-pixels and is disposed close to the corresponding column of the first sub-pixels; the second data line in each of the data line groups is electrically connected to the first data line through the switching module and is electrically connected to a column of the second sub-pixels; and A plurality of scan line groups, each of the scan line groups including a first scan line and a second scan line, the first scan line and the second scan line in each of the scan line groups being arranged at intervals on one side of the corresponding pixel row, and the first scan line in each of the scan line groups being located between the second scan line and the corresponding pixel row, the first scan line in each of the scan line groups being electrically connected to all the first sub-pixels in the corresponding pixel row, and the second scan line in each of the scan line groups being electrically connected to all the second sub-pixels in the corresponding pixel row; The driving circuit is electrically connected to the plurality of scan line groups and the first data lines in the plurality of data line groups in the display panel respectively, and the driving circuit is configured to control the switching module to turn off at a first moment during the blanking period of the current frame, and to increase the data voltage provided to the data line group at a second moment during the blanking period of the current frame; wherein, the first moment is earlier than or equal to the second moment.

2. The display device according to claim 1, wherein The driving circuit is specifically configured to jump from providing a first data voltage Vdata1 to providing a second data voltage Vdata2 at the second moment during the blanking period of the current frame; wherein, the first data voltage Vdata1 is the data voltage provided by the driving circuit to the data line group at the last moment of the display period of the current frame, and the second data voltage Vdata2 is the sum of the first data voltage Vdata1 and a compensation voltage ΔV; wherein, the compensation voltage ΔV is positively correlated with ΔV1 - ΔV2, ΔV1 is a first voltage change amount of a first array common electrode in the first sub-pixels electrically connected to the data line group, the first voltage change amount is caused by a scan signal in the first scan line corresponding to the first array common electrode jumping from a high level to a low level, and ΔV2 is a second voltage change amount of a second array common electrode in the second sub-pixels electrically connected to the data line group, the second voltage change amount is caused by a scan signal in the second scan line corresponding to the second array common electrode jumping from a high level to a low level.

3. The display device according to claim 2, characterized in that, The driving circuit further includes: A first detection circuit is electrically connected to a first array common electrode in one of the first sub-pixels, and is configured to receive a first actual common voltage of the first array common electrode and output a first detection voltage based on the first actual common voltage. Wherein, during the process that the scan signal in the first scan line corresponding to the first array common electrode jumps from a high level to a low level, causing the first actual common voltage to drop, the first detection voltage drops following the drop of the first actual common voltage. A second detection circuit is electrically connected to a second array common electrode in one of the second sub-pixels, and is configured to receive a second actual common voltage of the second array common electrode and output a second detection voltage based on the second actual common voltage. Wherein, during the process that the scan signal in the second scan line corresponding to the second array common electrode jumps from a high level to a low level, causing the second actual common voltage to drop, the second detection voltage drops following the drop of the second actual common voltage; and A timing controller is electrically connected to both the first detection circuit and the second detection circuit, and is configured to obtain the first detection voltage from the first detection circuit, obtain the second detection voltage from the second detection circuit, and determine a compensation voltage ΔV according to the first detection voltage and the second detection voltage.

4. The display device according to claim 3, wherein The timing controller is configured to determine the voltage value of the compensation voltage ΔV according to the difference obtained by subtracting the first minimum voltage value from the second minimum voltage value. Wherein, the first minimum voltage value is the minimum value of the first detection voltage, and the second minimum voltage value is the minimum value of the second detection voltage.

5. The display device according to claim 4, characterized in that, The first voltage change amount is the difference obtained by subtracting the first minimum voltage value from the voltage value of the initial common voltage, and the second voltage change amount is the difference obtained by subtracting the second minimum voltage value from the voltage value of the initial common voltage.

6. The display device according to claim 4, characterized in that, The first detection circuit includes: A first diode, the cathode of the first diode is electrically connected to a first array common electrode in one of the first sub-pixels; A first switching transistor, including a first connection end and a second connection end, the first connection end of the first switching transistor is configured to receive an initial common voltage, and the second connection end of the first switching transistor is electrically connected to the anode of the first diode; and A first capacitor, the first end of the first capacitor is electrically connected to both the anode of the first diode and the timing controller, and the second end of the first capacitor is grounded; Wherein, the first detection voltage output by the first detection circuit is the voltage of the first end of the first capacitor. During at least a part of the period when the scan signal in the corresponding first scan line is at a high level, the first switching transistor is turned on to charge the first capacitor, so that the first end of the first capacitor is charged to the initial common voltage; before the scan signal in the corresponding first scan line jumps from a high level to a low level, the first switching transistor is turned off, so that the first capacitor discharges to the first array common electrode through the first diode, so that the voltage value of the first end of the first capacitor discharges to the first minimum voltage value.

7. The display device according to claim 6, wherein, The first detection circuit further includes: A first voltage follower, the input end of the first voltage follower being electrically connected to the anode of the first diode; and A first analog-to-digital conversion circuit, electrically connected between the output end of the first voltage follower and the timing controller, for receiving the first detection voltage output by the first voltage follower, performing analog-to-digital conversion on the first detection voltage, and then outputting the result to the timing controller.

8. The display device according to claim 1, wherein A first parasitic capacitance is formed between the first data line in each data line group and the corresponding column of the first sub-pixels. At the second moment during the blanking period of the current frame, when the data voltage in the first data line of the data line group jumps, under the coupling action of the first parasitic capacitance, a corresponding voltage jump occurs in the first pixel electrode of the first sub-pixels corresponding to the first data line in the data line group.

9. The display device according to claim 3, wherein The driving circuit is further configured to control the switch module to turn on at the start moment or before the start moment of the display period of the next frame after controlling the switch module to turn off.

10. A control method for a display device, characterized in that, The control method is used to control the display device according to any one of claims 1 to 9 to perform display, and the control method includes: Controlling the switch module to turn off at the first moment during the blanking period of the current frame; and Boosting the data voltage provided to the data line group at the second moment during the blanking period of the current frame; wherein, the first moment is earlier than or equal to the second moment.

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