Battery charging and discharging system and battery discharging dynamic adjusting method
By dynamically adjusting the dead time of the battery charging and discharging system, the problem of insufficient current during low voltage discharge in the existing technology is solved, and an efficient battery charging and discharging process is achieved.
Patent Information
- Application Number
- CN202410111391.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-26
- Publication Date
- 2025-07-29
AI Technical Summary
Existing battery charging and discharging equipment fails to meet the expected high current standards when discharged at low voltage, resulting in low battery charging and discharging efficiency.
By designing a battery charging and discharging system, the dead time is dynamically adjusted by the processor and gate driver, the fixed or variable dead time is set according to the current feedback value, and the pulse width modulation signal is output to optimize the battery charging and discharging process.
The battery's high current output is realized in the low voltage range, improving the battery's charging and discharging efficiency.
Smart Images
Figure CN120389455A_ABST
Abstract
Description
Technical Field
[0001] This case relates to an electronic device and an adjustment method. Specifically, this case relates to a battery charge and discharge system and a method for dynamically adjusting battery discharge. Background Art
[0002] Existing battery charge and discharge devices are used to convert mains power or alternating current levels to charge the battery, and can also discharge the power of the battery to the mains through the battery charge and discharge device. However, with the evolution of technology, the redesign of the bidirectional boost / buck circuit of the battery charge and discharge device has instead caused the current of the battery during low-voltage discharge by the battery charge and discharge device to fail to reach the expected high-current standard.
[0003] Therefore, there are still many defects in the above technology, and it is necessary for practitioners in this field to develop other suitable battery charge and discharge systems. Summary of the Invention
[0004] One aspect of this case relates to a battery charge and discharge system. The battery charge and discharge system includes a charge and discharge circuit, a processor, and a gate driver. The charge and discharge circuit is used to discharge the battery according to a first pulse width modulation signal and a second pulse width modulation signal. The processor is coupled to the charge and discharge circuit and is used to detect the current of the charge and discharge circuit to obtain a feedback value according to the current. The processor is used to generate a duty cycle according to the feedback value and is used to determine whether the feedback value is less than a preset threshold to generate a comparison result. The processor is used to set the dead time to a fixed dead time duration or dynamically set it to a variable dead time duration according to the comparison result. The gate driver is coupled between the processor and the charge and discharge circuit and is used to output the first pulse width modulation signal and the second pulse width modulation signal to the charge and discharge circuit according to the dead time and the duty cycle.
[0005] In some embodiments, if the comparison result is that the feedback value is greater than or equal to the preset threshold, the gate driver is further used to output the first pulse width modulation signal and the second pulse width modulation signal according to the fixed dead time duration of the dead time and the duty cycle respectively.
[0006] In some embodiments, if the comparison result is that the feedback value is greater than or equal to the preset threshold, the processor subtracts the fixed dead time duration from the duty cycle to determine the duration of the first pulse width modulation signal at the second level, and subtracts the fixed dead time duration from the complement of the duty cycle to determine the duration of the second pulse width modulation signal at the second level.
[0007] In some embodiments, if the comparison result is that the feedback value is less than the preset threshold, the processor is further used to calculate the variable dead time duration according to the feedback value, and output the first pulse width modulation signal and the second pulse width modulation signal according to the variable dead time duration of the dead time and the duty cycle respectively.
[0008] In some embodiments, if the comparison result is that the feedback value is less than the preset threshold, the gate driver will subtract the variable dead time from the duty cycle to determine the duration for which the first pulse width modulation signal is at the second level.
[0009] In some embodiments, the ratio of the variable dead time of the dead time to the feedback value is less than 1.
[0010] In some embodiments, the charge and discharge circuit includes a first transistor and a second transistor. The first transistor is coupled to the battery and is used to conduct in response to the second level of the first pulse width modulation signal to form a loop. The second transistor is coupled to the first transistor and is used to turn off in response to the first level of the second pulse width modulation signal to form a loop.
[0011] In some embodiments, the processor includes a comparison circuit, a compensation circuit, and an adjustment circuit. The comparison circuit is coupled to the charge and discharge circuit and is used to detect the current and compare the current with a preset current to obtain a comparison value. The compensation circuit is coupled to the comparison circuit and is used to generate a feedback value and a duty cycle based on the comparison value. The adjustment circuit is coupled to the compensation circuit and is used to adjust the dead time to a fixed dead time and a variable dead time based on the feedback value.
[0012] Another aspect of the present case relates to a method for dynamically adjusting battery discharge. The method for dynamically adjusting battery discharge includes the following steps: discharging the battery through the charge and discharge circuit according to the first pulse width modulation signal and the second pulse width modulation signal. When both the first pulse width modulation signal and the second pulse width modulation signal are at the first level, the duration of the first level is the dead time; detecting the current of the charge and discharge circuit by the processor to obtain a feedback value and a duty cycle; judging by the processor whether the feedback value is less than the preset threshold to generate a comparison result; setting the dead time to a fixed dead time or dynamically setting it to a variable dead time by the processor according to the comparison result; and outputting the first pulse width modulation signal and the second pulse width modulation signal by the gate driver according to the dead time and the duty cycle.
[0013] In some embodiments, the step of setting the dead time to a fixed dead time duration or dynamically setting it to a variable dead time duration by a processor according to a comparison result, and thereby outputting a first pulse width modulation signal and a second pulse width modulation signal according to the dead time and the duty cycle, includes: if the comparison result is that the feedback value is greater than or equal to a preset threshold, outputting the first pulse width modulation signal and the second pulse width modulation signal respectively by a gate driver according to the fixed dead time duration of the dead time and the duty cycle; and if the comparison result is that the feedback value is less than the preset threshold, calculating a variable dead time duration by the gate driver according to the feedback value, and thereby outputting the first pulse width modulation signal and the second pulse width modulation signal respectively according to the variable dead time duration of the dead time and the duty cycle, wherein a ratio of the variable dead time duration of the dead time to the feedback value is less than 1.
[0014] In view of the foregoing disadvantages and deficiencies of the prior art, the present case provides a battery charging and discharging system and a method for dynamically adjusting battery discharge. Through the design of the battery charging and discharging system and the method for dynamically adjusting battery discharge, the battery can maintain a high current output when discharging in a low voltage range. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Referring to the embodiments in the following paragraphs and the following drawings, the content of the present case can be better understood:
[0016] Figure 1 A circuit block diagram of a battery charging and discharging system and a battery according to some embodiments of the present case;
[0017] Figure 2 A circuit diagram of a processor, a gate driver, a charging and discharging circuit, a battery, and an AC stage of a battery charging and discharging system according to some embodiments of the present case;
[0018] Figure 3 A circuit block diagram of a processor, a gate driver, and a charging and discharging circuit of a battery charging and discharging system according to some embodiments of the present case;
[0019] Figure 4 A diagram of the discharge voltage and current of a battery according to some embodiments of the present case;
[0020] Figures 5A to 5D A diagram of different duty cycles and different pulse width modulation signals according to some embodiments of the present case;
[0021] Figure 6 A diagram of a battery discharge curve according to some embodiments of the present case.
[0022]
SYMBOL DESCRIPTION
[0023] 100: Battery charging and discharging system
[0024] 110: Processor
[0025] 120: Gate driver
[0026] 130: Charge and discharge circuit
[0027] 111: Comparison circuit
[0028] 112: Compensation circuit
[0029] 113: Adjustment circuit
[0030] 131: Equivalent impedance circuit
[0031] L: Equivalent inductance
[0032] R: Equivalent resistance
[0033] T1 to T2: Transistor
[0034] 700: AC stage
[0035] 900: Battery
[0036] I1: Current
[0037] Ip: Preset current
[0038] 200: Method
[0039] 210 to 250: Steps
[0040] DI1 to DI2: Low voltage discharge interval
[0041] DUTY: Duty cycle
[0042] DT: Dead time
[0043] DTf: Fixed dead time duration
[0044] DTv: Variable dead time duration
[0045] CV: Feedback value
[0046] S1 to S2: Periods
[0047] L1 to L3: Curves
[0048] P1 to P7: Points
[0049] PWM1 to PWM2: Pulse width modulation signals
[0050] H: High level
[0051] L: Low level Detailed implementation manners
[0052] The spirit of the present case will be clearly illustrated below with the accompanying drawings and detailed description. After understanding the embodiments of the present case, any person with ordinary knowledge in the relevant technical field can make changes and modifications to the technology taught by the present case, which do not depart from the spirit and scope of the present case.
[0053] The terms used in this document are only for describing specific embodiments and are not intended to limit the present case. Singular forms such as "a", "this", "this", "the present", and "the", as used herein, also include plural forms.
[0054] Regarding the use of "including", "comprising", "having", "containing", etc. in this document, they are all open-ended terms, that is, they mean including but not limited to.
[0055] Regarding the terms used in this document, unless otherwise specified, they generally have their ordinary meanings in the relevant technical field, in the context of the present case, and in the specific context. Some terms used to describe the present case will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the present case.
[0056] Figure 1 FIG. 13 is a schematic circuit diagram of a battery charging and discharging system 100 and a battery 900 according to some embodiments of the present case. The battery charging and discharging system 100 can be applied to a DC / DC converter. The battery charging and discharging system 100 includes a processor 110, a gate driver 120, and a charging and discharging circuit 130. The processor 110 is electrically connected to the gate driver 120. The gate driver 120 is electrically connected to the charging and discharging circuit 130. The charging and discharging circuit 130 is electrically connected to the battery 900.
[0057] The processor 110 includes, but is not limited to, a single processor and the integration of multiple microprocessors. For example, a central processing unit (CPU) or a graphic processing unit (GPU), etc. The processor 110 is used to control the charging and discharging circuit 130 respectively according to the feedback of the battery 900 during charging and discharging in the charging and discharging circuit 130.
[0058] The gate driver 120 is used to process the original digital signal output by the processor 110 according to the built-in algorithm based on the overvoltage or overcurrent protection mechanism, so as to output a pulse width modulation signal to multiple transistors (not shown in the figure) in the charging and discharging circuit 130, thereby adjusting the charging and discharging of the battery 900. It should be noted that the processed pulse width modulation signal of the gate driver 120 is basically very similar to the original output signal output by the processor 110, and the difference between the two is only the time delay and the resistance-capacitance delay (RC Delay).
[0059] Next, see Figure 1 and Figure 2 , Figure 2 According to some embodiments of the present invention Figure 1 A circuit diagram of the battery charge-discharge system 100 includes a processor 110, a gate driver 120, a charge-discharge circuit 130, a battery 900, and an AC stage 700. The charge-discharge circuit 130 includes an equivalent impedance circuit 131, a transistor T1, and a transistor T2. The equivalent impedance circuit 131 includes an equivalent resistor R and an equivalent inductor L. The equivalent resistor R and the equivalent inductor L are connected in series. Transistor T1 is coupled to the equivalent impedance circuit 131 and the battery 900. Transistor T2 is coupled to transistor T1 and the equivalent impedance circuit 131.
[0060] In one embodiment, transistor T1 and transistor T2 are turned on or off based on pulse-width modulation signals PWM1 and PWM2 output by processor 110 and gate driver 120, respectively. In one embodiment, both transistor T1 and transistor T2 can be implemented using N-type metal-oxide-semiconductor field-effect transistors (NMOS). The types of transistors T1 and T2 can be adjusted based on actual needs and are not limited to the present embodiment.
[0061] In one embodiment, the AC stage 700 is an AC power supply or an AC / DC converter. In one embodiment, the battery 900 comprises a lithium battery pack or a lead-acid battery pack.
[0062] Furthermore, see Figure 1 and Figure 3 The processor 110 includes a comparison circuit 111, a compensation circuit 112, and an adjustment circuit 113. The comparison circuit 111 is electrically connected to the compensation circuit 112. The comparison circuit 111 is used to compare the current I1 of the charge and discharge circuit 130 according to the preset current Ip to obtain a comparison value between the two. The compensation circuit 112 is used to generate a feedback value CV and a duty cycle DUTY according to the comparison value of the comparison circuit 111. The adjustment circuit 113 is used to set the dead time DT to a fixed dead time duration or dynamically set it to a variable dead time duration according to the feedback value CV of the compensation circuit 112. In some embodiments, the current I1 is the instantaneous current of the charge and discharge circuit 130.
[0063] See also Figure 3 The gate driver 120 is used to generate a pulse width modulation signal PWM1 and a pulse width modulation signal PWM2 to the charge and discharge circuit 130 (ie, Figure 2(The transistors T1 and T2 in the charge and discharge circuit 130). It should be noted that the aforementioned dead time is a protection time set to prevent multiple transistors in the circuit from conducting simultaneously under high-frequency driving. The purpose of setting this dead time is to prevent component damage in the circuit caused by multiple transistors in the circuit conducting simultaneously.
[0064] To facilitate the understanding of the operation of the battery charge and discharge system 100 of this case, please refer to Figures 2 to 5A . Figure 4 It is a schematic diagram of the steps of the battery discharge dynamic adjustment method 200 illustrated according to some embodiments of this case. Figure 5A It is a schematic diagram of the pulse width modulation signals PWM1 and PWM2 generated when the duty cycle DUTY is 96% illustrated according to some embodiments of this case. The battery discharge dynamic adjustment method 200 can be implemented by Figure 1 the battery charge and discharge system 100. The battery discharge dynamic adjustment method 200 includes steps 210 to 240. Steps 210 to 240 will be described in the following paragraphs.
[0065] In step 210, please refer to Figure 2 and Figure 4 , the transistors T1 and T2 of the charge and discharge circuit 130 of the battery charge and discharge system 100 discharge the battery 900 according to the pulse width modulation signal PWM1 and the pulse width modulation signal PWM2.
[0066] In step 220, please refer to Figures 2 to 4 , the processor 110 of the battery charge and discharge system 100 continuously detects the current I1 of the charge and discharge circuit 130 to obtain the corresponding feedback value CV and duty cycle DUTY. For example, please refer to Figures 2 to 4 , Figure 5A , the comparison circuit 111 of the processor 110 compares the current I1 with the preset current Ip to obtain a comparison value. The compensation circuit 112 of the processor 110 calculates the feedback value CV based on the comparison value to be 6%. The comparison circuit 111 of the processor 110 calculates the duty cycle DUTY based on the 6% feedback value CV to be 96%.
[0067] In step 230, the adjustment circuit 113 of the processor 110 of the battery charge and discharge system 100 is used to continuously compare the feedback value CV with the preset threshold. The preset threshold is 4%. Please refer to Figures 2 to 4 , Figure 5A , the adjustment circuit 113 is used to compare whether the 6% feedback value CV is less than or equal to the 4% preset threshold to generate a comparison result.
[0068] In step 240, the processor 110 sets the dead time DT to a fixed dead time duration DTf according to the comparison result. Please refer to Figures 2 to 4 ,Figure 5A When the comparison result determined by the adjustment circuit 113 shows that the feedback value CV of 6% is greater than or equal to the preset threshold of 4%, the adjustment circuit 113 is used to set the dead time DT to a fixed dead time duration DTf, whose value is 2%.
[0069] In step 250, the gate driver 120 outputs the pulse width modulation signal PWM1 and the pulse width modulation signal PWM2 to the transistors T1 and T2 of the charge and discharge circuit 130 according to the dead time and the duty cycle. Please refer to Figures 2 to 4 、 Figure 5A , the dead time DT is the fixed dead time duration DTf, whose value is 2%. The processor 110 subtracts the fixed dead time duration DTf of 2% of the dead time DT from the duty cycle DUTY of 96% to determine the duration of 94% of the high level H of the output pulse width modulation signal PWM1. Due to the design of the fixed dead time duration DTf of the dead time DT, the duty cycle DUTY is directly proportional to the pulse width modulation signal PWM1, and the difference between the duty cycle DUTY and the pulse width modulation signal PWM1 is the fixed dead time duration DTf of the dead time DT. Then, the remaining duty cycle in the cycle S1 is 4%. The gate driver 120 subtracts the fixed dead time duration DTf of the dead time DT from the duty cycle DUTY of 96% and the complement of 2% to determine the duration of the high level H of the output pulse width modulation signal PWM2 as 2%. The gate driver 120 generates waveforms to the charge and discharge circuit 130 according to the pulse width modulation signal PWM1 and the pulse width modulation signal PWM2 output by the processor 110.
[0070] It should be noted that when both the pulse width modulation signal PWM1 and the pulse width modulation signal PWM2 are at the low level L, the duration of the low level L is the dead time DT. The transistor T1 of the charge and discharge circuit 130 conducts in response to the high level H of the pulse width modulation signal PWM1 to form a loop for discharging the battery 900. At the same time, the transistor T2 of the charge and discharge circuit 130 turns off in response to the low level L of the pulse width modulation signal PWM2 to form a loop for discharging the battery 900. As Figure 2 shown, the above loop starts from the battery 900, passes through the transistor T1, and returns to the battery 900 through the equivalent impedance circuit 131.
[0071] When the above Figure 5A duty cycle DUTY needs to be increased according to the feedback value CV of the current I1 of the charge and discharge circuit 130, please refer to Figure 5B . Figure 5B FIG. is a schematic diagram showing the pulse width modulation signals PWM1 and PWM2 generated when the duty cycle DUTY is 98% according to some embodiments of the present case. Please refer to Figure 2 and Figure 4 、Figure 5B The processor 110 re-executes the above steps 210 to 250 according to the situation of the current I1 of the charge and discharge circuit 130. The comparison circuit 111 of the processor 110 compares the current I1 with a preset current Ip to obtain a comparison value. The compensation circuit 112 of the processor 110 calculates a feedback value CV of 4% according to the comparison value. The comparison circuit 111 of the processor 110 outputs a duty cycle DUTY of 98% according to the feedback value CV of 4%.
[0072] Next, the adjustment circuit 113 is used to compare whether the feedback value CV of 4% is less than or equal to a preset threshold of 4% to generate a comparison result. When the comparison result determined by the adjustment circuit 113 is that the feedback value CV of 4% is greater than or equal to the preset threshold of 4%, the adjustment circuit 113 is used to set the dead time DT to a fixed dead time duration DTf, and its value is 2%. The dead time DT is the fixed dead time duration DTf, and its value is 2%. The processor 110 determines the duration of the high level H of the pulse width modulation signal PWM1 to be output by subtracting the fixed dead time duration DTf of the 2% dead time DT from the 98% duty cycle DUTY. Due to the design of the fixed dead time duration DTf of the dead time DT, the duty cycle DUTY is proportional to the pulse width modulation signal PWM1, and the difference between the duty cycle DUTY and the pulse width modulation signal PWM1 is the fixed dead time duration DTf of the dead time DT. Next, the remaining duty cycle in the period S1 is 2%. The processor 110 determines the duration of the high level H of the pulse width modulation signal PWM2 to be output to be 0% according to the complement of the 96% duty cycle DUTY and the fixed dead time duration DTf of the 2% dead time DT. The gate driver 120 generates waveforms to the charge and discharge circuit 130 according to the pulse width modulation signal PWM1 and the pulse width modulation signal PWM2 output by the processor 110.
[0073] The transistor T1 of the charge and discharge circuit 130 is partially turned on in response to the high level H of the pulse width modulation signal PWM1 in the period S1 or the period S2 to form a loop. At the same time, the transistor T2 of the charge and discharge circuit 130 is completely turned off in response to the pulse width modulation signal PWM2 to form a loop.
[0074] Please refer to this case again Figure 5A and Figure 5B, after the bidirectional boost / buck circuit of the existing battery charging and discharging device is redesigned, the reason why the battery charging and discharging device cannot achieve the expected high current standard when the battery discharges at a low voltage is the design of the fixed dead time DTf of the dead time DT, which causes the transistor T1 in the charge and discharge circuit 130 to not be fully turned on according to the pulse width modulation signal PWM1 in one cycle S1 or cycle S2. That is to say, even if the transistor T2 is fully turned off according to the pulse width modulation signal PWM2, the transistor T1 cannot be fully turned on in one cycle S1 or cycle S2 due to the fixed dead time DTf of the dead time DT (i.e., it cannot reach 100% conduction time), resulting in the battery 900 not achieving the optimal charging and discharging speed. The following content of this case will describe how to improve the above problems.
[0075] When the above Figure 5B duty cycle DUTY needs to be further increased according to the feedback value CV of the current I1 of the charge and discharge circuit 130, please refer to Figure 5C . Figure 5C FIG. is a schematic diagram of the pulse width modulation signals PWM1 and PWM2 generated when the duty cycle DUTY is 99% according to some embodiments of this case. Please refer to Figure 2 and Figure 4 , Figure 5C , the processor 110 re-executes the above steps 210 to 250 according to the situation of the current I1 of the charge and discharge circuit 130. The comparison circuit 111 of the processor 110 compares the current I1 with the preset current Ip to obtain a comparison value. The compensation circuit 112 of the processor 110 calculates the feedback value CV based on the comparison value to be 2%. The comparison circuit 111 of the processor 110 outputs a duty cycle DUTY of 99% based on the 2% feedback value CV.
[0076] Next, the adjustment circuit 113 is used to compare whether the 2% feedback value CV is less than or equal to the preset threshold of 4% to generate a comparison result. When the comparison result determined by the adjustment circuit 113 is that the 2% feedback value CV is less than the preset threshold of 4%, the adjustment circuit 113 is used to dynamically set the dead time DT to a variable dead time DTV, whose value is an arbitrary ratio of the 2% feedback value CV. For example, the variable dead time DTV can also be designed to be one-half of the feedback value CV, that is, 1%. For example, the variable dead time DTV can also be designed to be one-third of the feedback value CV, that is, 0.66%. In some embodiments, the ratio of the variable dead time DTV of the dead time DT to the feedback value CV is less than 1. It should be noted that the relationship between the variable dead time DTV of the dead time DT and the feedback value CV can be designed according to actual needs and is not limited to the embodiments of this case.
[0077] Furthermore, the processor 110 determines that the duration of the high level H of the output pulse width modulation signal PWM1 is 98% based on a variable dead time DTv that subtracts 1% dead time DT from a 99% duty cycle DUTY. Compared with Figure 5B the fixed dead time duration DTf of the dead time DT, Figure 5C the variable dead time duration DTV of the dead time DT reduces the gap between the duty cycle DUTY and the pulse width modulation signal PWM1. Then, the remaining duty cycle in cycle S1 is 1%. The processor 110 determines that the duration of the high level H of the output pulse width modulation signal PWM2 is 0% based on a 99% duty cycle DUTY and a variable dead time duration DTV of 1% dead time DT. The gate driver 120 generates waveforms to the charge and discharge circuit 130 according to the pulse width modulation signal PWM1 and the pulse width modulation signal PWM2 output by the processor 110.
[0078] Please refer again to Figure 2 and Figure 5C , in this case, the variable dead time duration DTV of the dead time DT is adjusted to enable the transistor T1 of the charge and discharge circuit 130 to be in a state close to full conduction in one cycle S1 or S2. Therefore, the conduction loop formed by the conduction of the transistor T1 allows the battery 900 to discharge quickly and the current I1 during discharge to be close to the target current value. In some embodiments, the target current value is 100 amperes (A).
[0079] When the above Figure 5C duty cycle DUTY needs to be further increased according to the feedback value CV of the current I1 of the charge and discharge circuit 130, please refer to Figure 5D . Figure 5D FIGURES are schematic diagrams of the pulse width modulation signals PWM1 and PWM2 generated when the duty cycle DUTY is 100% according to some embodiments of this case. Please refer to Figure 2 and Figure 4 , Figure 5D , the processor 110 re-executes the above steps 210 to 250 according to the situation of the current I1 of the charge and discharge circuit 130. The comparison circuit 111 of the processor 110 compares the current I1 with a preset current Ip to obtain a comparison value. The compensation circuit 112 of the processor 110 calculates a feedback value CV of 0% based on the comparison value. The comparison circuit 111 of the processor 110 outputs a duty cycle DUTY of 100% based on the feedback value CV of 0%.
[0080] Next, the adjustment circuit 113 is used to compare whether the feedback value CV of 0% is less than or equal to the preset threshold of 4% to generate a comparison result. When the comparison result determined by the adjustment circuit 113 is that the feedback value CV of 0% is less than the preset threshold of 4%, the adjustment circuit 113 is used to dynamically set the dead time DT to a variable dead time duration DTv, which is half of the feedback value CV of 0%, that is, 0%.
[0081] Furthermore, the processor 110 subtracts the variable dead time duration DTv of the dead time DT of 0% from the duty cycle DUTY of 100% to determine that the duration of the high level H of the output pulse width modulation signal PWM1 is 100%. Compared with Figure 5C the variable dead time duration DTv of the dead time DT, Figure 5D the variable dead time duration DTv of the dead time DT eliminates the gap between the duty cycle DUTY and the pulse width modulation signal PWM1. Next, the remaining duty cycle in the period S1 is 0%. The processor 110 determines that the duration of the high level H of the output pulse width modulation signal PWM2 is 0% according to the duty cycle DUTY of 100% and the variable dead time duration DTv of the dead time DT of 0%. The gate driver 120 generates waveforms to the charge and discharge circuit 130 according to the pulse width modulation signal PWM1 and the pulse width modulation signal PWM2 output by the processor 110.
[0082] Please refer to Figure 2 and Figure 5D again. In this case, the variable dead time duration DTv of the dead time DT is dynamically set to make the transistor T1 of the charge and discharge circuit 130 fully conduct in one period S1 or S2. Therefore, the conduction loop formed by the conduction of the transistor T1 enables the battery 900 to discharge quickly and the current I1 during discharge to be close to the target current value. In some embodiments, the target current value is 100 amperes (A).
[0083] It should be noted that all the numerical values in the foregoing embodiments are only examples, and the present invention is not limited thereto. Those of ordinary skill in the art should understand that various modifications and applications can be made without departing from the necessary features of the aspect. For example, any numerical values (such as the feedback value, the preset threshold, the ratio of the variable dead time duration to the duty cycle, etc.) described in detail in the above aspect can be modified. In addition, the differences related to these modifications and applications should be construed as being covered by the scope of the present invention defined by the following claims for patent.
[0084] Finally, the embodiments of the present case are summarized in the following table. Figures 5A to 5D as follows.
[0085] Table 1.
[0086]
[0087] In addition, the driving of the transistor T1 and the transistor T2 in the charge and discharge circuit 130 described above must satisfy the following relational expressions.
[0088] Equation 1: PWM1 + PWM2 + 2DT = 1.
[0089] PWM1 in Equation 1 corresponds to the above-mentioned pulse width modulation signal PWM1. PWM2 in Equation 1 corresponds to the above-mentioned pulse width modulation signal PWM2. DT in Equation 1 corresponds to the dead time DT in Table 1 above.
[0090] In this case, by dynamically setting the variable dead time duration DTv of the dead time DT, the gap between the duty cycle DUTY and the pulse width modulation signal PWM1 is reduced or even eliminated, thereby enabling the battery 900 to charge and discharge quickly and the current I1 during discharge to approach the target current value.
[0091] Figure 6 It includes curves L1 to L3. Curve L1 is the discharge curve of the existing battery charge and discharge device for the battery 900. The existing battery charge and discharge device is the battery charge and discharge device after the bidirectional boost / buck circuit is redesigned and without introducing the design of this case. Battery charge and discharge device. Curve L2 is the discharge specification curve of the battery charge and discharge device for the battery 900. Curve L3 is the discharge curve of the battery charge and discharge system 100 for the battery 900. In some embodiments, please refer to Figure 2 and Figure 6 , through the design of adjusting the dead time duration of the dead time DT (such as the fixed dead time duration DTf or the variable dead time duration DTv) in this case, the battery 900 can output close to a constant current (such as 100 A) in the low-voltage discharge interval DI1. In the low-voltage discharge interval DI2, since the discharge voltage of the battery 900 cannot continue to maintain a high-current output, the current I1 linearly decreases in proportion to the discharge voltage of the battery 900.
[0092] According to the foregoing embodiments, this case provides a battery charge and discharge system and a method for dynamically adjusting battery discharge. Through the design of the battery charge and discharge system and the method for dynamically adjusting battery discharge, the battery can maintain a high-current output when discharging in the low-voltage interval.
[0093] Although this case is disclosed in detail with the above embodiments, this case does not exclude other feasible implementation aspects. Therefore, the protection scope of this case shall be subject to what is defined by the attached patent application scope, rather than being limited by the foregoing embodiments.
[0094] For those skilled in the art, without departing from the spirit and scope of this case, various modifications and retouches can be made to this case. Based on the foregoing embodiments, all modifications and retouches made to this case are also covered by the protection scope of this case.
Claims
1. A battery charge and discharge system, characterized in that Comprising: A charge and discharge circuit for discharging a battery according to a first pulse width modulation signal and a second pulse width modulation signal, wherein when the first pulse width modulation signal and the second pulse width modulation signal are both at a first level, the duration is a dead time; A processor coupled to the charge and discharge circuit and configured to detect a current of the charge and discharge circuit to obtain a feedback value according to the current, wherein the processor is configured to generate a duty cycle according to the feedback value and to determine whether the feedback value is less than a preset threshold to generate a comparison result, and the processor is configured to set the dead time to a fixed dead time duration or dynamically set it to a variable dead time duration according to the comparison result; And A gate driver coupled between the processor and the charge and discharge circuit and configured to output the first pulse width modulation signal and the second pulse width modulation signal to the charge and discharge circuit according to the dead time and the duty cycle.
2. The battery charging and discharging system according to claim 1, wherein If the comparison result is that the feedback value is greater than or equal to the preset threshold, the gate driver is further configured to output the first pulse width modulation signal and the second pulse width modulation signal according to the fixed dead time duration of the dead time and the duty cycle respectively.
3. The battery charging and discharging system according to claim 1, wherein If the comparison result is that the feedback value is greater than or equal to the preset threshold, the processor subtracts the fixed dead time duration from the duty cycle to determine the duration when the first pulse width modulation signal is at a second level, and subtracts the fixed dead time duration from the complement of the duty cycle to determine the duration when the second pulse width modulation signal is at the second level.
4. The battery charging and discharging system according to claim 1, characterized in that, If the comparison result is that the feedback value is less than the preset threshold, the processor is further configured to calculate the variable dead time duration according to the feedback value, and to output the first pulse width modulation signal and the second pulse width modulation signal according to the variable dead time duration of the dead time and the duty cycle respectively.
5. The battery charge and discharge system according to claim 4, wherein If the comparison result is that the feedback value is less than the preset threshold, the gate driver subtracts the variable dead time duration from the duty cycle to determine the duration when the first pulse width modulation signal is at a second level.
6. The battery charging and discharging system according to claim 5, characterized in that, The ratio of the variable dead time duration of the dead time to the feedback value is less than 1.
7. The battery charging and discharging system according to claim 1, characterized in that, The charge and discharge circuit comprises: A first transistor coupled to the battery and configured to conduct in response to a second level of the first pulse width modulation signal to form a loop; and A second transistor coupled to the first transistor and configured to turn off in response to the first level of the second pulse width modulation signal to form the loop.
8. The battery charging and discharging system according to claim 1, wherein The processor comprises: A comparison circuit coupled to the charge and discharge circuit and configured to detect the current and to compare the current with a preset current to obtain a comparison value; A compensation circuit coupled to the comparison circuit and configured to generate the feedback value and the duty cycle according to the comparison value; and An adjustment circuit coupled to the compensation circuit and configured to adjust the dead time to the fixed dead time duration and the variable dead time duration according to the feedback value.
9. A method for dynamically adjusting battery discharge, characterized in that, Comprising: A charging and discharging circuit discharges a battery according to a first pulse width modulation signal and a second pulse width modulation signal, wherein when both the first pulse width modulation signal and the second pulse width modulation signal are at a first level, the duration of the first level is a dead time; A processor detects a current of the charging and discharging circuit to obtain a feedback value and a duty cycle; The processor determines whether the feedback value is less than a preset threshold to generate a comparison result; The processor sets the dead time to a fixed dead time duration or dynamically sets it to a variable dead time duration according to the comparison result; And A gate driver outputs the first pulse width modulation signal and the second pulse width modulation signal according to the dead time and the duty cycle.
10. The battery discharge dynamic adjustment method according to claim 9, characterized in that, The step of the processor setting the dead time to the fixed dead time duration or dynamically setting it to the variable dead time duration according to the comparison result, and thereby outputting the first pulse width modulation signal and the second pulse width modulation signal according to the dead time and the duty cycle includes: If the comparison result is that the feedback value is greater than or equal to the preset threshold, the gate driver outputs the first pulse width modulation signal and the second pulse width modulation signal respectively according to the fixed dead time duration of the dead time and the duty cycle; And If the comparison result is that the feedback value is less than the preset threshold, the gate driver calculates the variable dead time duration according to the feedback value, and thereby outputs the first pulse width modulation signal and the second pulse width modulation signal respectively according to the variable dead time duration of the dead time and the duty cycle, wherein the ratio of the variable dead time duration of the dead time to the feedback value is less than 1.