Capacitive battery equalization circuit and equalization method

Abstract

The invention relates to the technical field of battery equalization, and provides a capacitive battery equalization circuit, which uses a bus-type switched capacitor to replace a magnetic element in a traditional battery equalization circuit, so that the magnetic element is not needed in the circuit, the cost for constructing the battery equalization circuit is remarkably reduced, and meanwhile, the technical difficulty for realizing the battery equalization circuit is reduced. Meanwhile, due to the adoption of the bus type switched capacitor, the influence on the equalization time caused by different initial voltage values of the battery cells in each battery unit is reduced, and the influence that the equalization time is obviously prolonged when the number of the battery units in the battery unit group is increased is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of batteries, and particularly to a capacitive battery equalization circuit and a battery equalization method. Background Art

[0002] During the manufacturing and use of battery cells, due to differences in parameters such as self-discharge rate, internal resistance, and temperature, it is difficult to maintain the consistency among battery cells. This inconsistency will lead to a decline in the overall performance of the battery pack and shorten its service life. To solve the above problems, battery equalization technology improves the consistency of battery cells by adjusting the energy distribution among the cells in the battery pack, thereby increasing the effective capacity and service life of the series-connected battery pack.

[0003] Existing battery equalization technologies are mainly divided into two categories: passive equalization and active equalization. Passive equalization dissipates the excess energy in high-energy cells in the form of heat by connecting a discharge resistor in parallel outside the single-cell battery until its energy level is equal to that of the low-energy cells. In contrast, active equalization technology transfers the electrical energy of high-energy battery cells to low-energy battery cells through an additional equalization circuit, which has higher energy utilization efficiency and faster equalization speed, and is suitable for application scenarios that require fast response and high power.

[0004] According to the type of equalization circuit used in the energy transfer process, active equalization can be further divided into inductive type, transformer type, and capacitive type. The capacitive equalization circuit shows the advantages of low cost and simple control because it does not need to use bulky magnetic components. However, the equalization speed of the traditional switched-capacitor equalization circuit is closely related to the degree of voltage imbalance of the battery pack at the initial stage, and as the number of energy storage units increases, the equalization time increases exponentially. Summary of the Invention

[0005] The present application provides a capacitive battery equalization circuit that uses a bus-type switched-capacitor energy storage unit, overcoming the problems of high cost and complex control caused by the use of magnetic components in inductive and transformer-type battery equalization circuits, and at the same time solving the problem of too long equalization time in traditional switched-capacitor equalization circuits.

[0006] The capacitive battery equalization circuit provided by the embodiments of the present application includes a battery pack composed of n series-connected battery cells, where n is an integer greater than 2, a data acquisition unit, and a micro-control unit;

[0007] It further includes a bus-type switched-capacitor energy storage unit, and the bus-type switched-capacitor energy storage unit includes a first switch group composed of n MOS (metal-oxide-semiconductor field effect transistor) tubes, a second switch group composed of n MOS tubes, and n - 1 energy storage capacitors.

[0008] The drain of the first MOS transistor S1 of the first switch group is connected to the positive electrode of the first battery cell B1, and the drain of the i-th MOS transistor S i of the first switch group is respectively connected to the negative electrode of the (i - 1)-th battery cell B i－1 and the positive electrode of the i-th battery cell B i , where i ∈ [2, n];

[0009] The source of the k-th MOS transistor Q k of the second switch group is respectively connected to the negative electrode of the k-th battery cell B k and the positive electrode of the (k + 1)-th battery cell B k+1 , where k ∈ [1, n - 1]; The source of the n-th MOS transistor Q n of the second switch group is connected to the negative electrode of the n-th battery cell B n ;

[0010] The first end of the m-th energy storage capacitor C m is respectively connected to the source of the m-th MOS transistor S m of the first switch group and the drain of the m-th MOS transistor Q m of the second switch group. The second ends of all the energy storage capacitors are connected to each other, where m ∈ [1, n - 1];

[0011] The source of the n-th MOS transistor S n of the first switch group is connected to the drain of the n-th MOS transistor Q n of the second switch group and is connected to the second ends of all the energy storage capacitors;

[0012] The input end of the data acquisition unit is connected to the battery pack for collecting data of the battery pack, and the output end is connected to the input end of the micro control unit. The output end of the micro control unit is respectively connected to the gates of the MOS transistors in the first switch group and the second switch group. The micro control unit is used to output complementary PMW (Pulse - Width Modulation) pulse signals with a duty cycle of 50%.

[0013] The capacitive battery equalization circuit provided by the present application provides a bus - type switched - capacitor energy storage unit to replace the traditional LC energy storage unit or transformer energy storage unit, so that magnetic components are no longer required in the circuit, significantly reducing the cost of constructing the battery equalization circuit and the technical difficulty of its implementation. At the same time, due to the adoption of the bus - type switched - capacitor, the influence of different initial voltage values of the battery cells in each battery unit on the equalization time is reduced, and the influence of the significant increase in the equalization time when the number of battery cells in the battery unit group is increased is solved.

[0014] Preferably, the capacitance of the energy storage capacitor is from 30 uF to 100 uF, and the frequency of the complementary PWM pulse signal is from 15 kHz to 100 kHz;

[0015] Preferably, the capacitance of the energy storage capacitor is 50 uF, and the frequency of the PWM pulse signal is 19 kHz.

[0016] The embodiment of the present application also provides a battery equalization method based on a capacitive battery equalization circuit, including the above capacitive battery equalization circuit, and comprising the following steps:

[0017] S10. Collect the voltage values and current values of the battery cells in the battery pack through the data acquisition unit, and send the collected data to the micro control unit;

[0018] S20. The micro control unit detects the voltage values and current values in real time, and when the voltage values and / or current values meet the first preset threshold, generates a pair of complementary PMW pulse signals with a duty cycle of 50%, and outputs them to the first switch group and the second switch group;

[0019] S30. Charging step: Each MOS tube in the first switch group is turned on, each MOS tube in the second switch group is turned off, each battery cell is connected to the energy bus formed by each capacitor, and the current flows out from any battery cell to charge each energy storage capacitor;

[0020] S40. Discharging step: Each MOS tube in the first switch group is turned off, each MOS tube in the second switch group is turned on, each energy storage capacitor releases energy, and any battery cell with a lower voltage starts to receive energy, realizing the charge transfer from the high-energy battery cell to the low-energy battery cell;

[0021] S50. When the micro control unit detects that the voltage values and / or current values meet the second preset threshold, stop generating the pulse control signal.

[0022] The battery equalization method based on the capacitive battery equalization circuit provided by the embodiment of the present application controls the capacitive battery equalization circuit to achieve the equalization among the battery cells through charge and discharge, so that the battery cells maintain consistency, improve the performance of the entire battery pack, and ensure the service life of the battery pack.

[0023] The embodiment of the present application also provides a capacitive battery equalization circuit module, including two of the above capacitive battery equalization circuits and a connection capacitor. The first end of the connection capacitor is connected to the negative electrode of the nth battery cell B in the first capacitive battery equalization circuit and grounded; the second end is connected to the negative electrode of the nth battery cell B in the second capacitive battery equalization circuit. n and is grounded; the second end is connected to the negative electrode of the nth battery cell B in the second capacitive battery equalization circuit. n of the negative electrode.

[0024] The capacitive battery equalization circuit module provided by the embodiment of the present application connects two battery equalization circuits using bus-type switched capacitors and can achieve equalization among battery cells in the entire equalization circuit module, expanding the capacity of the battery pack. However, the overall battery equalization time is not significantly increased, improving the efficiency of battery equalization.

[0025] Preferably, the capacitance of the connecting capacitor is 50 uF. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1A 、 Figure 1B 、 Figure 1C are the simulation waveform diagrams of the chain switch circuit, double-layer switched capacitor, and bus-type switched capacitor equalization;

[0028] Figure 2 is the structural schematic diagram of the capacitive battery equalization circuit of the present application;

[0029] Figure 3 is the schematic diagram showing the influence of frequency change on the equalization time;

[0030] Figure 4 is the schematic diagram showing the influence of capacitance change on the equalization time;

[0031] Figure 5 is the schematic diagram of the relationship between frequency, capacitance, and equalization time;

[0032] Figure 6 is the schematic diagram showing the charging state and discharging state of the capacitive battery equalization circuit of the present application with two batteries as an example;

[0033] Figure 7 is the driving signal waveform diagram;

[0034] Figure 8 is the equalization current and voltage waveform diagram of two batteries;

[0035] Figure 9 is the simulation current and voltage waveform diagram;

[0036] Figure 10 is the equalization curve diagram of six battery cells;

[0037] Figure 11 is the equalization curve diagram of ten battery cells;

[0038] Figure 12 Schematic diagram of the modular structure of the balancing circuit;

[0039] Figure 13 For Figure 12 The simulation balance curve graph of the modular structure of the balancing circuit in Specific implementation manners

[0040] In the following, only some exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive.

[0041] It should be noted that terms such as "first", "second", "symmetric", "array", etc. are only used for the purpose of distinguishing descriptions and position descriptions, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "symmetric", etc. may explicitly or implicitly include one or more of such features; similarly, when certain features are not limited in quantity by words such as "two", "three", etc., it should be noted that such features also belong to explicitly or implicitly including one or more feature quantities;

[0042] In the present invention, unless otherwise clearly defined and limited, terms such as "installed", "connected", "fixed", etc. should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or integrally formed; it can be a mechanical connection, directly connected, welded, or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the accompanying drawings of the specification in combination with the specific situation.

[0043] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] The prior art provides battery balancing circuits based on inductive type, LC type, and transformer type. These battery balancing circuits are relatively large in volume and high in cost because they use bulky magnetic components. At the same time, the control is relatively complex. For example, in the LC type battery balancing circuit, at low frequencies, LC resonates, generating a ringing sound, which affects the loss of the circuit; when the number of battery packs increases, the resonance frequency of the LC circuit is significantly affected by the parasitic parameters of the inductor L and temperature, resulting in poor frequency stability and requiring complex calculations to obtain.

[0045] The prior art also provides a switched-capacitor type battery equalization circuit. However, the equalization speed of the traditional switched-capacitor equalization circuit is closely related to the degree of imbalance of the initial voltage of the battery pack, and as the number of energy storage units increases, the equalization time increases exponentially.

[0046] Based on the problems existing in the existing inductor-type and transformer-type battery equalization circuits, the inventors determined the direction of using a capacitor-type battery equalization. And a variety of capacitor-switch battery equalization circuits were studied and compared, such as Figures 1A to 1C shown, where in the figure, a is a chain switched-capacitor equalization circuit, b is a double-layer switched-capacitor equalization circuit, and c is a bus switched-capacitor equalization circuit. As Figure 1A 、 Figure 1B and Figure 1C shown, when the chain switched-capacitor has 6 battery cells, 8 battery cells, and 10 battery cells in the battery pack, its equalization times are 2.124 s, 3.49 s, and 4.841 s respectively. As the number of battery cells increases, its equalization time increases by more than 1 s; the equalization time of the double-layer switched-capacitor equalization circuit is 3.376 s, 5.763 s, and 9.024 s, and its equalization time changes most significantly. Moreover, as the number of battery cells increases, its equalization time increases significantly; while the equalization time of the bus switched-capacitor equalization circuit is 3.75 s, 4.13 s, and 4.36 s, its equalization change range is not large, and there is a trend that as the number of battery cells continues to increase, the change range of its equalization time will become smaller.

[0047] Based on the above findings from the research on the existing switched-capacitor equalization circuits, the inventors designed the capacitive battery equalization circuit of the present application. As Figure 2 shown, it includes a battery pack composed of n battery cells connected in series, where n is an integer greater than 2, a data acquisition unit, and a microcontroller unit (MCU);

[0048] It further includes a bus-type switched-capacitor energy storage unit, and the bus-type switched-capacitor energy storage unit includes a first switch group composed of n MOS transistors, a second switch group composed of n MOS transistors, and n - 1 energy storage capacitors,

[0049] The drain of the first MOS transistor S1 of the first switch group is connected to the positive electrode of the first battery cell B1, and the drain of the i-th MOS transistor S i of the first switch group is respectively connected to the negative electrode of the (i - 1)-th battery cell B i－1 and the positive electrode of the i-th battery cell B i , where i ∈ [2, n];

[0050] The source of the k-th MOS transistor Q k of the second switch group is respectively connected to the negative electrode of the k-th battery cell B k and the positive electrode of the (k + 1)-th battery cell B k+1is connected to the positive electrode, where k ∈ [1, n - 1]; the source electrode of the n-th MOS transistor Q of the second switch group n is connected to the n-th battery cell B n is connected to the negative electrode;

[0051] The first end of the m-th energy storage capacitor C m is respectively connected to the source electrode of the m-th MOS transistor S of the first switch group m and the drain electrode of the m-th MOS transistor Q of the second switch group m All the second ends of the energy storage capacitors are connected to each other, where m ∈ [1, n - 1];

[0052] The source electrode of the n-th MOS transistor S of the first switch group n is connected to the drain electrode of the n-th MOS transistor Q of the second switch group n and is connected to the second ends of all the energy storage capacitors;

[0053] The input end of the data acquisition unit is connected to the battery pack for acquiring data of the battery pack, and the output end is connected to the input end of the micro control unit. The output end of the micro control unit is respectively connected to the gate electrodes of the MOS transistors in the first switch group and the second switch group. The micro control unit is used to output a complementary PMW pulse signal with a duty cycle of 50%.

[0054] Among them, the data acquisition unit includes an AFE (Analog Front - End) chip for acquiring, conditioning and converting the analog signals generated by the battery pack. Its core task is to convert voltage, current, temperature, etc. into high-precision digital signals and send them to the micro control unit for processing and analysis. The micro control unit starts the equalization of the battery pack according to the preset conditions.

[0055] Based on the above capacitive battery equalization circuit, the inventor further studied the energy storage capacitors and the frequency of the PWM pulse signal. Taking a battery pack composed of 6 battery cells as an example, using a 0.1F farad capacitor to replace the battery, selecting a capacitor with a capacity of 10uF, and increasing the frequency of the PWM pulse signal from 10kHz to 100kHz, as Figure 3 shown, its equalization time starts to decrease rapidly in the low frequency band. Around 40kHz, with the increase of the frequency, the reduction of the equalization time is very limited; at the same time, selecting a PWM pulse signal frequency of 25kHz and changing the capacity of the energy storage capacitor, the capacity increases from 10uF to 100uF, as Figure 4 shown, its equalization time also shows that with the increase of the capacitor capacity, the equalization time decreases, and after reaching 40uF, the reduction of the equalization time brought by the increase of the capacity is very limited.

[0056] Then, the inventor further studied the frequency of the PWM pulse signal and the capacitance of the energy storage capacitor, and obtained the influence of the signal frequency and capacitance on the battery equalization time, as Figure 5 shown. The specific data is shown in Table 1:

[0057]

[0058] Table 1

[0059] When the frequency is 10 kHz, with a capacitance value of 10 μF, the equalization time of the equalization circuit reaches the maximum value, approaching 5 seconds, indicating that under the condition of a small capacitor, the energy transfer efficiency is low. In the range of 10 μF to 50 μF, as the capacitance value increases, the equalization time decreases rapidly. When the capacitance value exceeds 50 μF, the decreasing amplitude of the equalization time gradually becomes smaller, and further increasing the capacitance has limited improvement on the equalization time. When the capacitance value is fixed, the equalization time is relatively long between 10 kHz and 40 kHz. After the frequency is increased to 40 kHz, the equalization time decreases rapidly. When the frequency increases from 50 kHz to 100 kHz, the equalization time still decreases, but the change amplitude is relatively small, indicating that the high-frequency signal has a small influence on the equalization time.

[0060] In the embodiments of the present application, the capacitance of the energy storage capacitor is 30 μF to 100 μF, and the frequency of the complementary PWM pulse signal is 15 kHz to 100 kHz; specifically, the capacitance of the energy storage capacitor is 50 μF, and the frequency of the PWM pulse signal is 19 kHz. The capacitance and frequency have a non-linear influence on the performance of the equalization circuit. A large capacitor reduces the equalization time, but increases the circuit board area and system cost. An excessively high frequency brings an increase in switching losses and electromagnetic interference. Therefore, a comprehensive trade-off should be made between performance and losses in the design. When selecting the frequency and capacitance combination, issues such as system energy loss are also considered in addition to the equalization time. Although the equalization time of some combinations is shorter, at high frequencies or large capacitance values, the system switching losses increase, which cannot be ignored in the actual long-term operation of the capacitor equalization type equalization topology. After weighing, the combination of 19 kHz and 50 μF achieves a better balance among multiple key indicators such as equalization time, system stability, and energy loss, and is more in line with our expectations for the overall performance and actual application requirements.

[0061] For the capacitive battery equalization circuit provided by the embodiments of the present application, its battery equalization control method is as follows:

[0062] S10. Collect the voltage values and current values of each battery cell in the battery pack through the data acquisition unit, and send the collected data to the micro control unit;

[0063] S20. The microcontroller unit (MCU) continuously detects the voltage value and current value, and when the voltage value and / or current value meets a first preset threshold, generates a pair of complementary PMW pulse signals with a duty cycle of 50%, and outputs them to the first switch group and the second switch group;

[0064] S30. Charging step: Each MOS transistor in the first switch group is turned on, each MOS transistor in the second switch group is turned off, each battery cell is connected to the energy bus formed by each capacitor, and current flows out from any battery cell to charge each energy storage capacitor;

[0065] S40. Discharging step: Each MOS transistor in the first switch group is turned off, each MOS transistor in the second switch group is turned on, each energy storage capacitor releases energy, and any battery cell with a lower voltage starts to receive energy, realizing the charge transfer from a high-energy battery cell to a low-energy battery cell;

[0066] S50. When the MCU detects that the voltage value and / or current value meets a second preset threshold, it stops generating the pulse control signal.

[0067] Taking the dual-battery equalization circuit as an example, its structure is as Figure 6 shown. Without considering the dead time of the drive signal, the equalization process of the circuit includes two working states, corresponding to Mode 1 and Mode 2 respectively, as Figure 7 is the waveform of the drive signal. Mode 1 is as shown in (a) of Figure 6 , the S switch group is turned on, the Q switch group is closed, and current flows from the battery with a higher battery voltage into the equalizer energy storage. Mode 2 is as shown in (b) of Figure 6 , the S switch group is closed, the Q switch group is turned on, and the stored energy is released from the equalizer to the battery with a lower voltage to realize charge transfer. When the equalization state has not reached equilibrium, the two modes work alternately. The waveforms of the dual-battery equalization current and voltage of the experimental prototype are as Figure 8 shown, Figure 9 is the simulated current and voltage waveforms.

[0068] Embodiment 1

[0069] Figure 10 is the equalization curve of six battery cells. The simulation software is Matlab Simulink, and the simulation parameters of the circuit are: the working frequency is 19 kHz, the equalization capacitance is 50 μF, and a 100 mΩ resistor is set for each energy storage unit as the loop parasitic resistance; a 0.7 F supercapacitor is used to replace the battery, and its initial voltages are V B1 = 3.8 V, V B2 = 3.7 V, V B3 = 3.6 V, V B4 = 3.5 V, V B5 = 3.4 V, V B6= 3.3V, and the maximum initial pressure difference is 0.5V. Although the initial voltages of each battery are different, as the equalization time increases, the voltages of the six batteries in the battery pack gradually approach and finally reach the equalized state, and the equalization time is 3.75s. The experimental results show that the present invention can achieve equalization between any battery unit and any other battery unit, and the equalization speed is fast.

[0070] Embodiment 2

[0071] Figure 11 is the simulation waveform of the capacitive battery equalization circuit for a battery pack composed of ten battery units. The simulation parameters are the same as those in Embodiment 1, and the initial voltages are V B1 = 3.8V, V B2 = 3.7V, V B3 = 3.6V, V B4 = 3.5V, V B5 = 3.4V, V B6 = 3.3V, V B7 = 3.2V, V B8 = 3.1V, V B9 = 3.0V, V B10 = 2.9V, and the maximum pressure difference is 0.9V. After 4.357s, the voltages of all battery units converge to around 3.3V simultaneously. The increase in the number of batteries has little effect on the equalization speed of the bus-based capacitive equalization circuit. The circuit has excellent scalability and robustness. After equalization, the pressure differences between the batteries are small and the voltages tend to be consistent.

[0072] Based on the above capacitive battery equalization circuit, the present application provides an extended and optimized implementation scheme for it. The preferred embodiment of the present application provides a capacitive battery equalization circuit module, including the above capacitive battery equalization circuit and a connection capacitor. The first end of the connection capacitor is connected to the negative electrode of the nth battery unit B in the first capacitive battery equalization circuit n and grounded; the second end is connected to the negative electrode of the nth battery unit B in the second capacitive battery equalization circuit n . Among them, the capacitance of the connection capacitor is preferably 50uF.

[0073] Figure 12 shows the modular structure of the equalization circuit of the present invention. A capacitive battery equalization circuit composed of six battery units forms a module, and a total of two modules are included. Figure 13 is its simulation equalization curve. Analysis shows that by simply adding a capacitor energy storage module without an additional outer equalization circuit, automatic equalization between different battery packs can be achieved, reducing the complexity and cost of the system, making the energy distribution between different battery packs more accurate, and helping to extend the overall service life of the series-connected battery pack. At the same time, the equalization time is 4.52s, and the equalization time does not increase significantly.

[0074] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various changes or substitutions, and these should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described above.

Claims

1. A capacitive battery equalization circuit, comprising a battery pack composed of n battery cells connected in series, where n is an integer greater than 2, a data acquisition unit, and a microcontrol unit; characterized in that, it further comprises a bus-type switched-capacitor energy storage unit, and the bus-type switched-capacitor energy storage unit includes a first switch group composed of n MOS transistors, a second switch group composed of n MOS transistors, and n - 1 energy storage capacitors, The drain of the first MOS transistor S1 of the first switch group is connected to the positive electrode of the first battery unit B1, and the drain of the i-th MOS transistor S i of the first switch group is respectively connected to the negative electrode of the (i - 1)-th battery unit B i－1 and the positive electrode of the i-th battery unit B i , where i ∈ [2, n]; The source electrodes of the k-th MOS transistor Q k in the second switch group are respectively connected to the negative electrode of the k-th battery cell B k and the positive electrode of the (k + 1)-th battery cell B k+1 , where k ∈ [1, n - 1]; the source electrode of the n-th MOS transistor Q n in the second switch group is connected to the negative electrode of the n-th battery cell B n . The m-th energy storage capacitor C m has its first terminal connected to the source of the m-th MOS transistor S m of the first switch group and the drain of the m-th MOS transistor Q m of the second switch group. The second terminals of all the energy storage capacitors are connected to each other, where m ∈ [1, n - 1]; The source of the nth MOS transistor S of the first switch group n is connected to the drain of the nth MOS transistor Q of the second switch group n and is connected to the second ends of all energy storage capacitors; the input end of the data acquisition unit is connected to the battery pack for collecting data of the battery pack, and the output end is connected to the input end of the microcontrol unit. The output end of the microcontrol unit is respectively connected to the gates of the MOS transistors in the first switch group and the second switch group. The microcontrol unit is used to output a complementary PMW pulse signal with a duty cycle of 50%.

2. The capacitive battery equalization circuit according to claim 1, wherein The capacitance of the energy storage capacitor is 30 uF to 100 uF, and the frequency of the complementary PWM pulse signal is 15 kHz to 100 kHz.

3. The capacitive battery equalization circuit according to claim 2, wherein, The capacitance of the energy storage capacitor is 50 uF, and the frequency of the PWM pulse signal is 19 kHz.

4. A battery equalization method based on a capacitive battery equalization circuit, characterized in that, A capacitive battery equalization circuit according to any one of claims 1 to 3, comprising the following steps: S10. Collect the voltage values and current values of the battery cores of each battery cell in the battery pack through the data acquisition unit, and send the collected data to the microcontrol unit; S20. The microcontrol unit detects the voltage values and current values in real time, and when the voltage values and / or current values meet a first preset threshold, generates a pair of complementary PMW pulse signals with a duty cycle of 50%, and outputs them to the first switch group and the second switch group; S30. Charging step: Each MOS transistor in the first switch group is turned on, each MOS transistor in the second switch group is turned off, each battery cell is connected to the energy bus formed by each capacitor, and current flows out from any battery cell to charge each energy storage capacitor; S40. Discharging step: Each MOS transistor in the first switch group is turned off, each MOS transistor in the second switch group is turned on, each energy storage capacitor releases energy, and any battery cell with a lower voltage starts to receive energy, realizing the charge transfer from a high-energy battery cell to a low-energy battery cell; S50. When the microcontrol unit detects that the voltage values and / or current values meet a second preset threshold, stop generating the pulse control signal.

5. Capacitive battery equalization circuit module, characterized in that, It includes two capacitive battery equalization circuits as described in any one of claims 1 to 3 and a connecting capacitor. The first end of the connecting capacitor is connected to the negative electrode of the nth battery cell B in the first capacitive battery equalization circuit and grounded; the second end is connected to the negative electrode of the nth battery cell B in the second capacitive battery equalization circuit. n n ​​ 6. The capacitive battery equalization circuit module according to claim 5, wherein, The capacitance of the connection capacitor is 50 uF.

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