Totem pole PFC inductive current zero-crossing optimization method and system

Abstract

The invention provides a totem pole PFC inductive current zero-crossing optimization method and system, and the method comprises the steps: obtaining a network voltage instantaneous value through network voltage detection, obtaining a network voltage amplitude phase frequency through phase-locked loop calculation, obtaining an output load voltage through load voltage detection, obtaining 90-degree time delay through 90-degree time delay calculation, obtaining an outer loop output through voltage outer loop calculation, and obtaining a current inner loop given value after multiplying by the network voltage; a slope problem influence area is obtained through slope distortion calculation, a voltage drop problem influence area is obtained through voltage drop distortion calculation, whether a network voltage phase falls into the influence area or not is obtained through phase judgment, and the control output quantity of a single-phase PWM rectifier mode current inner loop is obtained through PWM current inner loop control; and PFC current inner loop control is carried out to obtain a control output quantity of a single-phase PFC rectifier mode current inner loop. Under the condition of sharing the voltage outer loop, seamless connection of PWM and PFC current control is completed, the inductive current zero-crossing waveform is optimized, the grid-side power factor is improved, the harmonic current content is reduced, the waveform optimization effect is good, and implementation is easy.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic converters, and in particular, to a method and system for optimizing the zero-crossing of the inductor current of a totem-pole PFC. Background Art

[0002] For a totem-pole power factor corrector, that is, a totem-pole PFC, which is a single-phase power factor corrector, namely a single-phase PFC. The totem-pole PFC has the same power topology as a single-phase PWM rectifier. The difference is that the totem-pole PFC adopts a high-frequency GaN HEMT bridge arm and a power-frequency SiC MOSFET bridge arm, while the single-phase PWM rectifier adopts two high-frequency SiC MOSFET bridge arms. Similar to the traditional single-phase PFC with power switches behind the bridge, the totem-pole PFC adopts a modulation algorithm similar to that of the single-phase PFC, which is different from the modulation algorithm of the single-phase PWM rectifier, so it can bring higher transmission efficiency. Even so, due to: (1) it is desired that the current rising slope of the inductor current is less than the actual current rising slope in a region after the grid voltage crosses zero, resulting in zero-crossing distortion of the inductor current theoretically after zero-crossing; (2) due to the voltage drops of power devices before and after the grid voltage crosses zero, including the voltage drops of power switches and the voltage drops of inductor distributed resistances, etc., resulting in zero-crossing distortion of the inductor current theoretically before and after zero-crossing; (3) when the input frequency is high, such as 360 Hz - 400 Hz of an aviation power supply, and the input voltage is low, such as 115 V of an aviation power supply and 120 V abroad, the distortion degree of the inductor current will be more serious. In summary, the problem sources causing zero-crossing distortion of the inductor current include the problem of the inductor current slope after zero-crossing and the problem of voltage drops before and after zero-crossing. For the problem of zero-crossing distortion of the inductor current of the totem-pole PFC and the traditional PFC before and after the grid voltage crosses zero, there is still a lack of effective solutions.

[0003] After retrieval, it is found that the Chinese invention patent "Buck-Boost Circuit with Unity Power Factor" with the patent number ZL201210253332.1 provides a buck-boost circuit. The grid side can approximately achieve unity power factor, overcoming the deficiency of the poor power factor on the grid side of the original buck-type Buck AC-DC converter. However, it does not address the problem of zero-crossing distortion of the input current or inductor current caused by the above voltage drop and slope. Moreover, it uses a relatively large number of power switches or power devices, including an electrolytic capacitor, two diodes, and two power switch IGBTs. Due to the excessive voltage drop of the electrolytic capacitor, the electrical stress on the buck inductor is relatively large, such as an additional increase in the voltage level, a large current ripple, which causes problems with insulation withstand voltage, reduces the output voltage quality of the Buck AC-DC converter, and at the same time, the cost is relatively high and the power integration degree is low. In addition, there are also some other solutions, such as: (1) The solution of inserting a DC power supply on the DC negative line of the original PFC. Its disadvantage is the lack of an independent DC power supply, and this solution has no practical value; (2) Changing the input AC voltage source so that there is only one zero-crossing moment, and the instantaneous voltage values before and after the zero-crossing are much greater than zero, so that the grid-side current distortion can be eliminated. However, this solution requires the transformation of the AC input power supply and also has no practical value.

[0004] Therefore, the above existing solutions are only applicable to traditional single-phase PFC and are not suitable for totem-pole PFC. In view of this, it is very necessary to design an optimization technology for the zero-crossing of the inductor current of totem-pole PFC to make it have a simple topology and strong waveform optimization ability. At present, no description or report of a technology similar to the present invention has been found, and no similar materials at home and abroad have been collected either. Summary of the Invention

[0005] The present invention aims at the above deficiencies existing in the prior art and provides an optimization method and system for the zero-crossing of the inductor current of totem-pole PFC.

[0006] According to one aspect of the present invention, an optimization method for the zero-crossing of the inductor current of totem-pole PFC is provided, including:

[0007] Obtain the instantaneous value of the grid voltage and judge the grid voltage;

[0008] Under the condition of normal grid voltage, perform the grid voltage phase-locked loop calculation to obtain the grid voltage amplitude, phase, and frequency information, and perform the load voltage detection to obtain the load voltage and judge the load voltage;

[0009] Under the condition of normal load voltage, perform a 90° delay judgment; if the delay has not arrived, directly perform the voltage outer loop calculation; if the delay has arrived, first perform the load voltage detection and judge the load voltage. Under the condition of normal load voltage, perform the load voltage average value calculation and then perform the voltage outer loop calculation;

[0010] The outer-loop output is calculated through the voltage outer loop, and after multiplying by the grid voltage, the given value of the current inner loop is obtained, which serves as the reference for the grid-side inductor current, so as to finally make the grid-side inductor current present a sinusoidal waveform;

[0011] The slope distortion region is calculated to obtain the zero-crossing distortion region of the inductor current affected by the slope problem; the voltage drop distortion region is calculated to obtain the zero-crossing distortion region of the inductor current affected by the voltage drop problem; the maximum range between the slope distortion calculation value and the module voltage drop distortion calculation value is obtained;

[0012] According to the grid voltage amplitude, phase and frequency information calculated by the current grid voltage phase-locked loop, it is judged whether the phase falls into any distortion region; if it falls, PWM current inner loop control is performed to obtain the control output of the current inner loop in the single-phase PWM rectifier mode; otherwise, PFC current inner loop control is performed to obtain the control output of the current inner loop in the single-phase PFC rectifier mode.

[0013] Preferably, it further includes:

[0014] According to the obtained control output, the final PWM drive pulse is generated.

[0015] Preferably, it further includes any one or more of the following:

[0016] - When the amplitude of the instantaneous grid voltage is greater than the set threshold a or less than the set threshold b, it is judged that the grid voltage is abnormal. At this time, a grid voltage abnormality alarm is given, and the process returns to restart the steps of obtaining the instantaneous grid voltage and judging the grid voltage;

[0017] - When the amplitude of the load voltage is greater than the set threshold c or less than the set threshold d, it is judged that the load voltage is abnormal. At this time, a load voltage abnormality alarm is given, and the process returns to restart the steps of obtaining the instantaneous grid voltage and judging the grid voltage;

[0018] - When the amplitude of the load voltage is greater than the set threshold e or less than the set threshold f, it is judged that the load voltage is abnormal. At this time, a load voltage abnormality alarm is given, and the process returns to restart the steps of obtaining the instantaneous grid voltage and judging the grid voltage;

[0019] - After generating the final PWM drive pulse, the process returns to restart the steps of obtaining the instantaneous grid voltage and judging the grid voltage.

[0020] According to another aspect of the present invention, a totem pole PFC inductor current zero-crossing optimization system is provided, including:

[0021] A grid voltage detection module, which is used to obtain the instantaneous grid voltage and judge the grid voltage;

[0022] The phase-locked loop calculation module is used to perform phase-locked loop calculation of the grid voltage to obtain grid voltage amplitude, phase, and frequency information when the grid voltage is normal;

[0023] The load voltage detection module is used to detect the load voltage, obtain the load voltage, and judge the load voltage;

[0024] The 90° delay calculation module is used to perform a 90° delay judgment when the load voltage is normal; if the delay has not arrived, directly perform voltage outer loop calculation; if the delay has arrived, first perform load voltage detection and judge the load voltage, and when the load voltage is normal, perform load voltage average value calculation and then perform voltage outer loop calculation;

[0025] The voltage outer loop calculation module is used to obtain the outer loop output through voltage outer loop calculation, and after multiplying by the grid voltage, obtain the current inner loop reference, which is used as the reference for the grid-side inductor current;

[0026] The slope distortion calculation module is used to calculate the slope distortion region to obtain the inductor current zero-crossing distortion region affected by the slope problem;

[0027] The voltage drop distortion calculation module is used to calculate the voltage drop distortion region to obtain the inductor current zero-crossing distortion region affected by the voltage drop problem;

[0028] The distortion region OR module is used to obtain the maximum range between the slope distortion calculation value and the module voltage drop distortion calculation value;

[0029] The phase judgment module is used to judge whether the phase falls into any distortion region according to the grid voltage amplitude, phase, and frequency information calculated by the current grid voltage phase-locked loop; if it falls into, perform PWM current inner loop control; otherwise, perform PFC current inner loop control;

[0030] The PWM current inner loop control module is used to perform PWM current inner loop control to obtain the control output of the current inner loop of the single-phase PWM rectifier mode;

[0031] The PFC current inner loop control module is used to perform PFC current inner loop control to obtain the control output of the current inner loop of the single-phase PFC rectifier mode.

[0032] Preferably, it further includes any one or any combination of the following:

[0033] - The delay arrival flag setting module is used to set the flag when a 90° delay is completed once;

[0034] - The delay arrival flag clearing module is used to clear the flag when starting the next 90° delay;

[0035] - A PWM drive pulse generation module, which is used to generate the final PWM drive pulse according to the obtained control output quantity.

[0036] Due to the adoption of the above technical solution, compared with the prior art, the present invention has at least one of the following beneficial effects:

[0037] The method and system for optimizing the zero-crossing of the inductor current of the totem-pole PFC provided by the present invention calculate the voltage drop influence area before and after the zero-crossing of the grid voltage at one time, and dynamically calculate the slope influence area after the zero-crossing of the grid voltage according to the expected inductor current amplitude, so as to obtain the accurate inductor current zero-crossing distortion area and set an appropriate margin.

[0038] The method and system for optimizing the zero-crossing of the inductor current of the totem-pole PFC provided by the present invention call the current inner-loop control program of the PWM rectifier within the inductor current zero-crossing distortion area to eliminate the zero-crossing distortion, which has a slight impact on the conversion efficiency; outside the inductor current zero-crossing distortion area, call the current inner-loop control program of the PFC rectifier to ensure high-efficiency conversion; when ensuring that the output results of the current inner loop are the same during switching, either hard switching or soft switching can be adopted between the two modes, and the test results show that both are good.

[0039] The method and system for optimizing the zero-crossing of the inductor current of the totem-pole PFC provided by the present invention, when the value of the electrolytic capacitor is large enough, adopt any 90° delay interval detection, and then calculate the average value to obtain the grid voltage average value. It is also possible to measure the output voltage at the zero-crossing and peak of the grid voltage and calculate the average value, perform rolling measurement on the detected data, store the measured data in the register group, first in first out, which has the advantages of less measurement overhead and the measurement result reflecting the average value of the output voltage. Description of the Drawings

[0040] By reading the detailed description of the non-restrictive embodiments with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:

[0041] Figure 1 It is the flowchart of the method for optimizing the zero-crossing of the inductor current of the totem-pole PFC in an embodiment of the present invention.

[0042] Figure 2 It is the flowchart of the method and system for optimizing the zero-crossing of the inductor current of the totem-pole PFC in a preferred embodiment of the present invention.

[0043] Figure 3 It is the schematic diagram of the power circuit of the totem-pole PFC in a specific application example of the present invention.

[0044] Figure 4 It is the schematic diagram of the control structure of the totem-pole PFC in a specific application example of the present invention.

[0045] Figure 5It is a schematic diagram of the control structure of a single-phase PWM rectifier in a specific application example of the present invention. Detailed implementation manners

[0046] The present invention will be described in detail below in conjunction with specific examples. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several changes and improvements can still be made. These all belong to the protection scope of the present invention.

[0047] In the prior art, there is a lack of a technical solution to effectively solve the problem of zero-crossing distortion of the inductor current before and after the grid voltage crosses zero. In view of this problem, an embodiment of the present invention provides a method for optimizing the zero-crossing of the inductor current of a totem-pole PFC. This method sets an influence area near the zero-crossing of the grid voltage in the original totem-pole PFC. PWM current control is adopted within the area, and PFC current control is adopted outside the area. Under the condition of sharing the voltage outer loop, seamless connection of PWM current control and PFC current control is completed, thereby optimizing the zero-crossing waveform of the inductor current, improving the grid-side power factor and reducing the harmonic current content, and having the advantages of good waveform optimization effect and easy implementation.

[0048] Specifically, as Figure 1 shown, the method for optimizing the zero-crossing of the inductor current of the totem-pole PFC provided by this embodiment may include:

[0049] S1, obtaining the instantaneous value of the grid voltage and judging the grid voltage;

[0050] S2, in the case of normal grid voltage, performing grid voltage phase-locked loop calculation to obtain grid voltage amplitude, phase and frequency information, and performing load voltage detection to obtain the load voltage and judging the load voltage;

[0051] S3, in the case of normal load voltage, performing a 90° delay judgment; if the delay has not arrived, directly perform voltage outer loop calculation; if the delay has arrived, first perform load voltage detection and judge the load voltage. In the case of normal load voltage, perform load voltage average calculation and then perform voltage outer loop calculation;

[0052] S4, obtaining the outer loop output through voltage outer loop calculation and obtaining the current inner loop given value after multiplying by the grid voltage;

[0053] S5, performing slope distortion area calculation to obtain the maximum range of the inductor current zero-crossing distortion area affected by the slope problem; performing voltage drop distortion area calculation to obtain the maximum range of the inductor current zero-crossing distortion area affected by the voltage drop problem;

[0054] S6. Based on the grid voltage amplitude, phase, and frequency information calculated by the current grid voltage phase-locked loop, determine whether the phase falls within the maximum range of any distortion region; if it falls within, perform PWM current inner-loop control to obtain the control output of the current inner-loop of the single-phase PWM rectifier mode; otherwise, perform PFC current inner-loop control to obtain the control output of the current inner-loop of the single-phase PFC rectifier mode.

[0055] In some preferred embodiments, the above method may further include:

[0056] S7. Generate the final PWM drive pulse according to the obtained control output.

[0057] In some preferred embodiments, the above S1 may further include:

[0058] When the amplitude of the grid voltage instantaneous value is greater than the set threshold a or less than the set threshold b, it is determined that the grid voltage is abnormal. At this time, an alarm for abnormal grid voltage is given, and the program entry is returned to restart the steps of obtaining the grid voltage instantaneous value and judging the grid voltage.

[0059] In some preferred embodiments, the above S2 may further include:

[0060] When the amplitude of the load voltage is greater than the set threshold c or less than the set threshold d, it is determined that the load voltage is abnormal. At this time, an alarm for abnormal load voltage is given, and the program entry is returned to restart the steps of obtaining the grid voltage instantaneous value and judging the grid voltage.

[0061] In some preferred embodiments, the above S3 may further include:

[0062] When the amplitude of the load voltage is greater than the set threshold e or less than the set threshold f, it is determined that the load voltage is abnormal. At this time, an alarm for abnormal load voltage is given, and the program entry is returned to restart the steps of obtaining the grid voltage instantaneous value and judging the grid voltage.

[0063] In some preferred embodiments, the above S7 may further include:

[0064] After generating the final PWM drive pulse, return to the program entry to restart the steps of obtaining the grid voltage instantaneous value and judging the grid voltage.

[0065] In some preferred embodiments, when performing the grid voltage phase-locked loop calculation in the above S2 to obtain the grid voltage amplitude, phase, and frequency information, it may further include:

[0066] Determine the frequency and phase of the grid voltage through the grid voltage phase-locked loop, and any phase-locked loop method suitable for the power frequency grid voltage of a strong grid or a weak grid can be adopted.

[0067] In some preferred embodiments, the above S3, when the load voltage is normal, performs the 90° delay judgment, and may further include:

[0068] The 90° delay can be realized by programming the delay program in the controller MCU or DSP that must be used in the power electronic converter.

[0069] The output DC voltage is measured every 90°, and the average of the two adjacent output DC voltages is calculated to obtain the output DC voltage detection value; where:

[0070] The output DC voltage is measured 90° after the grid voltage crosses zero to obtain the valley value of the output DC voltage. The output DC voltage is then measured again after a delay of 2x90°=90° to obtain the peak value of the output DC voltage. The average of the peak value and the valley value is the average of the two adjacent output DC voltages.

[0071] As long as the output voltage detection is performed at intervals of 90°, two rolling detection values are obtained, and the average of the two values is calculated, the output DC voltage mean value can be obtained. This can provide the output voltage detection value for the subsequent 90° angle range, with the advantages of low software resource overhead and the ability to output the influence of DC voltage ripple.

[0072] In some preferred embodiments, the above S4, performing voltage outer loop calculation to obtain outer loop output, may further include:

[0073] Through the voltage outer loop controller, the mean value of the output DC voltage is introduced and compared with the given voltage reference value (voltage given value), and the resulting error is adjusted. The result is the output of the voltage controller, that is, the outer loop output.

[0074] The voltage controller output increases and decreases as the load increases. The voltage controller output is multiplied by the grid voltage sinusoidal waveform to obtain the current reference value (current setpoint) for the inner current loop.

[0075] In some preferred embodiments, the above S5, performing slope distortion region calculation to obtain the inductor current zero-crossing distortion region affected by the slope problem, may further include:

[0076] For a short period of time after the grid voltage crosses zero, the actual inductor current's rising slope is lower than the expected slope of the reference current input by the current inner-loop controller, causing zero-crossing distortion of the inductor current (i.e., the grid-side current). This region is the zero-crossing distortion region caused by insufficient slope and can be calculated using the following formula:

[0077] ω i t=tan -1 (ω i L1I im / U im )=tan-1 (X L1 / R1)

[0078] Where ω i is the angular frequency of the grid voltage, t is time, L1 is the inductance, and I im is the amplitude of the inductor current, U im is the amplitude of the single-phase grid voltage, X L1 is the reactance of the inductor L1, and R1 is the load resistance.

[0079] In some preferred embodiments, in step S5 of calculating the voltage drop distortion region to obtain the zero-crossing distortion region of the inductor current affected by the voltage drop problem, it may further include:

[0080] Within a small angle before and after the grid voltage crosses zero, due to the on-state voltage drop mainly caused by power switches on the line, the inductor current will only be generated when the instantaneous value of the grid voltage is high enough, resulting in zero-crossing crossover distortion of the inductor current, i.e., the grid-side current. This region can be calculated by the formula:

[0081] ω i t = sin -1 (U ∑ / U im )

[0082] Where ω i is the angular frequency of the grid voltage, t is time, U Σ is the total voltage drop of the current path, and U im is the amplitude of the single-phase power supply voltage.

[0083] Based on the same inventive concept, an embodiment of the present invention also provides a totem-pole PFC inductor current zero-crossing optimization system.

[0084] Specifically, the totem-pole PFC inductor current zero-crossing optimization system provided by this embodiment may include:

[0085] A grid voltage detection module, which is used to obtain the instantaneous value of the grid voltage and judge the grid voltage;

[0086] A phase-locked loop calculation module, which is used to perform phase-locked loop calculation of the grid voltage to obtain grid voltage amplitude, phase, and frequency information when the grid voltage is normal;

[0087] A load voltage detection module, which is used to detect the load voltage, obtain the load voltage, and judge the load voltage;

[0088] A 90° delay calculation module, which is used to perform a 90° delay judgment when the load voltage is normal; if the delay has not arrived, directly perform the voltage outer loop calculation; if the delay has arrived, first perform the load voltage detection, judge the load voltage, and when the load voltage is normal, perform the load voltage average value calculation and then perform the voltage outer loop calculation as the reference of the grid-side inductor current.

[0089] A voltage outer loop calculation module, which is used to obtain the outer loop output through the voltage outer loop calculation and obtain the current inner loop given value after multiplying by the grid voltage.

[0090] A slope distortion calculation module, which is used to perform the slope distortion region calculation to obtain the inductor current zero-crossing distortion region affected by the slope problem.

[0091] A voltage drop distortion calculation module, which is used to perform the voltage drop distortion region calculation to obtain the inductor current zero-crossing distortion region affected by the voltage drop problem.

[0092] A distortion region OR module, which is used to obtain the maximum range of the slope distortion region and the module voltage drop distortion region.

[0093] A phase judgment module, which is used to judge whether the phase falls within the maximum range of any distortion region according to the grid voltage amplitude, phase and frequency information calculated by the current grid voltage phase-locked loop; if it falls within, perform the PWM current inner loop control; otherwise, perform the PFC current inner loop control.

[0094] A PWM current inner loop control module, which is used to perform the PWM current inner loop control to obtain the control output quantity of the current inner loop in the single-phase PWM rectifier mode.

[0095] A PFC current inner loop control module, which is used to perform the PFC current inner loop control to obtain the control output quantity of the current inner loop in the single-phase PFC rectifier mode.

[0096] In some preferred embodiments, the above system may further include any one or any combination of the following:

[0097] - A delay arrival flag setting module, which is used to set the flag when a 90° delay is completed once.

[0098] - A delay arrival flag clearing module, which is used to clear the flag when starting the next 90° delay.

[0099] - A PWM drive pulse generation module, which is used to generate the final PWM drive pulse according to the obtained control output quantity.

[0100] The totem-pole PFC inductor current zero-crossing optimization system provided by this embodiment mainly includes function modules such as line voltage detection, phase-locked loop calculation, load voltage detection, 90° delay calculation, voltage outer-loop calculation, slope distortion calculation, voltage drop distortion calculation, phase judgment, PWM current inner-loop control, and PFC current inner-loop control. Among them, the line voltage detection module is used to obtain the instantaneous line voltage value; the phase-locked loop calculation module is used to obtain the amplitude-phase-frequency of the line voltage; the load voltage detection module is used to obtain the output voltage, that is, the load voltage or the load voltage; the 90° delay calculation module is used to obtain a 90° delay; the voltage outer-loop calculation module is used to obtain the outer-loop output, and after multiplying by the line voltage, it obtains the current inner-loop reference; the slope distortion calculation module is used to obtain the size of the area affected by the slope problem; the voltage drop distortion calculation module is used to obtain the size of the area affected by the voltage drop problem; the phase judgment module is used to obtain whether the line voltage phase falls into the affected area; the PWM current inner-loop control module is used to obtain the control output of the current inner-loop in the single-phase PWM rectifier mode; the PFC current inner-loop control module is used to obtain the control output of the current inner-loop in the single-phase PFC rectifier mode.

[0101] The execution sequence among the above function modules is described as follows in combination with Figure 2 , as follows.

[0102] As Figure 2 shown, the execution sequence among the above function modules is as follows:

[0103] First, execute the line voltage detection module P1, and then perform line voltage judgment through the line voltage normal judgment module P2. If the line voltage amplitude is too large or too small, perform line voltage abnormal alarm through the line voltage abnormal alarm module P3 and return to the program entry. Otherwise, continue to execute the following steps;

[0104] Execute the phase-locked loop calculation module P4 to obtain the line voltage replica phase frequency information, that is, the amplitude-phase-frequency information. Execute the load voltage detection module P5, and then perform load voltage judgment through the load voltage normal judgment module P6. If the load voltage amplitude is too large or too small, perform load voltage abnormal alarm through the load voltage abnormal alarm module P7 and return to the program entry. Otherwise, continue to execute the following steps;

[0105] Module P8 determines whether there is a 90° delay flag. If it is 0, it jumps to P11 for 90° delay calculation. If it is 1, it performs the load voltage detection of P9, then sequentially executes P10 to clear the delay arrival flag bit, executes P11 for 90° delay calculation, and judges whether the delay has arrived through the delay arrival judgment module P11. If the delay has not arrived, it executes the voltage outer loop calculation module P17. If the delay has arrived, it first sets the delay arrival flag bit P13, then performs the load voltage detection through the load voltage detection module P14, and then performs the load voltage judgment through the load voltage normal judgment module P15. If the load voltage amplitude is too large or too small, it performs the load voltage abnormal alarm through the load voltage abnormal alarm module P7 and returns to the program entry. Otherwise, it executes the load voltage average value calculation module P16 and the voltage outer loop calculation module P17; then the following steps are executed;

[0106] Execute the slope distortion area calculation module P18, execute the voltage drop distortion area calculation module P19, execute the distortion area OR module P20, and then judge whether the phase falls into the distortion area through the falling into the distortion area module P21 according to the phase information generated by the current line voltage phase-locked loop calculation. If it falls into this area, execute the PWM current inner loop control module P22. Otherwise, execute the PFC current inner loop control module P23;

[0107] Execute the PWM drive pulse generation module P24 to generate the final drive pulse and complete the functions and performances of the totem pole PFC.

[0108] In the above description, the functional modules P5, P9, and P14 can be the same module, and the functional modules P6 and P15 can be the same module.

[0109] It should be noted that the steps in the method provided by the present invention can be implemented by corresponding modules, devices, units, etc. in the system. Those skilled in the art can refer to the technical solution of the method to implement the composition of the system, that is, the embodiments in the method can be understood as the preferred examples for constructing the system, which will not be elaborated here.

[0110] Next, a specific application example is combined to further elaborate in detail on the technical solution provided by the above embodiments of the present invention.

[0111] In this specific application example, for the totem pole PFC inductor current zero-crossing optimization system involved, the parameter settings of each functional module and electronic component are as follows:

[0112] Input voltage: AC 220V;

[0113] Output voltage: DC 385V;

[0114] Output power level: 3.50kW, or not limited;

[0115] Switching frequency: 50 kHz, or 100 kHz, or others;

[0116] Power switches S1 and S2: GaN HEMT 35 A @ 85 °, 650 V:

[0117] Power switches S3 and S4: SiC power MOSFET 35 A @ 85 °, 650 V:

[0118] Electrolytic capacitor C1: 0.47 μF, withstand voltage 275 V AC;

[0119] Electrolytic capacitor C2: 4 x 680 μF, withstand voltage 450 V DC;

[0120] Inductor L1: 1 mH, 16 A.

[0121] In this specific application example, the optimization method for the inductor current zero - crossing of the totem - pole PFC, its working principle is:

[0122] As Figure 3 shown, it is the power circuit of the totem - pole PFC; as Figure 4 shown, it is the control structure of the totem - pole PFC; as Figure 5 shown, it is the control structure of the single - phase PWM rectifier.

[0123] Please refer to Figures 3 to 5 simultaneously. Based on the power circuit as Figure 2 shown, when falling into the zero - crossing distortion region, switching the control structures of Figure 4 and Figure 5 can eliminate the grid - side current distortion and cause very small device losses. The power circuit of the totem - pole PFC is the same as that of the single - phase PWM rectifier, and they adopt different modulation algorithms and control structures. The power circuit of the totem - pole PFC uses a GaN bridge arm and a SiC MOSFET bridge arm, while the single - phase PWM rectifier uses two identical SiC MOSFET or IGBT bridge arms. The zero - crossing distortion region is jointly composed of the region caused by the slope and the region caused by the voltage drop. The region caused by the slope is at an angle after the grid voltage crosses zero, and the region caused by the voltage drop is at an angle before and after the grid voltage crosses zero.

[0124] When the grid voltage is in [0 °, 90 °] and [180 °, 360 °], especially close to 0 ° or 180 °, the actual boost inductor current waveform is completed by charging and discharging under the action of the power switch conduction and turn - off. When the power switch conducts, the current rises and charges, and the current waveform has a lagging trend. When the power switch turns off, the current drops and discharges, and the current waveform has a leading trend. The actually formed slope of the inductor current rise is u i / L1, and the expected slope of the inductor current rise is ω i I im cosωi t, requiring u L1 / L1 > ω i I im cosω i t, u L1 = u i , in order to achieve inductor current tracking the grid voltage, but when ω i t is close to 0° or 180°, that is, within a certain angle after the grid voltage crosses zero, this condition cannot hold. Among them, ω i is the grid voltage angular frequency, I im is the inductor current amplitude, t is the time, u L1 is the boost inductor voltage, u i is the input voltage. Actually, the slope of the formed inductor current decline is ( u i - u o ) / L1, and the expected slope of the inductor current decline is ω i I im cosω i t, requiring ( u i - u o ) / L1 < ω i I im cosω i t, u o is the output voltage of the totem-pole PFC, and this condition can hold. Theoretically, the influence area calculation formula is ω i t = tan -1 (ω i L1I im / U im ) = tan -1 (X L1 / R i ).

[0125] In practice, due to the non-ideal characteristics of power devices, there are power device voltage drops before and after the grid voltage crosses zero, including power switch voltage drops, inductor distributed resistance voltage drops, etc., resulting in zero-crossing distortion before and after the theoretical inductor current crosses zero. Considering the above voltage drop problems and slope problems comprehensively, the zero-crossing distortion problem of the inductor current inevitably appears, reducing the sinusoidality of the grid-side current and the input power factor is less than 1.

[0126] In this specific application example, by using the totem-pole PFC inductor current zero-crossing optimization method and system provided in the above embodiments of the present invention, the slope distortion region can be calculated and the slope influence region can be dynamically calculated. Then, within the inductor current zero-crossing distortion region, the PWM rectifier current inner-loop control program is called to eliminate the inductor current zero-crossing distortion. Outside the inductor current zero-crossing distortion region, the PFC rectifier current inner-loop control program is called to ensure high-efficiency conversion. When ensuring that the output results of the current inner loop are the same during switching, hard switching or soft switching can be adopted between the two modes, and the impact on the conversion efficiency is slight, and the simulation test results have been obtained. At the same time, in order to ensure accurate inductor current control and eliminate the influence of the carrier voltage, that is, the output voltage ripple, the method of detecting the output voltage with a 90° delay interval is adopted, with two detections and one calculation, and rolling measurement and rolling calculation. The method of detecting the output voltage with a 90° delay interval also includes special cases of measuring the output voltage at the zero-crossing and peak of the grid voltage and taking the average value. At this time, if the detection is accurate, it may not be necessary to calculate the average value.

[0127] The totem-pole PFC inductor current zero-crossing optimization method and system provided in the above embodiments of the present invention set an influence region near the zero-crossing of the grid voltage in the original totem-pole PFC. PWM current control is adopted within the region, and PFC current control is adopted outside the region. Under the condition of sharing the voltage outer loop, seamless connection of PWM current control and PFC current control is completed, thereby optimizing the inductor current zero-crossing waveform, improving the grid-side power factor and reducing the harmonic current content, and having the advantages of good waveform optimization effect and easy implementation.

[0128] The totem-pole PFC inductor current zero-crossing optimization method and system provided in the above embodiments of the present invention can suppress or eliminate the inductor current zero-crossing crossover distortion, make the total current distortion tend to zero, obtain a grid-side near unity power factor, and prevent harmonic current from polluting the power grid. The totem-pole PFC has a wide range of application scenarios and can be applied to commercial, household appliances, communication, charging piles, and wireless power transmission in automobiles. The circuit structure is simple and the operability is strong.

[0129] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various deformations or modifications within the scope of the claims, which does not affect the essence of the present invention. The above preferred features can be combined arbitrarily without conflict.

Claims

1. A method for optimizing the zero-crossing of the inductor current of a totem-pole PFC, characterized in that, It includes: Obtain the instantaneous value of the grid voltage and judge the grid voltage; When the grid voltage is normal, perform grid voltage phase-locked loop calculation to obtain grid voltage amplitude, phase and frequency information, and perform carrier voltage detection to obtain the load voltage, and judge the load voltage; When the load voltage is normal, perform a 90° delay judgment; if the delay has not arrived, directly perform voltage outer loop calculation; if the delay has arrived, first perform carrier voltage detection and judge the carrier voltage. When the carrier voltage is normal, perform carrier voltage average value calculation and then perform voltage outer loop calculation; Obtain the outer loop output through voltage outer loop calculation, and after multiplying by the grid voltage, obtain the current inner loop given value, which is used as the reference of the grid-side inductor current; Perform slope distortion region calculation to obtain the maximum range of the inductor current zero-crossing distortion region affected by the slope problem; perform voltage drop distortion region calculation to obtain the maximum range of the inductor current zero-crossing distortion region affected by the voltage drop problem; According to the grid voltage amplitude, phase and frequency information calculated by the current grid voltage phase-locked loop, judge whether the phase falls within the maximum range of any distortion region; if it falls, perform PWM current inner loop control to obtain the control output of the current inner loop in the single-phase PWM rectifier mode; otherwise, perform PFC current inner loop control to obtain the control output of the current inner loop in the single-phase PFC rectifier mode.

2. The optimized method for the inductor current of the totem-pole PFC to cross zero according to claim 1, wherein When the load voltage is normal, performing a 90° delay judgment further includes: Measure the output DC voltage every 90°, and obtain the average value of the adjacent two output DC voltages, that is, obtain the detected value of the output DC voltage; where: Measure the output DC voltage 90° after the grid voltage passes through zero to obtain the valley value of the output DC voltage, and then delay 2×90° = 90° to measure the output DC voltage to obtain the peak value of the output DC voltage. The average value of the peak value and the valley value is the average value of the adjacent two output DC voltages.

3. The method for optimizing the zero-crossing of the totem-pole PFC inductor current according to claim 1, wherein Performing voltage outer loop calculation to obtain the outer loop output includes: Through the voltage outer loop controller, introduce the average value of the output DC voltage to compare with the given voltage reference value, adjust the obtained error, and the obtained result is the output of the voltage controller, that is, obtain the outer loop output.

4. The method for optimizing the zero-crossing of the inductor current of the totem-pole PFC according to claim 1, wherein Performing slope distortion region calculation to obtain the inductor current zero-crossing distortion region affected by the slope problem includes: The inductor current zero-crossing distortion region affected by the slope problem is calculated by the following formula: ω i t = tan -1 (ω i L1I im / U im ) = tan -1 (X L1 / R1) Where ω i is the angular frequency of the grid voltage, t is time, L1 is the inductor, and I im is the amplitude of the inductor current, U im is the amplitude of the single-phase grid voltage, X L1 is the reactance of the inductor L1, and R1 is the load resistance.

5. The method for optimizing the zero-crossing of the totem-pole PFC inductor current according to claim 1, characterized in that, Performing voltage drop distortion region calculation to obtain the inductor current zero-crossing distortion region affected by the voltage drop problem includes: The inductor current zero-crossing distortion region affected by the voltage drop problem is calculated by the formula: ω i t = sin -1 (U Σ / U im ), where ω i is the angular frequency of the grid voltage, t is time, U Σ is the total voltage drop of the current path, and U im is the amplitude of the single-phase power supply voltage.

6. The method for optimizing the zero-crossing of the inductor current of the totem-pole PFC according to any one of claims 1-5, characterized in that, It also includes: Generate the final PWM drive pulse according to the obtained control output.

7. The optimized method for zero-crossing of the totem-pole PFC inductor current according to claim 6, wherein It also includes any one or any combination of the following: - When the amplitude of the instantaneous value of the grid voltage is greater than the set threshold a or less than the set threshold b, it is judged that the grid voltage is abnormal. At this time, perform grid voltage abnormal alarm, and return to restart the step of obtaining the instantaneous value of the grid voltage and judging the grid voltage; - When the amplitude of the load voltage is greater than the set threshold c or less than the set threshold d, it is judged that the load voltage is abnormal. At this time, perform load voltage abnormal alarm, and return to restart the step of obtaining the instantaneous value of the grid voltage and judging the grid voltage; - When the amplitude of the load voltage is greater than the set threshold e or less than the set threshold f, it is determined that the load voltage is abnormal. At this time, an alarm for abnormal load voltage is given, and the process returns to restart the steps of obtaining the instantaneous grid voltage value and judging the grid voltage. - After the final PWM drive pulse is generated, the process returns to restart the steps of obtaining the instantaneous grid voltage value and judging the grid voltage.

8. A totem-pole PFC inductor current zero-crossing optimization system, characterized in that, It includes: A grid voltage detection module, which is used to obtain the instantaneous grid voltage value and judge the grid voltage. A phase-locked loop calculation module, which is used to perform phase-locked loop calculation of the grid voltage under normal grid voltage conditions to obtain grid voltage amplitude-phase-frequency information. A load voltage detection module, which is used to detect the load voltage, obtain the load voltage, and judge the load voltage. A 90° delay calculation module, which is used to perform 90° delay judgment under normal load voltage conditions; if the delay has not reached, directly perform voltage outer loop calculation; if the delay has reached, first perform load voltage detection and judge the load voltage. Under normal load voltage conditions, perform load voltage average value calculation and then perform voltage outer loop calculation. A voltage outer loop calculation module, which is used to obtain the outer loop output through voltage outer loop calculation, and after multiplying by the grid voltage, obtain the current inner loop reference, which is used as the reference for the grid-side inductor current. A slope distortion calculation module, which is used to calculate the slope distortion area to obtain the inductor current zero-crossing distortion area affected by the slope problem. A voltage drop distortion calculation module, which is used to calculate the voltage drop distortion area to obtain the inductor current zero-crossing distortion area affected by the voltage drop problem. A distortion area OR module, which is used to obtain the maximum range of the slope distortion area and the module voltage drop distortion area. A phase judgment module, which is used to judge whether the phase falls within the maximum range of any distortion area according to the grid voltage amplitude-phase-frequency information obtained by the current grid voltage phase-locked loop calculation; if it falls within, perform PWM current inner loop control; otherwise, perform PFC current inner loop control. A PWM current inner loop control module, which is used to perform PWM current inner loop control to obtain the control output of the current inner loop in the single-phase PWM rectifier mode. A PFC current inner loop control module, which is used to perform PFC current inner loop control to obtain the control output of the current inner loop in the single-phase PFC rectifier mode.

9. The totem-pole PFC inductor current zero-crossing optimization system according to claim 8, wherein, It also includes any one or any combination of the following: - A delay arrival flag setting module, which is used to set a flag bit after a 90° delay is completed. - A delay arrival flag clearing module, which is used to clear the flag bit when starting the next 90° delay. - A PWM drive pulse generation module, which is used to generate the final PWM drive pulse according to the obtained control output.

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