Voltage divider adjustment circuit and amplifier circuit of stacked power amplifier

Abstract

The present disclosure discloses a voltage divider regulation circuit and an amplifier circuit for a stacked power amplifier. The stacked power amplifier includes a plurality of stacked transistors, wherein the output of the preceding transistor is connected to the input of the following transistor; the voltage divider regulation circuit includes: a voltage swing detection module connected to the output of each transistor, the voltage swing detection module including a voltage detection unit and a difference unit, for detecting and comparing the voltage swing between the input and output of the transistor, and outputting multiple voltage swings; a swing comparison module connected to the output of the voltage swing detection module, comparing the voltage swings of the two transistors, and outputting a calculation result; the swing comparison module connected to a control module, which outputs a control signal based on the calculation result; an adjustment module connected to the control end of the transistor, for controlling the bias voltage of the control end of the transistor and / or the capacitance value of the grounding capacitor of the control end of the transistor according to the control signal.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of electronic devices, and relate to, but are not limited to, a voltage divider adjustment circuit and an amplifier circuit of a stacked power amplifier. Background Art

[0002] With the continuous development of modern CMOS (Complementary Metal-Oxide-Semiconductor) integrated circuit technology, the channel length of transistors is getting smaller and smaller. The reduction in size can increase the operating speed of the device, thereby achieving better high-frequency performance. However, correspondingly, the maximum power supply voltage (V DD ) also continues to decrease as the size decreases, which brings challenges to the design of analog RF circuits, especially the design of modules such as PA (Power Amplifier) ​​that require large output power.

[0003] Traditionally, high-power PAs are designed using a III-V compound process, as these transistors offer higher voltage resistance, enabling greater power output. The PA is then integrated with other silicon-based modules. However, to reduce costs and increase chip integration, designing using a silicon-based process is becoming more attractive. To address these requirements, and considering the lower voltage resistance of silicon-based transistors, a stacked transistor approach is often used for silicon-based high-power PA design.

[0004] Stacked power amplifiers require uniform voltage division across each transistor to maximize swing amplitude and achieve optimal amplification performance. However, in scenarios such as when the power supply voltage is increased, uneven voltage division across each transistor in the voltage divider circuit often occurs, reducing amplifier performance and even creating reliability risks such as transistor breakdown. Therefore, achieving uniform voltage division across each transistor in stacked power amplifiers remains a technical challenge in this field. Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure provide a voltage divider adjustment circuit and an amplifier circuit for a stacked power amplifier, which can make the voltage division of each stage transistor of various stacked power amplifiers uniform, so that each stacked transistor has the maximum swing, and while ensuring the reliability of the transistor, the performance of the power amplifier can be improved as much as possible.

[0006] In one aspect, an embodiment of the present disclosure provides a voltage divider regulation circuit for a stacked power amplifier, wherein the stacked power amplifier includes a plurality of stacked transistors, wherein the output end of a preceding transistor is connected to the input end of a succeeding transistor; the voltage divider regulation circuit includes:

[0007] a voltage swing detection module, configured to detect a voltage swing between the input and output terminals of the transistors; the voltage swing detection module comprising a voltage detection unit and a difference unit, wherein the voltage detection unit is connected to the output terminals of the transistors and detects voltages at the output terminals of a plurality of the transistors based on the power or amplitude of signals at the output terminals of the transistors to obtain a plurality of output voltages; and the difference unit obtains a voltage swing between the input and output terminals of the transistors by taking a difference between adjacent output voltages;

[0008] a swing comparison module connected to the output end of the voltage swing detection module, comparing the voltage swings of the two transistors and outputting a calculation result; the swing comparison module is connected to the control module, and the control module outputs a control signal based on the calculation result;

[0009] An adjustment module is connected to the control terminal of the transistor and is used to control the bias voltage of the control terminal of the transistor and / or control the capacitance value of the grounding capacitor of the control terminal of the transistor according to the control signal.

[0010] In the embodiment of the present disclosure, by detecting the voltage swing of the stacked transistors and adjusting the bias voltage of the transistors or the capacitor to adjust the voltage swing of the transistors, voltage balancing of each level of transistors can be achieved, thereby improving the reliability and performance of the stacked power amplifier.

[0011] On the other hand, an embodiment of the present disclosure further provides an amplifier circuit, comprising:

[0012] A stacked power amplifier comprising a plurality of stacked transistors, wherein the output end of a preceding transistor is connected to the input end of a succeeding transistor;

[0013] Such as any voltage divider regulation circuit, connected to the stacked power amplifier.

[0014] The voltage divider regulation circuit provided by the embodiment of the present disclosure, through the coordinated work of the voltage swing detection module, the swing comparison module and the adjustment module, the voltage swing detection module can automatically detect the voltage swing of the transistors in the stacked power amplifier in real time, and the swing comparison module can detect in real time whether the voltage swings of the transistors are equal. Once the difference in the voltage swings of adjacent transistors is not equal, it means that the voltage division of the transistors is uneven. The adjustment module can adjust the bias voltage of the transistor and / or the capacitance value of the grounding capacitor accordingly to adjust the voltage division of the transistor, automatically realize the voltage division adjustment of the stacked power amplifier, so that the difference in the voltage swing of the transistor is reduced or even eliminated, thereby achieving uniform voltage division, reducing the risk of transistor breakdown due to uneven voltage distribution, and improving the efficiency and linearity of the amplifier.

[0015] Wherein, adjusting the bias voltage of the transistor can change the DC bias of the transistor, thereby changing the DC reference voltage value in the overall voltage output by the transistor, so as to change the voltage division of the transistor;

[0016] For transistors in a stacked power amplifier with a common gate, there's a grounding capacitor between the gate and ground. This capacitor, along with the parasitic capacitance between the transistor's gate and source, forms a voltage divider. The AC voltage (including RF signals) on the gate depends on the values ​​of these two capacitors. Therefore, adjusting the value of the transistor's gate-to-ground capacitor can change the AC voltage amplitude in the transistor's overall gate voltage, thereby altering the transistor's voltage divider. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1A It is a schematic diagram of the structure of a stacked power amplifier;

[0018] Figure 1B A schematic diagram of a ground capacitor voltage divider for a stacked power amplifier;

[0019] Figure 2A A schematic structural diagram of a voltage divider adjustment circuit for a stacked power amplifier provided in an embodiment of the present disclosure;

[0020] Figure 2B A schematic diagram of the specific structure of a voltage divider adjustment circuit of a stacked power amplifier provided in an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of the structure of a voltage swing detection module in a voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0022] Figure 4 A schematic structural diagram of a swing amplitude comparison module in a voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0023] Figure 5 A schematic structural diagram of a control module in a voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0024] Figure 6 A schematic structural diagram of an adjustment module in a voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0025] Figure 7A A schematic structural diagram of a bias voltage calibration unit in a voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0026] Figure 7B A schematic structural diagram of a capacitance calibration unit in a voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0027] Figure 8AA flow chart of a method for adjusting a voltage divider adjustment circuit of a stacked power amplifier provided in an embodiment of the present disclosure;

[0028] Figure 8B A flow chart of a method for adjusting a voltage divider adjustment circuit of a stacked power amplifier provided in another embodiment of the present disclosure;

[0029] Figure 9A A schematic structural diagram of another swing amplitude comparison module in the voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0030] Figure 9B A schematic structural diagram of another control module in the voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0031] Figure 10A A structural diagram of another swing amplitude comparison module in the voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0032] Figure 10B A schematic structural diagram of another control module in the voltage divider regulation circuit provided in an embodiment of the present disclosure;

[0033] Figure 11 A structural block diagram of an amplifier circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in a variety of different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure pertains. The terms used herein in the specification of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items. In the embodiments of the present disclosure, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first", "second", "third" and "fourth" may explicitly or implicitly include one or more of such features.

[0036] It should be understood that in the description of the embodiments of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements.

[0037] The terms involved in the embodiments of this disclosure are explained as follows:

[0038] A stacked power amplifier (Stack PA) is a technology used to improve the output power and efficiency of power amplifiers. It achieves higher voltage operation by stacking multiple transistors together, allowing each transistor to share a portion of the voltage. A stacked PA consists of multiple transistors connected in series, with the drain of each transistor connected to the source of the next. In this way, the supply voltage is distributed among the transistors, allowing the entire stack structure to withstand higher voltages.

[0039] A common-gate (CG) transistor is a basic circuit configuration. The gate of a common-gate transistor serves as the common input and output terminal, connected to ground or a fixed DC voltage. The source serves as the input terminal, and the drain serves as the output terminal. The gate is typically connected to ground or a fixed potential via a DC bias voltage. Common-gate transistors have the characteristics of low input impedance, high output impedance, and high voltage gain.

[0040] Common-source (CS) is a basic transistor circuit configuration. The source of a common-source transistor serves as the common terminal for input and output signals and is connected to ground or a fixed DC voltage. The gate serves as the input terminal, and the drain serves as the output terminal. Common-source transistors have the characteristics of high input impedance, high output impedance, and high voltage gain.

[0041] For a stacked power amplifier, the first-stage transistors have a common-source connection structure, and the other transistors have a common-gate connection structure.

[0042] Output Power at 1dB Compression Point (OP1dB) is a key performance indicator for power amplifiers. It represents the output power when the amplifier's gain decreases by 1dB relative to the small-signal gain. Improving OP1dB means the power amplifier can maintain linear operation at higher output powers.

[0043] Linearity is a key performance metric in wireless communications and radio frequency systems, describing the ability of a power amplifier (PA) to maintain a linear relationship between its input signal and its output. Specifically, transmit linearity refers to the degree to which the amplitude and phase relationships between the input and output signals of a PA or transmitter remain linear.

[0044] Saturation output power (Psat) is a key performance indicator of a power amplifier. It indicates the output power at which the input power of the power amplifier no longer increases significantly with the increase of input power or remains basically unchanged after the input power increases to a certain level.

[0045] Figure 1A A schematic diagram of a stacked power amplifier is shown. The stacked power amplifier includes four stacked transistors (M1-M4). The transistors here are NMOS transistors as an example. The source of the first-stage transistor M1 is grounded, and the drain is connected to the source of the second-stage transistor M2; the drain of the second-stage transistor M2 is connected to the source of the third-stage transistor M3; the drain of the third-stage transistor M3 is connected to the source of the fourth-stage transistor M4; and the drain of the fourth-stage transistor M4 is connected to the power supply terminal V through an inductor L. DD At the same time, the drain of the fourth-stage transistor M4 is also connected to the radio frequency output terminal RFout through the output capacitor C0.

[0046] In addition, the control electrode (gate) of the first-stage transistor M1 is connected to the input capacitor C1 and receives the RF input signal RFin through Cin. In addition, the control electrode of the first-stage transistor M1 is also connected to the first resistor R1 and receives the first bias voltage Vg1 through the first resistor R1.

[0047] The control electrodes (gates) of the second to fourth transistors M2 - M4 are grounded through gate grounding capacitors C2 , C3 , and C4 , respectively, and are connected to the second resistor R2 to the fourth resistor R4 , respectively, and receive the second bias voltage Vg2 to the fourth bias voltage Vg4 .

[0048] By proper bias and load design, combined with V DD By choosing the right number of transistors, you can achieve a uniform voltage distribution across the different layers of transistors. In principle, the maximum voltage swing that the PA can withstand as a whole is close to the drain-source breakdown voltage of a single device multiplied by the number of stacked transistor layers.

[0049] V DD The voltage can be some fixed value, such as 1.8V, 3.3V, 5V, etc. For example, if the V DD The voltage is 3.3V. For full-swing applications, the maximum voltage swing is about 2V. DDIf a three-layer transistor stack is chosen, the maximum voltage swing of each transistor layer reaches 2.2V. For transistors with a 1.2V threshold voltage, a maximum voltage exceeding 2V may significantly affect the service life. Therefore, a four-layer transistor stack is required. In this case, the maximum voltage of each transistor layer is 1.65V, which is less than the 2V limit and therefore does not fully utilize the maximum swing performance of the transistor.

[0050] By adjusting the PA's V DD Voltage can improve the key performance of PA. For linear working scenarios, such as communication systems, raising the V DD Voltage can increase the OP1dB of the transmission and improve the transmission linearity. For saturated working scenarios, such as radar applications, raising the V DD Voltage can increase the emission of P sat (saturated output power). It should be noted that the V DD is chosen relative to any conventional V DD Voltage (such as 1.8V, 3.3V, 5V) Higher power supply voltage.

[0051] When the circuit is working, the maximum voltage between the drain and source of the transistor may not reach the drain-source breakdown voltage of the transistor, and there is room for improvement. Therefore, there will be some independent pull-up of the PA V DD To achieve the performance improvement demand. However, directly raising V DD Failure to adjust the PA bias voltage will result in uneven voltage distribution across transistors on different layers. On the one hand, excessive voltage swings in a particular layer can lead to transistor breakdown in that layer. On the other hand, uneven transistor voltage distribution can reduce maximum output power and amplifier efficiency, impacting performance.

[0052] Based on the above Figure 1A It can be understood that in the four-stage stacked transistor, transistors M2-M4 are connected in a common gate mode, and transistor M1 is connected in a common source mode. If the four-stage transistors are evenly divided, the drain voltages Vd1 to Vd4 of transistors M1-M4 will increase proportionally to 1 / 4V. DD , 1 / 2V DD , 3 / 4V DD , and V DD .

[0053] If you pull up V DD The drain voltage of the last transistor M4 connected to the power supply terminal increases directly, but its source voltage does not change much, resulting in an unbalanced voltage distribution of each transistor. The inventors of this solution have found that by adjusting the bias voltage of the gate of each transistor, the drain voltage of each transistor can be restored to increase by 1 / 4V.DD ratio, thereby further making the transistor voltage division equal.

[0054] Furthermore, the gate of the first-stage transistor M1 receives the RF signal RFin, and its source is grounded to GND. The drain of the fourth-stage transistor M4 serves as an output terminal, outputting the amplified RF signal RFout. The gate capacitor C1 of the first-stage transistor M1 and the capacitor C0 at the output terminal function as DC isolation, while the resistor R1 provides bias and isolates the RF signal. The gate resistors R2-R4 of the second- to fourth-stage transistors M2-M4 provide bias and isolate the RF signal, while the gate capacitors C2-C4 reduce the transistor drain-to-gate voltage Vgd and source-to-drain voltage Vds.

[0055] It should be noted that there is a parasitic Cgs capacitance between the gate and source of the transistor, such as Figure 1B As shown, Figure 1B Taking the second-stage transistor M2 as an example, the voltage division relationship between the parasitic capacitance Cgs2 and the gate grounding capacitance C2 is shown. The gate grounding capacitance C2 can form a voltage divider with Cgs2 to divide the source voltage Vs2. Since the gate-source voltage Vgs and the gate-drain voltage Vgd also have voltage swing limitations, there is also a certain signal swing on the gate, and the gate voltage fluctuates with the source and drain. Therefore, compared with the method of directly grounding the gate, this voltage division method can reduce the gate-source voltage Vgs and the gate-drain voltage Vgd of the transistor, thereby making the drain-source voltage Vds (such as Figure 1B The difference between Vd2 and Vs2 shown in FIG can have a larger swing range.

[0056] Based on the above analysis, the embodiment of the present disclosure provides a voltage divider adjustment circuit for a stacked power amplifier, such as Figure 2A As shown, the stacked power amplifier includes multiple stacked transistors Mi (i is a positive integer, i is 1 to 4 in the figure as an example), the output of the previous transistor Mi-1 is connected to the input of the next transistor Mi; the gate of each transistor Mi receives its own bias voltage Vg1-Vg4, and the gates of transistors other than the first stage are connected to ground with grounding capacitors C2-C4. The multiple stacked transistors can include two or more, and the embodiment of the present disclosure uses four as an example for description. The voltage divider regulation circuit includes:

[0057] The voltage swing detection module 110 is used to detect the voltage swing between the input and output terminals of the transistor. The voltage swing detection module 110 includes a voltage detection unit 111 and a difference unit 112. The voltage detection unit 111 is connected to the output terminal of each transistor and detects the voltage level of the transistor output terminal based on the signal power or amplitude of the transistor output terminal to obtain multiple corresponding output voltages. The difference unit 112 is connected to the output terminal of the voltage detection unit 111 and takes the difference of adjacent output voltages to obtain the voltage swing between the input and output terminals of the transistor.

[0058] The swing comparison module 120 is connected to the output terminal of the voltage swing detection module, compares the voltage swings of the two transistors, and outputs a calculation result; the swing comparison module 120 is connected to the control module 130, and the control module 130 outputs a control signal based on the calculation result;

[0059] The adjustment module 140 is connected to the control terminal of the transistor Mi and is used to control the bias voltage of the control terminal of the transistor Mi and / or control the capacitance of the grounding capacitor of the control terminal of the transistor Mi according to the control signal.

[0060] Because the voltage swing detection module 110 can automatically detect the voltage swing of the transistors M1-M4 in the stacked power amplifier in real time, the swing comparison module 120 can compare the size of the voltage swings of the two transistors in real time to detect whether the voltage swings of different transistors Mi are equal. Once the voltage swings of the transistors Mi are not equal, it means that the voltage division of the transistors M1-M4 is uneven. At this time, the bias voltage of the transistor and / or the capacitance value of the ground capacitor can be adjusted accordingly to adjust the voltage division of the transistor, and the voltage division adjustment of the stacked power amplifier is automatically achieved, so that the difference in the voltage swing of the transistors is reduced or even eliminated, thereby achieving uniform voltage division, reducing the risk of transistor breakdown caused by uneven voltage distribution, and improving the amplifier efficiency and linearity.

[0061] Among them, adjusting the bias voltage of the transistor can change the DC bias of the transistor, thereby changing the DC reference voltage value in the transistor output signal to change the voltage division of the transistor and achieve uniform voltage division.

[0062] For transistors in a stacked power amplifier with a common gate, there are capacitors C2-C4 connecting the gate to ground. These capacitors, along with the parasitic capacitance between the transistor's gate and source, form a voltage divider. The AC voltage on the gate depends on the values ​​of these two capacitors. Therefore, adjusting the capacitance of the transistor's gate-to-ground capacitors can change the AC voltage amplitude in the transistor's overall gate voltage, thereby adjusting the voltage divider for a more uniform voltage distribution.

[0063] Here, voltage swing refers to the amplitude of the voltage difference between the input and output terminals of transistor Mi. Voltage swing detection module 110 is used to detect the voltage swing of each transistor and output the voltage swing as an output signal. Therefore, voltage swing detection module 110 has multiple output terminals, each of which outputs a voltage swing signal for each transistor Mi.

[0064] The swing comparison module 120 can be connected to a control module 130. It is understood that the control module 130 can receive the calculation results output by the swing comparison module 120 and, after processing, output a corresponding control signal. This control signal can be used to control the voltage value of the control terminal of the transistor, including at least one of the bias voltage of the transistor control terminal and the capacitance of the ground capacitor of the transistor control terminal. In some embodiments, the control module 130 can be located on the same chip as the stacked power amplifier; in other embodiments, the control module 130 and the stacked power amplifier can be located on different chips.

[0065] In addition, the voltage divider regulation circuit provided in the embodiments of the present disclosure may further include an adjustment module 140. The adjustment module 140 is connected to the control terminal of each transistor Mi and can receive a control signal. The adjustment module 140 can output a bias voltage to the control terminal of one or more transistors Mi or adjust the capacitance value of the ground capacitor based on the control signal.

[0066] Exemplarily, the adjustment module 140 can be used to output a gate bias voltage for each common-gate transistor M2-M4. Upon receiving a control signal, the adjustment module 140 can change the current bias voltage according to the control signal, for example, by increasing or decreasing the bias voltage corresponding to the control signal from the original bias voltage. Similarly, the adjustment module 140 can be used to control the capacitance of the grounding capacitor at the control terminal of each common-gate transistor M2-M4, thereby adjusting the transistor voltage divider.

[0067] The embodiment of the present disclosure provides a specific structure of a voltage divider adjustment circuit of a stacked power amplifier. Figure 2B As shown, the main amplifier circuit in the dashed box serves as a stacked power amplifier, with the output terminals of each transistor Mi connected to the voltage swing detection module 110. In this embodiment, the adjustment module 140 controls both the bias voltage of the transistor control terminal Mi and the capacitance of the ground capacitor at the control terminal of the transistor Mi. Specifically, the swing comparison module 120 outputs a first comparison result and a second comparison result, wherein the comparison accuracy of the first comparison result is lower than that of the second comparison result. The first comparison result is used to achieve coarse adjustment of the voltage swing distribution of each transistor, and the second comparison result is used to achieve fine adjustment of the voltage swing distribution of each transistor.

[0068] The control module 130 includes a first counter 131 and a second counter 133, each for counting the first comparison result and the second comparison result, respectively. The adjustment module 140 includes a bias voltage calibration unit 141 and a capacitance calibration unit 142. The first comparison result is processed by the first counter 131 in the control module 130 and provided to the bias voltage calibration unit 141 to adjust the gate bias voltage of any transistor stage Mi (i>1). The first comparison result can also be decoded by a decoder provided in the bias voltage calibration unit 141, and then the adjusted bias voltage is provided to the control terminal of each transistor stage, thereby achieving coarse adjustment of the voltage swing distribution of each transistor. In addition, the first comparison result is processed by the second counter 133 in the control module 130 and provided to the capacitance calibration unit 142. The first comparison result can also be decoded by the decoder to output a control signal to adjust the capacitance value of the gate-to-ground capacitor array of each transistor stage Mi (i>1), thereby achieving fine adjustment of the voltage swing distribution of each transistor.

[0069] In some embodiments, as Figure 3 As shown, the voltage detection unit 111 includes: a plurality of detectors (such as Figure 3 Detectors 01 to 04 are shown (the number of detectors can be equal to the number of transistors) connected to the output terminals of the corresponding transistors Mi (the drains M1d-M4d of M1-M4) to detect the voltage at the output terminals of the transistors Mi and obtain the corresponding output voltage Vdi (Vd1-Vd4).

[0070] The transistor can be a junction field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). Due to the voltage division effect of the transistor, the output terminal of each stage of the transistor, i.e., the drain voltage, increases proportionally, thereby achieving the amplification of the RF signal. Figure 3 The voltage swing detection module 110 can compare the output voltages Vdi of two adjacent transistors or take the difference to obtain the voltage swing of each transistor.

[0071] A detector is an electronic device or circuit typically used to extract the original signal from a modulated signal. It can separate the low-frequency modulated signal from a high-frequency carrier signal, or convert the amplitude or power of a high-frequency RF signal into a DC voltage signal for output. In the disclosed embodiments, an RMS (root mean square) detector can be used. This detector performs square, average, and square root operations on multiple sampled values ​​of the input signal, ultimately outputting a DC voltage value that reflects the signal power. Because signal power is related to signal amplitude, the DC voltage output by the RMS detector can reflect the voltage value of the transistor output signal and can be used to determine the transistor's voltage divider.

[0072] The difference unit 112 includes: a plurality of first subtractors (such as Figure 3 The first subtractors 01 to 04 are shown as follows, which are used to perform a difference based on the detected output voltages and output multiple voltage swings; the first input terminal of the first first subtractor is grounded, and the second input terminal is connected to the output terminal of the first detector; the first input terminals and second input terminals of the remaining first subtractors are respectively connected to the output terminals of adjacent detectors.

[0073] Thus, the plurality of first subtractors perform subtraction operations on adjacent output voltages Vd1-Vd4, determining the difference between the two, thereby obtaining voltage swings Vds1-Vds4. ​​The voltage swing Vds1 is obtained by subtracting the first output voltage Vd1 from 0V, or the first output voltage Vd1 can be directly used as the voltage swing Vds1.

[0074] In some embodiments, as Figure 4As shown, the swing comparison module 120 includes a second subtractor 121 for calculating the difference ΔVds2 between the first-stage voltage swing Vds1 and the second-stage voltage swing Vds2. The two input terminals of the second subtractor 121 are connected to the output terminals of the first-stage and second-stage first subtractors, respectively. For example, the second subtractor 121 can perform a subtraction process on the first-stage voltage swing Vds1 and the second-stage voltage swing Vds2 to obtain the difference ΔVds2. When the difference is not zero, it indicates that there is a voltage swing difference between different transistors, that is, there is an uneven voltage division between different transistors. In other embodiments, the second subtractor 121 can also be used to calculate the difference between the voltage swings of any other two stages in the multi-stage transistor. For example, the second subtractor 121 can perform a subtraction process on two adjacent stages, such as the second-stage voltage swing Vds2 and the third-stage voltage swing Vds3, or the third-stage voltage swing Vds3 and the fourth-stage voltage swing Vds4, to obtain the corresponding difference. It is also possible to perform a difference process on two non-adjacent stages, for example, the voltage swing Vds4 of the fourth stage and the voltage swing Vds1 of the first stage to obtain a difference. If the difference is not 0, it also indicates that there is a voltage swing difference between different transistors. Since the control terminal voltage of the first stage transistor is the input voltage, it is not the object of regulation. Figure 4 In the example, the difference ΔVds2 between the first-level voltage swing Vds1 and the second-level voltage swing Vds2 is used as a criterion for determining whether voltage sharing is achieved.

[0075] The swing difference refers to the difference signal of the voltage swing of adjacent transistors Mi. The larger the swing difference, the more uneven the voltage division between the transistors. The smaller the swing difference, the more uniform the voltage division between the adjacent transistors.

[0076] It should be noted that the swing difference here can be the voltage swing difference between any two transistors, for example, the voltage swing difference between the first-stage transistor M1 and the second-stage transistor M2, or the voltage swing difference between the second-stage transistor M2 and the third-stage transistor M3, etc.

[0077] The swing comparison module 120 also includes a first comparator 122. A first input of the first comparator 122 is connected to a set voltage signal terminal (the set voltage signal terminal is used to input the set voltage Vo1 to the first input terminal), and a second input is connected to the output terminal of the second subtractor 121. The first comparator 122 is configured to compare the difference ΔVds2 with the set voltage Vo1 and output a first comparison result. The first comparison result is a logic signal that can be either a high level or a low level. The output level varies depending on the magnitude of the difference ΔVds2 and the set voltage Vo1. For example, if the difference ΔVds2 is greater than the set voltage Vo1, the comparator outputs a high level; if the difference ΔVds2 is less than the set voltage Vo1, the comparator outputs a low level.

[0078] It is understood that the set voltage Vo1 can serve as a reference for determining whether the voltage swings at different levels are equal. For example, when the first comparator 122 compares the difference ΔVds2 with the set voltage Vo1, if the difference ΔVds2 is greater than the set voltage Vo1, the first-level voltage swing Vds1 and the second-level voltage swing Vds2 are considered unequal; if the difference ΔVds2 is less than or equal to the set voltage Vo1, the first-level voltage swing Vds1 and the second-level voltage swing Vds2 are considered equal. The value of the set voltage Vo1 depends on the accuracy of the comparison; the smaller the discernible difference ΔVds2, the higher the accuracy. For example, the value of the set voltage Vo1 can be the minimum adjustment range of the transistor gate bias voltage, that is, the minimum value of each adjustment. If the difference ΔVds2 is less than or equal to Vo1, even if the difference ΔVds2 is not zero, it is difficult to adjust the gate bias voltage. Therefore, the first comparison result is output as a low level, indicating that the transistor bias voltage does not need to be adjusted at this time. Correspondingly, if the difference ΔVds2 is greater than Vo1, the difference can be reduced after adjustment, so that the transistors of each stage are roughly in a state of equal voltage sharing.

[0079] Specifically, the swing comparison module 120 may further include a plurality of second comparators 123, such as Figure 4 As shown, the second comparator 123 is used to compare the voltage swings Vds2-Vds4 of each transistor Mi (i>1) with the voltage swing Vds1 of the first-stage transistor M1. The input of the second comparator 123 is connected to the first subtractor of the first-stage transistor M1 and to the output of the first subtractor of any other transistor Mi. The output of the second comparator 123 outputs a second comparison result. Because the second comparison result is based on a direct comparison of the voltage swings of adjacent transistors, the second comparison result has greater accuracy than the first comparison result. The second comparison result includes: the comparison result of Vds2 with Vds1, the comparison result of Vds3 with Vds1, and / or the comparison result of Vds4 with Vds1. The second comparison result is a logic signal that can be high or low, outputting different levels based on the magnitude relationship between the two voltage swings (e.g., Vds2 and Vds1). The operation result may also include the second comparison result, which is used to adjust the capacitance value of the grounding capacitor. The second comparison result can indicate whether there is a voltage swing difference between the transistors after the second stage and the first stage transistors, and therefore the second comparison result can indicate whether there is uneven voltage division between different transistors. For example, any one-stage transistor can be used as a reference, and the voltage swings of the transistors of other stages can be compared with the reference transistor to determine the magnitude relationship between the two, and then make adjustments. Since the control terminal of the first-stage transistor M1 is used to receive the input RF signal RFin and is not an adjustment object, the reference transistor is set to the first-stage transistor M1 here for ease of adjustment and detection.

[0080] According to the second comparison result, by adjusting the grounding capacitance of the gate, the voltage division of the gate parasitic capacitance can be adjusted, and then the voltage division of the transistor can be adjusted so that the voltage division of each level of transistor is basically consistent with the voltage division of the reference transistor, thereby achieving equal distribution.

[0081] In some embodiments, as Figure 5 As shown, the control module accumulates the count value according to the first comparison result and the second comparison result through the closed-loop feedback of the counter and the decoder to dynamically adjust the transistor bias voltage and / or capacitance value until the first comparison result and the second comparison result meet the requirements, thereby realizing automatic adjustment of the bias voltage and capacitance value.

[0082] The control signal includes a first sub-control signal and a second sub-control signal. The first comparison result is used for the control module to output the first sub-control signal, and the first sub-control signal is used to adjust the bias voltage; the second comparison result is used for the control module to output the second sub-control signal, and the second sub-control signal is used to adjust the capacitance value.

[0083] like Figure 5 As shown, the control module 130 includes: a first counter 131 and a first decoder 132;

[0084] The first counter 131 may be connected to the first comparator 122 and count the number of times that the first comparison result output by the first comparator 122 indicates that the difference ΔVds2 is greater than the set voltage Vo1 (eg, a high level or a low level);

[0085] The first decoder 132 is used for decoding the first count value of the first counter 131 to obtain a first sub-control signal for controlling the bias voltage of the transistor.

[0086] The first count value is used to control the bias voltage. For example, each first count value corresponds to a bias voltage. Therefore, the first count value can be decoded by the first decoder 132 according to a preset decoding rule to obtain the desired first sub-control signal and adjust the bias voltage accordingly. It should be noted that the first count value here can be one or more. For example, multiple first count values ​​corresponding to different stages of transistors can be used to adjust the bias voltages of different transistors.

[0087] In one embodiment, if ΔVds2 is greater than the set voltage Vo1, the first comparator 122 outputs a high level, the first count value of the first counter 131 is incremented by 1, and the first decoder 132 outputs a corresponding decoding result based on the current first count value. This decoding result serves as a first sub-control signal for adjusting the bias voltage at the control terminal of transistor M1. The adjustment module 140 applies this bias voltage to the corresponding transistor control terminal. The first comparator 122 then continues to perform comparisons. If the output remains high, the first count value of the first counter 131 is incremented by 1 again. The first decoder 132 outputs a corresponding first sub-control signal based on the current first count value, continuing to adjust the bias voltage at the control terminal of transistor M1. It will be understood that the bias voltage at this point is different from the previous bias voltage. Until the output of the first comparator 122 reaches a low level, the first count value of the first counter 131 no longer increases, and the bias voltage remains unchanged. At this point, the bias voltage adjustment is considered complete. After adjustment, the first count value can also be cleared.

[0088] In some embodiments, as Figure 5 As shown, the control module 130 further includes: a second counter 133 and a second decoder 134;

[0089] The second counter 133 is configured to count when the second comparison result indicates that the voltage swings of the transistors are not equal;

[0090] The second decoder 134 is configured to decode the second count value of the second counter 133 to obtain a second sub-control signal for controlling the capacitance value of the grounding capacitor.

[0091] In other embodiments, the first decoder and the second decoder may also be located in the adjustment module. Specifically, the first decoder may be disposed in the bias voltage calibration unit of the adjustment module, and the second decoder may be disposed in the capacitance calibration unit of the adjustment module.

[0092] The second comparison result is the comparison of the voltage swing Vdsi of any transistor Mi with the voltage swing Vds1 of the reference transistor (e.g., first-stage transistor M1). Multiple comparisons can be performed, with each comparison outputting a second comparison result. For example, when Vdsi > Vds1, a high level (or low level) is output, and the second counter performs a count. Next, the second decoder 134 decodes the current second count value, determines the second sub-control signal for controlling the capacitance, and adjusts the capacitance. The comparison continues. If Vdsi still exceeds Vds1, a high level (or low level) is output, the second counter 133 continues counting, and the second decoder 134 continues decoding the current second count value to obtain an updated second sub-control signal, which adjusts the capacitance again. The comparison is repeated until Vdsi ≤ Vds1, at which point a low level (or high level, i.e., a level different from the output level before the change) is output. The second counter 133 stops counting, and the second decoder 134 stops updating and decoding, and adjusts the capacitance using the current second sub-control signal. On the contrary, if the first comparison result obtained at the beginning of the comparison is Vdsi<Vds1, a high level (or low level) can also be output, the second counter 133 counts, and the second decoder 134 decodes to update the capacitance value, and the comparison is repeated until the second comparison result changes to Vdsi≥Vds1 and switches to output a low level (or high level, that is, different from the output level before the change), the second counter 133 stops counting, the second decoder 134 stops updating and decoding, and uses the current second sub-control signal to control the adjustment of the capacitance value.

[0093] That is, regardless of whether the second comparison result obtained from the first comparison is greater than or less than, counting and decoding are required to adjust the capacitance value until the second comparison result changes. At this point, it means that the adjustment limit has been reached, so no further adjustment is required.

[0094] It should be noted that if the second comparison result obtained by the first comparison is Vdsi=Vds1, no adjustment is required. Therefore, the second counter 133 does not need to count at this time.

[0095] In some embodiments, the amplitude comparison module includes multiple second comparators, and the control module 130 includes multiple second counters 133 and multiple second decoders 134. Each second comparator corresponds to a second counter 133 and a second decoder 134, which are used to count the second comparison results of the corresponding comparator. For example, Figure 4 The system includes three second comparators 134 , each of which corresponds to a second counter 133 and a second decoder 134 , and each second decoder 134 is used to adjust the capacitance value of a grounding capacitor of a transistor M2 .

[0096] It should be noted that the equality in this solution refers to approximate equality, and a certain error is allowed.

[0097] It should be noted that the first counter 131 and the second counter 133 in the control module 130 can be counters of the same specifications, or can be the same counter. Furthermore, the first decoder 132 and the second decoder 134 can be decoders of the same specifications, or can be the same decoder. If only one counter and one decoder are provided, then when adjusting the bias voltage of the transistor control terminal, the counter acts as the first counter 131, implementing the function of the first counter 131, and the decoder acts as the first decoder 132, implementing the function of the first decoder 132. When adjusting the capacitance value of the grounding capacitor at the transistor control terminal, the counter acts as the second counter 133, implementing the function of the second counter 133, and the decoder acts as the second decoder 134, implementing the function of the second decoder 134.

[0098] In some embodiments, as Figure 6 The adjustment module 140 shown includes:

[0099] The bias voltage calibration unit 141 is connected to the control end of the transistor Mi (i>1) after the second stage and is connected to the control module 130. The bias voltage calibration unit 141 adjusts the bias voltage provided to the transistor Mi (i>1) of the second stage and thereafter based on the first sub-control signal.

[0100] The gate bias voltage of the first-stage transistor M1 determines the source-drain voltage of each transistor in each stage. That is, as part of the input signal, it is a separate control item, not an adjustment item for voltage swing equalization. Therefore, the first-stage transistor M1 can be used as a reference transistor, and there is no need to adjust the voltage of its control terminal to adjust the voltage division of the transistor. In order to achieve voltage equalization of the transistors in each stage, the bias voltage of the control terminal of other transistors Mi (i>1) other than the reference transistor can be adjusted. Therefore, the bias voltage calibration unit 141 can be connected only to the control terminal of each transistor after the second stage, without connecting to the control terminal of the first-stage transistor M1.

[0101] In some embodiments, during each calibration, the bias voltage calibration unit adjusts the bias voltages of the transistors after the second stage according to a preset boost gradient. Here, the preset boost gradient is the bias voltage adjustment ratio for each transistor stage. The bias voltage adjustment ratio increases step by step as the number of transistor stages increases, thus increasing step by step.

[0102] refer to Figure 1A The explanation is that when the voltage division of multi-stage transistors is uniform, the output Vg of each stage transistor needs to be increased by 1 / nV in sequence. DD(n>1, where n is the number of transistor stages). Accordingly, the source-gate voltage Vgs of each transistor stage must be consistent, so the gate voltage Vgi at the control terminal also needs to change proportionally. Therefore, during calibration, the bias voltages of the transistors after the second stage must be adjusted proportionally according to the preset boost gradient.

[0103] The ideal bias voltage of each transistor can be referred to the following formula (1):

[0104] ,i=2,3,...,n (1)

[0105] Among them, i is the current transistor level, n is the total number of levels, V DD is the power supply voltage, V gsi-sat The source-gate voltage Vgs is the voltage that makes the transistor saturated. DD When pulling up, in order to make the bias voltage of the transistor still meet the conditions of formula (1) and ensure voltage equalization, the gate bias voltage of each transistor after the second stage needs to be synchronously increased proportionally.

[0106] The number of bias voltage calibration units 141 can be matched with the amount of bias voltage to be adjusted. Figure 6 In the illustrated embodiment, the adjustment module 140 adjusts the bias voltage of the transistors M2-4. Therefore, the adjustment module 140 includes three bias voltage calibration units 141. The three voltage calibration units 141 can respectively receive first sub-control signals from the three first decoders 132 to adjust the bias voltages of the transistors M2-4. Specifically, the three first decoders 132 respectively perform counting based on comparisons of the difference ΔVds2 (the difference between the first-level voltage swing Vds1 and the second-level voltage swing Vds2), the difference ΔVds3 (the difference between the second-level voltage swing Vds2 and the third-level voltage swing Vds3), and the difference ΔVds4 (the difference between the third-level voltage swing Vds3 and the fourth-level voltage swing Vds4) with a set voltage.

[0107] In some embodiments, the bias voltage calibration unit 141 may be a bias circuit configured to output a corresponding bias voltage to the control terminal of the transistor Mi according to the first sub-control signal. Figure 7A As shown, the bias voltage calibration unit 141 includes:

[0108] A plurality of resistance elements r are connected in series, and adjacent resistance elements r are connected to the first end of the first switch k1; the second end of the first switch k1 is connected to the control end of the transistor Mi;

[0109] The control end of the first switch k1 is connected to the control module 130 , and the first switch k1 switches a switch state based on the first sub-control signal.

[0110] The bias voltage calibration unit 141 can use multiple resistors connected in series to use the node voltage between adjacent resistor elements r as the control terminal of the bias voltage output transistor. Each node is connected to the control terminal of the transistor via a first switch k1. The first sub-control signal of the control module 130 can be used to control the on and off of these first switches k1. Based on different first sub-control signals, different first switches k1 are selected to be turned on, thereby switching different output voltages Vx as the bias voltage Vbias.

[0111] In this embodiment, if Figure 6 The adjustment module 140 shown includes:

[0112] The capacitance calibration unit 142 is connected to the grounding capacitor and the control module. The capacitance calibration unit 142 changes the capacitance value of the grounding capacitor at the control end of the transistor based on the second sub-control signal. It should be noted that, Figure 6 The capacitors C2-C4 shown in the figure are only used to illustrate the capacitance values ​​of the grounding capacitors of each transistor stage, and do not mean that capacitor elements need to be connected at the corresponding locations. In an actual circuit, the capacitor elements can be included in the capacitor calibration unit 142 or located outside the capacitor calibration unit 142, and the capacitance value thereof can be controlled by the capacitor calibration unit 142.

[0113] In some embodiments, the capacitance calibration unit changes the capacitance of a grounded capacitor at a transistor control terminal during each calibration. Furthermore, the capacitance calibration unit may change the capacitance of a grounded capacitor at a transistor control terminal according to a preset capacitance change amount, i.e., a minimum capacitance change amount.

[0114] In some specific embodiments, Figure 7B As shown, the grounding capacitor includes multiple parallel capacitor elements c, which are connected between the control terminal of the transistor Mi and the ground. The capacitance calibration unit 142 includes multiple second switches k2, each of which is connected in series with the corresponding capacitor element c. The control terminal of the second switch k2 is connected to the control module to receive a second sub-control signal. The second switch k2 switches the switch state based on the second sub-control signal to control the number of capacitor elements c connected to the control terminal of the transistor Mi, thereby adjusting the resistance value of the grounding capacitor. When the second switch k2 is turned on, the capacitor element c connected in series with it is connected to the circuit. When the second switch is turned off, the capacitor element c connected in series with it is not connected to the circuit.

[0115] It should be noted that the capacitance values ​​of the capacitor elements in each capacitor switch group can be the same or different. For example, if the capacitance values ​​are the same, the capacitance value of the connected capacitor can be adjusted by changing the number of second switches k2 that are turned on using the second sub-control signal. If the capacitance values ​​are different, the capacitor element c connected to the circuit can be directly selected by selecting the second switch k2, and different capacitance values ​​of the ground capacitor can be selected by selecting different capacitor elements c.

[0116] The adjustment method of the voltage divider regulation circuit is as follows Figure 8A and Figure 8B As shown below, combined Figure 2A and Figure 2B Provide explanation. Figure 8A The following steps are provided for adjusting the bias voltage:

[0117] Step S101: the voltage swing detection module 110 determines the voltage swings Vds1 and Vds2 of the first-stage and second-stage transistors;

[0118] Step S102 : the amplitude comparison module 120 calculates the difference between Vds2 and Vds1 to obtain ΔVds2 ;

[0119] Step S103: The amplitude comparison module 120 determines whether ΔVds2 is less than the preset voltage Vo1. If so, the coarse adjustment is completed. If not, the process proceeds to step S105.

[0120] Step S105: The count value of the first counter 131 is increased by one: the count value p=p+1; the bias voltage calibration unit 141 is controlled according to the count value of the first counter 131. The bias voltage calibration unit 141 increases the bias voltage of the transistor M1, and can increase the bias voltage of the transistor M1 by one level (minimum adjustment range). The bias voltages of the transistors Mi (i>1) of each level are synchronously increased in proportion until ΔVds2 is less than the preset voltage Vo1, so that the divided voltages of the transistors M1-M4 are basically the same.

[0121] Figure 8B A capacitor adjustment scenario is provided, including the following steps:

[0122] Step S201 : the voltage swing detection module 110 determines the voltage swing Vds1 to Vds4 of each stage of transistor Mi (i≥1);

[0123] Step S202: The amplitude comparison module 120 compares Vds2 and Vds1 to see if they are equal. If so, the process proceeds to step S203; otherwise, the process proceeds to step S205.

[0124] Step S204: The amplitude comparison module 120 compares Vds3 and Vds1 to see if they are equal. If so, the process proceeds to step S205; otherwise, the process proceeds to step S205;

[0125] Step S204: The swing comparison module 120 compares Vds4 with Vds1 to see if they are equal. If so, fine adjustment is completed. If not, the process proceeds to step S205.

[0126] Step S205: The count value of the corresponding second counter is increased by one: count value q=q+1; for example, if Vds2 is not equal to Vds1, the count value of the second counter corresponding to transistor M2 is increased; if Vds3 is not equal to Vds1, the count value of the second counter corresponding to transistor M3 is increased; if Vds4 is not equal to Vds1, the count value of the second counter corresponding to transistor M4 is increased; and the capacitance calibration module 142 is controlled according to the count value of the second counter 133 to adjust the ground capacitance of the corresponding transistor until ΔVds2 is less than the preset voltage Vo1, so that the divided voltages of transistors M1-M4 are the same.

[0127] It is understandable that since bias voltage adjustment directly changes the gate voltage of the transistor, thereby adjusting the transistor's turn-on level, the bias voltage has a significant impact on the transistor's voltage swing. Therefore, adjusting the bias voltage can quickly achieve coarse adjustment of the voltage swing. In contrast, adjusting the transistor's gate-to-ground capacitance has a smaller impact on the transistor's voltage swing and can therefore be used for fine adjustment. Therefore, in the above embodiment, the bias voltage of each transistor stage can be adjusted first using the first comparison result output by the first comparator to achieve coarse adjustment; then, the gate-to-ground capacitance of each transistor stage can be adjusted using the second comparison result output by the second comparator to achieve fine adjustment.

[0128] Specifically, the control module 130 may further include a control unit, which is used to control the execution order of coarse adjustment and fine adjustment. For example, the control unit can be connected to the first comparator 122 and the second comparator 123 to control whether the first comparator 122 or the second comparator 123 starts counting. In the above process, the control unit can first enable the first comparator 122, and the first comparator 122 counts the comparison result of the difference △Vds2 and the preset voltage Vo1, thereby adjusting the bias voltage (coarse adjustment). Because the gate voltage of the transistors above the second stage is proportionally increased, if Vds2 is close to Vds1, then the voltage swing of other transistors will also be close to Vds1. Therefore, only Vds1 and Vds2 can be compared to simplify the judgment process. Of course, this is just an example. In practice, the voltage swings Vdsi and Vdsj of any two other transistors can be compared. Whether the comparison result is greater than the set voltage Vo1 can be used to determine whether adjustments are necessary. A significant difference in the voltage swings of any two transistors indicates that the voltage swings of the other transistors are unequal, requiring adjustment. The disclosed embodiment compares Vds2 and Vds1 because the source voltage of the first-stage transistor M1 is fixed to ground, while the source and drain voltages of the other transistors vary with the power supply voltage. Therefore, using Vds1 as the comparison object facilitates calculation.

[0129] During coarse adjustment, the adjustment module (e.g., the bias voltage calibration unit) can be connected only to the control terminal of the second-stage transistor M2 and only adjust (raise) the bias voltage of the second-stage transistor M2. Because the bias voltages of the subsequent transistors M3 and M4 are based on the bias voltage of the second-stage transistor M2, the bias voltages of the subsequent transistors M3 and M4 will also be proportionally changed (raised). Of course, in other embodiments, the gate bias voltages of other transistors Mi (i>2) can also be adjusted. However, since the second-stage transistor M2 is the lowest-level transistor with adjustable bias voltage, the adjustment range is small, making it easier to control.

[0130] After adjusting the bias voltage, the control unit can then enable the second comparator 123. The second comparator 123 counts based on the comparison result, thereby adjusting the ground capacitance of each transistor gate (fine tuning). It is understandable that since the ground capacitance only affects the voltage division of the parasitic capacitance of the transistor to which it is connected, it does not affect other transistors. Therefore, it is necessary to use multiple second comparators 123 to individually determine whether each transistor Mi (i>1) needs to be adjusted, and adjust the ground capacitance accordingly.

[0131] Figure 9A and Figure 9BA schematic diagram of the swing comparison module and the control module in another embodiment is shown. In another embodiment, the operation result output by the swing comparison module 120 includes the first comparison result but does not include the second comparison result. The first comparison result is used to adjust the bias voltage of the transistor or the capacitance value of the ground capacitor. Specifically, Figure 9A As shown, the swing comparison module 120 includes:

[0132] A second subtractor 121 is used to calculate the difference between adjacent voltage swings, and an input end of the second subtractor 121 is connected to an output end of the adjacent first subtractor;

[0133] A first comparator 122, wherein a first input terminal of the first comparator 122 is connected to the set voltage signal terminal for receiving the set voltage Vo1, and a second input terminal of the first comparator 122 is connected to the output terminal of the second subtractor 121, for comparing the difference with the set voltage Vo1 and outputting a first comparison result;

[0134] The operation result includes a first comparison result, and the first comparison result is used to adjust the bias voltage or the capacitance value.

[0135] like Figure 9B As shown, in another embodiment, the control module 130 includes a first counter 131 and a first decoder 132. The first counter 131 is connected to the first comparator 122 to receive the first comparison result. The first counter 131 and the first decoder 132 are used to generate a control signal for adjusting the bias voltage or the grounding capacitance.

[0136] If the first counter 131 and the first decoder 132 are used to generate control signals for adjusting the bias voltage, the amplitude comparison module 120 may include multiple second subtractors 121 and multiple first comparators 122, and the control module 130 may include multiple first counters 131 and multiple first decoders 132. Each transistor Mi has a corresponding set of second subtractors 121, first comparators 122, first counters 131, and first decoders 132, which are respectively used to control the gate bias voltages of the multiple transistors Mi.

[0137] If the first counter 131 and the first decoder 132 are used to generate control signals for adjusting the ground capacitance, the amplitude comparison module 120 may include multiple second subtractors 121 and multiple first comparators 122, and the control module 130 may include multiple first counters 131 and multiple first decoders 132. Each transistor Mi has a corresponding set of second subtractors 121, first comparators 122, first counters 131, and first decoders 132, respectively, for controlling the ground capacitance of the multiple transistors Mi.

[0138] Here, another implementation is provided, that is, using the second subtractor 121 to compare with the first comparator 122. Figure 4 In the method provided, the second subtractor 121 here can determine the voltage swing difference △Vds between any two adjacent transistors, that is, the two input terminals of the second subtractor 121 can be connected to the output terminals of any two adjacent first subtractors respectively. Then, the first comparator 122 compares any difference △Vds with the set voltage Vo1 to determine whether there is an uneven voltage division, and then outputs a first comparison result for adjusting the bias voltage and / or capacitance value. Compared with this method, Figure 4 The combination of coarse and fine adjustment has a simple circuit and fast adjustment speed, and is suitable for scenarios with low adjustment accuracy requirements.

[0139] Figure 10A and Figure 10B A schematic diagram of the swing comparison module and the control module in another embodiment is shown. In another embodiment, the operation result output by the swing comparison module 120 includes a second comparison result but does not include the first comparison result. The second comparison result is used to adjust the bias voltage of the transistor or the capacitance value of the ground capacitor. Specifically, Figure 10A As shown, the swing comparison module 120 includes:

[0140] a plurality of second comparators 123 for comparing the voltage swing of each stage transistor Mi (i>1) with the voltage swing of the first stage transistor M1, wherein the input of the second comparator 123 is connected to the output of the first subtractor of the first stage transistor M1 and the output of the first subtractor of any other transistor Mi, and the output of the second comparator 123 outputs a first comparison result;

[0141] The comparison signal includes a first comparison result, and the first comparison result is used to adjust the bias voltage or the capacitance value.

[0142] Here, another implementation method is provided, that is, there is no need to compare the signal value with the set voltage Vo1, but instead directly compare the voltage swing of the reference transistor (for example, the first-stage transistor M1) and the other stages of the transistor Mi. In this way, it can be determined whether there is a difference between the voltage swing of the transistors at each stage and the reference transistor. If there is a difference, for example, the first comparison result is Vdsi>Vds1, or Vdsi<Vds1, it means that the voltage division is uneven. The voltage division can be adjusted by adjusting the bias voltage and / or grounding capacitance of the transistor Mi, thereby achieving voltage equalization.

[0143] like Figure 10BAs shown, in another embodiment, the control module 130 includes a second counter 133 and a second decoder 134, wherein the second counter 133 is connected to the second comparator 123 to receive the second comparison result. The second counter 133 and the second decoder 134 are used to generate a control signal for adjusting the bias voltage or the grounding capacitance.

[0144] If the second counter 133 and the second decoder 134 are used to generate a control signal for adjusting the bias voltage, the swing comparison module 120 may include multiple second comparators 123, and the control module 130 may include multiple second counters 133 and multiple second decoders 134. Each transistor Mi has a corresponding set of second comparators 123, second counters 133, and multiple second decoders 134, which are respectively used to control the gate bias voltages of the multiple transistors Mi.

[0145] If the second counter 133 and the second decoder 134 are used to generate control signals for adjusting the ground capacitance, the swing comparison module 120 may include multiple second comparators 123, and the control module 130 may include multiple second counters 133 and multiple second decoders 134. Each transistor Mi has a corresponding set of second comparators 123, second counters 133, and multiple second decoders 134, which are respectively used to control the ground capacitance of the multiple transistors Mi.

[0146] This method is compared to Figure 4 The combination of coarse and fine adjustment has a simple circuit and is suitable for scenarios with a small adjustment range and only fine adjustment is required, such as when the power supply voltage is increased by a small amount.

[0147] The above embodiment provides a case where the voltage swing detection module 110 and the swing comparison module 120 detect and process analog signals. In another embodiment, the voltage swing detection module 110 may extract a digital signal of the voltage swing, and the swing comparison module 120 may process the digital signal. Specifically:

[0148] In some embodiments, the voltage detection unit includes: a plurality of analog-to-digital converters connected to the output terminals of corresponding transistors, configured to sample the voltage values ​​of the output terminals of the transistors and convert the voltage values ​​into digital signals.

[0149] Here, the output signal of the transistor is sampled by an analog-to-digital converter, and a digital signal is obtained after conversion for calculating the voltage swing of the transistor.

[0150] In some embodiments, the difference unit includes: one or more first calculation units connected to the output end of the analog-to-digital converter, extracting the peak-to-peak value according to the digital signal to obtain the digital voltage swing.

[0151] Based on the digital signal of the output terminal signal Vd of the transistor, the peak-to-peak value is taken to determine the maximum value and the minimum value, thereby determining the voltage swing.

[0152] In some embodiments, the swing comparison module 120 includes a second calculation unit for comparing the voltage swings and outputting a calculation result.

[0153] Exemplarily, the first calculation unit and the second calculation unit may be processors, and the processors store a software program for performing a difference operation to calculate the voltage swing and the operation result.

[0154] Whether it is an analog signal or a digital signal, the same control module 130 and adjustment module 140 can be used for coarse adjustment or fine adjustment.

[0155] The present disclosure also provides an amplifier circuit. Figure 11 As shown, the amplifier circuit 300 includes:

[0156] The stacked power amplifier 100 includes a plurality of stacked transistors, wherein the output of a preceding transistor is connected to the input of a succeeding transistor;

[0157] Any of the above voltage divider adjustment circuits 200 is connected to the stacked power amplifier 100 .

[0158] It should be understood that “some embodiments”, “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0159] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0160] The above are only implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A voltage divider adjustment circuit for a stacked power amplifier, characterized in that: The stacked power amplifier includes a plurality of stacked transistors, wherein the output end of the preceding transistor is connected to the input end of the following transistor; the voltage divider adjustment circuit includes: a voltage swing detection module, configured to detect a voltage swing between the input and output terminals of the transistors; the voltage swing detection module comprising a voltage detection unit and a difference unit, wherein the voltage detection unit is connected to the output terminals of the transistors and detects voltages at the output terminals of a plurality of the transistors based on the power or amplitude of signals at the output terminals of the transistors to obtain a plurality of corresponding output voltages; and the difference unit obtains a voltage swing between the input and output terminals of the transistors by taking a difference between adjacent output voltages; a swing comparison module connected to the output end of the voltage swing detection module, comparing the voltage swings of the two transistors and outputting a calculation result; the swing comparison module is connected to the control module, and the control module outputs a control signal based on the calculation result; An adjustment module is connected to the control terminal of the transistor and is used to control the bias voltage of the control terminal of the transistor and / or control the capacitance value of the grounding capacitor of the control terminal of the transistor according to the control signal.

2. The voltage divider regulation circuit according to claim 1, wherein: The voltage detection unit includes: a plurality of detectors, each connected to the output end of each transistor, for detecting the voltage level of the output end of the transistor.

3. The voltage divider regulation circuit according to claim 2, wherein: The difference unit includes: multiple first subtractors, used to output multiple voltage swings; the first input end of the first first subtractor is grounded, and the second input end is connected to the output end of the first detector; the first input ends and second input ends of the remaining first subtractors are respectively connected to the output ends of adjacent detectors.

4. The voltage divider regulation circuit according to claim 3, wherein: The swing comparison module includes: a second subtractor, configured to calculate the difference between any two voltage swings, wherein the input terminals of the second subtractor are respectively connected to the output terminals of the corresponding first subtractors; a first comparator, wherein a first input terminal of the first comparator is connected to a set voltage, a second input terminal of the first comparator is connected to the output terminal of the second subtractor, and is configured to compare the difference with the set voltage and output a first comparison result; a plurality of second comparators, configured to compare the voltage swing of each stage of transistors with the voltage swing of any stage of transistors, wherein the input of each second comparator is connected to the output of the first subtractor of the first stage of transistors and the output of the first subtractor of any other transistor, and the output of each second comparator outputs a second comparison result; In which, the operation result includes the first comparison result and the second comparison result, and the control signal includes a first sub-control signal and a second sub-control signal; the first comparison result is used for the control module to output the first sub-control signal, and the first sub-control signal is used to adjust the bias voltage; the second comparison result is used for the control module to output the second sub-control signal, and the second sub-control signal is used to adjust the capacitance value.

5. The voltage divider regulation circuit according to claim 3, wherein: The swing comparison module includes: a second subtractor, configured to calculate the difference between any two voltage swings, wherein an input terminal of the second subtractor is connected to an output terminal of the corresponding first subtractor; a first comparator, wherein a first input terminal of the first comparator is connected to a set voltage, a second input terminal of the first comparator is connected to the output terminal of the second subtractor, and is configured to compare the difference with the set voltage and output a first comparison result; Among them, the operation result includes the first comparison result, and the control signal includes a first sub-control signal; the first comparison result is used by the control module to output the first sub-control signal, and the first sub-control signal is used to adjust the bias voltage or the capacitance value.

6. The voltage divider regulation circuit according to claim 3, wherein: The swing comparison module includes: a plurality of second comparators, configured to compare the voltage swing of each stage of transistors with the voltage swing of any stage of transistors, wherein the input of each second comparator is connected to the output of the first subtractor of the first stage of transistors and the output of the first subtractor of any other transistor, and the output of each second comparator outputs a second comparison result; Among them, the operation result includes the second comparison result, and the control signal includes a second sub-control signal; the second comparison result is used by the control module to output the second sub-control signal, and the second sub-control signal is used to adjust the bias voltage or the capacitance value.

7. The voltage divider regulation circuit according to claim 4 or 5, characterized in that: The second subtractor is configured to calculate the difference between adjacent voltage swings.

8. The voltage divider regulation circuit according to claim 4 or 6, characterized in that: The second comparator is used to compare the voltage swing of each stage transistor with the voltage swing of the first stage transistor.

9. The voltage divider regulation circuit according to claim 4 or 5, characterized in that: Also includes: a first counter and a first decoder; The first counter is configured to count when the first comparison result indicates that the difference is greater than the set voltage; The first decoder is used for decoding according to the first count value of the first counter to obtain the first sub-control signal.

10. The voltage divider regulation circuit according to claim 9, wherein: The first counter and the first decoder are both located in the control module; or the first counter is located in the control module, and the first decoder is located in the adjustment module.

11. The voltage divider regulation circuit according to claim 4 or 6, characterized in that: The control module includes: a second counter and a second decoder; The second counter is configured to count when the second comparison result indicates that the voltage swings of the transistors are not equal; The second decoder is used for decoding according to the second count value of the second counter to obtain the second sub-control signal.

12. The voltage divider regulation circuit according to claim 11, wherein: The second counter and the second decoder are both located in the control module; or the second counter is located in the control module, and the second decoder is located in the adjustment module.

13. The voltage divider regulation circuit according to claim 1, wherein: The voltage detection unit includes: a plurality of analog-to-digital converters connected to the output ends of the corresponding transistors, and used for sampling the voltage values ​​of the output ends of the transistors and converting them into digital signals.

14. The voltage divider regulation circuit according to claim 13, wherein: The difference unit includes: a first calculation unit connected to the output end of the analog-to-digital converter, extracting a peak-to-peak value according to the digital signal to obtain the voltage swing.

15. The voltage divider regulation circuit according to claim 14, wherein: The swing comparison module includes a second calculation unit, which is used to compare the magnitudes of the transistor voltage swings and output the calculation result.

16. The voltage divider regulation circuit according to claim 1, wherein: The adjustment module includes: A bias voltage calibration unit is connected to the control terminal of the transistor after the second stage and is connected to the control module. The bias voltage calibration unit adjusts the bias voltage provided to the transistor after the second stage based on the control signal.

17. The voltage divider regulation circuit according to claim 16, wherein: The bias voltage calibration unit includes: a plurality of resistance elements connected in series, wherein adjacent resistance elements are connected to a first end of a first switch; a second end of the first switch is connected to a control end of the transistor; The control end of the first switch is connected to the control module, and the first switch switches a switch state based on the control signal.

18. The voltage divider regulation circuit according to claim 1, wherein: The adjustment module includes: A capacitance calibration unit is connected to the grounding capacitor and the control module, and the capacitance calibration unit changes the capacitance value of the grounding capacitor based on the control signal.

19. The voltage divider regulation circuit according to claim 18, wherein: The grounding capacitor includes a plurality of parallel-connected capacitor elements, each of which is connected between the control terminal of the transistor and the ground; The capacitance calibration unit includes multiple second switches, which are connected in series with the capacitance elements. The control ends of the second switches are connected to the control module. The second switches switch states based on the control signal to control the number of the capacitance elements connected to the control ends of the transistors.

20. An amplifier circuit, characterized in that: include: A stacked power amplifier comprising a plurality of stacked transistors, wherein the output end of a preceding transistor is connected to the input end of a succeeding transistor; The voltage divider regulation circuit according to any one of claims 1 to 19, connected to the stacked power amplifier.

Images