Level shifter circuit

Abstract

A level shifter circuit includes a semiconductor substrate (226), a first ground terminal (GNDA), a second ground terminal (GNDB), a driver circuit (110), a capacitor (218), a receiver circuit (112), and a substrate bias circuit (216). A driver circuit (110) is on a semiconductor substrate (226). A driver circuit (110) is coupled to a first ground terminal (GNDA) and has a first output and a second output. A capacitor (218) has a first terminal coupled to the first output of the driver circuit (110) and a second terminal. A receiver circuit (112) is on the semiconductor substrate (226). A receiver circuit (112) is coupled to a second ground terminal (GNDB) and has a first input coupled to a second terminal of the capacitor (218) and a second input coupled to a second output of the driver circuit (110). A substrate bias circuit (216) has a first input coupled to the first ground terminal (GNDA), a second input coupled to the second ground terminal (GNDB), and an output coupled to the semiconductor substrate (226).

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 626,213, filed on January 29, 2024, entitled "Voltage Level Shifters with GND Shift Tolerance", which is hereby incorporated by reference herein. Technical Field

[0003] This disclosure generally relates to a semiconductor, and more particularly to a level shifter circuit. Background Art

[0004] Electronic systems often have circuits that are powered by different supply voltages or require different signal levels to activate circuit components. In such systems, level shifter circuits (level shifters) are used to convert a signal from one voltage level to another. For example, a level shifter can be used to convert a signal from a lower voltage to a higher voltage, or from a higher voltage to a lower voltage. Summary of the Invention

[0005] In one example, a circuit includes a semiconductor substrate, a first ground terminal, a second ground terminal, a driver circuit, a capacitor, a receiver circuit, and a substrate bias circuit. The driver circuit is located on the semiconductor substrate. The driver circuit is coupled to the first ground terminal and has a first output and a second output. The capacitor has a first terminal and a second terminal, with the first terminal coupled to the first output of the driver circuit. The receiver circuit is located on the semiconductor substrate. The receiver circuit is coupled to the second ground terminal and has a first input coupled to the second terminal of the capacitor and a second input coupled to the second output of the driver circuit. The substrate bias circuit has a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.

[0006] In another example, a circuit includes a semiconductor substrate, a first ground terminal, a second ground terminal, a driver circuit, a receiver circuit, a first capacitor, a second capacitor, and a substrate bias circuit. The driver circuit is coupled to the first ground terminal. The driver circuit includes a transmitter having a first output and a second output. The receiver circuit is coupled to the second ground terminal. The receiver circuit includes a pulse receiver having a first input and a second input. The first capacitor has a first terminal coupled to the first output of the transmitter and a second terminal coupled to the first input of the pulse receiver. The second capacitor has a first terminal coupled to the second output of the transmitter and a second terminal coupled to the second input of the pulse receiver. The substrate bias circuit has a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.

[0007] In another example, a system includes a first ground terminal, a second ground terminal, a first circuit, a second circuit, and a level shifter integrated circuit. The first circuit is coupled to the first ground terminal. The first circuit has an output for providing an output signal. The second circuit is coupled to the second ground terminal. The second circuit has an input. The level shifter integrated circuit has an input coupled to the output of the first circuit and an output coupled to the input of the second circuit. The level shifter integrated circuit includes a semiconductor substrate, a driver circuit, a capacitor, a receiver circuit, and a substrate bias circuit. The driver circuit is located on the semiconductor substrate. The driver circuit is coupled to the first ground terminal and has an input coupled to the input of the level shifter integrated circuit, a first output, and a second output. The capacitor has a first terminal and a second terminal, with the first terminal coupled to the first output of the driver circuit. The receiver circuit is located on the semiconductor substrate. The receiver circuit is coupled to the second ground terminal and has a first input coupled to the second terminal of the capacitor, a second input coupled to the second output of the driver circuit, and an output coupled to the output of the level shifter integrated circuit. The substrate bias circuit has a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an example system that includes circuits operating differently that communicate via a level shifter.

[0009] Figure 2 is Figure 1 a block diagram of an example of a level shifter.

[0010] Figure 3 is a block diagram of a portion of a level shifter that includes an example high-speed signal circuit Figure 2 of.

[0011] Figure 4 is Figure 2Schematic diagram of an example circuit system of a low-speed data circuit of a level shifter.

[0012] Figure 5 includes Figure 2 Cross-sectional view of an example integrated circuit of a level shifter.

[0013] Figure 6 is Figure 2 Schematic diagram of an example substrate bias circuit of a level shifter.

[0014] Figure 7 is Figure 2 Block diagram of an example logic circuit of the level shifter shown. Detailed implementation

[0015] Figure 1 Block diagram of a system 100 that includes circuits that operate differently. System 100 includes a circuit 102, a circuit 104, and a level shifter 106. Circuit 102 is coupled to a first power supply terminal (VCCA) and a first reference terminal (GNDA). Circuit 104 is coupled to a second power supply terminal (VCCB) and a second reference terminal (GNDB). The voltage at GNDA can be different from the voltage at GNDB. Similarly, the voltage between VCCA and GNDA can be different from the voltage between VCCB and GNDB. Circuit 102 has an output terminal and provides an output signal 114. The circuit 102 can be any circuit that provides an output signal. For example, circuit 102 can be a processor, such as a microcontroller, and the output signal 114 can be any signal provided by the processor (e.g., a serial communication signal). Circuit 104 has an input terminal for receiving a signal 116 provided by the level shifter 106. The signal 116 can be the output signal 114 shifted to the voltages provided at VCCB and GNDB. Circuit 104 can be any circuit that communicates with circuit 102 via the output signal 114. For example, circuit 104 can be an audio amplifier or any other circuit controlled by circuit 102.

[0016] The level shifter 106 receives the output signal 114 and generates the signal 116 by shifting the output signal 114 from the voltages at VCCA and GNDA to the voltages at VCCB and GNDB. The level shifter 106 is an integrated circuit that includes the die 108. The die 108 includes the driver circuit 110 and the receiver circuit 112. The driver circuit 110 is coupled to VCCA and GNDA. The receiver circuit 112 is coupled to VCCB and GNDB. Thus, the driver circuit 110 is located in the first ground domain 111 of the die 108, and the receiver circuit 112 is located in the second ground domain 113 of the die 108. A ground domain is an area in a die where circuits are coupled to a given ground terminal. For example, the circuits in the first ground domain 111 are coupled to GNDA, and the circuits in the second ground domain 113 are coupled to GNDB. Different ground domains can be isolated from each other by an isolation structure (e.g., an isolation trench filled with an insulator such as oxide). The driver circuit 110 receives the output signal 114 and generates the output signal 118, which is provided to the receiver circuit 112 across the ground domains of the driver circuit 110 and the receiver circuit 112.

[0017] Level shifter circuits typically shift signals across VCC domains but not across GND domains. Such level shifter circuits cannot provide ground level conversion or accommodate any differences in the grounds of the circuits coupled to the input and output of the level shifter circuit (e.g., DC shifts or AC bounces). An isolator circuit constructed as a multi-chip module can provide signal transmission across ground domains, but the need for multiple dies makes such circuits complex and expensive. The level shifter 106 provides signal transmission across ground domains while tolerating DC or AC voltage differences between the grounds, using a single die to reduce circuit complexity and cost.

[0018] Figure 2 is a block diagram of an example of the level shifter 106. The level shifter 106 includes the driver circuit 110, the receiver circuit 112, the substrate bias circuit 216, the capacitors 218 and 220. The driver circuit 110 and the receiver circuit 112 are disposed on a single semiconductor substrate 226 (e.g., a silicon substrate). The driver circuit 110 is coupled to VCCA and GNDA. The receiver circuit 112 is coupled to VCCB and GNDB. The driver circuit 110 has an input terminal (I / P) for receiving the input signal to be level shifted. The driver circuit 110 includes the transmitter 202, the pull current circuit 204, and the sink current circuit 206. The receiver circuit 112 has an output terminal (O / P) for providing the level shifted signal. The receiver circuit 112 includes the pulse receiver 208, the detector 210, and the output circuit 212.

[0019] Transmitter 202, capacitors 218, 220, and pulse receiver 208 are coupled in a high-speed data circuit that transfers the edges of an input signal received at I / P from driver circuit 110 to receiver circuit 112. Transmitter 202 has a differential output that is coupled to the differential inputs of pulse receiver 208 through capacitors 218 and 220. Transmitter 202 provides a digital signal at its differential output. Capacitors 218 and 220 block the DC of the digital signal and pass the pulses at the edges of the digital signal. The polarity of the pulses changes with the edge direction. A rising edge of the digital signal generates a positive-polarity pulse at the input of pulse receiver 208, and a falling edge of the digital signal generates a negative-polarity pulse at the input of pulse receiver 208. Pulse receiver 208 receives and amplifies the pulses passed by capacitors 218 and 220. Pulse receiver 208 includes a differential amplifier having differential inputs coupled to capacitors 218 and 220. In some embodiments, pulse receiver 208 may include a plurality of differential amplifiers coupled in series. The output of the differential amplifier provides the output of pulse receiver 208.

[0020] The input of output circuit 212 is coupled to the output of pulse receiver 208. Output circuit 212 includes logic circuit 214. Logic circuit 214 generates a digital signal representative of the input signal received at I / P in response to the pulses received from pulse receiver 208. For example, logic circuit 214 generates a rising edge of the digital signal (to generate a logic high on the digital signal) in response to a positive-polarity pulse received from pulse receiver 208, and generates a falling edge of the digital signal (to generate a logic low on the digital signal) in response to a negative-polarity pulse received from pulse receiver 208. Output circuit 212 may use the voltage at VCCB to provide the digital signal to level-shift the signal with respect to the voltage at VCCA. Output circuit 212 may include a driver coupled to the output of logic circuit 214 to drive the digital signal to O / P.

[0021] The pull current circuit 204, the sink current circuit 206, and the detector 210 are coupled in a low-speed data circuit that transfers the DC representation of an input signal received at I / P from the driver circuit 110 to the receiver circuit 112. If GNDA is at a higher voltage than GNDB, the pull current circuit 204 provides a pull current signal (draws current) to the detector 210. If GNDA is at a lower voltage than GNDB, the sink current circuit 206 provides a sink current signal (draws current from the detector) to the detector 210. When the input signal received at I / P is logic high, the pull current circuit 204 draws current to the detector 210, or the sink current circuit 206 sinks current from the detector 210. When the input signal at I / P is logic low, the pull current circuit 204 does not draw current to the detector 210, and the sink current circuit 206 does not sink current from the detector 210. Thus, logic high is transmitted by drawing or sinking current, and logic low is transmitted by not drawing or sinking current. The detector 210 has an output at which the detector 210 provides a detector signal (DS) representative of the input signal at I / P. The output of the detector 210 is coupled to the input of the output circuit 212 and the input of the logic circuit 214.

[0022] Since the transmitter 202 and the pulse receiver 208 are capacitively coupled in a high-speed data circuit, noise at the input of the pulse receiver 208 may generate a pulse that sets the digital signal generated by the logic circuit 214 to an incorrect state. The logic circuit 214 has an override input coupled to the output of the detector 210. The logic circuit 214 applies the detector signal to correct the state of the digital signal, which is a DC signal and is less likely to be corrupted by noise. For example, if within a selected time (e.g., 1 microsecond) after the transition of the digital signal, the state of the digital signal is different from the state of the detector signal, the logic circuit 214 may change the state of the digital signal to match the state of the detector signal.

[0023] The substrate bias circuit 216 provides a bias voltage to the semiconductor substrate 226 to reduce the likelihood of damaging the integrated circuit including the level shifter 106 due to an excessive voltage between the semiconductor substrate 226 and the circuit layer. The substrate bias circuit 216 is coupled to GNDA and GNDB and may drive the semiconductor substrate 226 to the lower of the voltage on GNDA (ground voltage) and the voltage on GNDB. Refer to Figure 4 Additional information regarding the operation of the substrate bias circuit 216 is provided.

[0024] Figure 3A block diagram of a portion of a level shifter 106 that includes an example high-speed signal circuit. The transmitter 202 includes a buffer 302 and a buffer 304. The input of the buffer 302 is coupled to the I / P. The output of the buffer 302 is coupled to the input of the buffer 304. The first output of the buffer 304 is coupled to the first terminal of the capacitor 218, and the second output of the buffer 304 is coupled to the first terminal of the capacitor 220. The pulse receiver 208 includes a differential amplifier 306 and a differential amplifier 308 coupled in series. The differential amplifier 306 and the differential amplifier 308 amplify the pulses received from the capacitors 218 and 220. The differential amplifier 306 and the differential amplifier 308 have differential inputs and outputs. The first input of the differential amplifier 306 is coupled to the second terminal of the capacitor 218, and the second terminal of the differential amplifier 306 is coupled to the second terminal of the capacitor 220. The first output of the differential amplifier 306 is coupled to the first input of the differential amplifier 308, and the second output of the differential amplifier 306 is coupled to the second input of the differential amplifier 308.

[0025] The differential amplifier 308 is coupled to the logic circuit 214. The first output of the differential amplifier 308 is coupled to the first input of the logic circuit 214, and the second output of the differential amplifier 308 is coupled to the second input of the logic circuit 214. A signal 316 is provided at the first output of the differential amplifier 308, and a signal 318 is provided at the second output of the differential amplifier 308. The logic circuit 214 changes the state of the receiver output signal 314 in response to the pulses received from the differential amplifier 308. For example, a pulse can be provided by the signal 316 to set the digital signal generated by the logic circuit 214 to logic high, and a pulse can be provided by the signal 318 to set the digital signal generated by the logic circuit 214 to logic low.

[0026] The output of the logic circuit 214 is coupled to the input of the level shifter 310. The level shifter 310 adjusts the voltage of the receiver output signal 314. The output of the level shifter 310 is coupled to the input of the buffer 312. The buffer 312 drives the level-shifted receiver output signal 314 to a circuit system external to the level shifter 106.

[0027] Figure 4FIG. 0 is a schematic diagram of an example circuit system 400 of a low-speed data circuit of a level shifter 106. The circuit system 400 includes a pull current circuit 204, a sink current circuit 206, and a detector 210. If GNDA is a higher voltage than GNDB, the pull current circuit 204 pulls current out to the detector 210. If GNDB is a higher voltage than GNDA, the sink current circuit 206 sinks current from the detector 210. The pull current circuit 204 includes a current mirror circuit 402, transistors 408 and 410, and a current source 412. The current mirror circuit 402 includes transistors 404 and 406. The transistors 404, 406, 408, and 410 may be p-type field effect transistors (PFETs). A first terminal (e.g., source) of the transistor 404 is coupled to VCCA. A second terminal (e.g., drain) of the transistor 404 is coupled to a control terminal (e.g., gate) of the transistor 404. A first terminal (e.g., source) of the transistor 406 is coupled to VCCA. A control terminal (e.g., gate) of the transistor 406 is coupled to the control terminal of the transistor 404.

[0028] A first terminal (e.g., source) of the transistor 408 is coupled to the second terminal of the transistor 404. A second terminal (e.g., drain) of the transistor 408 is coupled to an input of the current source 412. An output of the current source 412 is coupled to GNDA. A control terminal (e.g., gate) of the transistor 408 is coupled to I / P (e.g., through an inverter (not shown)) to receive a signal INPUT_BAR, which is an inverted version of an input signal received at I / P. A first terminal (e.g., source) of the transistor 410 is coupled to the second terminal of the transistor 406. A second terminal (e.g., drain) of the transistor 410 is coupled to the detector 210. A control terminal (e.g., gate) of the transistor 410 is coupled to the control terminal of the transistor 408. If the signal INPUT_BAR is logic low, the transistors 408 and 410 are turned on, and current flows through the transistors 404 and 408 to the current source 412, and through the transistors 406 and 410 to the detector 210.

[0029] Detector 210 includes circuitry 413 coupled to a sink current circuit 204. Circuitry 413 includes a current mirror circuit 414, a current mirror circuit 416, a resistor 428, and an inverter 430. Inverter 430 can be a Schmitt trigger circuit. The input of inverter 430 is coupled to current mirror circuit 414, and the output of inverter 430 is coupled to the input of logic gate 454. Current mirror circuit 414 includes transistors 418 and 420 and resistor 422. Transistors 418 and 420 can be PFETs. The first terminal (e.g., source) of transistor 418 is coupled to VCCB. The second terminal (e.g., drain) of transistor 418 is coupled to the control terminal (e.g., gate) of transistor 418. The first terminal (e.g., source) of transistor 420 is coupled to VCCB. The second terminal (e.g., drain) of transistor 420 is coupled to the input of inverter 430. The control terminal (e.g., gate) of transistor 420 is coupled to the control terminal of transistor 418. Resistor 422 is coupled between VCCB and the control terminal of transistor 418.

[0030] Current mirror circuit 416 includes transistors 424 and 426. Transistors 424 and 426 can be n-channel field effect transistors (NFETs). The first current terminal (e.g., drain) of transistor 424 is coupled to the second current terminal of transistor 410 and the control terminal (e.g., gate) of transistor 424. The second current terminal (e.g., source) of transistor 424 is coupled to GNDB. The first current terminal of transistor 426 is coupled to the second current terminal of transistor 418. The second current terminal (e.g., source) of transistor 426 is coupled to GNDB. The control terminal of transistor 426 is coupled to the control terminal of transistor 424. The current flowing through transistor 410 flows through transistor 424, and transistor 426 draws a current that is a mirror image of the current flowing through transistor 424 from transistor 418. As current flows through transistor 418, current also flows through transistor 420, and the voltage across resistor 428 drops.

[0031] The sink current circuit 206 includes a current source 432, transistors 434 and 436, and a current mirror circuit 438. Current mirror circuit 438 includes transistors 440 and 442. Transistors 434, 436, 440, and 442 can be NFETs. Transistor 440 has a first terminal (e.g., drain) coupled to the control terminal (e.g., gate) of transistor 440. The second terminal (e.g., source) of transistor 440 is coupled to GNDA. The first terminal (e.g., drain) of transistor 442 is coupled to transistor 436. The second terminal (e.g., source) of transistor 442 is coupled to GNDA. The control terminal (e.g., gate) of transistor 442 is coupled to the control terminal of transistor 440.

[0032] Current source 432 has an input coupled to VCCA and an output coupled to a first terminal (e.g., drain) of transistor 434. A second terminal (e.g., source) of transistor 434 is coupled to a first terminal of transistor 440. A control terminal (e.g., gate) of transistor 434 is coupled to I / P to receive input signal INPUT. A first terminal (e.g., drain) of transistor 436 is coupled to detector 210. A second terminal (e.g., source) of transistor 436 is coupled to a first terminal of transistor 442. A control terminal (e.g., gate) of transistor 436 is coupled to the control terminal of transistor 434. If INPUT is logic high, transistors 434 and 436 turn on, current flows from current source 432 through transistor 434 and transistor 440, and current flows from detector 210 through transistor 436 and transistor 442.

[0033] Detector 210 includes circuitry 443 coupled to sink current circuit 206. Circuitry 443 includes current mirror circuit 444, resistor 450, and inverter 452. Inverter 452 can be a Schmitt trigger circuit. An input of inverter 452 is coupled to current mirror circuit 444, and an output of inverter 452 is coupled to an input of logic gate 454. Current mirror circuit 444 includes transistors 446 and 448. Transistors 446 and 448 can be PFETs. A first terminal (e.g., source) of transistor 446 is coupled to VCCB. A second terminal (e.g., drain) of transistor 446 is coupled to a control terminal (e.g., gate) of transistor 446. A first terminal (e.g., source) of transistor 448 is coupled to VCCB. A second terminal (e.g., drain) of transistor 448 is coupled to the input of inverter 452. A control terminal (e.g., gate) of transistor 448 is coupled to the control terminal of transistor 446. The current flowing through transistor 436 flows through transistor 446, and transistor 448 draws a current that is a mirror image of the current flowing through transistor 446. The current flowing through transistor 448 also flows through resistor 450, and a voltage is generated across resistor 450.

[0034] Logic gate 454 logically combines (e.g., performs a logical NOR) OUT1 provided by inverter 452 and OUT2 provided by inverter 430 to generate detector signal DS. Detector signal DS is a representation of the signal received at I / P.

[0035] Figure 5 is a cross-sectional view of integrated circuit 500 that includes level shifter 106. Figure 5Shows a semiconductor substrate 226, an N buried layer (NBL), and a P epitaxial (P-EPI) layer in an integrated circuit 500. Portions of the P-EPI layer and the NBL layer form region-A and region-B. The driver circuit 110 may be located in region-A, and the receiver circuit 112 may be located in region-B. Region-A is isolated from region-B by isolation trenches 502. The isolation trenches 502 may contain an insulator, such as an oxide or other insulating material. In region-A, the P-EPI layer may be coupled to GNDA. In region-B, the P-EPI layer may be coupled to GNDB. The voltages on GNDA and GNDB may be different. The circuitry formed in the NBL layer of region-A of the driver circuit 110 may be coupled to VCCA, and the circuitry formed in the NBL layer of region-B of the receiver circuit 112 may be coupled to VCCB.

[0036] If the voltage between the layers of the integrated circuit 500 exceeds the maximum safe voltage, the integrated circuit 500 may be damaged. For example, if the voltage between the semiconductor substrate 226 and the NBL layer of region-A exceeds the maximum safe voltage, the integrated circuit 500 may be damaged. The substrate bias circuit 216 biases the semiconductor substrate 226 to reduce the interlayer voltage and reduce the likelihood of damage to the integrated circuit 500.

[0037] In Figure 5 the example, the junction between the NBL layer and the semiconductor substrate 226 or between the P_EPI layer and the NBL layer has a maximum safe voltage of about 90 volts. The substrate bias circuit 216 conducts from GNDA and GNDB to the semiconductor substrate 226 to prevent the voltage between the semiconductor substrate 226 and GNDA or GNDB from exceeding about 90 volts. For example, if the interlayer voltage exceeds about 50 volts, the substrate bias circuit 216 may conduct current between the substrate bias circuit 216 and GNDA or GNDB.

[0038] Figure 6 is a schematic diagram of an example substrate bias circuit 216. The substrate bias circuit 216 includes a bias circuit 600 coupled between GNDA and the semiconductor substrate 226, and a bias circuit 601 coupled between GNDB and the semiconductor substrate 226. The bias circuit 600 includes a Zener diode 602, a resistor 606, a transistor 608, and a diode 604. The Zener diode 602 includes one or more Zener diodes coupled in series. In Figure 6 the example, the Zener diode 602 includes a Zener diode 610 and a Zener diode 612 coupled in series. The cathode of the Zener diode 612 is coupled to GNDA. The anode of the Zener diode 612 is coupled to the cathode of the Zener diode 610. Examples of the Zener diode 602 may include any number of Zener diodes coupled in series to provide a desired reverse breakdown voltage.

[0039] The resistor 606 is coupled between the Zener diode 602 and the semiconductor substrate 226. A first terminal of the resistor 606 is coupled to the anode of the Zener diode 610, and a second terminal of the resistor 606 is coupled to the semiconductor substrate 226. The transistor 608 has a first terminal (e.g., drain) coupled to GNDA and a second terminal (e.g., source) coupled to the semiconductor substrate 226. A control terminal (e.g., gate) of the transistor 608 is coupled to the first terminal of the resistor 606. If the voltage between GNDA and the semiconductor substrate 226 exceeds a threshold set by the reverse breakdown voltage of the Zener diode 602 (the voltage on GNDA is higher than the voltage on the semiconductor substrate 226 by the reverse breakdown voltage of the Zener diode 602), the Zener diode 602 conducts current and a voltage is generated across the resistor 606. The voltage across the resistor 606 turns on the transistor 608, and current flows from GNDA to the semiconductor substrate 226 to reduce the voltage difference between GNDA and the semiconductor substrate 226.

[0040]

[0040] The diode 604 is coupled between GNDA and the semiconductor substrate 226. The cathode of the diode 604 is coupled to GNDA, and the anode of the diode 604 is coupled to the semiconductor substrate 226. If the voltage on the semiconductor substrate 226 is higher than the voltage on GNDA, the diode 604 conducts current from the semiconductor substrate 226 to GNDA to reduce the voltage difference.

[0041]

[0041] The bias circuit 601 is similar to the bias circuit 600. The bias circuit 601 includes a Zener diode 614, a resistor 618, a transistor 620, and a diode 616. The Zener diode 614 includes one or more Zener diodes coupled in series. Figure 6 Figure 6 In, the Zener diode 614 includes Zener diodes 622 and 624 coupled in series. The cathode of the Zener diode 624 is coupled to GNDB. The anode of the Zener diode 624 is coupled to the cathode of the Zener diode 622. An example of the Zener diode 614 may include any number of Zener diodes coupled in series to provide a desired reverse breakdown voltage.

[0042] ​Resistor 618 is coupled between Zener diode 614 and semiconductor substrate 226. A first terminal of resistor 618 is coupled to the anode of Zener diode 622, and a second terminal of resistor 618 is coupled to semiconductor substrate 226. Transistor 620 has a first terminal (e.g., drain) coupled to GNDB and a second terminal (e.g., source) coupled to semiconductor substrate 226. A control terminal (e.g., gate) of transistor 620 is coupled to the first terminal of resistor 618. If the voltage between GNDB and semiconductor substrate 226 exceeds the reverse breakdown voltage of Zener diode 614 (the voltage on GNDB is higher than the voltage on semiconductor substrate 226 by the reverse breakdown voltage of Zener diode 614), then Zener diode 614 conducts current and a voltage is generated across resistor 618. The voltage across resistor 618 turns on transistor 620, and current flows through transistor 620 from GNDB to semiconductor substrate 226 to reduce the voltage difference between GNDB and semiconductor substrate 226.

[0043] Diode 616 is coupled between GNDB and semiconductor substrate 226. The cathode of diode 616 is coupled to GNDB, and the anode of diode 616 is coupled to semiconductor substrate 226. If the voltage on semiconductor substrate 226 is higher than the voltage on GNDB, then diode 616 conducts current from semiconductor substrate 226 to GNDB to reduce the voltage difference.

[0044] Figure 7 is a block diagram of example logic circuit 214. Logic circuit 214 includes flip-flop 702, timer circuit 704, comparator circuit 706, and logic gate 708. Flip-flop 702 has a preset input coupled to a first output of differential amplifier 308 for receiving signal 316, and a reset input coupled to a second output of differential amplifier 308 for receiving signal 318. A pulse on signal 316 sets the receiver output signal 314 provided at the Q output of flip-flop 702 to logic high. A pulse on signal 318 sets the receiver output signal 314 provided at the Q output of flip-flop 702 to logic low. The D input of flip-flop 702 is coupled to the Q output of flip-flop 702 to provide an inversion of the receiver output signal 314 at the D input.

[0045] The flip - flop 702, timer circuit 704, comparison circuit 706, and logic gate 708 ensure the correction of errors in the state of the receiver output signal 314 based on the detector signal DS (e.g., errors caused by noise at the input of the differential amplifier 306). The timer circuit 704 has an input coupled to the Q output of the flip - flop 702. A change in the state of the receiver output signal 314 triggers the timer circuit 704. For example, a transition of the receiver output signal 314 from low to high or from high to low can trigger the timer circuit 704. When triggered by a transition on the receiver output signal 314, the timer circuit 704 generates a transition on the timer output signal 712 after a predetermined time. For example, a transition on the receiver output signal 314 can reset the timer circuit 704, and after a predetermined time (e.g., after 1 microsecond), the timer circuit 704 can provide a pulse on the timer output signal 712.

[0046] The comparison circuit 706 compares the receiver output signal 314 with the detector signal DS provided by the detector 210. The comparison circuit 706 provides a signal 710 indicating whether the receiver output signal 314 and DS have the same logical state (e.g., both are logically high or both are logically low). For example, if DS and the receiver output signal 314 have different logical states (e.g., DS is logically high and the receiver output signal 314 is logically low), the comparison circuit 706 can provide a signal 710 in the logically high state. In some instances, the comparison circuit 706 can include an exclusive - OR gate to compare the receiver output signal 314 and DS.

[0047] The logic gate 708 has a first input coupled to the output of the comparison circuit 706 and a second input coupled to the output of the timer circuit 704. If the signal 710 is logically high (indicating different logical states of DS and the receiver output signal 314), and there is a pulse on the timer output signal 712, the flip - flop 702 is clocked and the receiver output signal 314 is inverted. Thus, the state of the receiver output signal 314 is changed to match the state of DS. The logic gate 708 can be an AND gate.

[0048] In this specification, the term "coupled" can encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0049] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote an interconnect or an end thereof between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0050] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party.

[0051] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may actually be used with little or no change to the rest of the circuit system. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) (n-type transistors) or p-channel FETs (PFETs) (p-type transistors)), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0052] In the claims, reference may be made to the control input of a transistor and its current terminals. In the case of an FET, the control input (or transistor control terminal) is the gate, and the current terminals are the drain and source. In the case of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0053] As used herein, an FET being "on" means that there is a conductive channel in the FET and a drain current can flow through the FET. As used herein, an FET being "off" means that there is no conductive channel and thus no drain current flows through the FET. However, an "off" FET may allow current to flow through the body diode of the transistor.

[0054] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0055] Although some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0056] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about," "substantially," or "essentially" in front of a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable value that is approximately zero.

[0057] Modifications may be made within the scope of the claims, and other embodiments are possible, for the described embodiments.

Claims

1. A circuit, comprising: A semiconductor substrate; A first ground terminal; A second ground terminal; A driver circuit located on the semiconductor substrate, the driver circuit being coupled to the first ground terminal and having a first output and a second output; A capacitor having a first terminal and a second terminal, the first terminal being coupled to the first output of the driver circuit; A receiver circuit located on the semiconductor substrate, the receiver circuit being coupled to the second ground terminal and having a first input coupled to the second terminal of the capacitor and a second input coupled to the second output of the driver circuit; And A substrate bias circuit having a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.

2. The circuit according to claim 1, wherein the substrate bias circuit is configured to provide a bias voltage to the semiconductor substrate, the bias voltage being selected as the lower voltage of the voltage of the first ground terminal and the voltage of the second ground terminal.

3. The circuit according to claim 1, wherein: The capacitor is a first capacitor; The driver circuit includes a transmitter having an input, a first output, and a second output; The receiver circuit includes a pulse receiver having a first input, a second input, and an output; The first terminal of the first capacitor is coupled to the first output of the transmitter, and the second terminal of the first capacitor is coupled to the first input of the pulse receiver; And The circuit includes a second capacitor having a first terminal coupled to the second output of the transmitter and a second terminal coupled to the second input of the pulse receiver.

4. The circuit according to claim 3, wherein the pulse receiver includes a differential amplifier having a first input coupled to the first input of the pulse receiver, a second input coupled to the second input of the pulse receiver, and an output coupled to the output of the pulse receiver.

5. The circuit according to claim 3, wherein the receiver circuit includes a logic circuit having an input and an output coupled to the output of the pulse receiver, the logic circuit being configured to generate an output signal at the output of the logic circuit, the output signal having a first state in response to a pulse having a first polarity received from the pulse receiver and a second state in response to a pulse having a second polarity received from the pulse receiver.

6. The circuit according to claim 5, wherein the receiver circuit includes a level shifter circuit coupled to the output of the logic circuit.

7. The circuit according to claim 5, wherein: The driver circuit includes: A pull-up current circuit having an input and an output coupled to the input of the transmitter; A pull-down current circuit having an input and an output coupled to the input of the transmitter; and The receiver circuit includes a detector having a first input coupled to the output of the pull current circuit, a second input coupled to the output of the sink current circuit, and an output, the detector being configured to provide a detector signal based on a pull current signal received from the pull current circuit and a sink current signal received from the sink current circuit.

8. The circuit according to claim 7, wherein the logic circuit has an override input coupled to the output of the detector, and the logic circuit is configured to change the state of the output signal based on the state of the output signal being different from the state of the detector signal.

9. A circuit comprising: A semiconductor substrate; A first ground terminal; A second ground terminal; A driver circuit coupled to the first ground terminal, the driver circuit including a transmitter having a first output and a second output; A receiver circuit coupled to the second ground terminal, the receiver circuit including a pulse receiver having a first input and a second input; A first capacitor having a first terminal coupled to the first output of the transmitter and a second terminal coupled to the first input of the pulse receiver; And A second capacitor having a first terminal coupled to the second output of the transmitter and a second terminal coupled to the second input of the pulse receiver; And A substrate bias circuit having a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.

10. The circuit according to claim 9, wherein the substrate bias circuit is configured to provide a bias voltage to the semiconductor substrate, the bias voltage being selected as the lower ground voltage of the ground voltage of the first ground terminal and the ground voltage of the second ground terminal.

11. The circuit according to claim 9, wherein the substrate bias circuit is configured to: Conduct current from the first ground terminal to the semiconductor substrate in response to a voltage between the semiconductor substrate and the first ground terminal exceeding a threshold; and Conduct current from the second ground terminal to the semiconductor substrate in response to a voltage between the semiconductor substrate and the second ground terminal exceeding the threshold.

12. The circuit according to claim 9, wherein the pulse receiver includes a differential amplifier having a first input coupled to the first input of the pulse receiver, a second input coupled to the second input of the pulse receiver, and an output coupled to the output of the pulse receiver.

13. The circuit according to claim 12, wherein the receiver circuit includes a logic circuit having an input and an output coupled to the output of the differential amplifier, the logic circuit being configured to generate an output signal at the output of the logic circuit, the output signal having a first state in response to a pulse having a first polarity received from the differential amplifier and a second state in response to a pulse having a second polarity received from the differential amplifier.

14. The circuit according to claim 13, wherein the receiver circuit includes a level shifter circuit coupled to the output of the logic circuit.

15. The circuit according to claim 13, wherein: the driver circuit includes: a pull-up current circuit having an input and an output coupled to the input of the transmitter; a pull-down current circuit having an input and an output coupled to the input of the transmitter; and the receiver circuit includes a detector having a first input coupled to the output of the pull-up current circuit, a second input coupled to the output of the pull-down current circuit, and an output, the detector being configured to provide a detector signal based on a pull-up current signal received from the pull-up current circuit and a pull-down current signal received from the pull-down current circuit.

16. The circuit according to claim 15, wherein the logic circuit has an override input coupled to the output of the detector, and the logic circuit is configured to change the state of the output signal based on the state of the output signal being different from the state of the detector signal.

17. A system, comprising: a first ground terminal and a second ground terminal; a first circuit coupled to the first ground terminal, the first circuit having an output for providing an output signal; a second circuit coupled to the second ground terminal, the second circuit having an input; a level shifter integrated circuit having an input coupled to the output of the first circuit and an output coupled to the input of the second circuit, the level shifter integrated circuit including: a semiconductor substrate; a driver circuit located on the semiconductor substrate, the driver circuit being coupled to the first ground terminal and having an input coupled to the input of the level shifter integrated circuit, a first output, and a second output; a capacitor having a first terminal and a second terminal, the first terminal being coupled to the first output of the driver circuit; a receiver circuit located on the semiconductor substrate, the receiver circuit being coupled to the second ground terminal and having a first input coupled to the second terminal of the capacitor, a second input coupled to the second output of the driver circuit, and an output coupled to the output of the level shifter integrated circuit; and a substrate biasing circuit having a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.

18. The system according to claim 17, wherein the substrate biasing circuit is configured to provide a biasing voltage to the semiconductor substrate, the biasing voltage being selected as the lower ground voltage of the ground voltage of the first ground terminal and the ground voltage of the second ground terminal.

19. The system according to claim 17, wherein: the capacitor is a first capacitor; the level shifter integrated circuit includes a second capacitor; the driver circuit includes a transmitter having an input coupled to the input of the driver circuit, a first output, and a second output; the receiver circuit includes: A differential amplifier having a first input coupled to the first output of the transmitter through the first capacitor, a second input coupled to the second output of the transmitter through the second capacitor, and an output; And A logic circuit having an input coupled to the output of the differential amplifier and an output coupled to the output of the receiver circuit, the logic circuit being configured to generate an output signal at the output of the logic circuit, the output signal having a first state in response to a pulse having a first polarity received from the differential amplifier and having a second state in response to a pulse having a second polarity received from the differential amplifier.

20. The system according to claim 19, wherein: The driver circuit includes: A pull-up current circuit having an input and an output coupled to the input of the transmitter; A pull-down current circuit having an input and an output coupled to the input of the transmitter; and The receiver circuit includes a detector having a first input coupled to the output of the pull-up current circuit, a second input coupled to the output of the pull-down current circuit, and an output, the detector being configured to provide a detector signal based on a pull-up current signal received from the pull-up current circuit and a pull-down current signal received from the pull-down current circuit; And The logic circuit has an override input coupled to the output of the detector, and the logic circuit is configured to change the state of the output signal based on the state of the output signal being different from the state of the detector signal.

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