A design method for broadband transceiver reconfigurable channel architecture

Abstract

The present invention relates to the field of radio frequency integration technology, specifically a method for designing a broadband transceiver reconfigurable channel architecture, comprising the following steps: step S1: dividing the operating frequency band; step S2: designing a reconfigurable filter to achieve adjustable center frequency and bandwidth; step S3: utilizing a switch matrix to achieve a combination of different functional modules of the system; step S4: achieving high channel isolation design and channel consistency design. The method for designing a broadband transceiver reconfigurable channel architecture provided by the present invention utilizes a reconfigurable filter to replace a traditional filter, which can achieve radio frequency reconstruction of the communication system, not only reducing the size and cost of the radio frequency front end, but also reducing the insertion loss of the radio frequency front end caused by a large number of switches and branch networks; cascading different functional modules through the switch matrix not only simplifies the structure and control, but also enables a single device to be used by multiple channels, thereby reducing the redundancy of devices with the same function.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integration, and in particular to a design method for a broadband transceiver reconfigurable channel architecture. Background Art

[0002] With the continuous development of radio communication technology, the requirements for data transmission rate, capacity and reliability are constantly increasing. Radio frequency microwave circuits are developing towards miniaturization, low cost, easy operation and multi-frequency and multi-mode.

[0003] Currently, a single frequency band and a single communication mode are no longer sufficient to meet market demand. Therefore, RF microwave circuits need to be able to support multiple frequency bands and multiple communication modes. To meet the various performance requirements for transmitting and receiving signals in different frequency bands and formats, a broadband reconfigurable transceiver channel is required.

[0004] Wideband transceiver reconfiguration technology allows the communication system's transceiver front end to adapt to different frequency bands, modulation methods, and communication protocols through the flexible configuration and reconstruction of hardware circuits or software algorithms. This improves system flexibility and adaptability, and reduces development and maintenance costs. Typically, an ultra-wideband RF integrated transceiver front end requires high bandwidth, linearity, low noise, flexible RF channel switching, and multi-channel electromagnetic compatibility. It implements filtering, amplification, and frequency conversion during reception. The RF filter's center frequency and bandwidth must be flexibly adjustable based on different mission requirements. The RF channel must be adaptively adjusted according to mission requirements and target type.

[0005] Existing technologies for broadband reconfigurable transceiver channels include: low-IF RF transceivers based on CMOS technology, using switched capacitors to reconfigure RF output matching, suitable for multi-standard applications such as LTE, IoT, and WSN; combining ultra-wideband and reconfigurable technologies to achieve a 0.5-15 GHz ultra-wideband RF reconfigurable receiver chip based on a silicon-based UMC 28nm CMOS process; zero-IF dual-band receivers capable of operating simultaneously in the 22-29 GHz and 77-81 GHz bands; and parallel dual-band architectures utilizing secondary mixing to enable simultaneous transmission of signals from two frequency bands within a single channel. However, none of these specific technologies have yet achieved a complete architecture. Summary of the Invention

[0006] The purpose of the present invention is to provide a design method for a broadband transceiver reconfigurable channel architecture to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A method for designing a broadband transceiver reconfigurable channel architecture comprises the following steps:

[0009] Step S1: Divide the working frequency band;

[0010] Step S2: Design a reconfigurable filter to achieve adjustable center frequency and bandwidth;

[0011] Step S3: Using the switch matrix to realize the combination of different functional modules of the system;

[0012] Step S4: Implement high channel isolation design and consistency design.

[0013] Preferably, step S2 specifically includes:

[0014] Step S21: designing a reconfigurable MEMS filter;

[0015] Step S22: Design an on-chip reconfigurable filter.

[0016] Preferably, step S21 specifically includes:

[0017] The MEMS process supports high-Q passive devices, adopts LC lumped structure at low frequency, and integrated waveguide and waveguide cavity structure at high frequency, and is integrated with the RF front-end chip at the microsystem packaging level.

[0018] Preferably, step S22 specifically includes:

[0019] Variable gain is provided through a low-pass filter and a subsequent programmable amplifier to meet the dynamic range requirements of the entire channel, thereby configuring the filter gain and correction cutoff frequency.

[0020] Preferably, the switch matrix in step S3 is a switch matrix constructed by cascading specific types of DPDT switches, and the switch matrix has a 4P4T function.

[0021] Preferably, the high isolation design of the channel in step S4 specifically includes:

[0022] Step S41: Eliminating magnetic coupling between on-chip inductors;

[0023] Step S42: Eliminate electrical coupling.

[0024] Preferably, step S41 specifically includes:

[0025] S411. Optimize the layout: By optimizing the layout, sensitive inductors are placed in different areas for physical isolation to avoid near-field magnetic coupling.

[0026] S412. Optimize the inductor layout: Improve the inductor's resistance to external crosstalk by optimizing the inductor layout technology. Optimize the metal layer selection of the guard ring around the inductor to improve the inductor's ability to shield from external electromagnetic fields while maintaining its quality factor.

[0027] S413. Reasonable frequency planning: Reasonable frequency planning can prevent the resonant inductors from operating at the same frequency, thereby reducing the frequency deviation of the oscillator in the phase-locked loop.

[0028] Preferably, step S42 specifically includes:

[0029] S421. To address the mutual coupling of different modules through the power network, during the PCB layout stage, physically separate different areas. Use digital isolators and buffers to achieve cross-domain signal isolation, reasonably isolate the RF, analog, and digital power networks, and use local decoupling capacitors to protect key modules to reduce the impact of power network coupling.

[0030] S422. Shield key signal lines to protect them from mutual coupling, and avoid overlapping of sensitive signal lines through reasonable layout.

[0031] S423. When the transmitter is outputting high power, the signal leaks through the bottom of the substrate to the receiver signal chain and the clock generation circuit module. Due to the crosstalk of the substrate, spurious signals appear in the received signal and the clock signal, resulting in a decrease in the signal-to-noise ratio. Combined with deep hydrazine isolation and layout, the influence of substrate coupling is reduced to ensure the performance of the chip after integration.

[0032] Preferably, the channel consistency design in step S4 specifically includes:

[0033] The layout technology of multi-channel layout is used to reduce the coupling between channels and improve the interference suppression of channel input and output. At the system level, mismatch calibration technology is used to eliminate the influence of deviation factors between channels through calibration, and channel consistency is improved through collaborative design from the bottom layout to the top system.

[0034] Preferably, the mismatch calibration technique includes:

[0035] At the transmitter, after convolutional coding of the data stream, each group of bits is mapped to a constellation diagram using a specific modulation scheme, generating a complex signal sequence X. The signal sequence is precoded using an uplink channel estimation coding matrix. OFDM modulation transforms the precoded frequency domain signal sequence into the time domain, generating time domain OFDM symbols. These symbols are then combined into independent data streams and mapped to the transmit link, with corresponding weights assigned to the time domain signals on each link.

[0036] At the receiving end, after the antenna receives the wireless signal, it first undergoes amplitude and phase adjustment through the receiving end's beamforming network. Then, it is down-converted to baseband and sampled to generate a baseband digital signal. Next, the digital signals are combined in the digital domain to complete the beamforming process. Finally, through demodulation, demapping, and channel decoding, the original complex signal sequence is obtained from the received signal.

[0037] Receive signal It can be expressed as:

[0038] (1);

[0039] In formula (1): Represents the corresponding error matrix of the receiving channel; Represents the transmit channel error response matrix, which is also a function of frequency in broadband systems; represents a matrix used to combine digital signals on each RF link in the digital domain; represents the receiving end beamforming network, which is used for amplitude and phase adjustment; represents the matrix for analog domain beamforming; represents the matrix for digital domain beamforming; H represents the air channel response; X represents the complex signal sequence, and n represents Gaussian white noise;

[0040] Formula (1) includes the amplitude-phase mismatch coefficients of the transmitter and receiver, the transmitter beamforming coefficients, and the receiver beamforming coefficients. Narrowband-based single-carrier calibration can be applied to each subcarrier to achieve broadband calibration.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] The present invention provides a method for designing a broadband transceiver reconfigurable channel architecture. The method utilizes reconfigurable filters to replace traditional filters, thereby realizing RF reconfiguration of the communication system. This not only reduces the size and cost of the RF front end, but also reduces the insertion loss of the RF front end due to a large number of switches and distributed networks. By cascading different functional modules through a switch matrix, the structure and control are simplified, and a single device can be used by multiple channels, thereby reducing the redundancy of devices with the same function. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A flowchart of a broadband transceiver reconfigurable channel architecture design method provided by the present invention;

[0044] Figure 2 A schematic diagram of the structure of a reconfigurable filter in a broadband transceiver reconfigurable channel architecture design method provided by the present invention;

[0045] Figure 3 A schematic diagram of a switch matrix in a broadband transceiver reconfigurable channel architecture design method provided by the present invention;

[0046] Figure 4 A schematic diagram of channel isolation analysis in a broadband transceiver reconfigurable channel architecture design method provided by the present invention;

[0047] Figure 5 This is a schematic diagram of channel consistency analysis in a broadband transceiver reconfigurable channel architecture design method provided by the present invention. DETAILED DESCRIPTION

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0049] Figure 1 The present invention provides a flow chart of a broadband transceiver reconfigurable channel architecture design method. Figure 1 As shown, an embodiment of the present invention provides a method for designing a broadband transceiver reconfigurable channel architecture, comprising the following steps:

[0050] Step S1: Divide the working frequency band;

[0051] Step S2: Design a reconfigurable filter to achieve adjustable center frequency and bandwidth;

[0052] Step S3: Using the switch matrix to realize the combination of different functional modules of the system;

[0053] Step S4: Implement high channel isolation design and channel consistency design.

[0054] The present invention provides a method for designing a broadband transceiver reconfigurable channel architecture. The method utilizes reconfigurable filters to replace traditional filters, thereby realizing RF reconfiguration of the communication system. This not only reduces the size and cost of the RF front end, but also reduces the insertion loss of the RF front end due to a large number of switches and distributed networks. By cascading different functional modules through a switch matrix, the structure and control are simplified, and a single device can be used by multiple channels, thereby reducing the redundancy of devices with the same function.

[0055] In one embodiment of the present invention, step S1 specifically includes: considering the difficulty of optimizing the noise, linearity, gain flatness, etc. of the amplifier within the ultra-wideband range, the RF front end is divided into two paths: a low-frequency band and a high-frequency band.

[0056] Figure 2 This is a schematic diagram of the structure of a reconfigurable filter in a broadband transceiver reconfigurable channel architecture design method provided by the present invention. Figure 2 As shown, in one embodiment of the present invention, step S2 specifically includes:

[0057] Step S21: designing a reconfigurable MEMS filter;

[0058] Step S22: Design an on-chip reconfigurable filter.

[0059] Reconfigurable filter technology refers to the technology of changing the frequency characteristics of the filter, such as the center frequency, RF bandwidth or out-of-band selectivity, by tuning certain specific components. By replacing the traditional filter group with a reconfigurable filter, the RF reconstruction of the communication system can be achieved. It can not only reduce the size and cost of the RF front-end of the communication system, but also reduce the insertion loss caused by a large number of switches and distributed networks in the RF front-end.

[0060] Specifically, in one embodiment of the present invention, step S21 specifically includes:

[0061] The MEMS process supports high-Q passive devices, adopts LC lumped structure at low frequency, and integrated waveguide and waveguide cavity structure at high frequency, and is integrated with the RF front-end chip at the microsystem packaging level.

[0062] In order to meet the input dynamic range of the ADC at the back end of the filter and improve the signal-to-noise ratio of the output signal of the receiving channel to reduce the bit error rate, the filter on the receiving channel usually needs to provide a certain channel selectivity. Therefore, it is necessary to design a reconfigurable baseband bandwidth adjustable filter.

[0063] Specifically, in one embodiment of the present invention, step S22 specifically includes:

[0064] Variable gain is provided through a low-pass filter and a subsequent programmable amplifier to meet the dynamic range requirements of the entire channel, thereby configuring the filter gain and correction cutoff frequency.

[0065] The reconfigurable filter chip is realized based on the three architectures of integrated design of switch and filter bank, switching delay line and parameter adjustable RF filter. Figure 2 As shown in the figure, the passband phase difference (θ1-θ2) at a specific tap in the delay line at both ends of the power splitter and power combiner network is 0 or an integer multiple of 360°, realizing the synthesis of two equal-amplitude signals. Phase difference signals outside the passband cancel each other out to achieve suppression. The unit element selected by the switch ( Figure 2 The UE in the middle is a resonator, which further enhances the out-of-band suppression.

[0066] Figure 3Schematic diagram of a switch matrix in a broadband transceiver reconfigurable channel architecture design method provided by the present invention. In one embodiment of the present invention, Figure 3 As shown, the switch matrix in step S3 is a switch matrix constructed by cascading specific types of DPDT switches, and the switch matrix has a 4P4T function.

[0067] The switch matrix constructed using this method is relatively simple in structure and control, facilitating future PCB design. The switch matrix's switching function allows a single device to be reused across multiple paths, thereby reducing the number of devices with the same function. Furthermore, switching through the switch matrix allows different devices to be combined to create new signal transmission pathways.

[0068] Figure 4 This is a schematic diagram of channel isolation analysis in a broadband transceiver reconfigurable channel architecture design method provided by the present invention. Figure 4 As shown, the broadband transceiver reconfigurable channel architecture proposed by the present invention integrates a receiver, a transmitter, and a distributed clock generation circuit. The coupling properties are categorized as magnetic and electrical. Due to the limitations of the two-dimensional structure of the inductor, the magnetic field generated by the planar inductor on the chip inevitably interacts and couples with the magnetic fields of other inductors. The low-noise amplifier and baseband filter in the receiver, the oscillator in the clock generation circuit, the tuning buffer stage in the clock distribution circuit, and the output stage in the transmitter all utilize capacitor-inductor resonant cavities for tuning. Signal leakage during high-power transmitter outputs can cause crosstalk to the receiver, and the transmitter can also cause frequency offsets in the oscillator of the phase-locked loop (PLL), causing the VCO to deviate from its original resonant frequency.

[0069] In one embodiment of the present invention, the high isolation design of the channel in step S4 specifically includes:

[0070] Step S41: Eliminating magnetic coupling between on-chip inductors;

[0071] Step S42: Eliminate electrical coupling.

[0072] In one embodiment of the present invention, the present invention avoids the influence of magnetic coupling on on-chip integration through three approaches. Specifically, step S41 specifically includes:

[0073] S411. Optimize the layout: By optimizing the layout, sensitive inductors are placed in different areas for physical isolation to avoid near-field magnetic coupling.

[0074] S412. Optimize the inductor layout: Improve the inductor's resistance to external crosstalk by optimizing the inductor layout technology. Optimize the metal layer selection of the guard ring around the inductor to improve the inductor's ability to shield from external electromagnetic fields while maintaining its quality factor.

[0075] S413. Reasonable frequency planning: Reasonable frequency planning can prevent the resonant inductors from operating at the same frequency, thereby reducing the frequency deviation of the oscillator in the phase-locked loop.

[0076] Furthermore, the present invention optimizes the electrical coupling through the following three aspects, and step S42 specifically includes:

[0077] S421. To address the mutual coupling of different modules through the power network, during the PCB layout stage, physically separate different areas. Use digital isolators and buffers to achieve cross-domain signal isolation, reasonably isolate the RF, analog, and digital power networks, and use local decoupling capacitors to protect key modules to reduce the impact of power network coupling.

[0078] S422. Shield key signal lines to protect them from mutual coupling, and avoid overlapping of sensitive signal lines through reasonable layout.

[0079] S423. When the transmitter is outputting high power, the signal leaks through the bottom of the substrate to the receiver signal chain and the clock generation circuit module. Due to the crosstalk of the substrate, spurious signals appear in the received signal and the clock signal, resulting in a decrease in the signal-to-noise ratio. Combined with deep hydrazine isolation and layout, the influence of substrate coupling is reduced to ensure the performance of the chip after integration.

[0080] Figure 5 This is a schematic diagram of channel consistency analysis in a broadband transceiver reconfigurable channel architecture design method provided by the present invention. Figure 5 As shown, the deviations that affect channel consistency primarily come from three sources: first, electromagnetic coupling between channels; second, component mismatch caused by process variations during chip manufacturing, such as mismatch between identical components between channels, and clock deviation in clock distribution circuits due to variations in signal line resistance and capacitance; and third, channel characteristics vary under different temperatures and pressures. Based on their characteristics, these deviations can be categorized as random mismatch and deterministic mismatch. Random mismatch primarily arises from manufacturing process variations and can only be estimated during the design phase through Monte Carlo simulation. Deterministic mismatch typically arises from design and layout implementation, such as asymmetric placement and routing.

[0081] In one embodiment of the present invention, the channel consistency design in step S4 specifically includes:

[0082] The layout technology of multi-channel layout is used to reduce the coupling between channels and improve the interference suppression of channel input and output. At the system level, mismatch calibration technology is used to eliminate the influence of deviation factors between channels through calibration, and channel consistency is improved through collaborative design from the bottom layout to the top system.

[0083] In one embodiment of the present invention, the mismatch calibration technique includes:

[0084] At the transmitter, after convolutional coding of the data stream, each group of bits is mapped to a constellation diagram using a specific modulation scheme, generating a complex signal sequence X. The signal sequence is precoded using an uplink channel estimation coding matrix. OFDM modulation transforms the precoded frequency domain signal sequence into the time domain, generating time domain OFDM symbols. These symbols are then combined into independent data streams and mapped to the transmit link, with corresponding weights assigned to the time domain signals on each link.

[0085] At the receiving end, after the antenna receives the wireless signal, it first undergoes amplitude and phase adjustment through the receiving end's beamforming network. Then, it is down-converted to baseband and sampled to generate a baseband digital signal. Next, the digital signals are combined in the digital domain to complete the beamforming process. Finally, through demodulation, demapping, and channel decoding, the original complex signal sequence is obtained from the received signal.

[0086] Receive signal It can be expressed as:

[0087] (1);

[0088] In formula (1): Represents the corresponding error matrix of the receiving channel; Represents the transmit channel error response matrix, which is also a function of frequency in broadband systems; represents a matrix used to combine digital signals on each RF link in the digital domain; represents the receiving end beamforming network, which is used for amplitude and phase adjustment; represents the matrix for analog domain beamforming; represents the matrix for digital domain beamforming; H represents the air channel response; X represents the complex signal sequence, and n represents Gaussian white noise;

[0089] Formula (1) includes the amplitude-phase mismatch coefficients of the transmitter and receiver, the transmitter beamforming coefficients, and the receiver beamforming coefficients. Narrowband-based single-carrier calibration can be applied to each subcarrier to achieve broadband calibration.

[0090] The calibration process is actually to first obtain the corresponding error matrix, and then compensate the mismatch coefficient to the baseband digital signal through precoding.

[0091] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A design method for a broadband transceiver reconfigurable channel architecture, characterized in that: The following steps are involved: Step S1: Divide the working frequency band; Step S2: Design a reconfigurable filter to achieve adjustable center frequency and bandwidth; Step S3: Using the switch matrix to realize the combination of different functional modules of the system; Step S4: Implementing channel high isolation design and channel consistency design; Step S2 specifically includes: Step S21: designing a reconfigurable MEMS filter; Step S22: designing an on-chip reconfigurable filter; Step S21 specifically includes: The MEMS process supports high-Q passive components, adopts LC lumped structure at low frequencies, and integrated waveguide and waveguide cavity structure at high frequencies, and is integrated with the RF front-end chip at the microsystem packaging level; Step S22 specifically includes: Provide variable gain through the low-pass filter and the subsequent programmable amplifier to meet the dynamic range requirements of the entire channel, thereby configuring the filter gain and correction cutoff frequency; The high isolation design of the channel in step S4 specifically includes: Step S41: Eliminating magnetic coupling between on-chip inductors; Step S42: eliminating electrical coupling; Step S41 specifically includes: S411. Optimize the layout: By optimizing the layout, sensitive inductors are placed in different areas for physical isolation to avoid near-field magnetic coupling. S412. Optimize the inductor layout: Improve the inductor's resistance to external crosstalk by optimizing the inductor layout technology. Optimize the metal layer selection of the guard ring around the inductor to improve the inductor's ability to shield from external electromagnetic fields while maintaining its quality factor. S413. Reasonable frequency planning: Reasonable frequency planning can prevent the resonant inductors from operating at the same frequency, thereby reducing the frequency deviation of the oscillator in the phase-locked loop; Step S42 specifically includes: S421. To address the mutual coupling of different modules through the power network, during the PCB layout stage, physically separate different areas. Use digital isolators and buffers to achieve cross-domain signal isolation, reasonably isolate the RF, analog, and digital power networks, and use local decoupling capacitors to protect key modules to reduce the impact of power network coupling. S422. Shield key signal lines to protect them from mutual coupling, and avoid overlapping of sensitive signal lines through reasonable layout. S423. When the transmitter is outputting high power, the signal leaks through the substrate to the receiver signal chain and clock generation circuit module. Due to substrate crosstalk, spurious signals appear in the received signal and clock signal, resulting in a decrease in the signal-to-noise ratio. By combining deep hydrazine isolation and layout, the influence of substrate coupling is reduced to ensure the performance of the chip after integration. The channel consistency design in step S4 specifically includes: The layout technology of multi-channel layout is used to reduce the coupling between channels and improve the interference suppression of channel input and output. At the system level, mismatch calibration technology is used to eliminate the influence of deviation factors between channels through calibration, and channel consistency is improved through collaborative design from the bottom layout to the top system.

2. A method for designing a broadband transceiver reconfigurable channel architecture according to claim 1, characterized in that: The switch matrix in step S3 is a switch matrix constructed by cascading specific types of DPDT switches, and the switch matrix has a 4P4T function.

3. The method for designing a broadband transceiver reconfigurable channel architecture according to claim 1, wherein: The mismatch calibration technique includes: At the transmitter, after convolutional coding of the data stream, each group of bits is mapped to a constellation diagram using a specific modulation scheme, generating a complex signal sequence X. The signal sequence is precoded using an uplink channel estimation coding matrix. OFDM modulation transforms the precoded frequency domain signal sequence into the time domain, generating time domain OFDM symbols. These symbols are then combined into independent data streams and mapped to the transmit link, with corresponding weights assigned to the time domain signals on each link. At the receiving end, after the antenna receives the wireless signal, it first undergoes amplitude and phase adjustment through the receiving end's beamforming network. Then, it is down-converted to baseband and sampled to generate a baseband digital signal. Next, the digital signals are combined in the digital domain to complete the beamforming process. Finally, through demodulation, demapping, and channel decoding, the original complex signal sequence is obtained from the received signal. Receive signal It can be expressed as: （1）； In formula (1): Represents the corresponding error matrix of the receiving channel; Represents the transmit channel error response matrix, which is also a function of frequency in broadband systems; represents a matrix used to combine digital signals on each RF link in the digital domain; represents the receiving end beamforming network, which is used for amplitude and phase adjustment; represents the matrix for analog domain beamforming; represents the matrix for digital domain beamforming; H represents the air channel response; X represents the complex signal sequence, and n represents Gaussian white noise; Formula (1) includes the amplitude-phase mismatch coefficients of the transmitter and receiver, the transmitter beamforming coefficients, and the receiver beamforming coefficients. Narrowband-based single-carrier calibration can be applied to each subcarrier to achieve broadband calibration.

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