Radio frequency environment real-time computing device based on FPGA

Abstract

The invention discloses a radio frequency environment real-time computing device based on an FPGA (Field Programmable Gate Array). Based on the computing device, the invention also discloses a radio frequency environment real-time computing method based on the FPGA, and the method comprises the steps: obtaining a channel feature information set and a signal sampling time value; the channel characteristic information set comprises a channel multipath information set; the channel multipath information set comprises the path length of each multipath channel and a corresponding channel response sequence; performing time delay calculation processing on the channel characteristic information set and the signal sampling time value to obtain a multipath time delay value set; and on the basis of the multipath time delay value set and the channel characteristic information set, performing calculation processing on the acquired original signal to obtain a radio frequency environment signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal processing, and particularly relates to a real-time radio frequency environment computing device based on FPGA. Background Art

[0002] In fields such as wireless communication, during the system development process, an important part is the field test, that is, to evaluate the effectiveness of the developed device. In traditional tests, it is necessary to build these test environments in the real world. The construction of these environments is usually of high complexity, high cost, and low test efficiency, especially in scenarios involving long transmission distances, requiring the motion state of nodes, and needing a large number of accompanying test devices. To reduce the test complexity, currently, a wireless channel environment simulation device is mainly used to simulate the field test environment and evaluate the device under test. This involves using a real-time radio frequency environment computing device to achieve semi-physical simulation, that is, to digitize the real radio frequency signal of the device under test, perform real-time calculations in the digital domain, and then convert it into a radio frequency signal and send it to the device under test. This test method not only retains the real reliability of the test because the real radio frequency signal of the device under test is used for access, but also can greatly reduce the test complexity because only cable connection of devices is required in the laboratory, eliminating the complex process of constructing test conditions such as physical distance and moving speed in the field. In addition to being able to greatly reduce the complexity of building the field test environment, the use of a wireless channel environment simulation device also has a very good repeatability characteristic, that is, the wireless channel environment simulation device can very consistently reproduce the same test channel state. Due to the open characteristics of the wireless channel, there will always be some differences in practice, which is very difficult to achieve in field tests.

[0003] Currently, commercial wireless channel environment simulation devices can meet certain requirements for building test environments, but there are many disadvantages:

[0004] 1. Expensive. There are many factors causing the high price of commercial wireless channel environment simulation devices. One of them is that commercial wireless channel environment simulation devices usually have high specifications in order to have a certain universality, such as a wide frequency band coverage range, etc. And these are not necessarily required in the specific project usage requirements.

[0005] 2. Insufficient scene adaptation ability. Commercial wireless channel environment simulation devices usually adapt to some of the most typical scenarios in order to have universality in use. However, in real project requirements, the scenarios of wireless channels are usually complex and variable. In some scenarios, commercial wireless channel environment simulation devices may not be able to meet the requirements, or the cost is very high.

[0006] In view of the above reasons, the present invention proposes a real-time computing device for radio frequency environment based on FPGA, which has the characteristic of being reconfigurable and can flexibly determine the balance between the consumed FPGA resources and the performance of the implementation model according to needs. Summary of the Invention

[0007] The present invention mainly solves the problem of how to accurately simulate a wireless channel at low cost and in multiple types, and discloses a real-time computing method and device for radio frequency environment based on FPGA.

[0008] In the first aspect of the embodiment of the present invention, a real-time computing method for radio frequency environment based on FPGA is disclosed, including:

[0009] S1, obtaining a set of channel characteristic information and a signal sampling time value; the set of channel characteristic information includes a set of channel multipath information; the set of channel multipath information includes the path length of each multipath channel and the corresponding channel response sequence;

[0010] S2, performing delay calculation processing on the set of channel characteristic information and the signal sampling time value to obtain a set of multipath delay values;

[0011] S3, based on the set of multipath delay values and the set of channel characteristic information, performing calculation processing on the collected original signal to obtain a radio frequency environment signal.

[0012] The performing delay calculation processing on the set of channel characteristic information and the signal sampling time value to obtain a set of multipath delay values includes:

[0013] S21, dividing the path length of each multipath channel in the set of channel characteristic information by the speed of light respectively to obtain the corresponding multipath delay;

[0014] S22, dividing the multipath delay corresponding to the path length of each multipath channel by the signal sampling time value respectively to obtain the corresponding division result; determining the integer part of the division result as the integer delay corresponding to the path length of the multipath channel; determining the decimal part of the division result as the decimal delay corresponding to the path length of the multipath channel;

[0015] S23, using the integer delays and decimal delays corresponding to the path lengths of all multipath channels to construct a set of multipath delay values; the set of multipath delay values includes the integer delay and decimal delay corresponding to the path length of each multipath channel.

[0016] The performing calculation processing on the collected original signal based on the set of multipath delay values and the set of channel characteristic information to obtain a radio frequency environment signal includes:

[0017] S31. Using the integer delays corresponding to the path lengths of each multipath channel in the set of multipath delay values, construct an integer delay filter for the path lengths of the multipath channels;

[0018] S32. Using the fractional delays corresponding to the path lengths of each multipath channel in the set of multipath delay values, construct a fractional delay filter for the path lengths of the multipath channels;

[0019] S33. Using the channel response sequences corresponding to the path lengths of each multipath channel in the set of channel characteristic information, construct an amplitude response filter for the path lengths of the multipath channels;

[0020] S34. Connect in series the integer delay filter, the fractional delay filter, and the amplitude response filter for each path length of the multipath channels to obtain a multipath channel simulator corresponding to the path lengths of the multipath channels;

[0021] S35. Using the multipath channel simulator corresponding to each path length of the multipath channels, process the collected original signal respectively to obtain the corresponding output signal;

[0022] S36. Add up the output signals corresponding to all path lengths of the multipath channels to obtain a radio frequency environment signal.

[0023] The step of using the integer delays corresponding to the path lengths of each multipath channel in the set of multipath delay values to construct an integer delay filter for the path lengths of the multipath channels includes:

[0024] Determine that the integer delay corresponding to the path length of each multipath channel in the set of multipath delay values is the difference between the read address and the write address of the RAM memory; configure the working mode of the RAM memory as circular addressing, and determine that the RAM memory is the integer delay filter for the path lengths of the multipath channels.

[0025] The step of using the fractional delays corresponding to the path lengths of each multipath channel in the set of multipath delay values to construct a fractional delay filter for the path lengths of the multipath channels includes:

[0026] S321. Obtain the fractional delays corresponding to the path lengths of each multipath channel in the set of multipath delay values;

[0027] S322. Determine the fractional index value closest to the fractional delay value in a preset fractional delay filter coefficient lookup table; the fractional delay filter coefficient lookup table includes a number of fractional index values and the corresponding coefficient vectors of the fractional delay filter;

[0028] S323. Construct the fractional delay filter for the multipath channel path length by using the coefficient vector of the fractional delay filter corresponding to the fractional index value in the fractional delay filter coefficient lookup table.

[0029] The constructing the fractional delay filter for the multipath channel path length by using the fractional delay corresponding to each multipath channel path length in the set of multipath delay values includes:

[0030] S321. Obtain the fractional delay corresponding to each multipath channel path length in the set of multipath delay values;

[0031] S322. Determine the N fractional index values closest to the fractional delay value in the preset fractional delay filter coefficient lookup table;

[0032] S323. Based on the N closest fractional index values, respectively obtain the coefficient vectors of the fractional delay filters corresponding to them in the fractional delay filter coefficient lookup table;

[0033] S324. Perform a fusion calculation process on the obtained N coefficient vectors to obtain a fractional filter vector;

[0034] S325. Use the fractional filter vector as the coefficient vector of the fractional delay filter to construct the fractional delay filter for the multipath channel path length.

[0035] The expression of the fusion calculation process is:

[0036]

[0037] where x0 is the fractional delay corresponding to the multipath channel path length, xi is the i-th fractional index value among the N closest fractional index values, εij is the j-th term of the coefficient vector of the fractional delay filter corresponding to the i-th fractional index value in the fractional delay filter coefficient lookup table, and υj is the j-th term of the fractional filter vector. i is the i-th fractional index value among the N closest fractional index values, ε ij is the j-th term of the coefficient vector of the fractional delay filter corresponding to the i-th fractional index value in the fractional delay filter coefficient lookup table, υ j is the j-th term of the fractional filter vector.

[0038] In the second aspect of the embodiments of the present invention, a real-time calculation device for a radio frequency environment based on FPGA is disclosed. The device includes:

[0039] A memory storing executable program code;

[0040] A processor coupled to the memory;

[0041] The processor calls the executable program code stored in the memory and executes the above-mentioned real-time calculation method for the radio frequency environment based on FPGA.

[0042] In the third aspect of the embodiments of the present invention, a computer - storable medium is disclosed. The computer - storable medium stores computer instructions, which are used to execute the real - time calculation method of the radio frequency environment based on FPGA when called by a computer.

[0043] In the fourth aspect of the embodiments of the present invention, an information data processing terminal is disclosed. The information data processing terminal is used to implement the real - time calculation method of the radio frequency environment based on FPGA.

[0044] The beneficial effects of the present invention are as follows:

[0045] The present invention provides a reconfigurable radio frequency environment real - time calculation device based on FPGA. The advantages and positive effects of the present invention are as follows: Compared with the prior art, the present invention makes full use of the reconfigurable characteristics of FPGA and the characteristics of the storage resources being divided into blocks in FPGA, combines the integration degree and reconfigurability to implement the tapped delay line structure, greatly reduces the usage cost compared with commercial wireless channel environment simulation devices, and can flexibly provide scene adaptability for specific projects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is the flowchart of the implementation of the method of the present invention;

[0047] Figure 2 is a schematic diagram of a typical wireless channel environment simulation device constructed based on the method of the present invention;

[0048] Figure 3 is a schematic diagram of the continuous fractional - delay filter based on look - up table and interpolator of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] To better understand the content of the present invention, an embodiment is given here.

[0050] Figure 1 is the flowchart of the implementation of the method of the present invention; Figure 2 is a schematic diagram of a typical wireless channel environment simulation device constructed based on the method of the present invention; Figure 3 is a schematic diagram of the continuous fractional - delay filter based on look - up table and interpolator of the present invention.

[0051] In the first aspect of the embodiments of the present invention, a real - time calculation method of a radio frequency environment based on FPGA is disclosed, including:

[0052] S1, obtaining a set of channel characteristic information and a signal sampling time value; the set of channel characteristic information includes a set of channel multipath information; the set of channel multipath information includes the path length of each multipath channel and the corresponding channel response sequence;

[0053] S2. Perform a time delay calculation process on the channel characteristic information set and the signal sampling time value to obtain a multipath time delay value set;

[0054] S3. Based on the multipath time delay value set and the channel characteristic information set, perform a calculation process on the collected original signal to obtain a radio frequency environment signal.

[0055] The radio frequency environment signal is used to characterize the signal after the original signal passes through the channel;

[0056] The performing a time delay calculation process on the channel characteristic information set and the signal sampling time value to obtain a multipath time delay value set includes:

[0057] S21. Divide the length of each multipath signal path in the channel characteristic information set by the speed of light respectively to obtain the corresponding multipath time delay;

[0058] S22. Divide the multipath time delay corresponding to the length of each multipath signal path by the signal sampling time value respectively to obtain the corresponding division result; determine the integer part of the division result as the integer time delay corresponding to the length of the multipath signal path; determine the decimal part of the division result as the decimal time delay corresponding to the length of the multipath signal path;

[0059] S23. Use the integer time delay and decimal time delay corresponding to the length of all multipath signal paths to construct a multipath time delay value set; the multipath time delay value set includes the integer time delay and decimal time delay corresponding to the length of each multipath signal path.

[0060] The performing a calculation process on the collected original signal based on the multipath time delay value set and the channel characteristic information set to obtain a radio frequency environment signal includes:

[0061] S31. Use the integer time delay corresponding to the length of each multipath signal path in the multipath time delay value set to construct an integer time delay filter for the length of the multipath signal path;

[0062] S32. Use the decimal time delay corresponding to the length of each multipath signal path in the multipath time delay value set to construct a fractional time delay filter for the length of the multipath signal path;

[0063] S33. Use the channel response sequence corresponding to the length of each multipath signal path in the channel characteristic information set to construct an amplitude response filter for the length of the multipath signal path;

[0064] S34. Connect in series the integer time delay filter, fractional time delay filter, and amplitude response filter for the length of each multipath signal path to obtain a multipath channel simulator for the length of the multipath signal path;

[0065] S35. Use the multipath channel simulator corresponding to each multipath channel path length to process the originally collected signals respectively to obtain corresponding output signals;

[0066] S36. Add up the output signals corresponding to all multipath channel path lengths to obtain a radio frequency environment signal.

[0067] The method for constructing the integer delay filter for the multipath channel path length by using the integer delay corresponding to each multipath channel path length in the multipath delay value set includes:

[0068] Determine that the integer delay corresponding to each multipath channel path length in the multipath delay value set is the difference between the read address and the write address of the RAM memory; configure the working mode of the RAM memory as circular addressing, and determine that the RAM memory is the integer delay filter for the multipath channel path length.

[0069] The method for constructing the fractional delay filter for the multipath channel path length by using the fractional delay corresponding to each multipath channel path length in the multipath delay value set includes:

[0070] S321. Obtain the fractional delay corresponding to each multipath channel path length in the multipath delay value set;

[0071] S322. Determine the fractional index value closest to the fractional delay value in the preset fractional delay filter coefficient lookup table; the fractional delay filter coefficient lookup table includes several fractional index values and corresponding coefficient vectors of the fractional delay filter.

[0072] S323. Use the coefficient vector of the fractional delay filter corresponding to the fractional index value in the fractional delay filter coefficient lookup table to construct the fractional delay filter for the multipath channel path length.

[0073] The method for constructing the fractional delay filter for the multipath channel path length by using the fractional delay corresponding to each multipath channel path length in the multipath delay value set includes:

[0074] S321. Obtain the fractional delay corresponding to each multipath channel path length in the multipath delay value set;

[0075] S322. Determine N fractional index values closest to the fractional delay value in the preset fractional delay filter coefficient lookup table;

[0076] S323. Based on the closest N fractional index values, respectively obtain the coefficient vectors of the fractional delay filters corresponding to them in the fractional delay filter coefficient lookup table;

[0077] S324. Perform fusion calculation processing on the obtained N coefficient vectors to obtain a fractional filter vector;

[0078] S325. Use the fractional filter vector as the coefficient vector of the fractional delay filter to construct the fractional delay filter for the multipath signal path length.

[0079] The expression for the fusion calculation processing is:

[0080]

[0081] where x0 is the fractional delay corresponding to the multipath signal path length, x i is the i-th fractional index value of the N closest fractional index values, ε ij is the j-th term of the coefficient vector of the fractional delay filter corresponding to the i-th fractional index value in the fractional delay filter coefficient lookup table, v j is the j-th term of the fractional filter vector.

[0082] The fractional delay filter can be implemented using a fractional delay filter.

[0083] The performing fusion calculation processing on the obtained N coefficient vectors to obtain a fractional filter vector includes:

[0084] Use the obtained N coefficient vectors to construct a coefficient matrix;

[0085] Perform singular value calculation on the coefficient matrix to obtain singular values and singular vectors;

[0086] Calculate the rank value and trace value of the coefficient matrix;

[0087] Perform fractional filter vector calculation on the coefficient matrix and N fractional index values to obtain a fractional filter vector;

[0088] The expression for the fractional filter vector calculation is:

[0089]

[0090] where θ1 and θ2 are respectively a preset first weight value and a second weight value, z is the rank value, p is the trace value, λ0 is the average value of all singular values, x i is the i-th fractional index value of the N closest fractional index values, xs ij is the element in the i-th row and j-th column of the coefficient matrix, λ i is the i-th singular value of the coefficient matrix, qs ij is the j-th element of the i-th singular vector of the coefficient matrix.

[0091] The serial connection of the integer delay filter, the fractional delay filter, and the amplitude response filter is to use the input of the integer delay filter as the input of the multipath channel simulator, use the output of the amplitude response filter as the output of the multipath channel simulator, use the output of the integer delay filter as the input of the fractional delay filter, and use the output of the fractional delay filter as the input of the amplitude response filter.

[0092] The construction of the amplitude response filter for the multipath channel path length by using the channel response sequence corresponding to each multipath channel path length in the channel characteristic information set includes:

[0093] Using the channel response sequence corresponding to each multipath channel path length in the channel characteristic information set as the coefficients of the FIR filter, constructing an FIR filter, and using the FIR filter as the amplitude response filter for the multipath channel path length.

[0094] The method of the present invention can be implemented using an FPGA development board.

[0095] In summary, the advantages and positive effects of the present invention are as follows: Compared with the prior art, the present invention makes full use of the reconfigurable characteristics of the FPGA and the characteristics of the segmented storage resources in the FPGA, combines the integration and reconfigurability to implement the tapped delay line structure, greatly reduces the usage cost compared with commercial wireless channel environment simulation devices, and can flexibly provide scenario adaptability for specific projects.

[0096] In the second aspect of the embodiment of the present invention, a real-time computing device for a radio frequency environment based on an FPGA is disclosed. The device includes:

[0097] A memory storing executable program code;

[0098] A processor coupled to the memory;

[0099] The processor calls the executable program code stored in the memory to execute the above-mentioned real-time computing method for the radio frequency environment based on an FPGA.

[0100] In the third aspect of the embodiment of the present invention, a computer-readable storage medium is disclosed. The computer-readable storage medium stores computer instructions, and when the computer instructions are called by the computer, they are used to execute the above-mentioned real-time computing method for the radio frequency environment based on an FPGA.

[0101] In the fourth aspect of the embodiment of the present invention, an information data processing terminal is disclosed. The information data processing terminal is used to implement the above-mentioned real-time computing method for the radio frequency environment based on an FPGA.

[0102] In the fifth aspect of the embodiments of the present invention, a real-time computing device for radio frequency environment based on FPGA is disclosed. The device includes the following processing steps:

[0103] S1. For the input signal, use FIFO to form a tapped delay line structure, update the delay coefficient at the signal sampling rate, implement the integer delay part of the continuous delay change of the path, and form the original input signal of multiple paths.

[0104] S2. For each multipath, use a fractional delay filter, update the delay coefficient at the signal sampling rate, implement the fractional delay part of the continuous delay change of the path, and complete the simulation of the continuous delay change of the path.

[0105] S3. For the fractional delay filter, adopt the method of combining a look-up table and coefficient interpolation to implement continuous fractional delay simulation.

[0106] S4. Use a multi-tap FIR filter to form the simulation of channel characteristics, such as path fading, scattering characteristics of reflectors, etc.

[0107] The real-time computing device for radio frequency environment based on FPGA of the present invention can be flexibly tailored according to the reconfigurable characteristics of FPGA for different scenario requirements to achieve the required channel simulation effect. It can realize the simulation of time-varying channels including large-scale fading, small-scale fading, Doppler effect and time-selective fading, multipath effect and frequency-selective fading, etc.

[0108] In implementation, the propagation path distance generated in real time is converted into delay, and decomposed into an integer delay part and a fractional delay part according to the sampling rate, and respectively configured as the read and write addresses of the integer delay part FIFO and the fractional delay input of the fractional delay filter.

[0109] For the fractional delay filter, first store the coefficients of 64 groups of fractional delay filters in the local look-up table, covering the delay range of 0-1. For a given fractional delay input, first judge which two groups of the 64 groups of fractional delay filters it is located in, and then read out and use the linear interpolation method to generate the coefficients of the filter corresponding to the fractional delay input.

[0110] For each tap of the FIR filter, if the model is simplified to a single-point reflection, only 1 group of complex coefficients can be retained for the FIR filter. Its modulus is the amplitude fading of this path, the phase is the phase shift of this path, and the rest of the coefficients are 0. If the model needs to reflect a certain scattering characteristic of this path, multiple taps of the FIR can be used.

[0111] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A real-time calculation method for radio frequency environment based on FPGA, characterized in that Including: S1. Obtain a set of channel characteristic information and a signal sampling time value; the set of channel characteristic information includes a set of channel multipath information; the set of channel multipath information includes the path length of each multipath channel and the corresponding channel response sequence; S2. Perform delay calculation processing on the set of channel characteristic information and the signal sampling time value to obtain a set of multipath delay values; S3. Based on the set of multipath delay values and the set of channel characteristic information, perform calculation processing on the collected original signal to obtain a radio frequency environment signal.

2. The real-time computing method for radio frequency environment based on FPGA according to claim 1, wherein, The performing delay calculation processing on the set of channel characteristic information and the signal sampling time value to obtain a set of multipath delay values includes: S21. Divide the path length of each multipath channel in the set of channel characteristic information by the speed of light respectively to obtain the corresponding multipath delay; S22. Divide the multipath delay corresponding to the path length of each multipath channel by the signal sampling time value respectively to obtain the corresponding division result; determine the integer part of the division result as the integer delay corresponding to the path length of the multipath channel; determine the decimal part of the division result as the fractional delay corresponding to the path length of the multipath channel; S23. Use the integer delays and fractional delays corresponding to the path lengths of all multipath channels to construct a set of multipath delay values; the set of multipath delay values includes the integer delay and fractional delay corresponding to the path length of each multipath channel.

3. The real-time calculation method of radio frequency environment based on FPGA according to claim 1, characterized in that The performing calculation processing on the collected original signal based on the set of multipath delay values and the set of channel characteristic information to obtain a radio frequency environment signal includes: S31. Use the integer delay corresponding to the path length of each multipath channel in the set of multipath delay values to construct an integer delay filter for the path length of the multipath channel; S32. Use the fractional delay corresponding to the path length of each multipath channel in the set of multipath delay values to construct a fractional delay filter for the path length of the multipath channel; S33. Use the channel response sequence corresponding to the path length of each multipath channel in the set of channel characteristic information to construct an amplitude response filter for the path length of the multipath channel; S34. Connect in series the integer delay filter, fractional delay filter, and amplitude response filter for the path length of each multipath channel to obtain a multipath channel simulator corresponding to the path length of the multipath channel; S35. Use the multipath channel simulator corresponding to the path length of each multipath channel to process the collected original signal respectively to obtain the corresponding output signal; S36. Add up the output signals corresponding to the path lengths of all multipath channels to obtain a radio frequency environment signal.

4. The real-time computing method for radio frequency environment based on FPGA according to claim 3, wherein The using the integer delay corresponding to the path length of each multipath channel in the set of multipath delay values to construct an integer delay filter for the path length of the multipath channel includes: Determine the integer delay corresponding to the path length of each multipath channel in the set of multipath delay values as the difference between the read address and the write address of the RAM memory; configure the working mode of the RAM memory as circular addressing, and determine the RAM memory as the integer delay filter for the path length of the multipath channel.

5. The real-time calculation method of radio frequency environment based on FPGA according to claim 3, characterized in that Constructing the fractional delay filter for the multipath signal path length by using the fractional delays corresponding to the lengths of each multipath signal path in the set of multipath delay values includes: S321. Obtaining the fractional delay corresponding to the length of each multipath signal path in the set of multipath delay values; S322. Determining the fractional index value closest to the fractional delay value in a preset fractional delay filter coefficient look-up table; the fractional delay filter coefficient look-up table includes a plurality of fractional index values and corresponding coefficient vectors of the fractional delay filter; S323. Constructing the fractional delay filter for the multipath signal path length by using the coefficient vector of the fractional delay filter corresponding to the fractional index value in the fractional delay filter coefficient look-up table.

6. The real-time computing method for radio frequency environment based on FPGA according to claim 3, characterized in that Constructing the fractional delay filter for the multipath signal path length by using the fractional delays corresponding to the lengths of each multipath signal path in the set of multipath delay values includes: S321. Obtaining the fractional delay corresponding to the length of each multipath signal path in the set of multipath delay values; S322. Determining N fractional index values closest to the fractional delay value in a preset fractional delay filter coefficient look-up table; S323. Respectively obtaining the coefficient vectors of the fractional delay filter corresponding to them in the fractional delay filter coefficient look-up table based on the N closest fractional index values; S324. Performing a fusion calculation process on the N obtained coefficient vectors to obtain a fractional filter vector; S325. Constructing the fractional delay filter for the multipath signal path length by using the fractional filter vector as the coefficient vector of the fractional delay filter.

7. The real-time computing method for radio frequency environment based on FPGA according to claim 6, wherein The expression of the fusion calculation process is: where x0 is the fractional delay corresponding to the multipath channel path length, x i is the i-th fractional index value of the N closest fractional index values, ε ij is the j-th term of the coefficient vector of the fractional delay filter corresponding to the i-th fractional index value in the fractional delay filter coefficient lookup table, υ j is the j-th term of the fractional filter vector.

8. A real-time computing device for radio frequency environment based on FPGA, characterized in that, The device includes: A memory storing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory and executes the FPGA-based real-time radio frequency environment calculation method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, which are used to execute the FPGA-based real-time radio frequency environment calculation method according to any one of claims 1 to 7 when called by a computer.

10. An information data processing terminal, characterized in that, The information data processing terminal is used to implement the FPGA-based real-time radio frequency environment calculation method according to any one of claims 1 to 7.

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