Network card based on computational link protocol, data transmission method, equipment and product

Abstract

The invention discloses a network card based on a computing link protocol, a data transmission method, equipment and a product, which are applied to the technical field of communication, and comprise: an interface control module is used for receiving a data sending request sent by a host and sending the data sending request to a logic module; the storage control module is used for receiving a data sending request through the logic module and writing a data packet descriptor carried in the data sending request into a sending queue of a storage device connected with the network card; the logic module is used for sending the write-in address of the data packet descriptor to the network interface module; the network interface module is used for obtaining the data packet which is pointed by the data packet descriptor and is stored in the storage device through the interface control module after receiving the write-in address of the data packet descriptor, and outputting the data packet to the outside; the interface control module uses a computing link protocol to enable a storage device connected with the network card and a host memory to be addressed and used in a unified manner. By applying the scheme of the invention, the data transmission delay of the network card can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technologies, and in particular, to a network card, a data transmission method, a device, and a product based on a Compute Link protocol. Background Art

[0002] Traditional network cards implemented based on FPGA (Field Programmable Gate Array) can be connected to a host through a PCIe (Peripheral Component Interconnect express) protocol interface. With the development of computing systems, the requirements for high bandwidth, low latency, and efficient data transmission are increasing, and traditional PCIe-based interconnect technologies are increasingly unable to meet the needs.

[0003] In summary, how to effectively reduce the latency of a network card sending data is a technical problem that those skilled in the art urgently need to solve at present. Summary of the Invention

[0004] The present application provides a network card, a data transmission method, a device, and a product based on a Compute Link protocol to effectively reduce the latency of a network card sending data.

[0005] The present application provides a network card based on a Compute Link protocol, including: An interface control module, configured to receive a data sending request sent by a host and send it to a logic module; A storage control module, configured to receive the data sending request through the logic module and write a packet descriptor carried in the data sending request into a sending queue of a storage device connected to the network card; The logic module, configured to send a write address of the packet descriptor to a network interface module; The network interface module, configured to, after receiving the write address of the packet descriptor, obtain, through the interface control module, a packet stored in the storage device pointed to by the packet descriptor and output the packet externally; Wherein, the interface control module is an interface control module using a Compute Link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

[0006] The present application provides a data transmission method based on a Compute Link protocol, which is applied to an interface control module in the network card based on a Compute Link protocol as described above, and includes: Receive the data transmission request sent by the receiving host and send it to the logic module, so that the storage control module receives the data transmission request through the logic module, writes the packet descriptor carried in the data transmission request into the transmission queue of the storage device connected to the network card, and makes the logic module send the write address of the packet descriptor to the network interface module; After the network interface module receives the write address of the packet descriptor, obtain the packet stored in the storage device pointed to by the packet descriptor through communication with the network interface module, and send the packet to the network interface module, so that the network interface module outputs the packet externally; Wherein, the interface control module is an interface control module using the Compute Link Protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

[0007] This application provides an electronic device, including: A memory for storing computer programs; A processor for implementing the steps of the data transmission method based on the Compute Link Protocol as described above when executing the computer program.

[0008] This application provides a computer program product, including a computer program, and the computer program implements the steps of the data transmission method based on the Compute Link Protocol as described above when executed by a processor.

[0009] The solution of this application takes into account that the Compute Link Protocol is an innovative high-speed interconnect technology that can provide a more efficient and flexible connection method for processors, accelerators, and storage devices, can achieve more excellent performance and lower latency, and thus meet the requirements of modern computing applications for high bandwidth and low latency. However, there is currently no network card that supports the Compute Link Protocol, and the solution of this application is to implement a network card based on the Compute Link Protocol. Specifically, the hardware of the network card can be implemented by an FPGA acceleration card, with a storage device externally mounted on the FPGA, and can be controlled by a storage control module on the FPGA.

[0010] The interface control module inside the network card is connected to the host using the Compute Link protocol. It can receive the data transmission request sent by the host and send it to the logic module. It should be noted that since the interface control module is an interface control module using the Compute Link protocol, the storage device connected to the network card and the host memory are uniformly addressed. This means that during the operation of the network card in the solution of this application, there is no need to perform address conversion. When obtaining a packet descriptor through the data transmission request sent by the host, the packet descriptor can be directly written into the transmission queue of the storage device according to the write address of the data transmission request, which is simple and convenient to operate. Subsequently, when obtaining the packet using the packet descriptor, there is also no need to perform address conversion, which is simple and convenient to operate and is beneficial to reducing the transmission delay.

[0011] Furthermore, in the solution of this application, the process of writing the packet descriptor and the process of triggering the network interface module (i.e., triggering the network card doorbell) through the packet descriptor are carried out simultaneously, rather than being divided into two steps as in the traditional solution. Specifically, for the data transmission request sent by the host, the interface control module will send it to the logic module, enabling the logic module to trigger the network card doorbell, that is, the logic module will send the write address of the packet descriptor to the network interface module. At the same time, the logic module will also send the data transmission request to the storage control module, enabling the storage control module to write the packet descriptor carried in the data transmission request into the transmission queue of the storage device connected to the network card. Since the two processes are carried out simultaneously, the delay in sending packets is significantly reduced. Finally, after receiving the write address of the packet descriptor, the network interface module can obtain the packet stored in the storage device pointed to by the packet descriptor through the interface control module and output the packet externally. In addition, since both the packet descriptor and the packet are stored in the storage device mounted on the network card, the time taken for the network card of the solution of this application to read the packet descriptor and the packet is very short, which is also beneficial to reducing the delay in sending data by the network card.

[0012] In summary, it can be seen that the solution of this application can effectively reduce the delay in sending data by the network card. Brief Description of the Drawings

[0013] In order to more clearly illustrate the embodiments of this application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Figure 1 It is a schematic structural diagram of a traditional network card implemented based on FPGA; Figure 2 It is a schematic structural diagram of a network card based on the Compute Link protocol provided by a specific embodiment of the present invention; Figure 3 Schematic diagram of the network card based on the Compute Link Protocol provided by another specific embodiment of the present invention; Figure 4 Schematic diagram of a storage device provided by another specific embodiment of the present invention in which a plurality of transmission queues are provided; Figure 5 Schematic diagram of the conversion module in a specific embodiment of the present invention; Figure 6 Schematic diagram of the connection between the network card and the host in a specific embodiment of the present invention; Figure 7 Flowchart of the implementation of the data transmission method based on the Compute Link Protocol in a specific embodiment of the present invention; Figure 8 Schematic diagram of the electronic device in a specific embodiment of the present invention; Figure 9 Schematic diagram of a computer-readable storage medium of the present invention. Specific embodiments

[0014] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0015] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0016] Reference may be made to Figure 1 , Figure 1It is a schematic structural diagram of a traditional network card implemented based on FPGA. First, the host stores the network packet to be sent (packet) in the host memory, and writes the storage address and length of the packet in the host memory as a descriptor into the transmit queue (tx_queue). Then, the network card doorbell is triggered through the BAR (Base Address Register), that is, the position of the descriptor in the transmit queue is written into the doorbell register of the network card. After triggering the network card doorbell, a DMA (Direct Memory Access) read operation is initiated to the host through the PCIe terminal (PCIE_ED IP). First, the descriptor of the packet needs to be read from the host memory to the FPGA, and then, according to the descriptor content, a DMA read operation is initiated to the host to read the packet from the host memory to the FPGA, and finally the packet is sent to the network. The FPGA internally consists of two parts, one is the PCIe terminal with DMA function, and the other is the network card function logic (NIC). The DMA_rd_desc port of the PCIe terminal can receive the DMA read descriptor sent by the NIC, and the DMA_rd_AVMM port of the PCIe terminal can write the DMA read data into the NIC. With the development of computing systems, the requirements for high bandwidth, low latency, and efficient data transmission are getting higher and higher, Figure 1 this traditional PCIe-based interconnection technology is increasingly unable to meet the requirements.

[0017] To enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments. Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of a network card based on the Compute Link Protocol provided by a specific embodiment of the present invention. The network card based on the Compute Link Protocol may include: An interface control module 10, configured to receive a data transmission request sent by the host and send it to the logic module 20; A storage control module 30, configured to receive the data transmission request through the logic module 20, and write the packet descriptor carried in the data transmission request into the transmit queue of the storage device connected to the network card; A logic module 20, configured to send the write address of the packet descriptor to the network interface module 40; A network interface module 40, configured to, after receiving the write address of the packet descriptor, obtain the packet stored in the storage device pointed to by the packet descriptor through the interface control module 10, and output the packet externally; wherein, the interface control module 10 is an interface control module 10 using the Compute Link Protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

[0018] In the solution of this application, the hardware implementation of the network card can be set according to actual needs. For example, it can usually be implemented by an FPGA acceleration card. There is a storage device externally mounted on the network card. As HDM (Host-managed Device Memory), it can be controlled by the network interface module 40 on the network card, that is, controlled by the HDM_controller module on the network card. This storage device can be, for example, a DDR4 (Double Data Rate 4th Generation) storage device. In the solution of this application, both data packets and data packet descriptors are stored in the storage device.

[0019] The network card needs to be connected to the host using the Compute Link Protocol. Since the Compute Link Protocol is used, the storage device mounted on the network card and the host memory can be unifiedly addressed and used. That is, during the operation of the network card in this application, no address conversion is required for the address of the data packet descriptor and the address of the data packet, which is beneficial to improving efficiency and reducing the latency of the network card sending data.

[0020] The specific type of the Compute Link Protocol can be set and adjusted according to actual needs, as long as it can meet the requirements of the solution of this application and enable the storage device connected to the network card and the host memory to be unifiedly addressed and used. For example, in a specific implementation, considering that the CXL (Compute Express Link) protocol is a high-speed interconnect technology that can provide a more efficient and flexible connection method for processors, accelerators, and storage devices. The emergence of the CXL architecture has brought revolutionary changes to computer hardware design and system optimization, enabling more excellent performance and lower latency, and thus meeting the urgent needs of modern computing applications for high bandwidth and low latency. Therefore, the Compute Link Protocol described in this application can be specifically the CXL protocol, and specifically, for example, the type2 mode of CXL.

[0021] The interface control module 10 is an interface terminal using the Compute Link Protocol. When the Compute Link Protocol is specifically the CXL protocol and specifically uses the type2 mode, the interface control module 10 is specifically the CXL type2 terminal IP, which can be denoted as cxl_type2_ed ip.

[0022] The interface control module 10 can receive a data transmission request sent by a host. And the interface control module 10 can send the data transmission request to the logic module 20. The packet descriptor carried in the data transmission request is the content that needs to be specifically written into the transmission queue later, and the destination address of the data transmission request, which is also the write address of the packet descriptor, determines the specific position where the packet descriptor is written in the transmission queue. The packet descriptor usually consists of the starting address of the packet and the length of the packet, and is used to locate the storage position of the packet.

[0023] The storage control module 30, that is, the HDM_controller module, can receive the data transmission request through the logic module 20, and then write the packet descriptor carried in the data transmission request into the transmission queue of the storage device connected to the network card.

[0024] In a specific embodiment of the present invention, the storage control module 30 can be specifically used for: Through the logic module 20, receive the packet descriptor carried in the data transmission request from the write data channel, and receive the write address of the packet descriptor from the write address channel; Based on the write address of the packet descriptor, write the packet descriptor into the transmission queue of the storage device connected to the network card.

[0025] This embodiment takes into account that the interface control module 10 is usually specifically a CXL type2 terminal IP, and specifically uses an AXI bus port to connect to the storage control module 30 to control the reading and writing of the external storage device. In this embodiment, the storage control module 30 specifically receives the packet descriptor carried in the data transmission request through the write data channel, and receives the write address of the packet descriptor through the write address channel.

[0026] For easy understanding, refer to Figure 3 , Figure 3In the example, the interface control module 10 is specifically a CXL type2 terminal IP. The port used to connect to the storage control module 30 through the logic module 20 is an AXI bus port, and three channels of this AXI bus port are shown, namely the AW channel, the W channel, and the B channel. Among them, the AW channel is the write address channel, the W channel is the write data channel, and the B channel is the write confirmation channel. Correspondingly, the write address channel AW, the write data channel W, and the write confirmation channel B of the storage control module 30 can be connected to the corresponding channels of the storage control module 30 through the logic module 20. Therefore, in this implementation manner, the logic module 20 can obtain the packet descriptor carried in the data send request from the write data channel and determine the write address of the packet descriptor from the write address channel. After the packet descriptor and the write address of the packet descriptor are transmitted to the storage control module 30, the storage control module 30 can write the packet descriptor to the corresponding position of the send queue of the storage device according to this write address. In addition, other channels of this AXI bus port, such as the read data channel, etc., may not need to pass through the logic module 20 but be directly connected to the storage control module 30. Figure 3 For the sake of easy viewing, it is not shown in the figure.

[0027] In addition to being written to the send queue by the storage control module 30, the packet descriptor also needs to be used by the logic module 20 to trigger the network interface module 40, that is, to trigger the doorbell of the network interface module 40, so that the network interface module 40 will obtain the corresponding packet through the interface control module 10, and then realize the external output of the packet. And in the solution of this application, the process of writing the packet descriptor to the send queue and the process of triggering the doorbell are carried out simultaneously, rather than being divided into two steps as in the traditional solution, so the delay of sending packets is greatly reduced.

[0028] In a specific implementation manner of the present invention, a first register and a second register are provided in the logic module 20. The value in the first register is the starting physical address of the send queue of the storage device, and the value in the second register is the space size of the send queue of the storage device. The logic module 20 is specifically used for: Based on the values of the first register and the second register, determine whether the write address of the packet descriptor belongs to the address range of the send queue of the storage device. If so, send the write address of the packet descriptor to the doorbell register in the network interface module 40.

[0029] In this implementation manner, the logic module 20 specifically realizes address judgment based on the values of the first register and the second register, so as to determine whether to trigger the doorbell.

[0030] For example, in a specific scenario, the storage device externally attached to the network card has an address space of 4 GB, and for example, the physical address range is from 0x100000000 to 0x1ffffffff. The starting physical address of the transmit queue is, for example, 0x100000000, and the entire transmit queue occupies 0x400000 bytes of space. It can be seen that in this example, the starting physical address of the transmit queue is, for example, 0x100000000, and the ending physical address is 0x1003fffff. Then, 0x100000000 needs to be stored in the first register, and 0x400000 needs to be stored in the second register. And it can be seen that in this example, the starting physical address of the transmit queue is exactly the starting physical address of the entire address space of the storage device.

[0031] For example, in a specific scenario, the host software needs to send a certain data packet. The starting physical address of the data packet is 0x101000000, and the length is 1024 bytes. Then the host can use (0x101000000) and (1024) as the packet descriptor of the data packet, and through a data transmission request, write the packet descriptor into the transmit queue. And for example, the destination address of the data transmission request is 0x100001000. Then, based on the value (0x100000000) in the first register and the value (0x400000) in the second register, the logic module 20 can determine that the write address (0x100001000) of the packet descriptor belongs to the address range of the transmit queue of the storage device, that is, it belongs to the address range from 0x100000000 to 0x1003fffff. Therefore, the logic module 20 will send the write address of the packet descriptor to the doorbell register in the network interface module 40, thereby triggering the doorbell.

[0032] In addition, it can be understood that if it is determined based on the values in the first register and the second register that the address on the AW channel does not belong to the address range of the transmit queue of the storage device, it means that the current is not writing a packet descriptor, and there is no need to trigger the doorbell. That is, the logic module 20 does not need to write to the doorbell register, and only needs to transparently transmit the write address on the AW channel and the write data on the W channel from the interface control module 10 to the storage control module 30.

[0033] Multiple transmission queues can be set in the storage device. For example, in practical applications, thousands of transmission queues can be supported to independently transmit data packets. Since multiple transmission queues are set, in practical applications, in order to facilitate determining the data packet descriptor that needs to be written into the transmission queue currently and specifically which transmission queue it should be written into, these transmission queues in the storage device can have the same size and be consecutively addressed. That is to say, multiple consecutively addressed transmission queues are set in the storage device, and the storage space occupied by each transmission queue is the same, so that based on the write address of the data packet descriptor, the specific write position of the data packet descriptor can be determined conveniently and quickly. Refer to Figure 4 Figure Figure 4 is a schematic structural diagram of a storage device with multiple transmission queues set in a specific embodiment. The occupied space size of each transmission queue remains the same, and the addresses of each transmission queue are consecutive, that is Figure 4 In the example, from transmission queue 0 to transmission queue 2, they are consecutively addressed. Of course, Figure 4 only 3 transmission queues are shown in Figure Figure 4 . In practical applications, there can be a larger number of transmission queues.

[0034] In a specific embodiment of the present invention, the logic module 20 sends the write address of the data packet descriptor to the doorbell register in the network interface module 40, including: The logic module 20 calculates the difference between the write address of the data packet descriptor and the value of the first register, determines the transmission queue number and pointer based on the difference, and sends the transmission queue number and pointer to the doorbell register in the network interface module 40; Among them, the transmission queue number represents the number of the transmission queue that the data packet descriptor needs to be written into, and the pointer represents the position where the data packet descriptor is written into the transmission queue.

[0035] This embodiment takes into account that the occupied space size of each transmission queue remains the same, and the addresses of each transmission queue are consecutive, forming a continuous transmission queue space. Therefore, through the difference between the write address of the data packet descriptor and the value of the first register, it can be conveniently determined which transmission queue the data packet descriptor should be written into specifically, and the specific position where it is written into the transmission queue.

[0036] Still taking the storage device in the above embodiment having an address space of 4GB and a physical address range from 0x100000000 to 0x1ffffffff as an example, the starting physical address of the transmission queue is 0x100000000, and the ending physical address is 0x1003fffff.

[0037] For example, in one scenario, 1024 transmission queues are supported, denoted as transmission queue 0 to transmission queue 1023 respectively. From transmission queue 0 to transmission queue 1023, the addresses are consecutive. Each transmission queue, for example, supports storing 0x100 packet descriptors, that is, it supports storing 256 packet descriptors. Each packet descriptor, for example, occupies 0x10 bytes. Therefore, in this example, each transmission queue occupies 0x1000 bytes. Since there are 1024 transmission queues in total, the entire transmission queue space needs to occupy 0x400000 bytes of space. Therefore, the starting physical address of the transmission queue is 0x100000000, and the ending physical address is 0x1003fffff.

[0038] For example, if the host software needs to write a packet descriptor to the placement location of the first packet descriptor in transmission queue 1, then the destination address of the data transmission request, that is, the write address of the packet descriptor, needs to be 0x100001000. In Figure 3 this example, the address of the AW channel of interface control module 10 at this time is 0x100001000. After the logic module 20 receives the write address 0x100001000 of the packet descriptor through the AW channel of interface control module 10, the logic module 20 will calculate the difference between the write address 0x100001000 of the packet descriptor and the value 0x100000000 of the first register. The obtained difference is 0x1000. Since this difference is less than the value 0x400000 in the second register, a doorbell needs to be triggered.

[0039] In this implementation manner, when triggering the doorbell, specifically, the transmission queue number and pointer are determined based on this difference, and then the transmission queue number and pointer are sent to the doorbell register in network interface module 40.

[0040] It should be noted that when determining the transmission queue number and pointer based on the difference, specifically, according to the address rule of the transmission queue (the size of each transmission queue and the space occupied by a single packet descriptor in each transmission queue), the transmission queue number and pointer are determined. In the above implementation manner, after obtaining the difference, the value from the 22nd bit to the 12th bit in the difference is used as the transmission queue number, and the value from the 11th bit to the 4th bit is used as the pointer. And in the above specific example, the difference is specifically 0x1000, the value from the 22nd bit to the 12th bit is 1, that is, the determined transmission queue number is 1, and the value from the 11th bit to the 4th bit is 0. Therefore, the determined pointer is 0. Therefore, in this example, the packet descriptor will be written to the 0th position (the first position) in transmission queue 1.

[0041] In addition, it can be understood that in this embodiment, the logic module 20 specifically writes the send queue number and pointer into the doorbell register in the network interface module 40. This is equivalent to using the send queue number and pointer to describe the position of the packet descriptor in the send queue, that is, to describe the write address of the packet descriptor. Considering that the doorbell is usually triggered according to the send queue number and pointer, this embodiment enables the solution of the present application to use the conventional design of the network interface module 40 without the need for additional adjustment of the network interface module 40, improving the implementation convenience of the solution of the present application.

[0042] In a specific embodiment of the present invention, the network card further includes a conversion module 50. The network interface module 40 is specifically configured to: After receiving the write address of the packet descriptor, generate a first descriptor and send it to the interface control module 10 through the conversion module 50, so that the interface control module 10 reads the packet descriptor from the send queue of the storage device based on the first descriptor and feeds it back to the network interface module 40 through the conversion module 50; After receiving the packet descriptor, generate a second descriptor and send it to the interface control module 10 through the conversion module 50, so that the interface control module 10 reads the packet pointed to by the packet descriptor from the send queue of the storage device based on the second descriptor and feeds the packet back to the network interface module 40; Output the received packet externally.

[0043] Wherein, the source address of the first descriptor is the first address in the network interface module 40, the destination address of the first descriptor is the write address of the packet descriptor, and the first descriptor carries the length of the packet descriptor; the packet descriptor includes the start address and the packet length of the packet stored in the storage device pointed to by the packet descriptor; the source address of the second descriptor is the second address in the network interface module 40, the destination address of the second descriptor is the start address of the packet, and the second descriptor carries the length of the packet.

[0044] In this embodiment, after the doorbell is triggered, that is, after the network interface module 40 receives the write address of the packet descriptor, through the interaction with the interface control module 10, the network interface module 40 first uses the interface control module 10 to obtain the content of the packet descriptor, and then uses the interface control module 10 to obtain the content of the packet, so as to output the packet externally.

[0045] Specifically, taking the write address of the data packet descriptor as 0x100001000 in the above example. The network interface module 40 is a NIC module, which generates a first descriptor. The destination address of the first descriptor is the write address 0x100001000 of the data packet descriptor, and the source address of the first descriptor is an address in the network interface module 40 called the first address, which is specifically set to 0x8000 for example, and the length is 0x10 bytes (i.e., the length of the data packet descriptor). After generating the first descriptor, the network interface module 40 sends the first descriptor to the conversion module 50, and then sends it to the interface control module 10 through the conversion module 50, so that the interface control module 10 reads a data packet descriptor with a length of 0x10 bytes from the 0th position in the transmission queue 1 of the storage device according to the address 0x100001000, and then feeds it back to the network interface module 40 through the conversion module 50.

[0046] In a specific embodiment of the present invention, the conversion module 50 may specifically be used for: Sending the destination address of the first descriptor and the length of the data packet descriptor to the interface control module 10, and storing the source address of the first descriptor; After receiving the data packet descriptor fed back by the interface control module 10, storing it at the source address of the first descriptor; Sending the destination address of the second descriptor and the data packet length to the interface control module 10, and storing the source address of the second descriptor; After receiving the data packet fed back by the interface control module 10, storing it at the source address of the second descriptor.

[0047] This embodiment takes into account that the interface control module 10 only needs to utilize the destination address of the first descriptor and the length of the data packet descriptor to read the data packet descriptor accordingly. Therefore, the conversion module 50 only needs to send the destination address of the first descriptor and the length of the data packet descriptor to the interface control module 10, and locally store the source address of the first descriptor. Subsequently, when the conversion module 50 receives the data packet descriptor fed back by the interface control module 10, it can store the data packet descriptor at the source address of the first descriptor according to the source address of the first descriptor.

[0048] For example Figure 5Schematic diagram of the conversion module 50 in a specific embodiment. A first-in, first-out storage unit (FIFO) is provided in the conversion module 50, which can be used to store the source address of the first descriptor and the source address of the second descriptor. In the above example, the conversion module 50 specifically sends the destination address 0x100001000 of the first descriptor and the length 0x10 bytes of the packet descriptor to the interface control module 10, so that the interface control module 10 reads the packet descriptor of this address from the transmission queue of the storage device based on the destination address 0x100001000 of the first descriptor. For the source address 0x8000 of the first descriptor, the conversion module 50 saves it to the FIFO. When the conversion module 50 receives the packet descriptor fed back by the interface control module 10, the conversion module 50 can read the source address 0x8000 of the first descriptor from the FIFO, and then write the packet descriptor to the position 0x8000 of the network interface module 40, so that the packet descriptor is received by the network interface module 40.

[0049] After the network interface module 40 receives the packet descriptor, it generates a second descriptor and sends it to the interface control module 10 through the conversion module 50, so that the interface control module 10 reads the corresponding packet based on the second descriptor and feeds the packet back to the network interface module 40.

[0050] Taking the content of the packet descriptor as (0x101000000) and (1024) in the above example. The network interface module 40 generates a second descriptor according to the content of the packet descriptor. The destination address of the second descriptor is the starting address 0x101000000 of the packet, and the source address of the second descriptor is an address in the network interface module 40 called the second address, for example, specifically set to 0x4000, and the length is 1024 bytes (i.e., the length of the packet). After generating the second descriptor, the network interface module 40 sends the second descriptor to the conversion module 50, and then sends it to the interface control module 10 through the conversion module 50, so that the interface control module 10 reads the packet with a length of 1024 bytes from the storage device according to the address 0x101000000, and then feeds it back to the network interface module 40 through the conversion module 50.

[0051] In a specific embodiment, considering that the interface control module 10 only needs to utilize the destination address and the length of the data packet of the second descriptor to read the data packet accordingly, the conversion module 50 only needs to send the destination address and the length of the data packet of the second descriptor to the interface control module 10, and locally store the source address of the second descriptor. Subsequently, when the conversion module 50 receives the data packet fed back by the interface control module 10, it can store the data packet at the source address of the second descriptor according to the source address of the second descriptor.

[0052] In Figure 5 the example of, a first-in-first-out storage unit (FIFO) is provided in the conversion module 50, and the first-in-first-out storage unit can be used to store the source address of the first descriptor and the source address of the second descriptor. In the above example, the conversion module 50 specifically sends the destination address 0x101000000 and the length 1024 of the second descriptor to the interface control module 10, so that the interface control module 10 reads 1024 bytes of data from the storage device based on the destination address 0x101000000 of the second descriptor as the read data packet. The source address 0x4000 of the second descriptor is saved to the FIFO. When the conversion module 50 obtains the data packet fed back by the interface control module 10, the conversion module 50 can read the source address 0x4000 of the second descriptor from the FIFO, and then write the data packet to the position 0x4000 of the network interface module 40, so that the data packet is received by the network interface module 40.

[0053] In a specific embodiment of the present invention, a third register and a fourth register are provided in the conversion module 50. The value in the third register is the starting physical address of the storage device, and the value in the fourth register is the spatial size of the storage device. The conversion module 50 is further configured to: Based on the values of the third register and the fourth register, determine whether the destination address of the first descriptor belongs to the address range of the storage device; If so, output a first signal indicating that the storage device needs to be read to the interface control module 10; If not, output a second signal indicating that the host memory needs to be read to the interface control module 10; Based on the values of the third register and the fourth register, determine whether the destination address of the second descriptor belongs to the address range of the storage device; If so, output the first signal to the interface control module 10; If not, output the second signal to the interface control module 10.

[0054] In this embodiment, the conversion module 50 can also determine whether the destination address of the first descriptor belongs to the address range of the storage device, and can also determine whether the destination address of the second descriptor belongs to the address range of the storage device. For example Figure 5 In the example of Figure 5 , a comparator is specifically provided in the conversion module 50, and the determination can be implemented through the comparator.

[0055] For example, in the above example, the physical address range of the storage device is from 0x100000000 to 0x1ffffffff. Then, the value in the third register is the starting physical address 0x100000000 of the storage device, and the value in the fourth register is the space size 0x100000000 of the storage device. In the above example, the destination address of the first descriptor is the write address 0x100001000 of the packet descriptor. It can be seen that the destination address of the first descriptor belongs to the address range of the storage device. In this embodiment, at this time, a first signal indicating that the storage device needs to be read is output to the interface control module 10. On the contrary, if it does not belong to the address range of the storage device, in this embodiment, at this time, a second signal indicating that the host memory needs to be read is output to the interface control module 10. The above uses the first descriptor as an example for illustration, and the principle of the determination process of the second descriptor is the same and will not be repeated.

[0056] It can be seen that in this embodiment, by outputting the first signal and the second signal, the interface control module 10 can effectively determine whether it is necessary to read the storage device or the host memory currently.

[0057] Furthermore, in a specific embodiment of the present invention, outputting a first signal indicating that the storage device needs to be read to the interface control module 10 may include: Outputting a first signal indicating that the storage device needs to be read to the interface control module 10 through the read address receiving channel of the Advanced eXtensible Interface (AXI) bus provided by the interface control module 10.

[0058] This embodiment takes into account that the bus provided by the interface control module 10 is usually an AXI bus. For example Figure 3 In a specific embodiment of Figure 3 , the interface control module 10 is connected to the conversion module 50 through the AXI bus. The AR channel of this AXI bus can be connected to the read descriptor interface (DMA_rd_desc) of the network interface module 40 through the conversion module 50 to receive the first descriptor and the second descriptor. The R channel can be connected to the read data interface (DMA_rd_AVMM) of the network interface module 40 through the conversion module 50 to feedback the packet descriptor and the packet to the network interface module 40.

[0059] In this embodiment, specifically, a first signal indicating a need to read a storage device is output to the interface control module 10 through the read address receiving channel of the AXI bus provided by the interface control module 10, that is, the AR channel. For example, in Figure 5 In the specific embodiment, specifically, the transmission of the first signal or the second signal is implemented through the ARuser signal line of the AR channel, that is, the read address user-defined signal. When the 5th bit of the ARuser signal is set to 1, it is the first signal, indicating that the storage device needs to be read at this time. When the 5th bit of the ARuser signal is set to 0, it is the second signal, indicating that the host memory needs to be read at this time. Figure 5 In the specific embodiment of Figure 5 , the address signal of the AR channel can be used to transmit the address.

[0060] In a specific embodiment of the present invention, after receiving the packet descriptor fed back by the interface control module 10, storing it to the source address of the first descriptor includes: Receiving the packet descriptor fed back by the interface control module 10, and after converting it into the bus format supported by the network interface module 40, storing it to the source address of the first descriptor; After receiving the packet fed back by the interface control module 10, storing it to the source address of the second descriptor includes: After receiving the packet fed back by the interface control module 10 and after converting it into the bus format supported by the network interface module 40, feeding it back to the network interface module 40.

[0061] This embodiment takes into account that the interface control module 10 usually uses the AXI bus, which is different from that used by the network interface module 40. For example, the network interface module 40 usually uses the AVMM bus. And in order to improve the implementation convenience of the solution of this application and reduce the adjustment of the interface control module 10 and the network interface module 40, this embodiment considers that the bus format conversion can be implemented through the conversion module 50. Specifically, after receiving the packet descriptor fed back by the interface control module 10, the conversion module 50 can perform bus format conversion, that is, after converting it into the bus format supported by the network interface module 40, the packet descriptor will be stored to the source address of the first descriptor. Similarly, for the packet fed back by the interface control module 10, the conversion module 50 can perform bus format conversion, that is, after converting it into the bus format supported by the network interface module 40, the packet will be stored to the source address of the second descriptor.

[0062] In Figure 5 In the example of Figure 5 , a conversion unit is provided in the conversion module 50 and is connected to the R channel of the AXI bus provided by the interface control module 10. Figure 5The R channel denoted as AXI in the middle, and after converting the data into the bus format, the data in the AVMM bus format is output to the network interface module 40 to meet the bus format requirements of the network interface module 40.

[0063] In a specific embodiment of the present invention, the network interface module 40 has multiple Ethernet optical ports for outputting data packets, thereby effectively improving the data output efficiency. The network card can be mounted with multiple storage devices to provide sufficient storage space. Refer to Figure 6 , which is a schematic structural diagram of the connection between the network card and the host in a specific embodiment. Figure 6 In it, the network card is specifically connected to the central processing unit in the host through the CXL protocol, and 4 DIMM memory slots are set, so that 4 storage devices can be inserted. For example, in one case, the maximum storage device that can be mounted is 256GB DDR4. And Figure 6 the network card is implemented using FPGA, showing two 100G Ethernet optical ports.

[0064] In a specific embodiment of the present invention, the network interface module 40 can also be used for: After the data packet is successfully output, feedback to the host through the interface control module 10 the confirmation information indicating successful output; When the data packet output fails, feedback to the host through the interface control module 10 the prompt information indicating output failure so that the host initiates the retransmission of the data packet.

[0065] In this embodiment, the network interface module 40 is provided with a fault-tolerant retransmission mechanism. After the data packet is successfully output, the confirmation information indicating successful output can be fed back to the host through the interface control module 10. Correspondingly, when the data packet output fails, the prompt information indicating output failure is fed back to the host through the interface control module 10, so that the host can initiate the retransmission of the data packet.

[0066] The solution of this application considers that the Compute Express Link protocol is an innovative high-speed interconnection technology that can provide a more efficient and flexible connection method for processors, accelerators, and storage devices, and can achieve more excellent performance and lower latency, thereby meeting the requirements of modern computing applications for high bandwidth and low latency. However, there is currently no network card that supports the Compute Express Link protocol, and the solution of this application is to implement a network card based on the Compute Express Link protocol. Specifically, the hardware of the network card can be implemented by an FPGA acceleration card, with storage devices externally mounted to the FPGA, and can be controlled by the storage control module 30 on the FPGA.

[0067] The interface control module 10 inside the network card is connected to the host using the Compute Link protocol. It can receive the data transmission request sent by the host and send it to the logic module 20. It should be noted that since the interface control module 10 is an interface control module using the Compute Link protocol, the storage device connected to the network card and the host memory are uniformly addressed. This means that during the operation of the network card in the solution of this application, there is no need to perform address conversion. When obtaining the packet descriptor through the data transmission request sent by the host, the packet descriptor can be directly written into the transmission queue of the storage device according to the write address of the data transmission request. The operation is simple and convenient. When subsequently obtaining the packet using the packet descriptor, there is also no need to perform address conversion, and the operation is simple and convenient, which is beneficial to reducing the transmission delay.

[0068] Furthermore, in the solution of this application, the process of writing the packet descriptor and the process of triggering the network interface module 40 (i.e., triggering the network card doorbell) through the packet descriptor are carried out simultaneously, rather than being divided into 2 steps as in the traditional solution. Specifically, for the data transmission request sent by the host, the interface control module 10 will send it to the logic module 20, enabling the logic module 20 to trigger the network card doorbell, that is, the logic module 20 will send the write address of the packet descriptor to the network interface module 40. At the same time, the logic module 20 will also send the data transmission request to the storage control module 30, enabling the storage control module 30 to write the packet descriptor carried in the data transmission request into the transmission queue of the storage device connected to the network card. Since the two processes are carried out simultaneously, the delay of sending packets is significantly reduced. Finally, after receiving the write address of the packet descriptor, the network interface module 40 can obtain the packet stored in the storage device pointed to by the packet descriptor through the interface control module 10 and output the packet externally. In addition, since both the packet descriptor and the packet are stored in the storage device mounted on the network card, the time-consuming for the network card in this application to read the packet descriptor and the packet is very short, which is also beneficial to reducing the delay of the network card in sending data.

[0069] In summary, it can be seen that the solution of this application can effectively reduce the delay of the network card in sending data.

[0070] Corresponding to the above network card embodiment, the embodiment of the present invention also provides a data transmission method based on the Compute Link protocol, which can be mutually corresponding and referred to with the above text. This data transmission method based on the Compute Link protocol can be applied to the interface control module in the network card based on the Compute Link protocol in any of the above embodiments, and can be referred to Figure 7 , including the following steps: Step S701: Receive a data transmission request sent by a host and send it to a logic module, so that a storage control module receives the data transmission request through the logic module, writes a packet descriptor carried in the data transmission request into a transmission queue of a storage device connected to a network card, and enables the logic module to send a write address of the packet descriptor to a network interface module.

[0071] Step S702: After the network interface module receives the write address of the packet descriptor, obtain, through communication with the network interface module, a packet stored in the storage device pointed to by the packet descriptor, and send the packet to the network interface module, so that the network interface module outputs the packet externally.

[0072] Among them, the interface control module is an interface control module using a Compute Link protocol, so that a storage device connected to a network card and a host memory are uniformly addressed and used.

[0073] Corresponding to the above embodiments, embodiments of the present invention further provide an electronic device, a computer-readable storage medium, and a computer program product, which can be correspondingly referred to each other with the above text.

[0074] See Figure 8 As shown, the electronic device may include: A memory 801 for storing a computer program; A processor 802 for executing the computer program to implement the steps of the data transmission method based on the Compute Link protocol in any of the above embodiments.

[0075] The computer program product includes a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the data transmission method based on the Compute Link protocol in any of the above embodiments are implemented.

[0076] Refer to Figure 9 , a computer program 91 is stored on a computer-readable storage medium 90, and when the computer program 91 is executed by a processor, the steps of the data transmission method based on the Compute Link protocol in any of the above embodiments are implemented. The computer-readable storage medium 90 mentioned here includes RAM (Random Access Memory), memory, ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), registers, hard disks, removable disks, or any other form of storage medium known in the technical field.

[0077] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0078] The above has introduced in detail a network card, a data transmission method, a device, and a product based on a computing link protocol provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A network card based on the computational linking protocol, characterized in that, Including: An interface control module, configured to receive a data sending request sent by a host and send it to a logic module; A storage control module, configured to receive the data sending request through the logic module and write a packet descriptor carried in the data sending request into a sending queue of a storage device connected to a network card; The logic module, configured to send a writing address of the packet descriptor to a network interface module; The network interface module, configured to, after receiving the writing address of the packet descriptor, obtain, through the interface control module, a packet stored in the storage device pointed to by the packet descriptor and output the packet externally; Wherein, the interface control module is an interface control module using a Compute Link protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

2. The network card based on the computational linking protocol according to claim 1, wherein A first register and a second register are provided in the logic module, a value in the first register is a starting physical address of a sending queue of the storage device, and a value in the second register is a space size of the sending queue of the storage device; The logic module is specifically configured to: Based on values of the first register and the second register, determine whether a writing address of the packet descriptor belongs to an address range of the sending queue of the storage device; If so, send the writing address of the packet descriptor to a doorbell register in the network interface module.

3. The network card based on the computational linking protocol according to claim 2, wherein, Multiple continuously addressed sending queues are provided in the storage device, and storage space sizes occupied by each sending queue are the same.

4. The network card based on the computational linking protocol according to claim 3, wherein Sending the writing address of the packet descriptor to a doorbell register in the network interface module includes: Calculating a difference between the writing address of the packet descriptor and a value of the first register, and determining a sending queue number and a pointer based on the difference, and sending the sending queue number and the pointer to the doorbell register in the network interface module; Wherein, the sending queue number represents a number of the sending queue to which the packet descriptor needs to be written, and the pointer represents a position where the packet descriptor is written into the sending queue.

5. The network card based on the computational linking protocol according to claim 1, characterized in that The storage control module is specifically configured to: Receive, through the logic module, the packet descriptor carried in the data sending request from a write data channel and receive the writing address of the packet descriptor from a write address channel; Based on the writing address of the packet descriptor, write the packet descriptor into the sending queue of the storage device connected to the network card.

6. The network card based on the computational linking protocol according to claim 1, characterized in that The network interface module is further configured to: After the packet is successfully output, feedback, through the interface control module, a confirmation message indicating successful output to the host; When the packet output fails, feedback, through the interface control module, a prompt message indicating output failure to the host so that the host initiates a retransmission of the packet.

7. The network card based on the computational linking protocol according to any one of claims 1 to 6, characterized in that, A conversion module is further included in the network card; The network interface module is specifically configured to: After receiving the write address of the data packet descriptor, a first descriptor is generated and sent to the interface control module through the conversion module, so that the interface control module reads the data packet descriptor from the transmission queue of the storage device based on the first descriptor and feeds it back to the network interface module through the conversion module; After receiving the data packet descriptor, a second descriptor is generated and sent to the interface control module through the conversion module, so that the interface control module reads the data packet pointed to by the data packet descriptor from the transmission queue of the storage device based on the second descriptor and feeds the data packet back to the network interface module; Output the received data packet externally; Wherein, the source address of the first descriptor is the first address in the network interface module, the destination address of the first descriptor is the write address of the data packet descriptor, and the length of the data packet descriptor is carried in the first descriptor; The data packet descriptor includes the start address and the data packet length of the data packet stored in the storage device pointed to by the data packet descriptor; the source address of the second descriptor is the second address in the network interface module, the destination address of the second descriptor is the start address of the data packet, and the length of the data packet is carried in the second descriptor.

8. The network card based on the computational linking protocol according to claim 7, wherein The conversion module is specifically used for: Send the destination address of the first descriptor and the length of the data packet descriptor to the interface control module, and store the source address of the first descriptor; After receiving the data packet descriptor fed back by the interface control module, store it at the source address of the first descriptor; Send the destination address of the second descriptor and the data packet length to the interface control module, and store the source address of the second descriptor; After receiving the data packet fed back by the interface control module, store it at the source address of the second descriptor.

9. The network card based on the computational linking protocol according to claim 8, wherein A first-in-first-out storage unit is provided in the conversion module, and the first-in-first-out storage unit is used to store the source address of the first descriptor and the source address of the second descriptor.

10. The network card based on the computational linking protocol according to claim 8, characterized in that, A third register and a fourth register are provided in the conversion module, the value in the third register is the start physical address of the storage device, the value in the fourth register is the space size of the storage device, and the conversion module is further used for: Based on the values of the third register and the fourth register, judge whether the destination address of the first descriptor belongs to the address range of the storage device; If so, output a first signal indicating that the storage device needs to be read to the interface control module; If not, output a second signal indicating that the host memory needs to be read to the interface control module; Based on the values of the third register and the fourth register, judge whether the destination address of the second descriptor belongs to the address range of the storage device; If so, output the first signal to the interface control module; If not, output the second signal to the interface control module.

11. The network card based on the computational linking protocol according to claim 10, wherein Output a first signal indicating a need to read the storage device to the interface control module, including: Output a first signal indicating a need to read the storage device to the interface control module through the read address receiving channel of the Advanced Extensible Interface Bus provided by the interface control module.

12. The network card based on the computational linking protocol according to claim 8, characterized in that, After receiving the packet descriptor fed back by the interface control module, store it at the source address of the first descriptor, including: Receive the packet descriptor fed back by the interface control module, and after converting it into the bus format supported by the network interface module, store it at the source address of the first descriptor; After receiving the packet fed back by the interface control module, store it at the source address of the second descriptor, including: After receiving the packet fed back by the interface control module and after converting it into the bus format supported by the network interface module, feedback it to the network interface module.

13. A data transmission method based on a computational linking protocol, characterized in that, Applied to the interface control module in the network card based on the Compute Link Protocol as described in any one of claims 1 to 12, including: Receive a data transmission request sent by the host and send it to the logic module, so that the storage control module receives the data transmission request through the logic module, writes the packet descriptor carried in the data transmission request into the transmission queue of the storage device connected to the network card, and makes the logic module send the write address of the packet descriptor to the network interface module; After the network interface module receives the write address of the packet descriptor, through communication with the network interface module, obtain the packet stored in the storage device pointed to by the packet descriptor, and send the packet to the network interface module, so that the network interface module outputs the packet externally; Wherein, the interface control module is an interface control module using the Compute Link Protocol, so that the storage device connected to the network card and the host memory are uniformly addressed and used.

14. An electronic device, characterized in that, Including: A memory for storing a computer program; A processor for implementing the steps of the data transmission method based on the Compute Link Protocol as described in claim 13 when executing the computer program.

15. A computer program product comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the data transmission method based on the Compute Link Protocol as described in claim 13.

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