Body connected transistor devices and methods

Abstract

The invention relates to a body-connected transistor device and a method. Apparatuses and methods are disclosed, including transistors, semiconductor devices, and systems. Example semiconductor devices and methods include a dielectric isolation structure positioned at least partially below a semiconductor body and between the semiconductor body and a substrate. Example semiconductor devices and methods also include coupling the semiconductor body to an electrical contact of the substrate. In one example, the electrical contacts reduce or eliminate floating body effects in the semiconductor body.

Description

Technical Field

[0001] The present disclosure relates to a body-connected transistor device and a method. Background Art

[0002] A memory device is an electronic storage semiconductor circuit that provides data for a host system such as a computer or other electronic device. The memory device can be volatile or non-volatile. Volatile memory requires power to maintain data and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can hold stored data when not powered and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistive change memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM).

[0003] The host system typically includes a host processor, a first amount of main memory for supporting the host processor (such as typically volatile memory, such as DRAM), and one or more storage systems (such as typically non-volatile memory, such as flash memory) that provide additional storage devices to hold data in addition to or separate from the main memory.

[0004] A storage system such as a solid state drive (SSD) can include a memory controller and one or more memory devices, including several dies or logical units (LUNs). In a particular instance, each die can include several memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller can include interface circuitry configured to communicate with a host device (such as a host processor or interface circuitry) through a communication interface (such as a bidirectional parallel or serial communication interface).

[0005] This description generally relates to transistor structures and fabrication in complementary metal oxide semiconductor (CMOS) devices. Summary of the Invention

[0006] On the one hand, the present disclosure provides a semiconductor device, comprising: a first source / drain region extending upward from a semiconductor body; a second source / drain region extending upward from the semiconductor body; wherein the semiconductor body includes a channel fin coupled between the first source / drain region and the second source / drain region; a gate separated from the channel fin by a gate dielectric; a dielectric isolation structure at least partially positioned under the semiconductor body and between the semiconductor body and a substrate; and an electrical contact coupling the semiconductor body to the substrate.

[0007] On the other hand, the present disclosure further provides a semiconductor device, comprising: a first source / drain region extending upward from a semiconductor body; a second source / drain region extending upward from the semiconductor body; wherein the semiconductor body includes a channel fin coupled between the first source / drain region and the second source / drain region; a gate separated from the channel fin by a gate dielectric; a dielectric isolation structure at least partially positioned under the semiconductor body and between the semiconductor body and a substrate; an electrical contact coupling the semiconductor body to the substrate; and a dielectric isolation trench adjacent to the semiconductor body, wherein the dielectric isolation trench extends into the substrate.

[0008] On the other hand, the present disclosure further provides a method of forming a semiconductor device, comprising: forming a silicon germanium layer over a substrate; forming a silicon layer over the silicon germanium layer; forming a first source / drain region extending upward and a second source / drain region extending upward from the silicon layer, the first source / drain region being coupled to the second source / drain region through a remaining semiconductor body coupled to the silicon germanium layer; forming a contact opening from a surface of the silicon layer to the silicon germanium layer; removing a portion of the silicon germanium layer from under at least a portion of the semiconductor body to leave a remaining silicon germanium contact between the semiconductor body and the substrate; and forming a gate dielectric over a fin portion of the semiconductor body and forming a gate over the gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same reference numerals with different letter suffixes may represent different examples of similar components. The drawings generally illustrate, by way of example and not by way of limitation, the various embodiments discussed in this document.

[0010] Figure 1 Illustrate a memory device according to some example embodiments.

[0011] Figure 2A Illustrate a cross-section of a semiconductor device according to some example embodiments.

[0012] Figure 2B Another cross-section of a semiconductor device according to some example embodiments Figure 2A from

[0013] Figure 3A A diagram illustrating the manufacturing stages of a semiconductor device according to some example embodiments

[0014] Figure 3B A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0015] Figure 3C A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0016] Figure 3D A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0017] Figure 3E A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0018] Figure 3F A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0019] Figure 3G A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0020] Figure 3H A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0021] Figure 3I A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0022] Figure 3J A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0023] Figure 3K A diagram illustrating another manufacturing stage of a semiconductor device according to some example embodiments

[0024] Figure 4 A semiconductor device according to some example embodiments

[0025] Figure 5 An example method flowchart according to other example embodiments

[0026] Figure 6 An example block diagram of an information processing system according to some example embodiments DETAILED DESCRIPTION

[0027] The following description and drawings fully disclose specific embodiments such that those skilled in the art can practice the embodiments. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in or substituted for portions and features of other embodiments. The embodiments set forth in the claims cover all available equivalents of the claims.

[0028] Figure 1 FIG. shows a block diagram of an apparatus in the form of a memory device 100 in accordance with an embodiment of the present invention. The memory device 100 may include a memory array 102 having memory cells 103 that can be arranged in rows and columns, and lines (such as access lines) 104 and lines (such as data lines) 105. The memory device 100 may use the lines 104 to access the memory cells 103 and use the lines 105 to exchange information with the memory cells 103.

[0029] The memory cells 103 and other circuits 114, 116, etc. may include transistors and utilize Figures 2A to 4 methods described in more detail in. In one example, the memory array 102 includes a RAM storage device, and the peripheral circuits such as circuits 114, 116, 108, 109, etc. may include Figures 2A to 4 transistors described in more detail in. In one example, the memory array 102 includes a NAND storage device.

[0030] The row access 108 and column access 109 circuitry may respond to the address register 112 to access the memory cells 103 based on row address and column address signals on the lines 110, 111, or both. The data input / output circuit 114 may be configured to exchange information between the memory cells 103 and the line 110. The lines 110 and 111 may include nodes within the memory device 100 or pins (or solder balls) on a package in which the memory device 100 resides.

[0031] The control circuit 116 may control the operation of the memory device 100 based on signals present on the lines 110 and 111. Devices external to the memory device 100 (such as a processor or a memory controller) may use different combinations of signals on the lines 110, 111, or both to send different commands (such as read, write, or erase commands) to the memory device 100.

[0032] The memory device 100 may respond to commands to perform memory operations on the memory cells 103, such as performing a read operation to read information from the memory cells 103 or performing a write (such as program) operation to store (such as program) information into the memory cells 103. The memory device 100 may also perform an erase operation to clear information from some or all of the memory cells 103.

[0033] The memory device 100 can receive power supply voltages, including the power supply voltages Vcc and Vss. The power supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). The power supply voltage Vcc can include an external voltage supplied from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuit system to the memory device 100.

[0034] Each memory cell 103 can be programmed to store information representing a fraction of a bit, a value of a single bit, or a value of multiple bits (e.g., 2, 3, 4, or another number of bits). For example, each of the memory cells 103 can be programmed to store information representing the binary value “0” or “1” of a single bit. A single bit per cell is sometimes referred to as a single-level cell. In another example, each of the memory cells 103 can be programmed to store information representing a value of multiple bits, such as one of the 4 possible values “00”, “01”, “10”, and “11” of 2 bits, one of the 8 possible values “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” of 3 bits, or one of the other values of another number of multiple bits. A cell having the ability to store multiple bits is sometimes referred to as a multi-level cell (or multi-state cell).

[0035] The memory device 100 can include a non-volatile memory device and the memory cells 103 can include non-volatile memory cells such that when power (e.g., Vcc, Vss, or both) is disconnected from the memory device 100, the memory cells 103 can retain the information stored thereon. For example, the memory device 100 can be a flash memory device (e.g., a NAND flash or NOR flash memory device) or another memory device (e.g., a variable resistance memory device (e.g., a phase change or resistive RAM device)).

[0036] The memory device 100 can include a memory device in which the memory cells 103 can be physically located in multiple levels on the same device such that some of the memory cells 103 can be stacked in multiple levels above some other memory cells 103 above the substrate (e.g., a semiconductor substrate) of the memory device 100.

[0037] One of ordinary skill in the art will recognize that the memory device 100 can include other elements, some of which are not shown in Figure 1 to avoid obscuring the example embodiments described herein.

[0038] Figure 2A A semiconductor device 200 is shown. The transistor 210 is shown as part of the semiconductor device 200. The transistor 210 is located above the semiconductor substrate 202. In one example, the semiconductor substrate 202 includes silicon, but other semiconductor materials are also within the scope of the present invention.

[0039] The transistor 210 includes a first source / drain region 212 extending upward from a semiconductor body 211. A second source / drain region 214 extending upward from the semiconductor body 211 is also shown. A channel fin 216 is shown coupled between the first source / drain region 212 and the second source / drain region 214. The gate 218 is shown separated from the channel fin 216 by a gate dielectric 220. In operation, a charge selectively applied to the gate 218 actuates conduction in the channel fin 216 and turns on the transistor 210 to open a signal path 222 between the first source / drain region 212 and the second source / drain region 214 through the channel fin 216.

[0040] A dielectric isolation structure 224 is further shown, which is at least partially located below the semiconductor body 211 and between the semiconductor body 211 and the substrate 202. A region 225 is shown to illustrate the portion of the isolation structure 224 located below the semiconductor body 211. An electrical contact 226 is shown coupling the semiconductor body 211 to the substrate 202. In operation, it is desirable to provide a degree of electrical coupling between the semiconductor body 211 and the substrate 202. The connection reduces or eliminates the floating body effect in the semiconductor body 211 and the channel fin 216. If the semiconductor body 211 and the channel fin 216 are completely electrically isolated from the substrate 202, charges will be trapped in the semiconductor body 211 and the channel fin 216, thereby reducing the effectiveness of the signal path 222. Including the electrical contact 226 allows any floating body charges to dissipate and improves device performance.

[0041] Figure 2A and 2B The exemplary semiconductor device 200 in and includes a third source / drain region 230 extending upward from the semiconductor body 211 and a second channel fin 232 coupled between the third source / drain region 230 and the first source / drain region 212. In this configuration, two transistors are formed that share a common first source / drain region 212. This configuration provides a higher device area density by sharing components.

[0042] Figure 2B A cross-section of a semiconductor device from Figure 2A is shown. Figure 2BDescribe how the gate 218 is configured to be adjacent to the channel fins 216 on three sides, with the isolation structure 224 below. This configuration provides efficient control of the channel fins 216 without electrical interference from adjacent structures. In the example shown, an additional conductor layer 219 is included above the gate 218. In one example, the gate 218 includes a metal or conductive alloy. Example materials for the gate 218 include, but are not limited to, molybdenum, tungsten, ruthenium titanium nitride, and / or alloys containing these metals. In one example, the additional conductor layer 219 includes a material that modifies the work function of the gate 218 material. One example material for the conductor layer 219 includes an N+ polysilicon layer, but the present invention is not limited thereto.

[0043] Figures 3A to 3K Show selected manufacturing stages in an example method of forming a semiconductor device 300. Figure 3A Show a substrate 302 such as a silicon substrate. Other semiconductors are also within the scope of the present invention. Include a conductive layer 304, with a second semiconductor layer located above the conductive layer 304. In one example, the conductive layer 304 includes silicon germanium. In one example, the stoichiometric ratio of silicon germanium is Si x Ge (1-x) . As discussed in more detail below, varying the stoichiometric ratio Si x Ge (1-x) provides processing advantages in forming the Figures 2A to 2B electrical contacts 226 shown in.

[0044] In one example, the substrate 302 includes single-crystalline silicon, and the conductive layer 304 and the second semiconductor layer 306 are epitaxially formed on the substrate 302. Epitaxial formation provides a crystal structure with improved semiconducting properties for operating transistors and other semiconductor devices formed by the conductive layer 304 and the second semiconductor layer 306.

[0045] Figure 3B Show a mask layer 310 patterned above the second semiconductor layer 306. A plurality of trenches 312 are patterned and formed in the second semiconductor layer 306. In one example, the number of trenches 312 defines the number of isolation structures that electrically isolate the semiconductor devices. Figure 3B Show the depth 314 of the trenches 312 in. Devices formed using the methods described in the present disclosure enable the depth 314 to be shallower than other configurations. One configuration feature that contributes to achieving the shallow depth 314 includes the region 225 of the isolation structure 224 located below the semiconductor body 211. Increased isolation of the semiconductor body 211 reduces the need for deeper trenches 312.

[0046] Figure 3C Show the dielectric 316 that has been filled into the trenches 312. In Figure 3DIn [description], a mask 318 is formed with an opening 320 in the mask 318. Using the opening 320, a deep etch is performed in the dielectric 316 to at least the level of exposing the conductive layer 304. Figure 3E A deep etch opening 322 is shown in [description].

[0047] When the conductive layer 304 is exposed through the deep etch opening 322, a portion of the conductive layer 304 is dug out through the deep etch opening 322. In one example, a wet etch chemistry selective to the material in the conductive layer 304 is used. As Figure 3F illustrated in [description], only a portion of the conductive layer 304 is dug out to leave an electrical contact 326 coupled between the semiconductor layer 306 and the substrate 302. The portions of the conductive layer 304 are removed from regions 324 on both sides of the remaining electrical contact 326.

[0048] As discussed above, an example conductive layer 304 comprises silicon germanium. In one example, the stoichiometric ratio of silicon germanium is Si x Ge (1-x) . By varying "x" in the stoichiometric ratio, the conductive layer 304 is tuned to a high selectivity in the dig-out etch chemistry. In one example, the ratio of Si x Ge (1-x) has "x" between 0.1 and 0.8. In one example, the ratio of Si x Ge (1-x) has "x" between 0.2 and 0.6. In one example, the ratio of Si x Ge (1-x) has "x" between 0.3 and 0.5. By using selective etching, only the conductive layer 304 is affected, and the remaining silicon and dielectric structures are retained after digging out portions of the conductive layer 304.

[0049] In Figure 3G , the deep etch openings 322 and regions 324 on both sides of the remaining electrical contact 326 are filled with a dielectric material 328. In one example, the dielectric material 328 is the same as the dielectric 316, but the present invention is not limited thereto. Different dielectric materials may also be used. An example of the dielectric material comprises silicon oxide, but the present invention is not limited thereto. Other dielectric materials may also be used.

[0050] Figure 3H The formation of a second mask 330 and the subsequent formation of word line trenches 332 are shown. Figure 3I A top view of the semiconductor device 300 with word lines 334 formed in the word line trenches 332 is shown. The word lines 334 are formed above the channel fins 335, similar to the channel fins 216 from Figure 2A and 2B . Figure 3I The electrical contact 326 is also shown in [description].

[0051] Figure 3J Disclosed is a semiconductor device 300 having word lines similar to word line 334 formed by a first conductor layer 336 and a second conductor layer 337. The first conductor layer 336 is shown as being formed above the channel fins 340. The first conductor layer 336 is separated from the channel fins 340 by a gate dielectric 338. This configuration forms the main structure of a transistor gate that is part of the word line 334. In the illustrated example, the word line 334 includes two conductors 336, 337, but the present invention is not limited thereto. A single conductor for forming the word line 334 or more than two conductors for forming the word line 334 are also within the scope of the present invention. As discussed in the above example, an additional conductor layer 337 may be included to modify the work function of the transistor gate.

[0052] Figure 3K An additional processing stage of the exemplary semiconductor device 300 is shown. Figure 3K An interconnect layer 342 is shown. Examples of structures in the interconnect layer 342 include, but are not limited to, digital line connections, cell contact connections, etc. A combination of dielectric layers and conductor layers is used to form Figure 3K the interconnect layer 342.

[0053] Figure 4 Disclosed is a semiconductor device 400 in which several components are removed to illustrate the general geometry of the semiconductor device 400. In Figure 4 the example, the semiconductor device 400 is similar to Figures 3A to 3K the semiconductor device 300 shown in

[0054] In Figure 4 it, a first source / drain region 412 extending upward from a semiconductor body 411 is shown. Also shown is a second source / drain region 414A extending upward from the semiconductor body 411. Channel fins 416 are shown as a portion of the semiconductor body 411 coupled between the first source / drain region 412 and the second source / drain region 414A. An electrical contact 426 similar to the electrical contact 326 is shown as coupling the semiconductor body 411 to a substrate 402. Figure 4 A third source / drain region 414B extending upward from the semiconductor body 411 is further shown. In this configuration, two transistors sharing a common first source / drain region 412 are formed. This configuration provides a higher device area density by sharing components.

[0055] Figure 5A flowchart showing an example manufacturing method is presented. In operation 502, a silicon germanium layer is formed over a substrate. In operation 504, a silicon layer is formed over the silicon germanium layer. In operation 506, a first source / drain region extending upward and a second source / drain region extending upward are formed from the silicon layer, and the first source / drain region is coupled to the second source / drain region through the remaining semiconductor body coupled to the silicon germanium layer. In operation 508, an opening is formed from the surface of the silicon layer to the silicon germanium layer. In operation 510, a portion of the silicon germanium layer is removed from under at least a portion of the semiconductor body to leave a remaining silicon germanium contact between the semiconductor body and the substrate. In operation 512, a gate dielectric is formed over the fin portion of the semiconductor body and a gate is formed over the gate oxide.

[0056] Figure 6 A block diagram illustrating an example machine (e.g., a host system) 600 is shown, which may include one or more of the transistors, memory devices, and / or memory systems described above. As discussed above, the machine 600 may benefit from enhanced memory performance by using one or more of the described transistor structures and / or memory systems, thereby facilitating improved performance of the machine 600 (for many such machines or systems, efficient reading and writing of memory can facilitate improved performance of the processor or other components of the machine, as further described below).

[0057] In an alternative embodiment, the machine 600 may operate as a stand-alone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 600 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 600 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 600 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network device, an IoT device, an automotive system, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by the machine. Further, although only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0058] As described herein, an instance may include logic, components, devices, packages, or mechanisms or may operate via logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). Circuit system membership may vary flexibly over time and with underlying hardware variability. A circuit system includes members that may perform particular tasks individually or in combination when operating. In an instance, the hardware of a circuit system may be designed in an invariant manner to perform a particular operation (e.g., hardwired). In an instance, the hardware of a circuit system may include physically configurable components (e.g., execution units, transistors, simple circuits, etc.) including a computer-readable medium that is physically modified (e.g., magnetization, polarization, movable placement, etc. of invariant mass particles) to encode instructions for a particular operation. When physically configuring the components, the underlying electrical properties (e.g.) of the hardware composition change from an insulator to a conductor or vice versa. The instructions enable the participating hardware (e.g., an execution unit or a loading mechanism) to create members of the circuit system in the hardware via the physical configuration to perform a part of a particular task when operating. Thus, when the device operates, the computer-readable medium is communicatively coupled to other components of the circuit system. In an instance, any of the physical components may be used in more than one member of more than one circuit system. For example, in operation, an execution unit may be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system or by a third circuit in a second circuit system at a different time.

[0059] A machine (e.g., a computer system, a host system, etc.) 600 may include a processing device 602 (e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), a main memory 604 (e.g., a read only memory (ROM), a dynamic random access memory (DRAM) (e.g., a synchronous DRAM (SDRAM) or a Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., a static random access memory (SRAM), etc.), and a storage system 618, some or all of which may communicate with each other via a communication interface (e.g., a bus) 630. In one instance, the main memory 604 includes one or more memory devices described in the above instances.

[0060] The processing device 602 may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or one processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 may be configured to execute the instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate via the network 620.

[0061] The storage system 618 may include a machine-readable storage medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any or all of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 or the processing device 602 during execution by the computer system 600, which also constitutes a machine-readable storage medium.

[0062] The term "machine-readable storage medium" shall be taken to include a single medium or multiple media that store one or more sets of instructions or any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" shall be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media. In an example, a massed machine-readable medium includes a machine-readable medium having a plurality of particles with invariant (e.g., stationary) mass. Thus, a massed machine-readable medium is not a transitory propagated signal. Specific examples of massed machine-readable media may include: non-volatile memory such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0063] The machine 600 may further include a display unit, an alphanumeric input device (such as a keyboard), and a user interface (UI) navigation device (such as a mouse). In an example, one or more of the display unit, the input device, and the UI navigation device may be a touch screen display. The machine may include a signal generating device (such as a speaker) or one or more sensors (such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or one or more other sensors). The machine 600 may include an output controller, such as a serial (such as Universal Serial Bus (USB)), parallel, or other wired or wireless (such as Infrared (IR), Near Field Communication (NFC), etc.) connection for communicating or controlling one or more peripheral devices (such as a printer, a card reader, etc.).

[0064] Instructions 626 (such as software, programs, an operating system (OS), etc.) or other data are stored on the storage system 618 and can be accessed by the main memory 604 for use by the processing device 602. The main memory 604 (such as DRAM) is typically fast but volatile and is thus a different type of storage than the storage system 618 (such as an SSD), which is suitable for long-term storage (including under “off” conditions). Instructions 626 or data used by the user or the machine 600 are typically loaded into the main memory 604 for use by the processing device 602. When the main memory 604 is full, virtual space from the storage system 618 may be allocated to supplement the main memory 604; however, because storage system 618 devices are typically slower than the main memory 604 and the write speed is typically at least 2 times slower than the read speed, using virtual memory can significantly degrade the user experience (compared to the main memory 604 (such as DRAM)) due to storage system latency. In addition, using the storage system 618 for virtual memory will significantly shorten the usable life of the storage system 618.

[0065] Instructions 626 may be further transmitted or received via the network 620 using a transmission medium via a network interface device 608 that utilizes any of several transport protocols (such as Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include a Local Area Network (LAN), a Wide Area Network (WAN), a packet data network (such as the Internet), a mobile phone network (such as a cellular network), a Plain Old Telephone Service (POTS) network, and a wireless data network (such as the Institute of Electrical and Electronics Engineers (IEEE) 802.15 series of standards (referred to as ) and the IEEE 802.16 series of standards (referred to as ), IEEE 802.15.4 series standards, peer-to-peer (P2P) networks, and so on. In an example, the network interface device 608 may include one or more physical jacks (such as Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the network 620. In an example, the network interface device 608 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term "transmission medium" shall be regarded as including any non-tangible medium capable of storing, encoding, or carrying instructions executed by the machine 600, and including digital or analog communication signals or other non-tangible media that facilitate such software communication.

[0066] The detailed description above includes references to the accompanying drawings which form a part of the detailed description. The drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Additionally, the inventors also contemplate examples (or aspects thereof) using any combination or arrangement of those elements shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0067] All publications, patents, and patent documents referenced in this document are incorporated herein by reference in their entirety as if individually incorporated by reference. If there is an inconsistency in the usage between this document and those incorporated by reference, then the usage in the incorporated references shall be regarded as supplementary to the usage in this document; for irreconcilable inconsistencies, the usage in this document shall prevail.

[0068] In this document, as is common in patent documents, the term "a" is used to include one or more than one, independent of any other instances or uses of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise indicated. In the appended claims, the terms "comprising" and "in which" are used as the ordinary English equivalents of the respective terms "including" and "wherein". Also, in the appended claims, the terms "comprising" and "including" are open-ended, i.e., a system, device, article, or process that includes elements in addition to those listed after this term in the claim is still regarded as falling within the scope of the said claim. Further, in the appended claims, the terms "first", "second", and "third", etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0069] In various examples, the components, controllers, processors, parts, engines, or tables described herein may particularly include physical circuitry or firmware stored on a physical device. As used herein, "processor" refers to any type of computing circuitry, such as (but not limited to) a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuitry (including processor groups or multi-core devices).

[0070] The term "horizontal" as used in this document is defined as a plane parallel to the conventional plane or surface of the substrate (e.g., the plane underlying the wafer or die), regardless of the actual orientation of the substrate at any given point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions (e.g., "on", "above", and "below") are defined with respect to the top or exposed surface of the substrate relative to the conventional plane or surface, regardless of the orientation of the substrate; and "on" is intended to indicate direct contact of one structure with another structure located "on" it (in the absence of an explicit contrary indication); the terms "above" and "below" are explicitly intended to identify the relative placement of structures (or layers, features, etc.), which explicitly includes (but is not limited to) direct contact between the identified structures, unless explicitly so identified. Similarly, the terms "above" and "below" are not limited to a horizontal orientation, because if a structure is the outermost part of the construct being discussed at a given point in time, then the structure can be "above" the reference structure, even if this structure extends vertically rather than horizontally with respect to the reference structure.

[0071] The term "wafer" is generally used herein to refer to any structure on which an integrated circuit is formed and also refers to such structures during various stages of integrated circuit fabrication. The term "substrate" is used to refer to a wafer or other structure that supports or is connected to other components (such as a memory die or a portion thereof). Thus, the term "substrate" includes, for example, a circuit or "PC" board, an interposer, and other organic or inorganic support structures (which may also contain active or passive components in some cases). Accordingly, the following detailed description should not be construed in a limiting sense, and the scope of each embodiment is defined only by the appended claims and the full scope of equivalents authorized by such claims.

[0072] It should be understood that when an element is referred to as "on another element", "connected to another element", or "coupled to another element", it may be directly on the other element, directly connected to the other element, or directly coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as "directly on another element", "directly connected to another element", or "directly coupled to another element", there are no intervening elements or layers. If two elements are shown in a diagram as being connected by a line between them, then the two elements may be coupled or directly coupled, unless otherwise indicated.

[0073] The method examples described herein may be implemented, at least in part, by a machine or a computer. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Additionally, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to: hard disks, removable disks, removable optical disks (such as optical disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0074] To better illustrate the methods and devices disclosed herein, a non-limiting list of examples is provided here:

[0075] Example 1. A semiconductor device, comprising: a first source / drain region extending upward from a semiconductor body; a second source / drain region extending upward from the semiconductor body; wherein the semiconductor body includes a channel fin coupled between the first source / drain region and the second source / drain region; a gate separated from the channel fin by a gate dielectric; a dielectric isolation structure at least partially positioned below the semiconductor body and between the semiconductor body and a substrate; and an electrical contact coupling the semiconductor body to the substrate.

[0076] Example 2. The semiconductor device according to Example 1, wherein the electrical contact is centered below the semiconductor body.

[0077] Example 3. The semiconductor device according to Example 1, wherein the electrical contact includes silicon and germanium.

[0078] Example 4. The semiconductor device according to Example 3, wherein the electrical contact includes silicon and germanium having a ratio of Si x Ge (1-x) where x is between 0.1 and 0.8.

[0079] Example 5. The semiconductor device according to Example 1, further comprising a third source / drain region extending upward from the semiconductor body; and wherein the semiconductor body includes a second channel fin coupled between the third source / drain region and the first source / drain region.

[0080] Example 6. The semiconductor device according to Example 1, wherein the gate includes more than one layer of different conductors.

[0081] Example 7. The semiconductor device according to Example 1, wherein the electrical contact has a thickness of 10 to 20 nm.

[0082] Example 8. A semiconductor device, comprising: a first source / drain region extending upward from a semiconductor body; a second source / drain region extending upward from the semiconductor body; wherein the semiconductor body includes a channel fin coupled between the first source / drain region and the second source / drain region; a gate separated from the channel fin by a gate dielectric; a dielectric isolation structure at least partially positioned under the semiconductor body and between the semiconductor body and a substrate; an electrical contact coupling the semiconductor body to the substrate; and a dielectric isolation trench adjacent to the semiconductor body, wherein the dielectric isolation trench extends into the substrate.

[0083] Example 9. The semiconductor device according to Example 8, wherein the dielectric isolation trench extends deeper into the substrate than the bottom of the electrical contact.

[0084] Example 10. The semiconductor device according to Example 8, wherein the dielectric isolation trench extends into the substrate to a depth less than 250 nm.

[0085] Example 11. The semiconductor device according to Example 10, wherein the dielectric isolation trench extends into the substrate to a depth of 150 nm or less.

[0086] Example 12. The semiconductor device according to Example 8, wherein the gate surrounds the channel fin on three sides, and wherein a fourth side of the channel fin abuts the dielectric isolation structure.

[0087] Example 13. The semiconductor device according to Example 8, further comprising a third source / drain region extending upward from the semiconductor body; and wherein the semiconductor body includes a second channel fin coupled between the third source / drain region and the second source / drain region.

[0088] Example 14. The semiconductor device according to Example 13, wherein the gate is included in a word line.

[0089] Example 15. The semiconductor device according to Example 14, wherein the first source / drain region and the third source / drain region are coupled to a cell contact and the second source / drain region is coupled to a digit line.

[0090] Example 16. A method of forming a semiconductor device, comprising: forming a silicon germanium layer over a substrate; forming a silicon layer over the silicon germanium layer; forming a first source / drain region extending upwardly from the silicon layer and a second source / drain region extending upwardly from the silicon layer, the first source / drain region being coupled to the second source / drain region through a remaining semiconductor body coupled to the silicon germanium layer; forming a contact opening from a surface of the silicon layer to the silicon germanium layer; removing a portion of the silicon germanium layer from under at least a portion of the semiconductor body to leave a remaining silicon germanium contact between the semiconductor body and the substrate; and forming a gate dielectric over a fin portion of the semiconductor body and forming a gate over the gate dielectric.

[0091] Example 17. The method according to Example 16, wherein forming a silicon layer over the silicon germanium layer comprises epitaxially growing the silicon layer over the silicon germanium layer.

[0092] Example 18. The method according to Example 16, wherein removing a portion of the silicon germanium layer comprises etching.

[0093] Example 19. The method according to Example 16, wherein forming a silicon germanium layer over a substrate comprises forming a layer comprising silicon and germanium having a ratio Si x Ge (1-x) where x is in the range between 0.1 and 0.8.

[0094] Example 20. The method according to Example 19, wherein removing a portion of the silicon germanium layer from under at least a portion of the semiconductor body comprises selecting the ratio having the highest etch selectivity of the silicon germanium layer within the range.

[0095] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. For example, one of ordinary skill in the art may use other embodiments after reviewing the above description. The abstract is provided to comply with 37 C.F.R. § 1.72(b) to allow the reader to quickly ascertain the nature of the technical disclosure. It should be understood that it is not intended to be used to interpret or limit the scope or meaning of the claims. Also, in the "Detailed Description", various features may be grouped together to simplify the disclosure. This should not be interpreted as wishing that unclaimed disclosed features are essential to any claim. Rather, the inventive subject matter may have non-all features of a particular disclosed embodiment. Accordingly, the appended claims are hereby incorporated into the Detailed Description, where each claim stands on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims along with the full scope of equivalents to which such claims are entitled.

Claims

1. A semiconductor device, comprising: A first source / drain region extending upward from a semiconductor body; A second source / drain region extending upward from the semiconductor body; Wherein the semiconductor body includes a channel fin coupled between the first source / drain region and the second source / drain region; A gate separated from the channel fin by a gate dielectric; A dielectric isolation structure at least partially positioned under the semiconductor body and between the semiconductor body and a substrate; And An electrical contact coupling the semiconductor body to the substrate.

2. The semiconductor device according to claim 1, wherein the electrical contact is centered under the semiconductor body.

3. The semiconductor device according to claim 1, wherein the electrical contact comprises silicon and germanium.

4. The semiconductor device according to claim 3, wherein the electrical contact comprises silicon and germanium having a ratio Si x Ge (1-x) where x is between 0.1 and 0.

8.

5. The semiconductor device according to claim 1, further comprising a third source / drain region extending upward from the semiconductor body; and Wherein the semiconductor body includes a second channel fin coupled between the third source / drain region and the first source / drain region.

6. The semiconductor device according to claim 1, wherein the gate comprises more than one layer of different conductors.

7. The semiconductor device according to claim 1, wherein the electrical contact has a thickness of 10 to 20 nm.

8. A semiconductor device, comprising: A first source / drain region extending upward from a semiconductor body; A second source / drain region extending upward from the semiconductor body; Wherein the semiconductor body includes a channel fin coupled between the first source / drain region and the second source / drain region; A gate separated from the channel fin by a gate dielectric; A dielectric isolation structure at least partially positioned under the semiconductor body and between the semiconductor body and a substrate; An electrical contact coupling the semiconductor body to the substrate; And A dielectric isolation trench adjacent to the semiconductor body, wherein the dielectric isolation trench extends into the substrate.

9. The semiconductor device according to claim 8, wherein the dielectric isolation trench extends deeper into the substrate than the bottom of the electrical contact.

10. The semiconductor device according to claim 8, wherein the dielectric isolation trench extends into the substrate to a depth less than 250 nm.

11. The semiconductor device according to claim 10, wherein the dielectric isolation trench extends into the substrate to a depth of 150 nm or less.

12. The semiconductor device according to claim 8, wherein the gate surrounds the channel fin on three sides, and wherein a fourth side of the channel fin abuts the dielectric isolation structure.

13. The semiconductor device according to claim 8, further comprising a third source / drain region extending upward from the semiconductor body; and Wherein the semiconductor body includes a second channel fin coupled between the third source / drain region and the second source / drain region.

14. The semiconductor device according to claim 13, wherein the gate is included in a word line.

15. The semiconductor device according to claim 14, wherein the first source / drain region and the third source / drain region are coupled to a cell contact and the second source / drain region is coupled to a digital line.

16. A method of forming a semiconductor device, comprising: forming a silicon germanium layer over a substrate; forming a silicon layer over the silicon germanium layer; forming an upwardly extending first source / drain region and an upwardly extending second source / drain region from the silicon layer, the first source / drain region being coupled to the second source / drain region through a remaining semiconductor body coupled to the silicon germanium layer; forming a contact opening from a surface of the silicon layer to the silicon germanium layer; removing a portion of the silicon germanium layer from under at least a portion of the semiconductor body to leave a remaining silicon germanium contact between the semiconductor body and the substrate; and forming a gate dielectric over a fin portion of the semiconductor body and forming a gate over the gate dielectric.

17. The method according to claim 16, wherein forming a silicon layer over the silicon germanium layer comprises epitaxially growing the silicon layer over the silicon germanium layer.

18. The method according to claim 16, wherein removing a portion of the silicon germanium layer comprises etching.

19. The method according to claim 16, wherein forming a silicon germanium layer over the substrate comprises forming a layer comprising silicon and germanium having a ratio Si x Ge (1-x) where x is in the range between 0.1 and 0.

8.

20. The method according to claim 19, wherein removing a portion of the silicon germanium layer from under at least a portion of the semiconductor body comprises selecting the ratio having the highest etch selectivity of the silicon germanium layer within the range.

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