Doping profiles for reducing floating body effects in 4F2 DRAM

Abstract

The present technology includes a vertical cell array transistor (VCAAT) with an improved floating body effect. The arrays include one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The array includes one or more channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that the bit lines intersect source / drain regions of the plurality of channels and the word lines intersect gate regions of the plurality of channels. The array includes a source / drain region having a first section adjacent the source / drain junction and a second section adjacent the channel body, wherein the doping concentration of the first section is greater than the doping concentration of the second section.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Patent Application No. 63 / 589,920, filed October 12, 2023, entitled “DOPING PROFILE FOR REDUCED FLOATING BODY EFFECT IN 4F2 DRAM,” which is hereby incorporated by reference in its entirety.

[0002] The present disclosure generally describes a 4F 2 design of a dynamic random access memory array. More specifically, the present disclosure describes a 4F 2 memory array with reduced floating body effect and improved threshold voltage stability. BACKGROUND

[0003] As computing technology has advanced, computing devices have become smaller and more powerful. Accordingly, there has been a need to increase storage and memory to meet the programming and computing demands of devices. Increases in storage capacity have been achieved by increasing the number of memory cells of smaller and smaller geometry.

[0004] Dynamic random access memory (DRAM) architectures have been shrinking over time. For example, a one transistor, one capacitor (1T-1C) DRAM cell architecture has been successfully scaled from an 8F2 size to a 6F2 size (where F is the minimum feature size). Further scaling the design from 6F2 to 4F2 can help to further increase the area density. In a 4F2 DRAM scheme, the storage node (capacitor) and bit line are located on top and bottom of the vertical cell transistor, isolating the channel completely from the body. Due to this arrangement, there is no floating body effect issue due to the body connection of the channel for current 8F2 or 6F2 DRAM cell structures, but for 4F2 DRAM, floating body effect becomes a significant technical challenge. Accordingly, improvements in the technology are needed. SUMMARY

[0005] The technology is generally directed to vertical cell array transistors (VCATs) and methods of forming such devices. The transistors include one or more bitlines arranged along a first horizontal direction, one or more wordlines arranged along a second horizontal direction, and one or more channels extending along a vertical direction. The transistors include where the vertical direction is substantially orthogonal to the first and second horizontal directions, such that the one or more bitlines intersect source / drain regions of the one or more channels and the one or more wordlines intersect gate regions of the one or more channels. The transistors include where the source / drain regions include a first section adjacent to a source / drain junction and a second section adjacent to a channel body, where a doping concentration of the first section is greater than a doping concentration of the second section.

[0006] In specific embodiments, the doping concentration of the source / drain regions exhibits a Gaussian (normal) distribution with a peak concentration approximately at the source / drain junction. In further specific embodiments, the doping concentration of the first section is greater than or about 2 times the doping concentration of the second section. Additionally, in specific embodiments, the doping concentration of the first section is greater than 1 x 1019cm-3. 19 −3 In further specific embodiments, the doping concentration of the first section is greater than 4 x 1019cm-3. 19 −3 Additionally or alternatively, in specific embodiments, the doping concentration of the second section is less than or about 1 x 1019cm-3. 19 −3 In further specific embodiments, the channel further includes one or more P-type doped regions. Specific embodiments include where the channel exhibits a height extending between the source / drain region and the second source / drain region, where the one or more P-type doped regions are formed at a height of about 20% to about 80% of the height of the channel height. In further specific embodiments, the doping concentration of the one or more P-type doped regions is greater than or about 5 x 1019cm-3to about 1 x 1020cm-3. 16 −3 20 −3 Additionally, in specific embodiments, the channel exhibits a height extending between the source / drain region and the second source / drain region, where the one or more P-type doped regions have a thickness of about 5% to about 30% of the height of the channel height.

[0007] ​​​​​​The technology relates generally to vertical cell array transistors (VCATs). The transistor includes a plurality of bit lines arranged along a first horizontal direction, a plurality of word lines arranged along a second horizontal direction, and a plurality of channels extending along a vertical direction from a first source / drain region to a second source / drain region. The transistor includes where the vertical direction is substantially orthogonal to the first horizontal direction and the second horizontal direction, such that the plurality of bit lines intersect the first source / drain region and / or the second source / drain region of the plurality of channels, and the plurality of word lines intersect the gate region of the plurality of channels. The transistor includes where at least a portion of the plurality of channels includes one or more P-type doped regions disposed between the first source / drain region and the second source / drain region.

[0008] In specific embodiments, at least a portion of the plurality of channels exhibits a height extending between the first source / drain region and the second source / drain region, where the one or more P-type doped regions are formed at a height of about 20% to about 80% of the height of the channel height. In more specific embodiments, the transistor further includes at least a second P-type doped region of the one or more P-type doped regions. Further, in specific embodiments, the one or more P-type doped regions exhibit a doping concentration greater than or about 5 x 1019cm-3to about 1 x 1020cm-3. 16 cm −3 20 cm −3 In more specific embodiments, the channel exhibits a height extending between the first source / drain region and the second source / drain region, where the one or more P-type doped regions have a thickness of about 5% to about 30% of the height of the channel height.

[0009] The technology also relates generally to methods of forming vertical cell array transistors (VCATs). The method includes etching a substrate to form one or more shallow trench isolations and a plurality of vertically extending channels. The method includes implanting one or more ions to contact one or more channels of the plurality of vertically extending channels to form a first source / drain region. The method includes forming a P-type doped region along one or more channels of the plurality of vertically extending channels to form a second source / drain region. The method includes where the first source / drain region includes a first section adjacent to a source / drain junction and a second section adjacent to a channel body, where a doping concentration of the first section is greater than a doping concentration of the second section.

[0010] In specific embodiments, the P-type doped region is formed using a second ion implantation. In more specific embodiments, the method includes annealing the one or more ion implantations and / or the second ion implantation. In more specific embodiments, the method includes etching a portion of one or more channels of the plurality of channels and forming the P-type doped region within the etched portion. Further, in specific embodiments, the forming includes epitaxially growing the P-type doped region. ​

[0011] This technology offers numerous advantages compared to conventional systems and techniques. For example, these processes and systems can reduce the floating body effect and the decay of the threshold voltage over time. Additionally, these processes and systems can significantly improve gate-induced drain leakage, for example, by allowing a gradual change in the potential of the storage node contacts in one or more source / drain regions compared to the channel potential. These and other specific embodiments, along with their many advantages and features, will be described in more detail below in conjunction with the accompanying drawings. Attached Figure Description

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and the accompanying drawings.

[0013] Figure 1A A top plan view of an exemplary processing chamber according to a specific embodiment of the present technology is shown.

[0014] Figure 1B A top view of a conventional 4F2 memory array is shown.

[0015] Figure 1C A perspective view of a conventional 4F2 memory array is shown.

[0016] Figure 2 The selected operation in the formation method according to a specific embodiment of the present technology is shown.

[0017] Figure 3A A perspective view of a semiconductor structure according to a specific embodiment of the present technology is shown, wherein the semiconductor structure is filled with dielectric material after shallow trench isolation is formed.

[0018] Figure 3B A perspective view of a semiconductor structure according to a specific embodiment of the present technology is shown, the semiconductor structure being patterned for the formation of a second shallow trench isolation.

[0019] Figure 3C A perspective view of a semiconductor structure according to a specific embodiment of the present technology is shown, the semiconductor structure having gate oxide and low work function material deposition word line isolation.

[0020] Figure 3D A perspective view of a semiconductor structure having doped source / drain regions according to a specific embodiment of the present technology is shown.

[0021] Figure 4A A cross-sectional view of the interface according to a specific embodiment of the present technology is shown.

[0022] Figure 4B A cross-sectional view of the interface according to a specific embodiment of the present technology is shown.

[0023] Several of the illustrations are schematic. It should be understood that these illustrations are for reference only and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, as illustrative, these illustrations are provided to aid understanding and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

[0024] In the accompanying drawings, similar parts and / or features may have the same element symbol. Furthermore, various parts of the same type may be distinguished by adding a letter after the element symbol to differentiate them. If only the first element symbol is used in the specification, the description applies to any similar part having the same first element symbol, regardless of the letter used. Detailed Implementation

[0025] Historically, the node growth rate of DRAM chip bit density has been around 25%. However, in recent generations, this trend has slowed to nearly 20%, primarily due to the challenges of expanding cell area. Modern DRAM cell design architectures have historically been based on a 6F2 geometry, where "F" represents the minimum feature size for a given technology node. Converting from 6F2 to a 4F2 cell architecture can increase the bit density of the same technology node by 33%. Furthermore, 4F2 DRAM is significantly less complex to pattern than 6F2. This is at least partly because in 4F2 DRAM, capacitors and bit lines are located at opposite ends of the vertical cell transistors, rather than being tightly packed on the same side as in 6F2 DRAM.

[0026] However, the design of 4F2 DRAM also presents its own challenges. For example, the transistor channels of a 4F2 memory cell are arranged between the bit lines and the capacitor layer, leaving no common substrate connecting the channels, causing these transistors to exhibit a floating body effect. For instance, it is believed that conventional 4F2 DRAM access devices suffer from off-leakage current problems. Off-leakage current stems from the floating body effect, where holes accumulate in the body of a 4F2 DRAM device due to channel isolation. Electron-hole pairs form in the semiconductor channels due to inter-band tunneling. While electrons can flow into the n-type source or drain regions of the transistor, holes cannot. For 4F2 DRAM devices without substrate connections, holes have no path to leave the channel and accumulate continuously. Therefore, the floating body effect can cause channels to be enabled without gate activation, eventually translating into leakage current from capacitors or the device data memory side, leading to a drop in threshold voltage over time. Some have attempted to provide body connectivity using buried body contact schemes. However, this approach may result in the gate overlapping with the source / drain junction edge, causing unwanted gate-induced drain leakage, or limiting scalability to smaller sizes. Furthermore, this design can produce aspect ratio structures that challenge existing doping techniques.

[0027] Vertical channel access array transistors (VCAATs) are more susceptible to increased leakage current, such as gate-induced drain leakage current, at least in part due to the floating body effect. This phenomenon can further exacerbate the floating body effect. For example, as holes accumulate, charge can build up on the bit lines, lowering the potential between the channel and the storage node. This can increase inter-band tunneling and further reduce the threshold voltage of the access transistor.

[0028] This technique overcomes the aforementioned and other problems by providing a source / drain doping profile to reduce the rate of change of the storage node contact potential in one or more source / drain regions. In other words, by carefully controlling the doping profile of one or more source / drain regions, the barrier between the channel potential and the storage node contact potential can be increased. Since band-to-band tunneling is exponentially related to the barrier thickness, the systems and devices discussed herein exhibit a significant reduction in band-to-band tunneling, thereby reducing the floating body effect. Furthermore, this technique also finds that by carefully forming one or more busbars in the channel region, holes can be further dissipated, further improving the floating body effect. Therefore, unlike previous attempts, this technique provides a word line that maintains the necessary threshold voltage to achieve low turn-off current leakage while reducing gate-induced drain leakage current and even the floating body effect of vertical channel access array transistors (VCAAT).

[0029] While other disclosures routinely identify specific deposition and etching processes for forming Vertical Cell Access Array (VCAAT) transistors (such as 4F2 DRAM devices), it is readily understood that these systems and methods are equally applicable to other DRAM devices, including Gate-All-Around and Schottky Barrier VCAATs, other devices affected by the floating body effect and their variations, and the processes used to form such devices. Therefore, this technology should not be considered limited to use with these specific devices or systems. Before making additional changes and adjustments to the device according to specific embodiments of this technology, this disclosure discusses a possible semiconductor device that may include one or more components utilizing one or more word lines.

[0030] Figure 1A A top plan view of a multi-chamber processing system 100 is shown. The multi-chamber processing system 100 can be specifically configured to implement aspects or operations of some embodiments according to the present technology. The multi-chamber processing system 100 can be configured to perform one or more manufacturing processes on individual substrates (e.g., any number of semiconductor substrates) to form a semiconductor device. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer loading and locking chambers 110 and 112 (and possibly dual-wafer loading and locking chambers), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. Single-wafer loading and locking chambers 110 and 112 may include a heating element 113 and may be connected to the buffer chamber 108. Processing chambers 114, 116, 118, and 120 may be connected to the transfer chamber 106. Processing chambers 122 and 124 can be connected to buffer chamber 108. Two substrate transfer platforms 102 and 104 can be arranged between transfer chamber 106 and buffer chamber 108, facilitating transfer between robots 126 and 128. Platforms 102 and 104 can be open to both the transfer chamber and the buffer chamber, or the platforms can be selectively isolated from or sealed to maintain different operating pressures between transfer chamber 106 and buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105, for example, for orientation or measurement operations.

[0031] The execution of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any means or combination of means configured to perform the operations described below. Accordingly, the computer system 130 may be a controller or controller array and / or a general-purpose computer configured with software stored on a non-transitory, computer-readable medium, which, when executed, can perform the operations described in the methods according to specific embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in semiconductor structure fabrication. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing operations, including dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and any number of other substrate processes.

[0032] Figure 1B and 1C Top and perspective views of a conventional 4F2 memory array 150 are shown. The memory array 150 may include a plurality of word lines 152 arranged in a first layer on a substrate. The word lines 152 may be conductive traces used to select word lines for memory cells within the memory array 150. The memory array 150 may also include a plurality of bit lines 154 arranged in a second layer on the substrate. The bit lines may be conductive traces used to select bit lines for memory cells within the memory array 150. Enabling one of the bit lines 154 and one of the word lines 152 selects a single cell in the memory array 150. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer with word lines 152 may be formed over the second layer with bit lines 154, such that the two layers do not intersect.

[0033] A plurality of vertical memory cells may be arranged at the intersections between a plurality of word lines 152 and a plurality of bit lines 154. Each of the plurality of vertical memory cells may include a vertical transistor, which may be referred to as a vertical pillar transistor or a vertical row transistor. The channel material of the transistor may be formed from a single-crystal silicon pillar or from any other substrate discussed in detail below. Such a silicon channel may be formed by etching the substrate. Each of the plurality of vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing charge on the vertical capacitor 156 to indicate the stored memory state. However, although Figure 1B and 1CThe illustration depicts the arrangement of vertical transistors and capacitors in a rectangular, generally orthogonal grid pattern (where "generally orthogonal" can be within approximately 10° of orthogonality, e.g., less than or about 7.5°, e.g., less than or about 5°, e.g., less than or about 2.5°, e.g., less than or about 1°, or any range or value in between; "generally" can be used to similarly change "vertical," "horizontal," etc.). It should be understood that other orientations can be considered for this technique. For example, in a specific embodiment, capacitors and vertical transistors can be alternately spaced in columns, with the distance between the vertical transistors offset by half. That is, the first column of memory cells can be regularly spaced in a straight line along a first direction, and the second column of memory cells can also be regularly spaced in a straight line along the first direction, but in a specific embodiment, the second column of memory cells can be offset from the first column of memory cells, e.g., aligned approximately half the distance between the vertical transistors and capacitors in the first column. Figure 1B and Figure 1C Compared to the square pattern shown, this pattern can be called a "honeycomb" or "hexagonal pattern". Therefore, it should be understood that this technique can be used for any suitable orientation.

[0034] Characterizing the size of the unit cell area 166 of this conventional 4F2 memory array is useful for comparison with the simpler memory array described below. For example, the capacitor footprint 158 ​​can be defined as a circular region surrounding each vertical capacitor 156. The capacitor footprint 158 ​​can include the horizontal cross-sectional area of ​​the capacitors up to the capacitor region of the adjacent memory cell. Assume that the word line spacing 162 of the complex number of word lines 152 and the bit line spacing 164 of the complex number of bit lines 154 can be defined as 2F. Therefore, the total cross-sectional area of ​​the unit cell area 166 is 4F2.

[0035] Figure 2 Exemplary operations in method 200 according to some specific embodiments of the present invention are shown. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of optional operations, which may or may not be relevant to some specific embodiments of the method according to the present invention. For example, many operations are described to provide a broader range of structure formations, but these operations are not critical to the present invention or may be performed by easily understood alternative methods. Furthermore, while the method may be described vertically as a formation method, it should be understood that other orientations from the bit line to the word line side may be utilized.

[0036] Method 200 may include additional operations prior to initiating the listed operations. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include forming and removing material. The previous processing operations may be performed in the chamber in which method 200 is performed, or the processing operations may be performed in one or more other processing chambers prior to feeding the substrate into the semiconductor processing chamber in which method 200 is performed. In any case, method 200 may optionally include transporting the semiconductor substrate to a processing region of the semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include the components described above. The substrate may be deposited on a substrate support / transfer platform, which may be a base such as substrate support 104, and may reside in a processing region of the chamber, such as the processing region of processing chamber 120 described above. Method 200 describes... Figures 3A-3D The operations illustrated in 4A and 4B will be described in conjunction with the operations of method 200. It should be understood that... Figures 3A-3D Figures 4A and 4B are only schematic representations of some parts. The semiconductor substrate may include further and alternative components as shown in the figures, and any size or configuration thereof may still benefit from various aspects of the technology.

[0037] Method 200 may or may not involve optional operations such as developing and extending the semiconductor structure to a specific manufacturing operation. It should be understood that method 200 can be performed on any number of semiconductor structures 300 or substrates 302, such as... Figures 3A-3D As shown in 4A and 4B, exemplary structures include those on which selectively deposited materials can be formed. Figure 3A The substrate 302 shown can be any number of materials, such as a substrate wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed on the substrate during semiconductor processing.

[0038] In a specific embodiment, structure 300 may be a semiconductor substrate, including a bulk substrate, an epitaxial growth substrate, and / or silicon on an insulator wafer. The term "semiconductor substrate" as used herein refers to a substrate whose entire substrate is made of semiconductor material. A semiconductor substrate may include any suitable semiconductor material and / or a combination of semiconductor materials used to form the semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor material may include silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In one or more embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials from which substrates may be formed are described herein, any material that can serve as the basis for the construction of passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is within the spirit and scope of this disclosure.

[0039] In specific embodiments, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In specific embodiments, the substrate can be doped using any suitable process, such as ion implantation. The term "n-type" as used herein refers to a semiconductor produced during manufacturing by doping an intrinsic semiconductor with an electron donor element. The term n-type originates from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. The term "p-type" as used herein refers to the positive charge of wells (or holes). Compared to n-type semiconductors, p-type semiconductors have a greater hole concentration than electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0040] like Figure 3A As shown, the provided structure 300 includes a substrate 302 that has undergone shallow trench isolation formation 308, and a first dielectric material 306 filled in the shallow trench isolation 308. Furthermore, two or more walls 305 are formed between the respective first shallow trench isolations 308, wherein the illustrated walls 305 are spaced in horizontally extending columns generally perpendicular to the word line direction in this specific embodiment. However, as those skilled in the art will understand, in this specific embodiment, the shallow trench isolations may first be cut in a direction generally parallel to the word line direction.

[0041] While various deposition and fill processes will be described, it should be understood that, in specific embodiments, the semiconductor structure may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or fill processes, including chambers for processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or similar chambers. Therefore, unless specifically stated otherwise, it should be understood that any one or more of the above methods known in the art may be employed. Similarly, the semiconductor structure may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, such as one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, and other etching processes known in the art.

[0042] Nevertheless, in operation 201, method 200 may include forming such as Figure 3A The first shallow trench isolation shown and as Figure 3B The second shallow trench isolation 346 is shown. For example, in a specific embodiment, the substrate 302 can be loaded into loading locking chambers 110, 112 and transferred to a processing chamber (e.g., processing chamber 114) via robots 126, 128. In the processing chamber, the semiconductor structure 300 can be formed at operation 201 by forming a mask 340 and a second shallow trench isolation 346. Since the second shallow trench isolation 346 can extend in a generally horizontal direction that is generally parallel to the word line direction, it can also be referred to here as word line trench formation. For example, Figure 3B A mask 340 is shown, which can be any patterned mask known in the art, and the wall 305 is etched into channels 348 by etching in a direction extending in a second horizontal direction that is substantially perpendicular to the first horizontal direction in a specific embodiment. In other words, the formation of shallow trench isolation 308 between walls 305 as discussed above can be achieved using a pattern or mask 340 that defines a second shallow trench isolation 346 to form isolation between channels 348, which in this embodiment are formed in a row parallel to word lines or on a plane by an etching process. The channels 348 thus formed can have uniform or non-uniform widths, and / or widths substantially equal to the wall 305. The second shallow trench isolation 346 can serve to isolate adjacent channels 348. Therefore, as Figure 3A and 3BAs shown, a semiconductor structure 300 including first and second shallow trench isolations can be provided, wherein the first shallow trench isolation may comprise a deposited or filled dielectric material as described above. It should be understood that the substrate may be transferred between each operation step, or only between some operation steps, since some operation steps may be performed in the same processing chamber.

[0043] like Figure 3C As shown, in a specific embodiment, the formation of the source / drain region 304 is performed and may include one or more ion implantations, followed by a subsequent annealing process. The implantation process can be a single implantation or include a series of multiple implantations, as will be discussed in detail below. When using multiple implantations, each implantation may utilize the same ions or different ions. While it should be understood that the source / drain region 304 can be formed by any suitable process, in a specific embodiment, the source / drain region 304 may be endowed with one or more doping gradients. That is, as will be discussed below... Figure 4A and Figure 4B As discussed in more detail below, this technology has surprisingly discovered that by utilizing the doping gradients of the first source / drain region 304 and / or the second source / drain region 324, the rate of change of the storage node contact potential of each source / drain region can be precisely tailored, thereby reducing the risk of band-to-band tunneling and the floating body effect. Nevertheless, the method may include providing a semiconductor structure having first source / drain regions 304 for a plurality of vertical channels and forming a plurality of word lines in contact with the first source / drain regions. However, in a specific embodiment, the formation of the first source / drain regions 304 may be performed prior to operation 201. Overall, this process incrementally forms each stage of the transistor based on a previously completed stage.

[0044] Optional operation 203 may include forming one or more P-type doped regions in one or more channels 348. While the source / drain regions 304 / 324 uniquely formed according to this technology can solve the floating body effect and other problems discussed above, in specific embodiments, it may be desirable to further include one or more P-type doped regions 310. In other words, this technology surprisingly finds that by including one or more P-type doped regions 310 within one or more channels 348, the P-type doped regions can serve as convergence points for hole accumulation. Furthermore, such P-type doped regions 310 can also increase the threshold voltage of the channel, widen the voltage range of the channel in turn-off orientation, and reduce gate-induced drain leakage.

[0045] In a specific implementation, one or more doped regions 310 may have a sufficient doping level to prevent significant charge sharing; for example, the doping level may be sufficient to provide a Vt above the gate threshold for the respective channels 348 forming the P-type doped regions 310. Nevertheless, since the doping level of each P-type doped region 310 is higher than that of the channels 348, dopant may diffuse from the center of each P-type doped region 310 toward adjacent channels 348. Thus, diffusion can create a dopant gradient from each P-type doped region 310 toward the source / drain regions 304, 324. This phenomenon can improve hole attraction and reduce the floating body effect, as holes can move from problem areas of one or more channels 348 to the P-type doped regions 310, collect holes, and dissipate the effect. However, if the doping level in one or more P-type doped regions 310 is too high compared to the respective channels 348, dopant diffusion may raise the doping level of one or more channels 348 above the threshold of the channel 348. Therefore, in specific embodiments, the doping level of each P-type doped region 310 compared to channel 348 is carefully selected. In any case, this technology has surprisingly found that the P-type doped region 310 significantly reduces the floating body effect, for example, by reducing the increase in channel potential and lowering the turn-off leakage current.

[0046] In a specific embodiment, the doping concentration of one or more P-type doped regions 310 can be greater than or approximately 5 x 10⁻⁶. 16 cm −3 If greater than or approximately 6x10 16 cm −3 If greater than or approximately 7x10 16 cm −3 If greater than or approximately 8x10 16 cm −3 If greater than or approximately 9x10 16 cm −3 If greater than or approximately 1x10 17 cm −3 If greater than or approximately 2x10 17 cm −3 If greater than or approximately 4x10 17 cm −3 If greater than or approximately 6x10 17 cm −3 If greater than or approximately 8x10 17 cm −3 If greater than or approximately 1x10 18 cm−3, such as greater than or approximately 2 x 10 18 cm −3 If greater than or approximately 4x10 18 cm −3 If greater than or approximately 6x1018 cm −3 If greater than or approximately 8x10 18 cm −3 If greater than or approximately 1x10 19 cm −3 If greater than or approximately 2 x 10 19 cm −3 or less than or about 1x10 20 cm −3 If smaller than or approximately 8x10 19 cm −3 If smaller than or approximately 6x10 19 cm −3 If less than or approximately 4x10 19 cm −3 If less than or approximately 2x10 19 cm −3 , or any range or value between the two.

[0047] Nevertheless, in specific embodiments, one or more P-type doped regions 310 may use a variety of different materials. For example, one or more P-type doped regions 310 may comprise crystalline semiconductors, such as silicon, germanium, silicon-germanium, one or more dielectric materials, and / or other suitable structural support materials. In specific embodiments, one or more P-type doped regions may be formed of crystalline silicon, such as the single-crystal silicon described in the embodiments, or any one or more semiconductor materials, dielectric materials, and any other materials suitable for deposition between adjacent channels to provide structural support, as discussed above. Nevertheless, these materials may also be in the form of polycrystalline semiconductors.

[0048] In a specific embodiment, one or more P-type doped regions 310 may be formed by epitaxially growing material on the trench channel material 348 in the shallow trench isolation 308. Therefore, in this specific embodiment, this process may be referred to as a selective epitaxial deposition process. Alternatively, one or more P-type doped regions 310 may be formed by conformally filling one or more P-type doped region 310 materials between adjacent shallow trench isolations 308, or by depositing one or more P-type doped region 310 materials using other deposition methods known in the art. Additionally or alternatively, a portion of the channel 348 may be doped, for example, through implantation and annealing processes. Regardless of the method used, it should be clear that the material used for the one or more P-type doped regions 310 is deposited, grown, or formed. If a deposition or growth method is used, a second channel material may be formed on the P-type doped regions 310, which may be the same channel material discussed above, forming the channel 348.

[0049] In a specific embodiment, one or more P-type doped regions 310 are formed only in a portion of one or more channels 348. For example, as Figure 3C As shown, the thickness t of one or more P-type doped regions 310 is approximately 5% to approximately 30% of the height h of each channel 348, for example, greater than or about 7.5%, greater than or about 10%, greater than or about 12.5%, greater than or about 15%, greater than or about 17.5%, greater than or about 20%, greater than or about 22.5%, greater than or about 25%, greater than or about 27.5%, or less than or about 30%, less than or about 27.5%, less than or about 25%, less than or about 22.5%, less than or about 20%, or any range or value between the two. By selecting one or more P-type doped regions 310, each having a certain thickness, or the total thickness of the P-type doped regions according to the above range, excellent floating body effect and leakage current characteristics can be exhibited without negatively impacting the channel.

[0050] In other words, in a specific embodiment, the thickness t of one or more P-type doped regions 310 can be greater than or about 2 nm, for example greater than or about 4 nm, for example greater than or about 6 nm, for example greater than or about 8 nm, for example greater than or about 10 nm, for example greater than or about 12 nm, for example greater than or about 14 nm, for example greater than or about 16 nm, for example greater than or about 18 nm, for example greater than or about 20 nm, for example greater than or about 22 nm, for example greater than or about 24 nm, for example greater than or about 26 nm, for example greater than or about 28 nm, for example greater than or about 30 nm, for example greater than or about 32 nm, for example greater than or about 34 nm, for example greater than or about 36 nm, for example greater than or about 38 nm, for example greater than or about 40 nm, or for example less than or about 70 nm, for example less than or about 60 nm, for example less than or about 50 nm, for example less than or about 55 nm, for example less than or about 50 nm, for example less than or about 45 nm, for example less than or about 40 nm, or any range or value between the two. In other words, in specific implementations, the thickness can be selected to provide sufficient sedimentation and doping characteristics without affecting the overall electrical characteristics of the corresponding channel.

[0051] Furthermore, as described above, in a specific embodiment, one or more P-type doped regions 310 may be formed at approximately the center point of the respective channel 348 between the first and second source / drain regions, or as... Figure 3CBetween the source / drain 304 and the top surface 307. That is, by utilizing one or more P-type doped regions 310 at approximately the center point, a larger hole distribution and reduced gate-induced drain leakage can be achieved. However, it should be understood that in specific embodiments, more than one P-type doped region 310 can be used within each channel, and any one or more of these P-type doped regions 310 may not be located at an approximately center point. For example, since one P-type doped region 310 can be arranged adjacent to the source / drain region 304, and another P-type doped region 310 can be formed adjacent to the second source / drain region of the semiconductor structure 300 (e.g., see...). Figure 4B Nevertheless, regardless of the number of P-type doped regions 310 utilized in each respective channel, channel 348 may have a height h extending between the first and second source / drain regions, and at least one P-type doped region may be formed at a height of about 20% to about 80% of the channel height, for example about 30% to about 70%, for example about 40% to about 60%, for example about 45% to about 55%, or any range or value therebetween.

[0052] After forming one or more P-type regions 310 and, if necessary, the upper portion of channel 348, the structure 300 can re-enter the normal process flow of a vertical cell DRAM array (e.g., a 4F2 DRAM array) and undergo one or more further processing steps until the second source / drain region 324 is doped during operation 204. For example, as shown, gate dielectric 326 and gate metal 328 can be formed along shallow trench isolation 346. Furthermore, after forming gate dielectric 326 and gate metal 328, a second dielectric 330 can be filled into the shallow trench isolation 346.

[0053] In a specific embodiment, the gate metal 328 may be a low-resistance metal or other material, including tungsten, titanium nitride, titanium, ruthenium, cobalt, molybdenum, or combinations thereof. In a specific embodiment, the gate dielectric 326 may be formed of any dielectric material known in the art, such as silicon nitride, silicon oxynitride, silicon dioxide, silicon oxide, or other similar materials. Furthermore, the second dielectric material 330 may be formed of any one or more dielectric materials discussed herein. Nevertheless, as shown, the second source / drain region 324 may be formed by any one or more methods discussed above, or as will be discussed in more detail below. In a specific embodiment, the second source / drain region 324 may be formed before filling the second dielectric material 330. Alternatively or additionally, the second dielectric material 330 may be filled, and etched back to a depth below the desired source / drain region 324 of the channel 348. After etching, the second source / drain region 324 may be formed using implantation, placement, or other methods, and then the second dielectric material 330 may be refilled.

[0054] Nevertheless, in specific embodiments, one or more of the first source / drain region 404 and / or the second source / drain region 424 can be configured to exhibit a doping gradient, such as Figure 4A and 4B As shown. In a specific embodiment, the first source / drain region 404, the second source / drain region 424, or both the first source / drain region 404 and the second source / drain region 424 may have a first portion 404a / 424a adjacent to the end face of the bit line 462 of the channel 448 and the storage node contact 464. The first portion 404a / 424a exhibits a higher doping concentration than other portions of the source / drain region 404 / 424 (such as all other portions). In a specific embodiment, the first portion of each source / drain region may be directly adjacent to the end face of the channel, such as the bit line 462 and the storage node contact 464, and may form all or part of the end face (e.g., may form the source / drain contact).

[0055] Figure 4A and 4B Reference numeral 426 in the reference numeral 426 denotes the gate oxide layer of a transistor, which may be a single layer or multiple layers formed of a dielectric layer. One or more gate oxide layers may include SiO2, SiON, SiN, HfO2, HfZrO, differently doped HfOx, other oxides known in the art, and combinations thereof. Although Figure 4A and Figure 4B As shown in cross-section, but in a specific embodiment, the gate oxide 426 may extend around the channel 448, for example, in a gate-all-around structure.

[0056] In addition, by Figure 4A and Figure 4B The opposed terminal region shown in portions 404f / 424f can be arranged adjacent to the gate 430 of the transistor, which can also serve as a word line 430, and can form an interface with the word line 430. In a specific embodiment, the portion adjacent to the channel body can have a lower doping concentration than other portions (e.g., all other portions) of the source / drain regions 404 / 424. Although Figure 4A and 4B The diagram is shown in cross-section, but it should be understood that in specific implementations, word line 430 may extend around channel 448, for example, in a fully surrounding gate structure.

[0057] For example, in a specific embodiment, all or part of the first portion 404a and / or 424a may have a size greater than or about 5 x 10. 19 cm −3 If greater than or approximately 6x1019 cm −3 If greater than or approximately 7x10 19 cm −3 Doping concentration, such as greater than or about 8 x 10 19 cm −3 If greater than or approximately 9x10 19 cm −3 If greater than or approximately 1x10 20 cm −3 If greater than or approximately 2x10 20 cm −3 If greater than or approximately 3x10 20 cm −3 If greater than or approximately 4x10 20 cm −3 If greater than or approximately 5x10 20 cm −3 If greater than or approximately 6x10 20 cm −3 If greater than or approximately 7x10 20 cm −3 If greater than or approximately 8x10 20 cm −3 If greater than or approximately 9x10 20 cm −3 or less than or about 1x10 21 cm −3 If smaller than or approximately 9x10 20 cm −3 If smaller than or approximately 8x10 20 cm −3 If less than or approximately 7x10 20 cm −3 If smaller than or approximately 6x10 20 cm −3 Or any range or value between the two. In a specific embodiment, end faces 462 and / or 464 may exhibit any one or more of the above concentrations, and the concentration may decrease as it moves from end faces 462 / 464 toward the channel body 428.

[0058] Furthermore, in specific embodiments, the doping concentration of 404f and / or 424f, in whole or in part, can be less than or approximately 5 x 10⁻⁶. 19 cm −3 If less than or approximately 4x10 19 cm −3 If less than or approximately 3x10 19 cm −3 If less than or approximately 2x10 19 cm −3 If less than or approximately 1x10 19 cm−3 If less than or approximately 9x10 18 cm −3 If less than or approximately 8x10 18 cm −3 If less than or approximately 7x10 18 cm −3 If less than or approximately 6x10 18 cm −3 If less than or approximately 5x10 18 cm −3 If less than or approximately 4x10 18 cm −3 If less than or approximately 3x10 18 cm −3 If less than or approximately 2x10 18 cm −3 If less than or approximately 1x10 18 cm −3 or greater than or approximately 5x10 17 cm −3 or greater than or approximately 6x10 17 cm −3 Or, for example, greater than or about 7x10 17 cm −3 or, for example, greater than or about 8x10 17 cm −3 or, for example, greater than or about 9x10 17 cm −3 or, for example, greater than or about 1x10 18 cm −3 , or any range or value between the two.

[0059] Therefore, in a specific embodiment, the doping concentration of the first segment 404a and / or 424a may be higher than the doping concentration of the segment 404f and / or 424f. In a specific embodiment, the doping concentration of the first segment 404a and / or 424a adjacent to one or more ends 462 / 464 may be greater than or about 1.5 times, for example greater than or about 2 times, for example greater than or about 2.5 times, for example greater than or about 3 times, for example greater than or about 3.5 times, for example greater than or about 4 times, for example greater than or about 4.5 times, for example greater than or about 5 times, for example greater than or about 5.5 times, for example greater than or about 6 times, for example greater than or about 6.5 times, for example greater than or about 7 times, for example greater than or about 7.5 times, for example greater than or about 8 times, for example greater than or about 8.5 times, for example greater than or about 9 times, for example greater than or about 9.5 times, for example even greater than or about 10 times the doping concentration of the portion adjacent to or forming contact with the channel body 428 or the gate / word line 430.

[0060] Surprisingly, this technology discovers that in the dual-gate VCAAT implementation, by utilizing a general Gaussian or normal distribution related to doping concentration, extending from end faces 462 and / or 464 to portions 404f and / or 424f adjacent to the channel body 428, and in the omnidirectional gate VCAAT implementation, by utilizing word lines (e.g., when the peak concentration is arranged at or approximately at end faces 462 and / or 464), the contact potential of the storage node can be controlled to significantly reduce (if not mitigate) the occurrence of band-to-band tunneling, floating body effects, and / or gate-induced leakage current. That is, without wishing to be bound by theory, we believe that by forming one or more source-drain regions according to the gradient discussed herein, the slope of the potential change can be smaller, thereby increasing the barrier thickness between the storage node contact potential and the channel potential. This reduces the risk of band-to-band tunneling due to increased barrier thickness, while also increasing hole accumulation before band-to-band tunneling occurs due to increased channel potential. Therefore, this technology can also reduce the decay of the threshold voltage over time.

[0061] Although four additional portions are illustrated in the source / drain regions 404 / 424 (404b-404e, 424b-424e), it should be clear that the source / drain regions 404 and / or 424 can have any number of portions, thereby allowing one or more source / drain regions 404 / 424 to exhibit the gradient discussed above. Furthermore, in specific embodiments, there may be undoped sections, as the doping concentration may instead gradually decrease from the ends 462 / 464 toward the channel body 428, or gradually increase from the region 404f / 424f adjacent to the channel body 428 toward the channel ends 462 / 464 in the dual-gate VCAAT embodiment, and from the word line toward the channel ends 462 / 464 in the omnidirectional gate VCAAT embodiment, according to the distribution discussed above.

[0062] In specific embodiments, the source / drain regions 404 / 424 can be formed using any one or more methods known in the art, provided a gradient is provided. Various implantation methods can be employed in specific embodiments. For example, the source / drain regions can first be contacted with a lightly doped implant adjacent to the channel body, and then moved outwards to the end faces 462 / 464 by one or more higher-energy implants. Alternatively, single or multiple implantations can be used, but various annealing temperatures can be employed. Furthermore, in specific embodiments, combinations of various methods can be used, such as forming one or more lightly doped regions followed by high-energy implantation and / or different annealing temperatures. Nevertheless, it should be understood that various methods can be employed to form the source / drain regions 404 / 424 as long as a suitable gradient is provided.

[0063] Regardless of how or when the source / drain regions 304 and 324 are formed, the semiconductor structure 300 / 400 can re-enter the normal process flow and undergo one or more further processing steps. For example, the semiconductor structure may undergo contact redistribution, bonding pad formation, and / or copper contact formation. Nevertheless, the semiconductor structure can still exhibit significantly reduced gate-induced leakage current, turn-off leakage current, and / or floating body effect.

[0064] It should be understood that the specific steps illustrated in the figures provide a particular method for forming a 4F2 DRAM array according to various specific embodiments. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments may perform the above steps in a different order. Furthermore, each step shown in the figures may include multiple sub-steps, which may be performed in different orders depending on the specific application. Additionally, extra steps may be added or removed depending on the application. Many variations, modifications, and alternatives also fall within the scope of this disclosure.

[0065] The terms “approximately”, “about”, or “substantially” as used herein are to be interpreted as within the range that a person skilled in the art would expect from the specification.

[0066] In the preceding description, for ease of explanation, numerous specific details have been listed to provide a thorough understanding of the various embodiments. However, it will be apparent that some embodiments can be implemented without some of these specific details. In other cases, well-known structures and apparatuses are represented in block diagram form.

[0067] The foregoing description provides specific embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments will provide an advantageous disclosure for implementing at least one specific embodiment. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the spirit and scope of some of the specific embodiments set forth in the appended claims.

[0068] Specific details have been provided in the foregoing description to offer a thorough understanding of the specific implementation. However, it is understood that this implementation can be carried out without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form to avoid obscuring the specific implementation with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary details to avoid obscuring the specific implementation.

[0069] Furthermore, it should be noted that the specific implementation may be described as a process, which may be depicted as a flowchart, data flow diagram, structural diagram, or block diagram. Although a flowchart may describe operations as a sequential process, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. When the operations of a process are completed, the process terminates, but there may be additional steps not included in the diagram. A process can correspond to a method, a function, a procedure, a subroutine, etc. When a procedure corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0070] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical devices, wireless channels, and other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction can represent any combination of programs, functions, subroutines, routines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment can be coupled to another code segment or hardware circuit by passing and / or receiving information, data, parameters, or memory contents. Information, parameters, data, etc., can be passed, forwarded, or transmitted in any suitable manner, including memory sharing, message passing, token passing, network transmission, etc.

[0071] Furthermore, specific implementations can be achieved through hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented through software, firmware, middleware, or microcode, the program code or code segments that perform the necessary tasks can be stored in a machine-readable medium. The processor can then perform the necessary tasks.

[0072] In the foregoing description, features are described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of some specific embodiments may be used individually or in combination. Furthermore, the specific embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of this specification. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0073] Furthermore, for illustrative purposes, the methods are described in a specific order. It should be understood that in another embodiment, the methods may be executed in a different order. It should also be understood that the above methods can be executed by hardware components or embodied as a sequence of machine-executable instructions that can be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuit programmed with these instructions, to execute the methods. These machine-executable instructions may be stored on one or more machine-readable media, such as optical discs or other types of optical disks, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Additionally, these methods may also be executed through a combination of hardware and software.

Claims

1. A vertical cell access array transistor (VCAAT), comprising: one or more bit lines arranged along a first horizontal direction; one or more word lines arranged along a second horizontal direction; one or more channels extending in a vertical direction that is substantially orthogonal to the first and second horizontal directions, such that the one or more bit lines intersect source / drain regions of the one or more channels and the one or more word lines intersect gate regions of the one or more channels; wherein the source / drain regions comprise a first section adjacent to a source / drain junction and a second section adjacent to a channel body, wherein a doping concentration of the first section is greater than a doping concentration of the second section.

2. The VCAAT of claim 1, wherein the doping concentration of the source / drain regions exhibits a Gaussian (normal) distribution with a peak concentration located substantially at the source / drain junction.

3. The VCAAT of claim 1, wherein the doping concentration of the first section is greater than or about 2 times the doping concentration of the second section.

4. The vertical cell array transistor (VCAAT) of claim 1, wherein the doping concentration of the first section is greater than 1 x 1018 cm 19 3 −3 .

5. The vertical cell array transistor (VCAAT) of claim 4, wherein the doping concentration of the first section is greater than 4 x 10 19 cm −3 -2.

6. The vertical cell array transistor (VCAAT) of claim 1, wherein the doping concentration of the second section is less than or about 1 x 10 19 cm −3 .

7. The VCAAT of claim 1, wherein the channel further comprises one or more P-type doped regions.

8. The VCAAT of claim 7, wherein the channel comprises a height extending between the source / drain region and a second source / drain region, wherein the one or more P-type doped regions are formed at a height of about 20% to about 80% of the height of the channel height.

9. The vertical cell array transistor (VCAAT) of claim 7, wherein the one or more P-type doped regions comprise a doping concentration greater than or about 5 x 1018 cm-3 to about 1 x 1020 cm-3. 16 cm −3 -3. 20 cm −3 -3.

10. The VCAAT of claim 7, wherein the channel comprises a height extending between the source / drain region and a second source / drain region, wherein the one or more P-type doped regions comprise a thickness of about 5% to about 30% of the height of the channel height.

11. A vertical cell access array transistor (VCAAT), comprising: a plurality of bit lines arranged along a first horizontal direction; a plurality of word lines arranged along a second horizontal direction; a plurality of channels extending in a vertical direction from a first source / drain region to a second source / drain region, the vertical direction being substantially orthogonal to the first and second horizontal directions, such that the plurality of bit lines intersect the first source / drain region and / or the second source / drain region of the plurality of channels and the plurality of word lines intersect gate regions of the plurality of channels; wherein at least a portion of the plurality of channels comprise one or more P-type doped regions disposed between the first source / drain region and the second source / drain region.

12. The vertical cell array transistor (VCAAT) of claim 11, wherein the channel comprises a height extending between the first source / drain region and the second source / drain region, wherein the one or more P-type doped regions are formed at a height of about 20% to about 80% of the height of the channel.

13. The vertical cell array transistor (VCAAT) of claim 11, further comprising at least a second P-type doped region of the one or more P-type doped regions.

14. The vertical cell array transistor (VCAAT) of claim 13, wherein the one or more P-type doped regions comprise a doping concentration greater than or about 5 x 10 16 cm −3 to about 1 x 10 20 cm −3 .

15. The vertical cell array transistor (VCAAT) of claim 11, wherein the channel comprises a height extending between the first source / drain region and the second source / drain region, wherein the one or more P-type doped regions comprise a thickness of about 5% to about 30% of the height of the channel.

16. A method of forming a vertical cell array transistor (VCAAT), the method comprising the steps of: etching a substrate to form one or more shallow trench isolations and a plurality of vertically extending channels; contacting one or more channels of the plurality of vertically extending channels with one or more ion implants to form a first source / drain region; forming a P-type doped region along one or more channels of the plurality of vertically extending channels; and forming a second source / drain region; wherein the first source / drain region comprises a first section adjacent to a source / drain junction and a second section adjacent to a channel body, wherein a doping concentration of the first section is greater than a doping concentration of the second section.

17. The method of claim 16, wherein the P-type doped region is formed using a second ion implant.

18. The method of claim 17, comprising the steps of: annealing the one or more ion implants and / or the second ion implant.

19. The method of claim 16, comprising the steps of: etching a portion of the one or more channels of the plurality of channels and forming the P-type doped region within the etched portion.

20. The method of claim 19, wherein the forming step comprises the step of epitaxially growing the P-type doped region.

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