Semiconductor device, manufacturing method thereof and electronic device

Abstract

The semiconductor device, preparation method thereof, and electronic device disclosed herein include an N-drift layer; an N+ substrate located on one side of the N-drift layer; a trench penetrating the N+ substrate; an N-buffer layer located on the side of the trench close to the N-drift layer; a P+ anode wrapped by the N-buffer layer on the side of the trench close to the N-drift layer; an anode conductive layer in contact with a surface of the P+ anode away from the N-drift layer within the trench and in contact with a surface of the N+ substrate away from the N-drift layer outside the trench; an N-layer in contact with a surface of the N+ substrate facing the N-drift layer and a surface of the N-drift layer facing the N+ substrate, wherein the thickness of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-drift layer is T NL Greater than or equal to 0, and at least in T NL When it is equal to 0, the doping concentration of the N-layer is less than that of the N-drift layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Art

[0002] Reverse-conducting power devices achieve reverse current capability by integrating a freewheeling diode with a bipolar device on a single chip. This not only reduces the parasitic inductance and resistance caused by conventional external parallel diodes, but also reduces terminal area, thereby increasing device power density, improving device performance, and reducing system size. However, conventional reverse-conducting devices, such as reverse-conducting IGBTs, implement reverse conduction by introducing an N+ collector region at the device collector, short-circuiting the P+ collector region. This creates a PiN diode structure within the device. However, the presence of the N+ collector region causes the device to initially enter unipolar conduction mode during forward conduction. As the anode voltage gradually increases, the P+ collector region gradually becomes conductive, and the device enters bipolar conduction mode. The transition from unipolar to bipolar conduction mode can easily lead to a sharp drop in device on-resistance and a snapback in the device collector voltage. This can lead to uneven current distribution within the device and hinder parallel connection, necessitating further optimization and improvement. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device, to improve the voltage rebound phenomenon existing in the prior art.

[0004] The semiconductor device, its manufacturing method and electronic device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a semiconductor device, comprising:

[0006] N-drift layer;

[0007] An N+ substrate, located on one side of the N-drift layer;

[0008] A trench extending through the N+ substrate;

[0009] An N-buffer layer is located on a side of the trench close to the N-drift layer;

[0010] A P+ anode, wrapped by the N-buffer layer on a side of the trench close to the N-drift layer;

[0011] an anode conductive layer, contacting a surface of the P+ anode away from the N-drift layer within the trench, and contacting a surface of the N+ substrate away from the N-drift layer outside the trench;

[0012] An N-layer is in contact with a surface of the N+ substrate facing the N-drift layer and a surface of the N-drift layer facing the N+ substrate, and a thickness T of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-drift layer is NL Greater than or equal to 0, and at least in T NL When it is equal to 0, the doping concentration of the N-layer is less than the doping concentration of the N-drift layer.

[0013] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N-buffer layer is wrapped by the N-layer.

[0014] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N-buffer layer is wrapped by the N-drift layer, T NL Greater than 0.

[0015] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the surface of the N-buffer layer away from the trench contacts the N-drift layer, and the side of the N-buffer layer contacts the N-layer; or, the surface and part of the side of the N-buffer layer away from the trench are embedded in the N-drift layer, and the non-embedded side contacts the N-layer.

[0016] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the trench extends into the N-layer, T NL Greater than 0.

[0017] In some embodiments, the semiconductor device provided in the embodiments of the present disclosure further includes an anode dielectric layer disposed in the trench, and the N-layer and the anode conductive layer in the trench are separated by the anode dielectric layer.

[0018] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N+ substrate is separated from the anode conductive layer in the trench by the anode dielectric layer.

[0019] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N-layer is in contact with the anode conductive layer in the trench.

[0020] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the P+ anode and the N-buffer layer are further disposed between the side surface of the trench and the N-layer.

[0021] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N-buffer layer and the P+ anode are in contact with the N+ substrate outside the trench.

[0022] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N+ substrate is in contact with the anode conductive layer in the trench.

[0023] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the trench is strip-shaped, and orthographic projections of a plurality of strip-shaped trenches on the N-drift layer are arranged side by side.

[0024] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, an orthographic projection of the trench on the N-drift layer is mesh-shaped.

[0025] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the trench is closed, and a plurality of closed trenches are concentrically arranged on the orthographic projection of the N-drift layer.

[0026] In some embodiments, the above-mentioned semiconductor device provided by the embodiments of the present disclosure further includes a P-type well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer, wherein the P-type well region is wrapped by the N-drift layer, the N+ cathode region and the P+ cathode region are arranged in the P-type well region, the cathode conductive layer is in contact with the N+ cathode region and the P+ cathode region, the gate dielectric layer is in contact with the N+ cathode region, the P-type well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer from the cathode conductive layer.

[0027] On the other hand, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned semiconductor device, comprising:

[0028] Providing an N+ substrate;

[0029] epitaxially growing an N-layer and an N-drift layer in sequence on the N+ substrate;

[0030] After thinning the N+ substrate to a target thickness, forming a first hard mask on the back side of the N+ substrate, and then selectively etching to form a trench penetrating the N+ substrate;

[0031] Keeping the first hard mask in a state, implanting N-type impurities on the back side of the N+ substrate to form an N-buffer layer at the bottom of the trench;

[0032] Depositing a second hard mask on the side where the first hard mask is located, and etching the second hard mask using a reactive ion etching method, leaving only the second hard mask on the side of the trench;

[0033] Implanting P-type impurities on the back side of the N+ substrate to form a P+ anode wrapped by the N- buffer layer;

[0034] The first hard mask and the second hard mask are removed by stripping, and annealing is performed to activate the implanted ions and repair lattice damage.

[0035] On the other hand, an embodiment of the present disclosure provides an electronic device, including the above-mentioned semiconductor device provided by an embodiment of the present disclosure.

[0036] The beneficial effects of the present disclosure are as follows:

[0037] The semiconductor device, preparation method thereof, and electronic device provided by the embodiments of the present disclosure include an N-drift layer; an N+ substrate located on one side of the N-drift layer; a trench penetrating the N+ substrate; an N-buffer layer located on the side of the trench close to the N-drift layer; a P+ anode wrapped by the N-buffer layer on the side of the trench close to the N-drift layer; an anode conductive layer in contact with a surface of the P+ anode away from the N-drift layer within the trench and in contact with a surface of the N+ substrate away from the N-drift layer outside the trench; an N-layer in contact with a surface of the N+ substrate facing the N-drift layer and a surface of the N-drift layer facing the N+ substrate; a T-type contact between the bottom surface of the N-layer and the surface of the N+ substrate facing the N-drift layer. NL The thickness is greater than or equal to 0, and at least T NL When it is equal to 0, the doping concentration of the N-layer is less than that of the N-drift layer. The doping concentration of the N-layer is lower than that of the N-drift layer, thereby increasing the resistance from the N-buffer layer on the P+ anode to the N+ substrate. Therefore, under the same forward conduction current, the potential difference between the N-buffer layer on the P+ anode and the N+ substrate is larger, which makes the PN junction of the P+ anode / N-buffer layer of the present disclosure easier to turn on, which is beneficial to suppressing the voltage rebound phenomenon. The N-layer is thickened in the vertical direction (i.e., T NL greater than 0) further increases the resistance between the N-buffer layer on the P+ anode and the N+ substrate, making it easier for the P+ anode / N-layer to turn on, and the voltage rebound phenomenon can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0039] Figure 2 for Figure 1 The schematic diagram of the semiconductor device for improving voltage rebound is shown;

[0040] Figure 3 for Figure 1 Equivalent circuit diagram of the semiconductor device shown;

[0041] Figure 4 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0042] Figure 5A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0043] Figure 6 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0044] Figure 7 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0045] Figure 8 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0046] Figure 9 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0047] Figure 10 A schematic diagram of groove distribution provided in an embodiment of the present disclosure;

[0048] Figure 11 A schematic diagram of another groove distribution provided in an embodiment of the present disclosure;

[0049] Figure 12 A schematic diagram of another groove distribution provided in an embodiment of the present disclosure;

[0050] Figure 13 for Figure 1 A schematic diagram of the structure of a semiconductor device during the preparation process is shown;

[0051] Figure 14 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0052] Figure 15 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0053] Figure 16 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0054] Figure 17 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0055] Figure 18 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0056] Figure 19 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0057] Figure 20 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0058] Figure 21 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0059] Figure 22 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0060] Figure 23 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0061] Figure 24 for Figure 1 Another structural schematic diagram of a semiconductor device during the preparation process is shown. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0063] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0064] The present disclosure provides a semiconductor device that can be fabricated based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc., through processes such as epitaxy and ion implantation. Figure 1As shown, the semiconductor device provided by the present disclosure may include: an N-drift layer 101, an N+ substrate 102, an N-buffer layer 103, a P+ anode 104, an anode conductive layer 105, an N-layer 106 and a trench V; wherein the N+ substrate 102 is located on one side of the N-drift layer 101; the trench V penetrates the N+ substrate 102, and optionally, the trench V may only penetrate the N+ substrate 102, or may extend into the N-layer 106 while penetrating the N+ substrate 102; the N-buffer layer 103 is located on the side of the trench V close to the N-drift layer 101; the P+ anode 104 is located on the side of the trench V close to the N-drift layer 105; One side of the N-drift layer 101 is wrapped by the N-buffer layer 103, that is, the N-buffer layer 103 is in contact with the upper surface and side surface of the P+ anode 104; the anode conductive layer 105 is in contact with the surface of the P+ anode 104 away from the N-drift layer 101 in the trench V, and is in contact with the surface of the N+ substrate 102 away from the N-drift layer 101 outside the trench V. The anode conductive layer 105 can be led out as the anode of the device; the N-layer 106 is in contact with the surface of the N+ substrate 102 facing the N-drift layer 101, and the surface of the N-drift layer 101 facing the N+ substrate 102. The N-layer 106 can also wrap the N-buffer layer 103. In some embodiments, it can also be provided that the N-drift layer 101 wraps the N-buffer layer 103 (such as Figure 4 Alternatively, the surface of the N-buffer layer 103 away from the trench V may be in contact with the N-drift layer 101, and the side surface of the N-buffer layer 103 may be in contact with the N-layer 106 (as shown). Figure 5 Alternatively, the N-buffer layer 103 is away from the surface and part of the side of the trench V and is embedded in the N-drift layer 101, and the side of the N-buffer layer 103 not embedded in the N-drift layer 101 is in contact with the N-layer 106 (as shown in FIG. Figure 6 As shown). The thickness T of the N-layer 106 between the bottom surface of the trench V and the surface of the N+ substrate 102 facing the N-drift layer 101 is NL Can be greater than or equal to 0, and at least in T NL When ρ is equal to 0, the doping concentration of the N-layer 106 is lower than the doping concentration of the N-drift layer 101 .

[0065] Continue to see Figure 1It can be seen that the semiconductor device of the present disclosure may further include: a P-type well region 107 , an N+ cathode region 108 , a P+ cathode region 109 , a cathode conductive layer 110 , a gate dielectric layer 111 , a gate conductive layer 112 , and an isolation dielectric layer 113 . Among them, the P-type well region 107 is located in the N-drift layer 101, the N+ cathode region 108 is located within the P-type well region 107, the P+ cathode region 109 contacts the P-type well region 107 and contacts the N+ cathode region 108, the cathode conductive layer 110 contacts both the N+ cathode region 108 and the P+ cathode region 109, the lower surface of the gate dielectric layer 111 contacts the upper surfaces of the P-type well region 107, the upper surfaces of the N+ cathode region 108, and the upper surface of the N-drift layer 101, and the gate conductive layer 112 is located on the upper surface of the gate dielectric layer 111. The upper surface and side surfaces of the gate conductive layer 112 contact the isolation dielectric layer 113, and the upper surface and side surfaces of the isolation dielectric layer 113 contact the cathode conductive layer 110. The isolation dielectric layer 113 and the gate dielectric layer 111 completely enclose the gate conductive layer 112. The gate conductive layer 112 is extended to form the device gate, and the cathode conductive layer 110 is extended to form the device cathode.

[0066] Figure 3 for Figure 1 The equivalent circuit diagram of the semiconductor device shown in FIG. 1 shows that the parasitic resistance R between the P+ anode 104 and the N+ substrate 102 is PN It will affect the switching of the device from unipolar conduction to bipolar conduction, and increase the parasitic resistance R PN It can make the device easier to enter the bipolar conduction mode. Device working principle: When the device cathode is connected to a low potential and the device anode is connected to a high potential, when the gate voltage is changed from 0 potential or negative potential to positive potential, the surface of the P-type well region 107 under the gate dielectric layer 111 is inverted to form an electron channel. The device first works in a unipolar forward conduction mode. Electrons pass through the electron channel, N-drift layer 101, N-layer 106, N-buffer layer 103 in sequence from the N+ cathode region 108, and finally enter the N+ substrate 102. The N-layer 106 is a high-resistance region with a doping concentration lower than that of the N-drift layer 101, which increases the parasitic resistance R from the N-buffer layer 103 on the P+ anode 104 to the N+ substrate 102. PN ;in addition, Figure 2 T NL When it is greater than 0, it increases Figure 2 The distance from point B to point A1 or A2 shown above makes the corresponding parasitic resistance R PN Further increase. Under the same current, the parasitic resistance R PN The larger the parasitic resistance R PN Since the N+ substrate 102 and the P+ anode 104 have the same potential, the parasitic resistance R from point B to point A1 or from point B to point A2 is PNThe larger the upper voltage drop, the greater the voltage difference between the P+ anode 104 and the N-buffer layer 103 near point B, making it easier to reach the turn-on voltage of the PN junction of the P+ anode 104 / N-buffer layer 103, thereby turning on the PN junction and entering the device into bipolar conduction mode. Thus, by increasing the longitudinal distance between the N+ substrate 102 and the P+ anode 104 and / or reducing the doping concentration of the N-layer 106, the present disclosure can make it easier for the device to transition from unipolar conduction mode to bipolar conduction mode, thereby effectively improving voltage rebound.

[0067] In some embodiments, Figure 7 Another semiconductor device structure provided by the embodiment of the present disclosure is given. Figure 1 and Figure 7 As shown, the semiconductor device provided by the embodiment of the present disclosure may further include an anode dielectric layer 114 provided in the trench V. The N- layer 106 and the anode conductive layer 105 in the trench V may be separated by the anode dielectric layer 114. The N+ substrate 102 may be separated from the anode conductive layer 105 in the trench V by the anode dielectric layer 114 (as shown in FIG. Figure 1 Alternatively, the N+ substrate 102 contacts the anode conductive layer 105 in the trench V (as shown in FIG. Figure 7 As shown). Since the doping concentration of the N+ substrate 102 is often very high, the anode conductive layer 105 contacts the side of the N+ substrate 102, which increases the parasitic resistance R from the N+ substrate 102 to the N- buffer layer 103 above the P+ anode 104. PN The impact is small, in other words, Figure 1 and Figure 7 The two embodiments have comparable improvement effects on voltage rebound.

[0068] In some embodiments, Figure 8 Another structural diagram of the semiconductor device provided by the embodiment of the present disclosure is given. Figure 8 As shown, in the semiconductor device provided by the embodiment of the present disclosure, the anode dielectric layer 114 may not be provided. In this case, both the N-layer 106 and the N+ substrate 102 may be in contact with the anode conductive layer 105 in the trench V. Since the anode conductive layer 105 is in direct contact with the N-layer 106, the parasitic resistance R from the N+ substrate 102 to the N-buffer layer 103 above the P+ anode 104 is reduced. PN , the voltage rebound suppression effect is relatively Figure 1 The embodiment shown is inferior.

[0069] In some embodiments, Figure 9 Another structural diagram of the semiconductor device provided by the embodiment of the present disclosure is given. Figure 9As shown, in the semiconductor device provided by the embodiment of the present disclosure, the P+ anode 104 and the N-buffer layer 103 can also be provided between the side of the trench V and the N-layer 106, and the N-buffer layer 103 and the P+ anode 104 are in contact with the N+ substrate 102 outside the trench V. In other words, the anode conductive layer 105 is not in contact with the N-layer 106, and the two are separated by the P+ anode 104 and the N-buffer layer 103. Figure 1 Compared with the embodiment shown, Figure 9 The P+ anode region 104 of the illustrated embodiment has a large area and a relatively higher injection efficiency.

[0070] It should be understood that in some embodiments, the N-buffer layer 103 and the P+ anode 104 may also extend downward to cover part of the side surface of the trench V, so that a portion of the side surface of the anode conductive layer 105 close to the N-drift layer 101 is separated from the N-layer 106 by the P+ anode 104 and the N-buffer layer 103, and another portion of the side surface of the anode conductive layer 105 close to the N+ substrate 102 is in contact with the N-layer 106, which is equivalent to Figure 7 The embodiment shown and Figure 9 In this embodiment, it is still possible to ensure Figure 9 The embodiment shown has a large area of ​​the P+ anode region 104 and a high injection efficiency. At the same time, since only part of the side of the anode conductive layer 105 is directly in contact with the N- layer 106, compared to Figure 7 The embodiment shown increases the parasitic resistance R from the N+ substrate 102 to the N- buffer layer 103 above the P+ anode 104. PN , the voltage rebound suppression effect is relatively Figure 7 The embodiment shown is better.

[0071] In some embodiments, the P-type well region 107, P+ cathode region 109, N+ cathode region 108, and cathode conductive layer 110 disclosed herein may belong to the cathode region, the gate dielectric layer 111, the gate conductive layer 112, and the isolation dielectric layer 113 may belong to the gate region, the N-drift layer 101 may belong to the drift region, and the N+ substrate 102, the N-buffer layer 103, the P+ anode 104, the N-layer 106, the anode conductive layer 105, and the anode dielectric layer 114 (optional) may belong to the anode region. Figure 1 、 Figures 4 to 9 The diagram shows a drift region, a cathode region, and a gate region disposed on an anode region. In some embodiments, multiple drift regions, cathode regions, and gate regions may be disposed on an anode region, depending on process capabilities and required device performance. The N-drift layers 101 of adjacent drift regions are integrally disposed, as are adjacent P-type well regions 107, adjacent P+ cathode regions 109, and cathode conductive layers 110 in adjacent cathode regions. Adjacent gate regions are separated by cathode conductive layers 110.

[0072] In some embodiments, as Figure 10 As shown, the trench V can be strip-shaped, and the orthographic projections of multiple strip-shaped trenches V on the N-drift layer 101 can be arranged side by side. The transverse cross-sectional structure of any trench V (for example, the cross-sectional structure along the II' line) can refer to Figure 1 、 Figures 4 to 9 , I will not go into details here.

[0073] In some embodiments, as Figure 11 As shown, the orthographic projection of the trench V of the present disclosure on the N-drift layer 101 can also be a mesh, and the shape defined by the mesh trench V can be Figure 11 The square shown may also be circular or other shapes, which are not specifically limited in the present disclosure; and the cross-sectional views on the horizontal and vertical grid lines of the groove V (such as the positions shown by the II-II' line and the III-III' line) can all be referred to. Figure 1 、 Figures 4 to 9 , I will not go into details here.

[0074] In some embodiments, as Figure 12 As shown, the trench V of the present disclosure can also be closed (for example, a square, a circle, or other closed shapes), and the orthographic projections of multiple closed trenches V on the N-drift layer 101 can be concentrically arranged; the cross-sectional view of any side of the trench V (for example, the cross-sectional view at the IV-IV' line and the VI-VI' line) can refer to Figure 1 、 Figures 4 to 9 , I will not go into details here.

[0075] As can be seen from the above, the doping concentration of the N-layer 106 in the present disclosure is lower than that of the N-drift layer 101, thereby increasing the parasitic resistance from the N-buffer layer 103 on the P+ anode 104 to the N+ substrate 102. Therefore, under the same forward conduction current, the potential difference between the N-buffer layer 103 on the P+ anode 104 and the N+ substrate 102 is greater, which makes it easier to turn on the PN junction of the P+ anode 104 / N-buffer layer 103, which is beneficial for suppressing voltage rebound. The vertical thickening of the N-layer 106 further increases the parasitic resistance between the N-buffer layer 103 on the P+ anode 104 and the N+ substrate 102, thereby making it easier to turn on the P+ anode 104 / N-layer 106, further improving the voltage rebound phenomenon, and further reducing the device cell size. It is best that the anode conductive layer 105 and the N-layer 106 do not contact each other, but are separated by the anode dielectric layer 114. This can maximize the parasitic resistance between the N-buffer layer 103 on the P+ anode 104 and the N+ substrate 102. If contact is made, the contact can be a Schottky contact or an ohmic contact. Among them, the Schottky contact is more effective in improving the voltage rebound phenomenon than the ohmic contact.

[0076] Based on the same inventive concept, the present disclosure also provides a method for preparing the semiconductor device, which may include the following steps:

[0077] Providing an N+ substrate;

[0078] Epitaxially growing an N-layer and an N-drift layer on an N+ substrate in sequence;

[0079] After thinning the N+ substrate to a target thickness, forming a first hard mask on the back side of the N+ substrate, and then selectively etching to form a trench penetrating the N+ substrate;

[0080] Keeping the first hard mask in the state, N-type impurities are implanted on the back side of the N+ substrate to form an N- buffer layer at the bottom of the trench;

[0081] Depositing a second hard mask on the side where the first hard mask is located, and etching the second hard mask by reactive ion etching to leave only the second hard mask on the side of the trench;

[0082] P-type impurities are injected into the back of the N+ substrate to form a P+ anode wrapped by an N- buffer layer;

[0083] The first hard mask and the second hard mask are removed by stripping, and annealing is performed to activate the implanted ions and repair lattice damage.

[0084] In order to better understand the technical solution of the preparation method provided by the present disclosure, the following Figure 1 The fabrication of the semiconductor device shown is described in detail as an example.

[0085] In some embodiments, the present disclosure also provides Figure 1 The manufacturing process of the semiconductor device shown may specifically include the following steps:

[0086] (1) If Figure 13 As shown, an N- layer 106 is epitaxially grown on an N+ substrate 102 .

[0087] (2) If Figure 14 As shown, an N-drift layer 101 is grown on the surface of the N-layer 106 .

[0088] (3) If Figure 15 As shown, a P-type well region 107 , an N+ cathode region 108 , and a P+ cathode region 109 are selectively implanted on the surface of the N-drift layer 101 using a hard mask and ion implantation.

[0089] (4) If Figure 16 As shown, after the N+ substrate 102 is thinned to a target thickness, a first hard mask HM1 is formed on the back side of the N+ substrate 102 , and then selective etching is performed, and the N+ substrate 102 is etched by dry etching until at least the N- layer 106 is exposed.

[0090] (5) If Figure 17 As shown, the first hard mask HM1 is maintained in a state, and N-type impurities are implanted into the back surface of the N+ substrate 102 to form an N- buffer layer 103 .

[0091] (6) If Figure 18 As shown, a second hard mask HM2 is deposited on the back side of the device.

[0092] (7) If Figure 19 As shown, reactive ion etching is used on the back of the device to etch away the second hard mask HM2 on the lower surface of the N+ substrate 102 and the middle area of ​​the lower surface of the N- buffer layer 103, leaving only the second hard mask HM2 on the side of the trench V.

[0093] (8) If Figure 20 As shown, P-type impurities are implanted into the back side of the N+ substrate 102 to form a P+ anode 104 .

[0094] (9) Figure 21 As shown, the first hard mask HM1 and the second hard mask HM2 are stripped, and then an annealing process is performed to activate the implanted ions and repair lattice damage.

[0095] (10) Figure 22 As shown, the chip surface structure is formed: including a gate dielectric layer 111, a gate conductive layer 112, an isolation dielectric layer 113, a source contact hole, a gate contact hole (not shown in the figure), a cathode conductive layer 110, and a gate lead-out layer (not shown in the figure).

[0096] (11) Figure 23 As shown, an anode dielectric layer 114 is deposited on the back side of the device.

[0097] (12) Figure 24 As shown, reactive ion etching is used on the back of the device to etch away the anode dielectric layer 114 in the middle area of ​​the lower surface of the N+ substrate 102 and the lower surface of the P+ anode 104, leaving only the anode dielectric layer 114 on the side of the trench V.

[0098] (13) Figure 1 As shown, the anode conductive layer 105 is filled and formed on the back side of the device by using a sputtering method.

[0099] So far, it is completed Figure 1 Preparation of the semiconductor device shown.

[0100] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device including the aforementioned semiconductor device provided in embodiments of the present disclosure. Because the principles underlying the problems solved by the electronic device are similar to those of the aforementioned semiconductor device, the implementation of the electronic device provided in embodiments of the present disclosure can refer to the implementation of the aforementioned semiconductor device provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0101] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, and household appliances. Of course, the electronic devices provided by the present disclosure may include not only semiconductor devices but also other structures. For example, when the electronic device is a radar, it may also include structures such as a transmitter, antenna, and receiver; when the electronic device is a mixer, it may also include structures such as input ports, output ports, and other structures.

[0102] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0103] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A semiconductor device, characterized in that: include: N-drift layer; An N+ substrate, located on one side of the N-drift layer; A trench extending through the N+ substrate; An N-buffer layer is located on a side of the trench close to the N-drift layer; A P+ anode, wrapped by the N-buffer layer on a side of the trench close to the N-drift layer; an anode conductive layer, contacting a surface of the P+ anode away from the N-drift layer within the trench, and contacting a surface of the N+ substrate away from the N-drift layer outside the trench; N-layer, and the surface of the N+ substrate facing the N-drift layer, and the surface of the N-drift layer facing the N+ substrate; the thickness T of the N-layer between the plane where the bottom of the trench is located and the surface of the N+ substrate facing the N-drift layer NL Greater than or equal to 0, and at least in T NL When it is equal to 0, the doping concentration of the N-layer is less than the doping concentration of the N-drift layer.

2. The semiconductor device according to claim 1, wherein The N-buffer layer is wrapped by the N-layer.

3. The semiconductor device according to claim 1, wherein The N-buffer layer is wrapped by the N-drift layer, T NL Greater than 0.

4. The semiconductor device according to claim 1, wherein The surface of the N-buffer layer away from the trench contacts the N-drift layer, and the side surface of the N-buffer layer contacts the N-layer; alternatively, the surface and part of the side surface of the N-buffer layer away from the trench are embedded in the N-drift layer, and the non-embedded side surface contacts the N-layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The trench extends into the N-layer, T NL Greater than 0.

6. The semiconductor device according to claim 5, wherein The invention also includes an anode dielectric layer disposed in the trench, wherein the N-layer and the anode conductive layer in the trench are separated by the anode dielectric layer.

7. The semiconductor device according to claim 6, wherein The N+ substrate is separated from the anode conductive layer in the trench by the anode dielectric layer.

8. The semiconductor device according to claim 5, wherein The N-layer contacts the anode conductive layer in the trench.

9. The semiconductor device according to claim 5, wherein The P+ anode and the N-buffer layer are also disposed between the side surfaces of the trench and the N-layer.

10. The semiconductor device according to claim 9, wherein The N-buffer layer and the P+ anode are in contact with the N+ substrate outside the trench.

11. The semiconductor device according to any one of claims 6, 8 to 10, wherein: The N+ substrate contacts the anode conductive layer in the trench.

12. The semiconductor device according to any one of claims 1 to 4 and 6 to 10, wherein: The trenches are strip-shaped, and the orthographic projections of a plurality of strip-shaped trenches on the N-drift layer are arranged side by side.

13. The semiconductor device according to any one of claims 1 to 4 and 6 to 10, wherein: The orthographic projection of the trench on the N-drift layer is in a mesh shape.

14. The semiconductor device according to any one of claims 1 to 4 and 6 to 10, wherein: The trench is closed, and a plurality of closed trenches are concentrically arranged on the orthographic projection of the N-drift layer.

15. The semiconductor device according to any one of claims 1 to 4 and 6 to 10, wherein: It also includes a P-type well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer, wherein the P-type well region is wrapped by the N-drift layer, the N+ cathode region and the P+ cathode region are arranged in the P-type well region, the cathode conductive layer is in contact with the N+ cathode region and the P+ cathode region, the gate dielectric layer is in contact with the N+ cathode region, the P-type well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer from the cathode conductive layer.

16. A method for preparing a semiconductor device according to any one of claims 1 to 15, characterized in that: include: Providing an N+ substrate; epitaxially growing an N-layer and an N-drift layer in sequence on the N+ substrate; After thinning the N+ substrate to a target thickness, forming a first hard mask on the back side of the N+ substrate, and then selectively etching to form a trench penetrating the N+ substrate; Keeping the first hard mask in a state, implanting N-type impurities on the back side of the N+ substrate to form an N-buffer layer at the bottom of the trench; Depositing a second hard mask on the side where the first hard mask is located, and etching the second hard mask using a reactive ion etching method, leaving only the second hard mask on the side of the trench; Implanting P-type impurities on the back side of the N+ substrate to form a P+ anode wrapped by the N- buffer layer; The first hard mask and the second hard mask are removed by stripping, and annealing is performed to activate the implanted ions and repair lattice damage.

17. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 15.

Images