Semiconductor device, manufacturing method thereof and electronic device

Abstract

The semiconductor device, preparation method thereof, and electronic device disclosed herein include an N-drift layer; an N+ substrate on one side of the N-drift layer; a trench penetrating the N+ substrate; a surface of the N-drift layer facing the N+ substrate in contact with an N-buffer layer; a P+ anode on the side of the trench facing the N-buffer layer; an anode conductive layer in contact with a surface of the P+ anode away from the N-drift layer within the trench and in contact with a surface of the N+ substrate away from the N-drift layer outside the trench; an N-layer in contact with a surface of the N-buffer layer facing the N+ substrate and a surface of the N+ substrate facing the N-buffer layer; a thickness T of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-buffer layer. NL1 ≥0, and / or, the thickness T of the N-layer between the surface of the P+ anode facing the N-buffer layer and the surface of the N-buffer layer facing the P+ anode NL2 ≥0, at least in T NL1 、T NL2 When it is 0, the doping concentration of the N-layer is lower than that of the N-drift layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Art

[0002] Bipolar power semiconductor devices, such as IGBTs and GTOs, utilize both hole and electron carriers during conduction. The minority carrier concentration in the drift region is significantly higher than the drift region's doping concentration, resulting in a conductivity modulation effect in the drift region, significantly reducing the on-resistance. This characteristic makes bipolar power semiconductor devices widely used in applications requiring high voltage and high current. Conventional bipolar devices, such as IGBTs, lack reverse current capability due to the presence of a PN junction in their anode region. When a reverse bias voltage is applied between the anode and cathode, this PN junction enters a reverse-biased withstand state. Consequently, these devices often require an antiparallel freewheeling diode to conduct reverse current. Integrating a freewheeling diode with a bipolar device on a single chip not only reduces the parasitic inductance and resistance of the connecting leads, but also reduces terminal area, thereby increasing device power density, improving device performance, and reducing system size. To integrate the freewheeling diode within the bipolar device, reverse-conducting devices, such as reverse-conducting IGBTs and reverse-conducting GTOs, have been proposed. Conventional reverse-conducting IGBTs incorporate an N+ anode region at the anode of the device, short-circuiting the P+ anode region. This creates a PiN diode structure within the device, achieving freewheeling. However, the introduction of the N+ anode region makes conventional reverse-conducting devices susceptible to voltage snapback during forward conduction, and there is a serious conflict between their forward and reverse conduction characteristics, requiring further optimization and improvement. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and an electronic device, to improve the voltage rebound phenomenon existing in the prior art.

[0004] The semiconductor device, its manufacturing method and electronic device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a semiconductor device, comprising:

[0006] N-drift layer;

[0007] An N+ substrate, located on one side of the N-drift layer;

[0008] A trench extending through the N+ substrate;

[0009] An N-buffer layer, in contact with a surface of the N-drift layer facing the N+ substrate;

[0010] A P+ anode, located on a side of the trench facing the N-buffer layer;

[0011] an anode conductive layer, contacting a surface of the P+ anode away from the N-drift layer within the trench, and contacting a surface of the N+ substrate away from the N-drift layer outside the trench;

[0012] N-layer, in contact with the surface of the N-buffer layer facing the N+ substrate and the surface of the N+ substrate facing the N-buffer layer; the thickness T of the N-layer between the bottom surface of the trench and the surface of the N+ substrate facing the N-buffer layer NL1 is greater than or equal to 0, and / or the thickness T of the N-layer between the surface of the P+ anode facing the N-buffer layer and the surface of the N-buffer layer facing the P+ anode ... NL2 Greater than or equal to 0, at least in T NL1 and T NL2 When both are 0, the doping concentration of the N-layer is lower than the doping concentration of the N-drift layer.

[0013] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the surface of the N-buffer layer away from the N-drift layer is planar; the N-layer wraps the P+ anode, or the surface of the P+ anode facing the N-buffer layer contacts the N-buffer layer, and the side of the P+ anode contacts the N-layer.

[0014] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the P+ anode is embedded in the N-buffer layer toward the surface and part of the side surface of the N-buffer layer, and the non-embedded side surface is in contact with the N-layer.

[0015] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the trench extends into the N-layer, T NL1 Greater than 0.

[0016] In some embodiments, the semiconductor device provided in the embodiments of the present disclosure further includes an anode dielectric layer disposed in the trench, and the N-layer and the anode conductive layer in the trench are separated by the anode dielectric layer.

[0017] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N+ substrate is separated from the anode conductive layer in the trench by the anode dielectric layer.

[0018] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N-layer is in contact with the anode conductive layer in the trench.

[0019] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the P+ anode is further provided between the anode conductive layer and the N-layer on the sidewall of the trench.

[0020] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the P+ anode is further provided between the anode conductive layer on the sidewall of the trench and the N+ substrate.

[0021] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the N+ substrate is in contact with the anode conductive layer in the trench.

[0022] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the trench is strip-shaped, and orthographic projections of a plurality of strip-shaped trenches on the N-drift layer are arranged side by side.

[0023] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, an orthographic projection of the trench on the N-drift layer is mesh-shaped.

[0024] In some embodiments, in the semiconductor device provided by the embodiments of the present disclosure, the trench is closed, and a plurality of closed trenches are concentrically arranged on the orthographic projection of the N-drift layer.

[0025] In some embodiments, the above-mentioned semiconductor device provided by the embodiments of the present disclosure further includes a P-well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer, wherein the P-well region is wrapped by the N-drift layer, the N+ cathode region and the P+ cathode region are arranged in the P-well region, the cathode conductive layer is in contact with the N+ cathode region and the P+ cathode region, the gate dielectric layer is in contact with the N+ cathode region, the P-well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer from the cathode conductive layer.

[0026] On the other hand, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned semiconductor device, comprising:

[0027] Providing an N+ substrate;

[0028] Epitaxially growing an N-layer, an N-buffer layer and an N-drift layer in sequence on the N+ substrate;

[0029] After thinning the N+ substrate to a target thickness, forming a hard mask on the back side of the N+ substrate, and then selectively etching to form a trench penetrating the N+ substrate;

[0030] Keeping the hard mask in a state, implanting P-type impurities on the back side of the N+ substrate to form a P+ anode;

[0031] The hard mask is removed by stripping, and annealing is performed to activate the implanted ions and repair lattice damage.

[0032] On the other hand, an embodiment of the present disclosure provides an electronic device, including the above-mentioned semiconductor device provided by an embodiment of the present disclosure.

[0033] The beneficial effects of the present disclosure are as follows:

[0034] The semiconductor device, preparation method thereof, and electronic device provided by the embodiments of the present disclosure include an N-drift layer; an N+ substrate located on one side of the N-drift layer; a groove penetrating the N+ substrate; an N-buffer layer in contact with a surface of the N-drift layer facing the N+ substrate; a P+ anode located on the side of the groove facing the N-buffer layer; an anode conductive layer in contact with a surface of the P+ anode away from the N-drift layer within the groove, and in contact with a surface of the N+ substrate away from the N-drift layer outside the groove; an N-layer in contact with a surface of the N-buffer layer facing the N+ substrate and a surface of the N+ substrate facing the N-buffer layer; a thickness T of the N-layer between the bottom surface of the groove and the surface of the N+ substrate facing the N-buffer layer NL1 is greater than or equal to 0, and / or the thickness T of the N-layer between the surface of the P+ anode facing the N-buffer layer and the surface of the N-buffer layer facing the P+ anode is greater than or equal to 0, and / or the thickness T of the N-layer between the surface of the P+ anode facing the N-buffer layer NL2 Greater than or equal to 0, at least in T NL1 and T NL2 When it is equal to 0, the doping concentration of the N-layer is less than that of the N-drift layer. A low-doping concentration N-layer is introduced between the N-buffer layer and the N+ substrate, thereby increasing the parasitic resistance from the N-buffer layer to the N+ substrate, increasing the potential difference between the N-layer on the P+ anode surface and the N+ substrate, thereby making it easier to open the PN junction formed by the P+ anode / N-layer; the N-layer is thickened in the vertical direction (i.e., T NL1 and / or T NL2 greater than 0) can further increase the parasitic resistance between the N+ substrate and the N- buffer layer, and the voltage rebound phenomenon can be further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0036] Figure 2 for Figure 1 The schematic diagram of the semiconductor device for improving voltage rebound is shown;

[0037] Figure 3 for Figure 1 Equivalent circuit diagram of the semiconductor device shown;

[0038] Figure 4 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0039] Figure 5 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0040] Figure 6 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0041] Figure 7 Another structural schematic diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0042] Figure 8 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0043] Figure 9 A schematic diagram of another structure of a semiconductor device provided in an embodiment of the present disclosure;

[0044] Figure 10 A schematic diagram of groove distribution provided in an embodiment of the present disclosure;

[0045] Figure 11 A schematic diagram of another groove distribution provided in an embodiment of the present disclosure;

[0046] Figure 12 A schematic diagram of another groove distribution provided in an embodiment of the present disclosure;

[0047] Figure 13 for Figure 1 A schematic diagram of the structure of a semiconductor device during the preparation process is shown;

[0048] Figure 14 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0049] Figure 15 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0050] Figure 16 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0051] Figure 17 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0052] Figure 18 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0053] Figure 19 for Figure 1 Another structural schematic diagram of the semiconductor device during the manufacturing process is shown;

[0054] Figure 20 for Figure 1 Another structural schematic diagram of a semiconductor device during the preparation process is shown. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0056] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0057] The present disclosure provides a semiconductor device that can be fabricated based on semiconductor materials such as silicon, silicon carbide, gallium nitride, etc., through processes such as epitaxy and ion implantation. Figure 1As shown, the semiconductor device provided by the present disclosure may include: an N-drift layer 101, an N+ substrate 102, an N-buffer layer 103, a P+ anode 104, an anode conductive layer 105, an N-layer 106 and a trench V; wherein the N+ substrate 102 is located on one side of the N-drift layer 101; the trench V penetrates the N+ substrate 102, optionally, the trench V may only penetrate the N+ substrate 102, or may extend into the N-layer 106 while penetrating the N+ substrate 102; the N-buffer layer 103 and the N-drift layer 101 face each other. The surface of the N+ substrate 102 is in contact; the P+ anode 104 is on the side of the trench V facing the N-buffer layer 103; the anode conductive layer 105 is in contact with the surface of the P+ anode 104 away from the N-drift layer 101 inside the trench V, and is in contact with the surface of the N+ substrate 102 away from the N-drift layer 101 outside the trench V. The anode conductive layer 105 is led out to serve as the device anode; the N-layer 106 is in contact with the surface of the N-buffer layer 103 facing the N+ substrate 102, and the surface of the N+ substrate 102 facing the N-buffer layer 103; Figure 1 It can be seen that the N-layer 106 can also wrap the P+ anode 104 (ie, the N-layer 106 is in contact with the upper surface and side surfaces of the P+ anode); or Figure 4 As shown, the N-layer 106 contacts the side of the P+ anode 104, and the N-buffer layer 103 contacts the upper surface of the P+ anode 104; or Figure 5 As shown, the upper surface and part of the side surface of the P+ anode 104 are embedded in the N-buffer layer 103, and the side surface of the P+ anode 104 not embedded in the N-buffer layer 103 is in contact with the N-layer 106; the thickness T of the N-layer 106 between the surface of the P+ anode 104 away from the N-buffer layer 103 and the surface of the N+ substrate 102 facing the N-buffer layer 103 NL1 Greater than or equal to 0, T NL1 When it is greater than 0, the surface of the N+ substrate 102 facing the N- buffer layer 103 is only in contact with the N- layer 106, and T NL1 When it is equal to 0, the surface of the N+ substrate 102 facing the N-buffer layer 103 is in contact with the N-layer 106 and the P+ anode 104 at the same time; and / or, the thickness T of the N-layer 106 between the surface of the P+ anode 104 facing the N-buffer layer 103 and the surface of the N-buffer layer 103 facing the P+ anode 104 is NL2 Greater than or equal to 0, where T NL2 When it is greater than 0, the surface of the P+ anode 104 facing the N-buffer layer 103 contacts the N-layer 106, and T NL2 When T is equal to 0, the surface of the P+ anode 104 facing the N-buffer layer 103 contacts the N-buffer layer 103; at least when T NL1 and T NL2 When θ is equal to 0, the doping concentration of the N-layer 106 is lower than the doping concentration of the N-drift layer 101 .

[0058] Continue to see Figure 1 It can be seen that the semiconductor device of the present disclosure may further include: a P-type well region 107 , an N+ cathode region 108 , a P+ cathode region 109 , a cathode conductive layer 110 , a gate dielectric layer 111 , a gate conductive layer 112 , and an isolation dielectric layer 113 . Among them, the P-type well region 107 is located in the N-drift layer 101, the N+ cathode region 108 is located within the P-type well region 107, the P+ cathode region 109 contacts the P-type well region 107 and contacts the N+ cathode region 108, the cathode conductive layer 110 contacts both the N+ cathode region 108 and the P+ cathode region 109, the lower surface of the gate dielectric layer 111 contacts the upper surfaces of the P-type well region 107, the upper surfaces of the N+ cathode region 108, and the upper surface of the N-drift layer 101, and the gate conductive layer 112 is located on the upper surface of the gate dielectric layer 111. The upper surface and side surfaces of the gate conductive layer 112 contact the isolation dielectric layer 113, and the upper surface and side surfaces of the isolation dielectric layer 113 contact the cathode conductive layer 110. The isolation dielectric layer 113 and the gate dielectric layer 111 completely enclose the gate conductive layer 112. The gate conductive layer 112 is extended to form the device gate, and the cathode conductive layer 110 is extended to form the device cathode.

[0059] Figure 3 for Figure 1 The equivalent circuit diagram of the semiconductor device shown in FIG. 1 shows that the parasitic resistance R between the P+ anode 104 and the N+ substrate 102 is PN It will affect the switching of the device from unipolar conduction to bipolar conduction, and increase the parasitic resistance R PN It can make the device easier to enter the bipolar conduction mode. Device working principle: When the cathode of the device is connected to a low potential and the anode of the device is connected to a high potential, when the gate voltage is changed from 0 potential or negative potential to positive potential, the surface of the P-type well region 107 under the gate dielectric layer 111 is inverted to form an electron channel. The device first works in a unipolar forward conduction mode, and electrons pass through the electron channel, N-drift layer 101, N-buffer layer 103, N-layer 106 in sequence from the N+ cathode region 108, and finally enter the N+ substrate 102. Since the N-layer 106 is low-doped, it forms a Schottky contact or an ohmic contact with the anode conductive layer 105 with high contact resistance. Therefore, electrons tend to flow through the N+ substrate 102, the low contact resistance N+ substrate 102 / anode conductive layer 105 interface, and the anode conductive layer 105, rather than flowing through the high resistance N-layer 106 and the anode conductive layer 105 interface. In addition, T NL1 and / or T NL2 When it is greater than 0, it increases Figure 2 The distance from point B to point A1 or A2 is the corresponding parasitic resistance R PN Increase, parasitic resistance R under the same current PN The larger the parasitic resistance R PNSince the N+ substrate 102 and the P+ anode 104 have the same potential, the parasitic resistance R from point B to point A1 or from point B to point A2 is PN The larger the upper voltage drop, the greater the voltage difference between the P+ anode 104 and the N-layer 106 near point B, making it easier to reach the turn-on voltage of the PN junction formed by the P+ anode 104 / N-layer 106, thereby turning on the PN junction and causing the device to enter bipolar conduction mode. Therefore, the present disclosure improves the voltage rebound phenomenon by increasing the longitudinal distance between the N+ substrate 102 and the P+ anode 104 and / or reducing the doping concentration of the N-layer 106, making it easier for the device to transition from unipolar conduction mode to bipolar conduction mode.

[0060] In some embodiments, Figure 6 and Figure 7 Another semiconductor device structure provided by the embodiment of the present disclosure is given respectively. Figure 1 The N-layer 106 shown is in contact with the anode conductive layer 105 in the trench V. Figure 6 and Figure 7 As shown, the present disclosure may further include an anode dielectric layer 114 disposed within the trench V, and the N-layer 106 and the anode conductive layer 105 within the trench V may be separated by the anode dielectric layer 114. The anode conductive layer 105 is not in direct contact with the N-layer 106, thereby increasing the parasitic resistance from the N+ substrate 102 to the N-layer 106 directly above the center of the P+ anode 104, which is more conducive to mitigating voltage rebound.

[0061] Continue to see Figure 6 It can be seen that in the present disclosure, the N+ substrate 102 and the anode conductive layer 105 in the trench V can be separated by the anode dielectric layer 114. Alternatively, as Figure 1 and Figure 7 As shown, the N+ substrate 102 can also directly contact the anode conductive layer 105 in the trench V. Since the doping concentration of the N+ substrate 102 is often very high, the contact between the anode conductive layer 105 and the side of the N+ substrate 102 has a relatively small impact on the parasitic resistance from the N+ substrate 102 to the N- layer 106 above the P+ anode 104. In other words, whether the N+ substrate 102 is in direct contact with the anode conductive layer 105 in the trench V or separated by the anode dielectric layer 114, the improvement effect on voltage rebound is equivalent.

[0062] In some embodiments, Figure 8 and Figure 9 Another semiconductor device structure provided by the embodiment of the present disclosure is given respectively. Figure 8 and Figure 9 It can be seen that the P+ anode 104 can also be disposed between the anode conductive layer 105 and the N- layer 106 on the sidewall of the trench V. Figure 1 The embodiment shown, Figure 8 and Figure 9 The embodiment shown increases the area of ​​the P+ anode 104, which results in higher injection efficiency and better conduction characteristics. Figure 8 The N+ substrate 102 is in direct contact with the anode conductive layer 105 in the trench V. Figure 9 The N+ substrate 102 is separated from the anode conductive layer 105 on the sidewall of the trench V by the P+ anode 104. Figure 8 Compared with the embodiment shown, Figure 9 In the embodiment shown, the contact area between the anode conductive layer 105 and the N+ substrate 102 is narrower, thereby further increasing the parasitic resistance from the N+ substrate 102 to the N- layer 106 just above the center of the P+ anode 104, which is more conducive to alleviating voltage rebound.

[0063] In some embodiments, the P-type well region 107, N+ cathode region 108, P+ cathode region 109 and cathode conductive layer 110 disclosed herein may belong to the cathode region, the gate dielectric layer 111, gate conductive layer 112 and isolation dielectric layer 113 may belong to the gate region, the N-drift layer 101 may belong to the drift region, and the N+ substrate 102, N-buffer layer 103, P+ anode 104, anode conductive layer 105, N-layer 106, and anode dielectric layer 114 (optional) may belong to the anode region. Figure 1 、 Figures 4 to 9 The diagram shows a drift region, a cathode region, and a gate region disposed on an anode region. In some embodiments, multiple drift regions, cathode regions, and gate regions may be disposed on an anode region, depending on process capabilities and required device performance. The N-drift layers 101 of adjacent drift regions are integrally disposed, as are adjacent P-type well regions 107, adjacent P+ cathode regions 109, and cathode conductive layers 110 in adjacent cathode regions. Adjacent gate regions are separated by cathode conductive layers 110.

[0064] In some embodiments, as Figure 10 As shown, the trench V can be strip-shaped, and the orthographic projections of multiple strip-shaped trenches V on the N-drift layer 101 can be arranged side by side. The transverse cross-sectional structure of any trench V (for example, the cross-sectional structure along the II' line) can refer to Figure 1 、 Figures 4 to 9 , I will not go into details here.

[0065] In some embodiments, as Figure 11 As shown, the orthographic projection of the trench V of the present disclosure on the N-drift layer 101 can also be a mesh, and the shape defined by the mesh trench V can be Figure 11 The square shown may also be circular or other shapes, which are not specifically limited in the present disclosure; and the cross-sectional views on the horizontal and vertical grid lines of the groove V (such as the positions shown by the II-II' line and the III-III' line) can all be referred to. Figure 1 、 Figures 4 to 9 , I will not go into details here.

[0066] In some embodiments, as Figure 12 As shown, the trench V of the present disclosure can also be closed (for example, a square, a circle, or other closed shapes), and the orthographic projections of multiple closed trenches V on the N-drift layer 101 can be concentrically arranged; the cross-sectional view of any side of the trench V (for example, the cross-sectional view at the IV-IV' line and the VI-VI' line) can refer to Figure 1 、 Figures 4 to 9 , I will not go into details here.

[0067] From the above content, it can be seen that the present disclosure introduces a low-doping concentration N-layer 106 between the N-buffer layer 103 and the N+ substrate 102, thereby increasing the parasitic resistance from the N-buffer layer 103 to the N+ substrate 102, and increasing the potential difference between the N-layer 106 on the upper surface of the P+ anode 104 and the N+ substrate 102, thereby making it easier to turn on the P+ anode 104 / N-layer 106; the vertical thickening of the N-layer 106 can further increase the parasitic resistance between the N+ substrate 102 and the N-buffer layer 103, the voltage rebound phenomenon can be further improved, and the device cell size can be further reduced. The contact between the P+ anode 104 and the N-layer 106 can be a Schottky contact or an ohmic contact. If it is a Schottky contact, the improvement effect on the voltage rebound phenomenon will be better. It is best that the N- layer 106 does not contact the anode conductive layer 105, and can be blocked by the P+ anode 104 or the anode dielectric layer 114, so as to maximize the parasitic resistance between the N+ substrate 102 and the N- buffer layer 103, which is more conducive to improving the voltage rebound phenomenon.

[0068] Based on the same inventive concept, the present disclosure also provides a method for preparing the semiconductor device, which may include the following steps:

[0069] Providing an N+ substrate;

[0070] Epitaxially growing an N-layer, an N-buffer layer and an N-drift layer on an N+ substrate in sequence;

[0071] After thinning the N+ substrate to a target thickness, a hard mask is formed on the back of the N+ substrate, and then a trench penetrating the N+ substrate is formed by selective etching;

[0072] Keeping the hard mask in the state, P-type impurities are injected into the back of the N+ substrate to form a P+ anode;

[0073] The hard mask is removed by stripping, and annealing is performed to activate the implanted ions and repair lattice damage.

[0074] In order to better understand the technical solution of the preparation method provided by the present disclosure, the following Figure 1The fabrication of the semiconductor device shown is described in detail as an example.

[0075] In some embodiments, the present disclosure also provides Figure 1 The manufacturing process of the semiconductor device shown may specifically include the following steps:

[0076] (1) If Figure 13 As shown, an N- layer 106 is epitaxially grown on an N+ substrate 102 .

[0077] (2) If Figure 14 As shown, an N-buffer layer 103 and an N-drift layer 101 are epitaxially formed in sequence on the surface of the N-layer 106 .

[0078] (3) If Figure 15 As shown, a P-type well region 107 , an N+ cathode region 108 and a P+ cathode region 109 are selectively implanted on the surface of the N-drift region layer using a hard mask and ion implantation.

[0079] (4) If Figure 16 As shown, the N+ substrate 102 is thinned to a target thickness.

[0080] (5) If Figure 17 As shown, a hard mask HM is formed on the back side of the N+ substrate 102, and then selective etching is performed, and the N+ substrate 102 is etched by dry etching until at least the N- layer 106 is exposed.

[0081] (6) If Figure 18 As shown, the hard mask HM state is maintained, and P-type impurities are implanted into the back side of the N+ substrate 102 to form a P+ anode 104 .

[0082] (7) If Figure 19 As shown, the hard mask HM is stripped off and then annealed to activate the implanted ions and repair lattice damage.

[0083] (8) If Figure 20 As shown, the device surface structure is formed: including a gate dielectric layer 111, a gate conductive layer 112, an isolation dielectric layer 113, a source contact hole, and a gate contact hole (the gate contact hole is not shown in the figure), a cathode conductive layer 110 and a gate lead-out layer (not shown in the figure).

[0084] (9) If Figure 1 As shown, the anode conductive layer 105 is filled and formed on the back side of the device by using a sputtering method.

[0085] So far, it is completed Figure 1 Preparation of the semiconductor device shown.

[0086] Based on the same inventive concept, embodiments of the present disclosure provide an electronic device including the aforementioned semiconductor device provided in embodiments of the present disclosure. Because the principles underlying the problems solved by the electronic device are similar to those of the aforementioned semiconductor device, the implementation of the electronic device provided in embodiments of the present disclosure can refer to the implementation of the aforementioned semiconductor device provided in embodiments of the present disclosure, and any repetitions will not be repeated.

[0087] In some embodiments, the electronic devices provided by the embodiments of the present disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, and household appliances. Of course, the electronic devices provided by the present disclosure may include not only semiconductor devices but also other structures. For example, when the electronic device is a radar, it may also include structures such as a transmitter, antenna, and receiver; when the electronic device is a mixer, it may also include structures such as input ports, output ports, and other structures.

[0088] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0089] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A semiconductor device, characterized in that: include: N-drift layer; An N+ substrate, located on one side of the N-drift layer; A trench extending through the N+ substrate; An N-buffer layer, in contact with a surface of the N-drift layer facing the N+ substrate; A P+ anode, located on a side of the trench facing the N-buffer layer; an anode conductive layer, contacting a surface of the P+ anode away from the N-drift layer within the trench, and contacting a surface of the N+ substrate away from the N-drift layer outside the trench; N-layer, and the surface of the N-buffer layer facing the N+ substrate, and the surface of the N+ substrate facing the N-buffer layer; the thickness T of the N-layer between the plane where the bottom surface of the groove is located and the surface of the N+ substrate facing the N-buffer layer NL1 is greater than or equal to 0, and the thickness T of the N-layer between the surface of the P+ anode facing the N-buffer layer and the surface of the N-buffer layer facing the P+ anode is NL2 Greater than or equal to 0, at least in T NL1 and T NL2 When both are 0, the doping concentration of the N-layer is lower than the doping concentration of the N-drift layer.

2. The semiconductor device according to claim 1, wherein The surface of the N-buffer layer away from the N-drift layer is flat; the N-layer wraps the P+ anode, or the surface of the P+ anode facing the N-buffer layer contacts the N-buffer layer, and the side of the P+ anode contacts the N-layer.

3. The semiconductor device according to claim 1, wherein The P+ anode is embedded in the N-buffer layer toward a surface and a portion of a side surface of the N-buffer layer, and the unembedded side surface is in contact with the N-layer.

4. The semiconductor device according to claim 2 or 3, wherein: The trench extends into the N-layer, T NL1 Greater than 0.

5. The semiconductor device according to claim 4, wherein The invention also includes an anode dielectric layer disposed in the trench, wherein the N-layer and the anode conductive layer in the trench are separated by the anode dielectric layer.

6. The semiconductor device according to claim 5, wherein The N+ substrate is separated from the anode conductive layer in the trench by the anode dielectric layer.

7. The semiconductor device according to claim 4, wherein The N-layer contacts the anode conductive layer in the trench.

8. The semiconductor device according to claim 4, wherein The P+ anode is also disposed between the anode conductive layer and the N-layer on the sidewall of the trench.

9. The semiconductor device according to claim 8, wherein The P+ anode is also provided between the anode conductive layer and the N+ substrate on the sidewall of the trench.

10. The semiconductor device according to claim 5 or 8, wherein The N+ substrate contacts the anode conductive layer in the trench.

11. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, wherein: The trenches are strip-shaped, and the orthographic projections of a plurality of strip-shaped trenches on the N-drift layer are arranged side by side.

12. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, wherein: The orthographic projection of the trench on the N-drift layer is in a mesh shape.

13. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, wherein: The trench is closed, and a plurality of closed trenches are concentrically arranged on the orthographic projection of the N-drift layer.

14. The semiconductor device according to any one of claims 1 to 3 and 5 to 9, wherein: It also includes a P-well region, an N+ cathode region, a P+ cathode region, a cathode conductive layer, a gate dielectric layer, a gate conductive layer, and an isolation dielectric layer, wherein the P-well region is wrapped by the N-drift layer, the N+ cathode region and the P+ cathode region are arranged in the P-well region, the cathode conductive layer is in contact with the N+ cathode region and the P+ cathode region, the gate dielectric layer is in contact with the N+ cathode region, the P-well region, and the gate conductive layer, and the isolation dielectric layer separates the gate conductive layer from the cathode conductive layer.

15. A method for preparing a semiconductor device according to any one of claims 1 to 14, characterized in that: include: Providing an N+ substrate; Epitaxially growing an N-layer, an N-buffer layer and an N-drift layer in sequence on the N+ substrate; After thinning the N+ substrate to a target thickness, forming a hard mask on the back side of the N+ substrate, and then selectively etching to form a trench penetrating the N+ substrate; Keeping the hard mask in a state, implanting P-type impurities on the back side of the N+ substrate to form a P+ anode; The hard mask is removed by stripping, and annealing is performed to activate the implanted ions and repair lattice damage.

16. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 14.

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