Semiconductor structure and forming method thereof
By forming trenches of different widths in the semiconductor substrate and growing epitaxial layers, the silicon germanium height is controlled by using sacrificial oxide layer and chemical mechanical grinding process, the problem of height difference in the silicon germanium channel grinding process is solved, and the reliability and performance consistency of the device are improved.
Patent Information
- Application Number
- CN202410108273.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-25
- Publication Date
- 2025-07-29
AI Technical Summary
After the 5nm technology node, the grinding process of the silicon germanium channel causes differences in silicon germanium height in different regions, affecting device performance, especially in the small and large regions, resulting in differences in fin and gate heights, affecting device reliability.
By forming trenches of different widths in the semiconductor substrate and growing epitaxial layers in the trenches, the silicon germanium height is controlled using sacrificial oxide layers and chemical mechanical grinding processes to make the surface of the epitaxial layer in different regions flush to ensure that the silicon germanium height is consistent.
The uniform control of silicon germanium height in different regions is achieved, improving the reliability and performance consistency of the device.
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Figure CN120390440A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] After the 5nm technology node, to further improve PMOS device performance, silicon germanium (SiGe) with higher carrier mobility replaced traditional silicon as the PMOS channel. Before the active area process, the SiGe channel undergoes trench etching, SiGe filling, and SiGe polishing to form two substrates: silicon and SiGe.
[0003] Among them, the silicon germanium grinding process is crucial and is the key point to control the height of silicon germanium. However, since the CMO grinding process targets silicon germanium areas of different area sizes, the proportion of the CMP grinding stop layer varies greatly, resulting in different grinding effects between the two. For small-size areas (such as SRAM or 6T), silicon germanium is easy to grind flat; but for silicon germanium in large areas such as TSK, due to the small proportion of the grinding stop layer, the middle cannot be ground down, resulting in a large protrusion. The height difference of silicon germanium in different areas leads to large differences in the fin height and gate height, which seriously affects the performance of the device. Therefore, controlling the height of silicon germanium in different areas is of great significance to further improve device performance.
[0004] Based on this, the present application provides a more effective and reliable technical solution that can control the height of silicon germanium in different areas, thereby improving device reliability. Summary of the Invention
[0005] The present application provides a semiconductor structure and a method for forming the same, which can control the height of silicon germanium in different regions, thereby improving device reliability.
[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a first trench and a second trench are formed in the semiconductor substrate, the width of the first trench being smaller than the width of the second trench, a pad oxide layer and a hard mask layer being sequentially formed on the surface of the semiconductor substrate, a first epitaxial layer and a second epitaxial layer being formed in the first trench and the second trench, respectively, the surface of the second epitaxial layer being flush with the surface of the semiconductor substrate, and the surface of the first epitaxial layer being higher than the surface of the pad oxide layer; forming a sacrificial oxide layer on the surfaces of the first epitaxial layer, the second epitaxial layer and the hard mask layer; making the surface of the sacrificial oxide layer flush with the surface of the pad oxide layer; removing the hard mask layer; making the surface of the first epitaxial layer flush with the surfaces of the pad oxide layer and the sacrificial oxide layer; removing the pad oxide layer and the sacrificial oxide layer and making the surface of the first epitaxial layer flush with the surfaces of the semiconductor substrate and the second epitaxial layer.
[0007] In some embodiments of the present application, the width ratio of the first trench to the second trench is less than 1:2.
[0008] In some embodiments of the present application, the first trench and the second trench have the same depth.
[0009] In some embodiments of the present application, the surface of the first epitaxial layer is lower than the surface of the hard mask layer.
[0010] In some embodiments of the present application, the thickness of the sacrificial oxide layer is 2500 to 3500 angstroms.
[0011] In some embodiments of the present application, the method for making the surface of the sacrificial oxide layer flush with the surface of the pad oxide layer includes: using a chemical mechanical polishing process to polish the sacrificial oxide layer and the hard mask layer until the surfaces of the sacrificial oxide layer and the hard mask layer are flush with the first epitaxial layer; etching the sacrificial oxide layer until the surface of the sacrificial oxide layer is flush with the surface of the pad oxide layer.
[0012] In some embodiments of the present application, the method for etching the sacrificial oxide layer until the surface of the sacrificial oxide layer is flush with the surface of the pad oxide layer includes wet etching.
[0013] In some embodiments of the present application, the materials of the first epitaxial layer and the second epitaxial layer include silicon germanium.
[0014] In some embodiments of the present application, the method for removing the pad oxide layer and the sacrificial oxide layer and making the surface of the first epitaxial layer flush with the surface of the semiconductor substrate and the surface of the second epitaxial layer includes: wet etching.
[0015] Another aspect of the present application further provides a semiconductor structure formed by the method for forming a semiconductor structure as described above, including: a semiconductor substrate, in which a first trench and a second trench are formed, the width of the first trench is less than the width of the second trench, a first epitaxial layer and a second epitaxial layer are respectively formed in the first trench and the second trench, and the surfaces of the first epitaxial layer and the second epitaxial layer are flush with the surface of the semiconductor substrate.
[0016] The present application provides a semiconductor structure and a method for forming the same, which can control the height of silicon germanium in different regions, thereby improving the device reliability. Description of the Drawings
[0017] The following drawings detail the exemplary embodiments disclosed in the present application. The same reference numerals denote similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale.
[0018] Wherein:
[0019] Figures 1 to 8 are schematic structural diagrams of the steps in the method for forming the semiconductor structure according to the embodiments of the present application. Detailed Description of Specific Embodiments
[0020] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content of the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the disclosed embodiments, but has the broadest scope consistent with the claims.
[0021] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.
[0022] Figures 1 to 8 are schematic structural diagrams of the steps in the method for forming the semiconductor structure according to the embodiments of the present application. The method for forming the semiconductor structure according to the embodiments of the present application will be described in detail below in conjunction with the drawings.
[0023] Referring to Figure 2 as shown, a semiconductor substrate 100 is provided. A first trench 101 and a second trench 102 are formed in the semiconductor substrate 100. The width of the first trench 101 is less than the width of the second trench 102. A pad oxide layer 110 and a hard mask layer 120 are sequentially formed on the surface of the semiconductor substrate 100. A first epitaxial layer 130 and a second epitaxial layer 140 are respectively formed in the first trench 101 and the second trench 102. The surface of the second epitaxial layer 140 is flush with the surface of the semiconductor substrate 100, and the surface of the first epitaxial layer 130 is higher than the surface of the pad oxide layer 110.
[0024] In some embodiments of the present application, forming Figure 2 the method of the semiconductor structure shown includes: Referring to Figure 1As shown, a semiconductor substrate 100 is provided. A first trench 101 and a second trench 102 are formed in the semiconductor substrate 100. The width of the first trench 101 is smaller than that of the second trench 102. A pad oxide layer 110 and a hard mask layer 120 are sequentially formed on the surface of the semiconductor substrate 100.
[0025] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide; or (iv) a combination of the above.
[0026] In some embodiments of the present application, the method for forming the first trench 101 and the second trench 102 is as follows: Provide a semiconductor substrate 100, and a pad oxide layer 110 and a hard mask layer 120 are sequentially formed on the surface of the semiconductor substrate 100; Form a patterned photoresist layer on the surface of the hard mask layer 120, and the patterned photoresist layer defines the positions of the first trench 101 and the second trench 102; Use the patterned photoresist layer as a mask to etch the hard mask layer 120 and the pad oxide layer 110 into the semiconductor substrate 100 to form the first trench 101 and the second trench 102; Remove the patterned photoresist layer.
[0027] In some embodiments of the present application, the small-sized first trench 101 is used to form small-sized devices such as SRAM (Static Random Access Memory) or 6T (6 transistors); the large-sized second trench 102 is used to form large-sized devices such as TSK (test key).
[0028] In some embodiments of the present application, the number of the first trenches 101 may be multiple. Here, only one first trench 101 is taken as an example in the present application. In some embodiments of the present application, the number of the second trenches 102 may be multiple. Here, only one second trench 102 is taken as an example in the present application.
[0029] In some embodiments of the present application, the width ratio of the first trench 101 to the second trench 102 is less than 1:2, for example, 1:200. The widths of the first trench 101 and the second trench 102 are, for example, 250 nanometers and 50 micrometers respectively.
[0030] In some embodiments of the present application, the first trench 101 and the second trench 102 have the same depth. The depth of the first trench 101 and the second trench 102 in the semiconductor substrate 100 is, for example, 500 to 650 angstroms.
[0031] In some embodiments of the present application, the material of the pad oxide layer 110 includes silicon oxide. The thickness of the pad oxide layer 110 is 30 angstroms to 80 angstroms.
[0032] In some embodiments of the present application, the material of the hard mask layer 120 includes silicon nitride. The thickness of the hard mask layer 120 is 200 to 500 angstroms.
[0033] In some embodiments of the present application, forming Figure 2 the semiconductor structure shown further includes: referring to Figure 2 as shown, a first epitaxial layer 130 and a second epitaxial layer 140 are respectively formed in the first trench 101 and the second trench 102 by an epitaxial growth process. The surface of the second epitaxial layer 140 is flush with the surface of the semiconductor substrate 100, and the surface of the first epitaxial layer 130 is higher than the surface of the pad oxide layer 110.
[0034] It should be noted that the surface of the second epitaxial layer 140 being flush with the surface of the semiconductor substrate 100 means that most of the surface (or the main part surface) of the second epitaxial layer 140 is flush with the surface of the semiconductor substrate 100. In the actual epitaxial growth process, although the growth height of the main part is set, there will generally be a certain bulge at the position of the sidewall of the second trench 102 due to the extrusion during growth, making this small part protrude from the height of the main part of the second epitaxial layer 140. In the technical solution of the present application, the set height of the second epitaxial layer 140 is flush with the surface of the semiconductor substrate 100, that is, only most of the surface of the second epitaxial layer 140 needs to be flush with the surface of the semiconductor substrate 100. The small part of the bulge at the sidewall of the second trench 102 due to the inevitable process nature does not fall within the design scope.
[0035] For the same reason, the surface of the first epitaxial layer 130 in the first trench 101 is also uneven but has a certain bulge. However, due to the different widths of the first trench 101 and the second trench 102, the proportion of the bulging part of the first epitaxial layer 130 in the first trench 101 is larger, making the overall height of the first epitaxial layer 130 higher.
[0036] In some embodiments of the present application, the surface of the first epitaxial layer 130 is lower than the surface of the hard mask layer 120.
[0037] In some embodiments of the present application, the materials of the first epitaxial layer 130 and the second epitaxial layer 140 include silicon germanium.
[0038] Referring to Figure 3As shown, a sacrificial oxide layer 150 is formed on the surfaces of the first epitaxial layer 130, the second epitaxial layer 140, and the hard mask layer 120. The surface of the sacrificial oxide layer 150 is higher than the surface of the hard mask layer 120 and covers the first epitaxial layer 130, the second epitaxial layer 140, and the hard mask layer 120.
[0039] In some embodiments of the present application, the thickness of the sacrificial oxide layer 150 is 2500 to 3500 angstroms.
[0040] In some embodiments of the present application, the material of the sacrificial oxide layer 150 is the same as that of the pad oxide layer 110, for example, silicon oxide.
[0041] In some embodiments of the present application, the method of forming the sacrificial oxide layer 150 includes the PEOX process (Plasma-enhanced OX DEP, plasma-enhanced silicon oxide deposition process).
[0042] Reference Figure 4 and Figure 5 As shown, the surface of the sacrificial oxide layer 150 is made flush with the surface of the pad oxide layer 110.
[0043] In some embodiments of the present application, the method of making the surface of the sacrificial oxide layer 150 flush with the surface of the pad oxide layer 110 includes: Referring to Figure 4 As shown, the sacrificial oxide layer 150 and the hard mask layer 120 are polished using a chemical mechanical polishing process until the surfaces of the sacrificial oxide layer 150 and the hard mask layer 120 are flush with the first epitaxial layer 130; Referring to Figure 5 As shown, the sacrificial oxide layer 150 is etched until the surface of the sacrificial oxide layer 150 is flush or substantially flush with the surface of the pad oxide layer 110.
[0044] In some embodiments of the present application, the method of etching the sacrificial oxide layer 150 until the surface of the sacrificial oxide layer 150 is flush with the surface of the pad oxide layer 110 includes wet etching or the Certas etching process (a gas reaction etching (without plasma) in which one of the etchants includes HF / NH3).
[0045] Reference Figure 6 As shown, the hard mask layer 120 is removed using a wet etching process such as HPO (hot phosphoric acid).
[0046] Reference Figure 7As shown, the surface of the first epitaxial layer 130 and the raised portion of the second epitaxial layer 140 are made flush with the surfaces of the pad oxide layer 110 and the sacrificial oxide layer 150 using a chemical mechanical polishing process. Since the area of the actual polished portion (the raised portions of the first epitaxial layer 130 and the second epitaxial layer 140) is not large, it can be polished flat.
[0047] Reference Figure 8 As shown, the pad oxide layer 110 and the sacrificial oxide layer 150 are removed and the surfaces of the first epitaxial layer 130 and the second epitaxial layer 140 are made flush with the surface of the semiconductor substrate 100.
[0048] In some embodiments of the present application, the method of removing the pad oxide layer 110 and the sacrificial oxide layer 150 and making the surfaces of the first epitaxial layer 130 and the second epitaxial layer 140 flush with the surface of the semiconductor substrate 100 includes: wet etching.
[0049] The present application provides a method for forming a semiconductor structure, which can control the silicon germanium height in different regions, thereby improving device reliability.
[0050] Embodiments of the present application also provide a semiconductor structure formed by the method for forming a semiconductor structure as described above, reference Figure 8 As shown, it includes: a semiconductor substrate 100, a first trench and a second trench are formed in the semiconductor substrate 100, the width of the first trench is less than the width of the second trench, a first epitaxial layer 130 and a second epitaxial layer 140 are respectively formed in the first trench and the second trench, and the surfaces of the first epitaxial layer 130 and the second epitaxial layer 140 are flush with the surface of the semiconductor substrate 100.
[0051] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide, etc.; or (iv) a combination of the above.
[0052] In some embodiments of the present application, the small-sized first trench 101 is used to form small-sized devices such as SRAM (Static Random Access Memory) or 6T (6 transistors); the large-sized second trench 102 is used to form large-sized devices such as TSK (test key).
[0053] In some embodiments of the present application, the number of the first trenches 101 may be multiple. Herein, only one first trench 101 is taken as an example. In some embodiments of the present application, the number of the second trenches 102 may be multiple. Herein, only one second trench 102 is taken as an example.
[0054] In some embodiments of the present application, the width ratio of the first trench 101 to the second trench 102 is less than 1:2, for example, 1:200. The widths of the first trench 101 and the second trench 102 are, for example, 250 nanometers and 50 micrometers respectively.
[0055] In some embodiments of the present application, the first trench 101 and the second trench 102 have the same depth. The depth of the first trench 101 and the second trench 102 in the semiconductor substrate 100 is, for example, 500 to 650 angstroms.
[0056] In some embodiments of the present application, the materials of the first epitaxial layer 130 and the second epitaxial layer 140 include silicon germanium.
[0057] The present application provides a semiconductor structure and a method for forming the same, which can control the height of silicon germanium in different regions, thereby improving the device reliability.
[0058] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content may be presented only by way of example and may not be restrictive. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.
[0059] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be intermediate elements.
[0060] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be intermediate elements. In contrast, the term "directly" means without intermediate elements. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in this application document, specify the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.
[0061] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.
[0062] In addition, the present application specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Thus, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, Including: Providing a semiconductor substrate in which a first trench and a second trench are formed, the width of the first trench being smaller than the width of the second trench. A pad oxide layer and a hard mask layer are sequentially formed on the surface of the semiconductor substrate. A first epitaxial layer and a second epitaxial layer are respectively formed in the first trench and the second trench. The surface of the second epitaxial layer is flush with the surface of the semiconductor substrate, and the surface of the first epitaxial layer is higher than the surface of the pad oxide layer; Forming a sacrificial oxide layer on the surfaces of the first epitaxial layer, the second epitaxial layer and the hard mask layer; Making the surface of the sacrificial oxide layer flush with the surface of the pad oxide layer; Removing the hard mask layer; Making the surface of the first epitaxial layer flush with the surfaces of the pad oxide layer and the sacrificial oxide layer; Removing the pad oxide layer and the sacrificial oxide layer and making the surface of the first epitaxial layer flush with the surface of the semiconductor substrate and the surface of the second epitaxial layer.
2. The method for forming a semiconductor structure according to claim 1, wherein The width ratio of the first trench to the second trench is less than 1:
2.
3. The method for forming a semiconductor structure according to claim 1, wherein The first trench and the second trench have the same depth.
4. The method for forming a semiconductor structure as claimed in claim 1, wherein, The surface of the first epitaxial layer is lower than the surface of the hard mask layer.
5. The method for forming a semiconductor structure according to claim 1, wherein The thickness of the sacrificial oxide layer is 2500 to 3500 angstroms.
6. The method for forming a semiconductor structure according to claim 1, wherein, The method for making the surface of the sacrificial oxide layer flush with the surface of the pad oxide layer includes: Using a chemical mechanical polishing process to polish the sacrificial oxide layer and the hard mask layer until the surfaces of the sacrificial oxide layer and the hard mask layer are flush with the first epitaxial layer; Etching the sacrificial oxide layer until the surface of the sacrificial oxide layer is flush with the surface of the pad oxide layer.
7. The method for forming a semiconductor structure according to claim 6, wherein The method for etching the sacrificial oxide layer until the surface of the sacrificial oxide layer is flush with the surface of the pad oxide layer includes wet etching.
8. The method for forming a semiconductor structure according to claim 1, wherein The materials of the first epitaxial layer and the second epitaxial layer include silicon germanium.
9. The method for forming a semiconductor structure according to claim 1, wherein The method for removing the pad oxide layer and the sacrificial oxide layer and making the surface of the first epitaxial layer flush with the surface of the semiconductor substrate and the surface of the second epitaxial layer includes: wet etching.
10. A semiconductor structure formed by a method of forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, Including: A semiconductor substrate in which a first trench and a second trench are formed, the width of the first trench being smaller than the width of the second trench. A first epitaxial layer and a second epitaxial layer are respectively formed in the first trench and the second trench, and the surfaces of the first epitaxial layer and the second epitaxial layer are flush with the surface of the semiconductor substrate.