Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same, belonging to the field of semiconductor technology. The manufacturing method comprises: providing a substrate, on which a gate structure and sidewall structures on both sides are formed, and lightly doped regions and heavily doped regions are formed in the substrate on both sides of the gate structure; forming a first etch stop layer covering the substrate, the gate structure and the sidewall structure on the substrate; etching the first etch stop layer to form an opening, the opening exposing a portion of the heavily doped region and at least a portion of the gate structure; forming a compensation epitaxial layer in the opening, the compensation epitaxial layer covering a portion of the heavily doped region; metallizing at least the compensation epitaxial layer to form a metal silicide layer; forming an interlayer dielectric layer on the substrate and the metal silicide layer; etching the interlayer dielectric layer to the metal silicide layer to form a connection hole; and forming a barrier layer and a conductive structure in the connection hole. The semiconductor device and the manufacturing method provided by the present invention can increase the saturation current and improve the performance and yield of the semiconductor device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, integrated circuit chips are moving towards higher semiconductor device density and higher integration levels to achieve faster computing speeds, larger data storage capacities, and more functionality. As semiconductor device feature sizes continue to shrink, gate and sidewall dimensions are increased to optimize threshold voltage or leakage current. However, the distance between adjacent gate structures decreases, resulting in insufficient etching windows for metal silicide and contact holes (CTs). This can damage the lightly doped regions, leading to high horizontal resistance and semiconductor device failure under high voltage. Alternatively, contact holes may not be etched into the active area, causing CT short circuits and impacting semiconductor device yield. Furthermore, as physical gate lengths drop below 30nm, the source-drain parasitic resistance becomes significant relative to the channel resistance, and ion implantation alone cannot reduce this parasitic resistance. Summary of the Invention

[0003] The present invention aims to provide a semiconductor device and a method for manufacturing the same. The semiconductor device and method provided by the present invention can avoid damage to heavily doped and lightly doped regions when forming contact holes, effectively preventing the consumption of dopant ions in the heavily doped and lightly doped regions, increasing saturation current, and eliminating hot carrier effects. The device can also reduce the potential barrier between the metal silicide layer and the substrate, enabling bidirectional conduction in the channel. The contact hole etching height can be reduced, thereby reducing the difficulty of contact hole etching, avoiding contact hole disconnection, and improving the performance and yield of the semiconductor device.

[0004] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising at least the following steps:

[0005] A substrate is provided, on which a gate structure and sidewall structures on both sides of the gate structure are formed, and a lightly doped region and a heavily doped region are formed in the substrate on both sides of the gate structure;

[0006] forming a first etch stop layer on the substrate, covering the substrate, the gate structure and the spacer structure;

[0007] Etching to form an opening in the first etch stop layer, wherein the opening exposes a portion of the heavily doped region and at least a portion of the gate structure;

[0008] forming a compensation epitaxial layer in the opening, wherein the compensation epitaxial layer covers a portion of the heavily doped region and at least a portion of the gate structure;

[0009] Metallizing at least the compensation epitaxial layer to form a metal silicide layer;

[0010] forming an interlayer dielectric layer on the substrate and the metal silicide layer;

[0011] Etching the interlayer dielectric layer to the metal silicide layer to form a connection hole; and

[0012] A barrier layer and a conductive structure are formed in the connection hole.

[0013] In one embodiment of the present invention, the manufacturing method further comprises the following steps:

[0014] forming a bottom anti-reflective layer and a first photoresist layer on the first etch stop layer;

[0015] exposing and developing the first photoresist layer and the bottom anti-reflective layer through a mask to form a first opening, wherein the first opening exposes a portion of the first etch stop layer;

[0016] dry-etching the first etch-stop layer at the bottom of the first opening to form a second opening;

[0017] Laterally etching the first etch-stop layer exposed by the second opening to form a third opening; and

[0018] The first photoresist layer and the bottom anti-reflection layer are removed to form a fourth opening, wherein the fourth opening exposes a portion of the heavily doped region and at least a portion of the gate structure.

[0019] In one embodiment of the present invention, the mask used to form the first opening is the same as the mask used to form the connection hole.

[0020] In one embodiment of the present invention, the manufacturing method further comprises the following steps:

[0021] After forming the compensation epitaxial layer, removing the first etch stop layer; and

[0022] The compensation epitaxial layer and a portion of the substrate are metallized to form the metal silicide layer.

[0023] In one embodiment of the present invention, the metal silicide layer on the heavily doped region includes a first division and a second division. The first division is obtained by metallization treatment of the compensation epitaxial layer and is formed protruding on the substrate. The second division is obtained by metallization treatment of the heavily doped region outside the compensation epitaxial layer and extends from the surface of the substrate into the substrate. The connection between the first division and the second division is arc-shaped.

[0024] In one embodiment of the present invention, the sidewall structure includes a stacked first sublayer, a second sublayer, a third sublayer and a fourth sublayer, starting from the side close to the gate structure. After the metal silicide layer is formed, the fourth sublayer and the third sublayer are removed, and a compensating doping region is formed at the bottom of the second section and in the substrate between the heavily doped region and the second sublayer.

[0025] In one embodiment of the present invention, the depth of the compensating doped region is greater than the depth of the second portion.

[0026] In one embodiment of the present invention, the manufacturing method further includes:

[0027] After forming the compensating doped region, forming a second etch stop layer on the substrate;

[0028] forming the interlayer dielectric layer, the hard mask layer and the photoresist mask layer in sequence on the second etch stop layer, wherein a recess is formed in the photoresist mask layer; and

[0029] The hard mask layer, the interlayer dielectric layer, the second etch stop layer and a portion of the metal silicide layer exposed in the recess are etched using the photolithography mask layer as a mask to form the connection hole.

[0030] In one embodiment of the present invention, the manufacturing method further includes:

[0031] After forming the metal silicide layer, forming an interlayer dielectric layer, a hard mask layer, and a photolithography mask layer on the substrate and the metal silicide layer, wherein a recess is formed in the photolithography mask layer; and

[0032] The hard mask layer, the interlayer dielectric layer and a portion of the metal silicide layer exposed in the recess are etched using the photolithography mask layer as a mask to form the connection hole.

[0033] The present invention also provides a semiconductor device, which is obtained by the above-mentioned manufacturing method and at least comprises

[0034] a substrate, on which a gate structure and sidewall structures on both sides of the gate structure are provided, and in which a lightly doped region and a heavily doped region are provided in the substrate on both sides of the gate structure;

[0035] an etch stop layer, at least disposed on the substrate and the sidewall structure;

[0036] a metal silicide layer, disposed at least on the heavily doped region and the gate structure, and protruding from surfaces of the substrate and the gate structure;

[0037] an interlayer dielectric layer, disposed on the substrate and the metal silicide layer;

[0038] a connecting hole, provided in the interlayer dielectric layer; and

[0039] The barrier layer and the conductive structure are arranged in the connection hole.

[0040] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. By improving the semiconductor device and the method for manufacturing the same, the unexpected technical effect of the present application is that it can ensure that the range of forming the metal silicide layer is larger than the range of forming the connection hole. When forming the connection hole, when problems such as the critical dimension of the connection hole becomes larger, the overlay offset or the connection hole is over-etched occur, damage to the heavily doped and lightly doped regions can be avoided, thereby improving the quality of the device. The difficulty of masking and etching can be reduced, and by adopting a mask plate for subsequently forming the connection hole, the etching of the first etch stop layer can be achieved, which can reduce the development of the mask plate and reduce costs. By forming a compensating epitaxial layer, when forming the metal silicide layer, the height of the active area and the gate structure can be avoided from being consumed, and at the same time, the consumption of doped ions in the heavily doped area and the lightly doped area can be effectively avoided, thereby improving the saturation current and ensuring the performance of the device. The metal silicide layer on the heavily doped area can play the role of voltage and current division, and can eliminate the hot carrier effect. This method can timely adjust the manufacturing process to compensate for the consumption of the lightly doped region by the metal silicide layer, thereby reducing the potential barrier between the metal silicide layer and the substrate and enabling bidirectional conduction in the channel. It can effectively prevent semiconductor device failure under high supply voltages and avoid high-voltage failure caused by high resistance across the device channel width. It can also reduce stress on the gate structure and minimize leakage from the gate to the source and drain. It can also reduce the contact hole etching height, thereby reducing the difficulty of contact hole etching, avoiding contact hole disconnection, and improving the performance and yield of semiconductor devices.

[0041] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 Schematic diagram of a semiconductor device after a gate structure, a spacer structure, and a heavily doped region are formed on a substrate according to an embodiment of the present invention.

[0044] Figure 2 FIG. 1 is a schematic diagram of forming a first etch stop layer, a bottom anti-reflective layer, and a first photoresist layer in accordance with an embodiment of the present invention.

[0045] Figure 3FIG. 1 is a schematic diagram of forming a first opening in a bottom anti-reflective layer and a first photoresist layer according to an embodiment of the present invention.

[0046] Figure 4 FIG. 1 is a schematic diagram of etching the first etch stop layer at the bottom of the first opening to form a second opening in one embodiment of the present invention.

[0047] Figure 5 FIG. 1 is a schematic diagram of forming a third opening by laterally etching the first etch stop layer exposed by the second opening in one embodiment of the present invention.

[0048] Figure 6 FIG. 1 is a schematic diagram of removing the bottom anti-reflective layer and the first photoresist layer to form a fourth opening according to an embodiment of the present invention.

[0049] Figure 7 FIG. 1 is a schematic diagram of forming a compensation epitaxial layer in one embodiment of the present invention.

[0050] Figure 8 FIG. 1 is a schematic diagram of an embodiment of the present invention after the first etch stop layer is removed.

[0051] Figure 9 FIG. 4 is a schematic diagram of forming a metal silicide layer according to an embodiment of the present invention.

[0052] Figure 10 FIG. 1 is a schematic diagram of a sidewall structure after removing the fourth sublayer and the third sublayer in an embodiment of the present invention.

[0053] Figure 11 FIG. 4 is a schematic diagram of forming a first compensating doped region in one embodiment of the present invention.

[0054] Figure 12 FIG. 4 is a schematic diagram of forming a second compensating doping region in one embodiment of the present invention.

[0055] Figure 13 Schematic diagram of forming a second etch stop layer, an interlayer dielectric layer, a hard mask layer and a photolithography mask layer in one embodiment of the present invention.

[0056] Figure 14 FIG. 1 is a schematic diagram of a connection hole formed in one embodiment of the present invention.

[0057] Figure 15 FIG. 1 is a schematic diagram of a barrier layer and a conductive structure formed in one embodiment of the present invention.

[0058] Figure 16 FIG. 4 is a schematic diagram of forming a compensation epitaxial layer in another embodiment of the present invention.

[0059] Figure 17 FIG. 4 is a schematic diagram of forming a metal silicide layer according to another embodiment of the present invention.

[0060] Figure 18 FIG. 1 is a schematic diagram of another embodiment of the present invention after forming an interlayer dielectric layer, a hard mask layer, and a photolithography mask layer.

[0061] Figure 19 FIG. 1 is a schematic diagram of another embodiment of the present invention after forming a barrier layer and a conductive structure.

[0062] Description of labels:

[0063] 10. Substrate; 100. First region; 200. Second region; 101. First well region; 102. Second well region; 11. Shallow trench isolation structure; 12. Gate dielectric layer; 13. First lightly doped region; 14. Second lightly doped region; 15. Gate structure; 16. Spacer structure; 161. First sublayer; 162. Second sublayer; 163. Third sublayer; 164. Fourth sublayer; 17. First heavily doped region; 18. Second heavily doped region; 19. First etch stop layer; 20. Bottom anti-reflective layer; 21. First photoresist layer; 211. First opening; 212. Second opening; 213. Third opening; 214. Fourth opening; 22. Compensated epitaxial layer; 23. Metal silicide layer; 231. First division; 232. Second division; 24. First patterned photoresist layer; 25. First compensating doped region; 26. Second patterned photoresist layer; 27. Second compensating doped region; 28. Second etch stop layer; 29. ​​Interlayer dielectric layer; 30. Hard mask layer; 31. Photolithography mask layer; 311. Recess; 312. Connecting hole; 32. Barrier layer; 33. Conductive structure. DETAILED DESCRIPTION

[0064] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0066] In the description of this specification, it should be understood that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "front," "back," "left," and "right" are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this solution and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific direction, be constructed, or operate in a specific direction. Therefore, they should not be construed as limitations on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0067] The present invention provides a semiconductor device and a method for manufacturing the same. When forming a connection hole, it is possible to avoid damage to the heavily doped and lightly doped regions, effectively avoid the consumption of doping ions in the heavily doped and lightly doped regions, increase the saturation current, and prevent the hot carrier effect. It is possible to reduce the potential barrier between the metal silicide layer and the substrate so that the channel can conduct in both directions. It is possible to reduce the etching height of the contact hole, thereby reducing the difficulty of etching the contact hole, avoiding the disconnection of the contact hole, and improving the performance and yield of the semiconductor device. The manufacturing method of the present invention can be widely used in the preparation of different semiconductor devices, and the obtained semiconductor devices can be applied to various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, household appliances, and aerospace.

[0068] See also Figure 1 As shown, a substrate 10 is provided. Substrate 10 can be any material suitable for forming a semiconductor device. Examples of substrate 10 include silicon carbide (SiC), indium phosphide (InP), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, a silicon wafer, or other semiconductor materials formed from III / V compounds. This also includes stacked structures composed of these semiconductor materials, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SLSI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). The present invention does not limit the type of substrate 10; it can be flexibly configured based on requirements and can be configured based on the type of semiconductor device. In this embodiment, substrate 10 is, for example, a doped silicon wafer, and the doping type can be either P-type or N-type.

[0069] See also Figure 1As shown, in one embodiment of the present invention, a plurality of semiconductor devices are formed on a substrate 10 , and the present invention does not limit the types of semiconductor devices. The semiconductor device may be, for example, a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a thyristor, a charge coupled device (CCD image sensor), a constant voltage diode, a high frequency diode, a light-emitting diode (LED), a gate turn off thyristor (GTO), a digital signal processor (DSP), a fast recovery diode (FRD), a high-speed and high-efficiency rectifier diode (HED), a light triggered thyristor (LTT), a photo relay or a microprocessor, and the specific selection may be made during the manufacturing process. In this embodiment, the substrate 10 includes a first region 100 and a second region 200 , wherein the first region 100 is used to form an NMOS transistor, and the second region 200 is used to form a PMOS transistor. The NMOS transistor and the PMOS transistor are isolated by a shallow trench isolation structure 11 .

[0070] See also Figure 1 As shown, in one embodiment of the present invention, a first well region 101 and a second well region 102 are provided within substrate 10. First well region 101 is provided within first region 100 and is doped with P-type dopant ions, such as boron (B) or gallium (Ga). Second well region 102 is provided within second region 200 and is doped with N-type dopant ions, such as phosphorus (P) or arsenic (As). In this embodiment, the implantation depths of first well region 101 and second well region 102 are, for example, equal, or less than or equal to the depth of shallow trench isolation structure 11.

[0071] See also Figure 1As shown, in one embodiment of the present invention, the semiconductor device includes a gate structure 15, which is protrudingly disposed on a substrate 10, and a gate dielectric layer 12 is disposed between the gate structure 15 and the substrate 10. The gate dielectric layer 12 is, for example, silicon dioxide or a high-k dielectric layer, and the gate structure 15 is, for example, a polysilicon gate or a metal gate. Spacer structures 16 are disposed on both sides of the gate structure 15, and the spacer structure 16 is, for example, a nitride layer or a stack of an oxide layer and a nitride layer, and the outermost layer of the spacer structure 16 is a nitride layer. In this embodiment, the spacer structure 16 is, for example, a stack of silicon oxide and silicon nitride. Starting from the side close to the gate structure 15, the spacer structure 16 includes, for example, a stacked first sublayer 161, a second sublayer 162, a third sublayer 163, and a fourth sublayer 164, wherein the first sublayer 161 and the third sublayer 163 are, for example, silicon oxide layers, and the second sublayer 162 and the fourth sublayer 164 are, for example, silicon nitride layers. By setting the first sub-layer 161 as a silicon oxide layer, the stress of the spacer structure 16 on the gate structure can be reduced, and the leakage from the gate to the source and drain can be reduced.

[0072] See also Figure 1 As shown, in one embodiment of the present invention, the semiconductor device includes a lightly doped region and a heavily doped region, wherein the lightly doped region includes a first lightly doped region 13 and a second lightly doped region 14. The first lightly doped region 13 is disposed in a first region 100, and the second lightly doped region 14 is disposed in a second region 200. The edges of the lightly doped region partially overlap with the gate structure 15, and the lightly doped region is formed after the gate structure is formed. The heavily doped region includes a first heavily doped region 17 and a second heavily doped region 18. The first heavily doped region 17 is disposed in the first region 100, and the second heavily doped region 18 is disposed in the second region 200. The edges of the heavily doped region are aligned with the edge of the sidewall structure 16 away from the gate structure 15, and the heavily doped region is formed after the sidewall structure is formed, forming to serve as the source and drain of the semiconductor device. The first lightly doped region 13 and the first heavily doped region 17 have the same doping type, which is opposite to the doping type of the first well region 101. The second lightly doped region 14 and the second heavily doped region 18 have the same doping type, which is opposite to the doping type of the second well region 102. The doping concentration of the heavily doped region is greater than the doping concentration of the lightly doped region, and the doping depth of the heavily doped region is greater than the doping depth of the lightly doped region.

[0073] See also Figures 1 to 2As shown, in one embodiment of the present invention, after forming the heavily doped region, a first etch stop layer 19 is formed on the substrate 10. The first etch stop layer 19, for example, covers the spacer structure 16, the gate structure 15, the substrate 10, and the shallow trench isolation structure 11. The first etch stop layer 19 is, for example, a silicon nitride layer. The first etch stop layer 19 is obtained, for example, by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition. The thickness of the first etch stop layer 19 is, for example, 25 nm to 40 nm.

[0074] See also Figures 2 to 3 As shown, in one embodiment of the present invention, after forming a first etch stop layer 19, a bottom anti-reflective layer (BARC) 20 and a first photoresist layer 21 are formed on the first etch stop layer 19. The BARC 20 and the first photoresist layer 21 are formed, for example, by spin coating or doctor blade coating, and have smooth surfaces. The BARC 20 and the first photoresist layer 21 are, for example, a resin-based composite material. A mask for subsequently forming connection holes is used, followed by exposure and development processes to form a first opening 211 in the first photoresist layer 21 and the BARC 20. The first opening 211 is located above the heavily doped region and the gate structure 15 and exposes a portion of the first etch stop layer 19.

[0075] See also Figures 3 to 5 As shown, in one embodiment of the present invention, after forming the first opening 211, the first etch-stop layer 19 at the bottom of the first opening 211 is removed, for example, by dry etching, to form a second opening 212. After forming the second opening 212, the first etch-stop layer 19 exposed by the second opening 212 is laterally etched, for example, by wet etching, to form a third opening 213. The wet etching solution is, for example, phosphoric acid with a mass fraction of 80% to 95%, and the etching temperature is 155°C to 165°C. The amount of lateral etching of the first etch-stop layer 19 is controlled by controlling the concentration of phosphoric acid, the etching temperature, and the etching time. In this embodiment, for example, the first etch-stop layer 19 on the gate structure 15 is removed, leaving a portion of the first etch-stop layer 19 on the heavily doped region. Forming the first opening through development can reduce the difficulty of etching. Furthermore, by using a mask for subsequently forming the connection hole to etch the first etch-stop layer, mask development can be reduced, thereby lowering costs.

[0076] See also Figures 5 and 6As shown, in one embodiment of the present invention, after lateral etching, the first photoresist layer 21 and the bottom anti-reflective layer 20 are removed, and a fourth opening 214 is formed on the gate structure 15 and the heavily doped region. The fourth opening 214 exposes a portion of the heavily doped region and at least a portion of the gate structure 15. In this embodiment, the fourth opening 214 exposes the entire gate structure 15 and a portion of the heavily doped region. The first photoresist layer 21 and the bottom anti-reflective layer 20 are removed, for example, by an asher process and wet etching. The asher process involves plasma treatment at 200°C to 300°C using oxygen or a mixture of oxygen, nitrogen, and hydrogen. The oxygen plasma removes the first photoresist layer 21 and the bottom anti-reflective layer 20, and then wet etching is performed using an organic solvent such as isopropyl alcohol to ensure that no photoresist or bottom anti-reflective layer residue remains, thereby improving the yield of the semiconductor process. After the third opening 213 is formed on the basis of a mask plate for subsequently forming a connection hole, fourth openings 214 are etched on both sides to form a compensation epitaxial layer and a metal silicide layer for the subsequent formation of the compensation epitaxial layer. This ensures that the range of forming the metal silicide layer is larger than the range of forming the connection hole. When the mask plate is subsequently used to form the connection hole, when problems such as the critical dimension (CD) of the connection hole becomes larger, overlay shift, or over-etching of the connection hole occur, damage to the heavily doped and lightly doped regions can be avoided, thereby improving device quality.

[0077] See also Figures 6 and 7 As shown, in one embodiment of the present invention, after forming the fourth opening 214, a compensation epitaxial layer 22 is formed within the fourth opening 214. Specifically, the compensation epitaxial layer 22 covers a portion of the heavily doped region and at least a portion of the gate structure 15. The compensation epitaxial layer 22 is, for example, a single crystal silicon layer, and its thickness is, for example, equal to the thickness of the first etch stop layer 19. Specifically, the compensation epitaxial layer 22 is formed, for example, by selective epitaxial growth, wherein the epitaxial growth gas source is, for example, silicon tetrachloride (SiCl4), trichlorosilane (SiHCl3), or dichlorosilane (SiH2Cl2), or a mixture thereof, and further, dichlorosilane, with a dichlorosilane flow rate of, for example, 200 sccm to 400 sccm, and the epitaxial growth temperature is, for example, 700°C to 900°C. During the formation of the compensation epitaxial layer 22, due to the presence of the first etch stop layer 19, the compensation epitaxial layer 22 is formed only on the substrate 10 and gate structure 15 exposed by the fourth opening 214.

[0078] See also Figures 7 and 8As shown, in one embodiment of the present invention, after forming the compensation epitaxial layer 22, the first etch stop layer 19 is removed. In this embodiment, the first etch stop layer 19 is removed by, for example, wet etching, and the wet etching solution is, for example, phosphoric acid, and the mass fraction of phosphoric acid is 80% to 95%, and the etching temperature is 155°C to 165°C.

[0079] See also Figures 8 and 9 As shown, in one embodiment of the present invention, after removing the first etch stop layer 19, the compensation epitaxial layer 22 and a portion of the substrate 10 are metallized to form a metal silicide layer 23 to reduce subsequent contact resistance with the conductive plug. Specifically, a silicon oxide layer and a silicon nitride layer (not shown) are deposited on the substrate 10, the shallow trench isolation structure 11, the compensation epitaxial layer 22, and the spacer structure 16. Etching is then performed to expose the area where the metal silicide layer 23 is to be formed. A SiCoNi pre-cleaning process is then performed to remove possible contaminants on the substrate 10 to improve the quality of the formed metal silicide layer 23. A layer of metal material (not shown) is then deposited, such as at least one of titanium, cobalt, or nickel. In this embodiment, a mixture of nickel and titanium is deposited, with a thickness of, for example, 10 nm to 15 nm. A titanium nitride layer (not shown) is formed on the metal material, with a thickness of, for example, 3 nm to 8 nm, to prevent oxidation of the metal material. The exposed substrate 10 and the compensation epitaxial layer 22 are metallized by rapid annealing, such as annealing at 260°C to 300°C for 30s to 40s, to form a high-resistance metal silicide Ni2PtSi, and then annealed at 400°C to 900°C for 30s to 40s to form a low-resistance NiPtSi2, i.e., a metal silicide layer 23. Finally, the unreacted metal material is removed.

[0080] See also Figures 8 and 9As shown, in one embodiment of the present invention, the metal silicide layer 23 on the heavily doped region includes a first portion 231 and a second portion 232. The first portion 231 is formed by the reaction between the compensation epitaxial layer 22 and the metal material and protrudes from the substrate 10. The second portion 232 is formed by the reaction between the substrate 10 and the metal material outside the compensation epitaxial layer 22 and extends from the surface of the substrate 10 into the substrate 10. The junction between the first portion 231 and the second portion 232 is arc-shaped. In this embodiment, the width of the compensation epitaxial layer 22 is consistent with that of the gate structure 15. Therefore, the metal silicide layer 23 on the gate structure 15 protrudes from the surface of the gate structure 15. In other embodiments, if the width of the compensation epitaxial layer 22 on the gate structure 15 is smaller than the width of the gate structure 15, that is, when the fourth opening is formed, the width of the fourth opening on the gate structure 15 is smaller than the width of the gate structure 15, then the shape of the metal silicide layer 23 on the gate structure 15 is consistent with that on the heavily doped region. This is not further explained in this application. By forming the compensating epitaxial layer 22, the height of the active region and gate structure can be reduced during the formation of the metal silicide layer 23. This effectively prevents the consumption of dopant ions in the heavily doped and lightly doped regions, reducing source-drain parasitic resistance and ensuring device performance. Furthermore, the metal silicide layer 23 on the heavily doped region can act as a voltage divider and current divider, eliminating hot carrier effects.

[0081] See also Figures 9 and 10 As shown, in one embodiment of the present invention, based on the wafer acceptance test (WAT) data of the previous batch of substrates, such as the saturation current (IDSat), it is determined whether the doping concentration in the lightly doped region meets the performance requirements. If the doping concentration is too low and cannot meet the electrical requirements, after forming the metal silicide layer 23, the fourth sub-layer 164 and the third sub-layer 163 in the spacer structure 16 are removed. The removal process is performed, for example, by wet etching. The etchant for the fourth sub-layer 164 is, for example, phosphoric acid, with a mass fraction of 80% to 95%, and the etching temperature is 155°C to 165°C. The etchant for the third sub-layer 163 is, for example, hydrofluoric acid or buffered oxide etchant (BOE).

[0082] See also Figures 9 to 11As shown, in one embodiment of the present invention, after removing the fourth sub-layer 164 and the third sub-layer 163, a first patterned photoresist layer 24 is formed on the substrate 10. The first patterned photoresist layer 24 covers the first region 100. Ion implantation is performed on the second region 200, and a first compensating doping region 25 is formed in the substrate 10 at the bottom of the second sub-portion 232 and between the second heavily doped region 18 and the second sub-layer 162. That is, the depth of the first compensating doping region 25 is greater than the depth of the second sub-portion 232. The doping ions in the first compensating doping region 25 are, for example, boron or boron fluoride ions (BF2 + ) and other P-type ions. The specific doping dosage is confirmed based on the IDSat of the previous batch.

[0083] See also Figures 11 to 12 As shown, in one embodiment of the present invention, after forming the first compensating doping region 25, the first patterned photoresist layer 24 is removed, for example, by ashing or wet etching, and a second patterned photoresist layer 26 is formed on the substrate 10. The second patterned photoresist layer 26 covers the second region 200. Ions are implanted into the first region 100 to form a second compensating doping region 27 in the substrate 10 at the bottom of the second sub-portion 232 and between the first heavily doped region 17 and the second sub-layer 162. That is, the depth of the second compensating doping region 27 is greater than the depth of the second sub-portion 232. The doping ions in the second compensating doping region 27 are, for example, N-type ions such as phosphorus or arsenic. The specific doping dosage is determined based on the IDSat of the previous batch. In other embodiments, based on the IDSat data, the compensating doping region can be selectively formed only in the first region or the second region to increase the IDSat and improve the performance of the semiconductor device. In this embodiment, the depth of the compensating doped region is greater than that of the second subsection, compensating for the loss of the lightly doped region caused by the formation of the metal silicide layer 23. This reduces the potential barrier between the metal silicide layer 23 and the substrate 10, enabling bidirectional conduction in the channel. Furthermore, this effectively prevents semiconductor device failure under high supply voltages (High Voltage Current Condense, HVCC), avoiding high-voltage failures caused by high resistance across the device's channel width (from source to drain).

[0084] See also Figures 12 to 13 As shown, in one embodiment of the present invention, after forming the second compensating doped region 27, the second patterned photoresist layer 26 is removed, for example, by ashing or wet etching, to form a second etch-stop layer 28 on the substrate 10. The second etch-stop layer 28, for example, covers the metal silicide layer 23, the sidewall structure, the substrate 10, and the shallow trench isolation structure 11. The second etch-stop layer 28 is, for example, a silicon nitride layer, and is obtained, for example, by low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition. The thickness of the second etch-stop layer 28 is, for example, 15 nm to 25 nm.

[0085] See also Figure 13 As shown, in one embodiment of the present invention, an interlayer dielectric layer 29 is formed on the second etch stop layer 28. The interlayer dielectric layer 29 is, for example, silicon oxide. A silicon oxide layer is first formed covering the metal silicide layer 23 by, for example, high aspect ratio chemical vapor deposition (HARP-CVD) until it completely fills the area between adjacent gate structures 15. The silicon oxide layer is then planarized, for example, by chemical mechanical polishing (CMP) to improve the filling energy of the interlayer dielectric layer, prevent voids that affect the fabrication yield of the conductive plug, and achieve a planarized surface that facilitates subsequent operations. A silicon oxide layer is then sequentially formed by plasma-enhanced chemical vapor deposition and chemical vapor deposition to obtain the interlayer dielectric layer 29. The present application does not limit the thickness of the silicon oxide layer formed by various deposition methods. In this embodiment, the thickness of the interlayer dielectric layer 29 on the substrate 10 is, for example, 250 nm to 280 nm. The interlayer dielectric layer 29 is formed by combining different methods to improve the deposition quality of the interlayer dielectric layer 29 while reducing deposition costs.

[0086] See also Figure 13 As shown, in one embodiment of the present invention, a hard mask layer 30 is formed on the interlayer dielectric layer 29 to protect the interlayer dielectric layer 29, improve the etching selectivity, reduce the micro-groove effect, and improve the quality of the subsequent formation of the connection hole. In this embodiment, the hard mask layer 30 includes, for example, an amorphous carbon layer, a silicon oxynitride layer, and a silicon oxide layer, which are sequentially arranged on the interlayer dielectric layer 29. The thickness of each layer, such as the amorphous carbon layer, the silicon oxynitride layer, and the silicon oxide layer, is not limited in this application and is selected according to the manufacturing requirements. In a specific embodiment of the present invention, the thickness of the amorphous carbon layer is, for example, 160nm to 240nm, the thickness of the silicon oxynitride layer is, for example, 30nm to 40nm, and the thickness of the silicon oxide layer is, for example, 5nm to 10nm. By providing a multi-layer hard mask layer, the quality of the subsequent formation of the connection hole is improved.

[0087] See also Figure 13As shown, in one embodiment of the present invention, a photolithography mask layer 31 is formed on the hard mask layer 30. In this embodiment, the photolithography mask layer 31 includes, for example, an anti-reflection layer and a photoresist layer sequentially arranged on the hard mask layer 30. The anti-reflection layer is a resin-based composite material. The thickness of each layer such as the anti-reflection layer and the photoresist layer is not limited in this application and is selected according to the manufacturing requirements. In a specific embodiment of the present invention, the thickness of the anti-reflection layer is, for example, 20nm~30nm, and the thickness of the photoresist layer is, for example, 90nm~110nm. By forming a mask plate for forming a connection hole, exposure, development and other processes are performed to form a recess 311 in the photolithography mask layer 31. The recess 311 is located on the heavily doped region and the gate structure 15 and exposes the hard mask layer 30 at the bottom to locate the position of the connection hole.

[0088] See also Figures 13 and 14 As shown, in one embodiment of the present invention, the hard mask layer 30, the interlayer dielectric layer 29, the second etch stop layer 28, and a portion of the metal silicide layer 23 are etched using a photolithography mask layer 31 as a mask through dry etching, wet etching, or a combination of dry etching and wet etching to form a connection hole 312. In this embodiment, dry etching is used, for example, for etching. During the etching process, the second etch stop layer 28 is used as an etch stop layer in sequence according to the different materials being etched. After etching to the same material at different locations, the etching gas is replaced to form the connection hole 312, and the connection hole 312 stops at the same depth within the metal silicide layer 23. During the etching process, since the metal silicide layer 23 protrudes from the surface of the substrate 10 or the gate structure 15, the etching height of the connection hole 312 is reduced. Therefore, the etching difficulty of the connection hole 312 can be reduced, thereby avoiding the disconnection of the connection hole 312 and improving the yield of the semiconductor device.

[0089] See also Figures 14 and 15As shown, in one embodiment of the present invention, after forming the connection hole 312, a barrier layer 32 is formed on the sidewalls and bottom of the connection hole 312. The barrier layer 32 is formed, for example, by electroplating or physical vapor deposition, and the barrier layer 32 is made of a material with good adhesion, such as tantalum, tantalum nitride, or titanium nitride. The thickness of the barrier layer 32 is, for example, 5 nm to 15 nm. Metal is deposited on the barrier layer 32 to form a conductive structure 33. The barrier layer 32 and the conductive structure 33 constitute a conductive plug. Specifically, the metal material is deposited, for example, by physical vapor deposition or electroplating, and the metal material is, for example, copper, aluminum, or tungsten. Deposition is stopped until the metal material completely fills the connection hole 312. The conductive structure 33 is then planarized by chemical mechanical polishing, so that the conductive structure 33 is flush with the interlayer dielectric layer 29 on both sides. In this embodiment, the conductive structure 33 is made of, for example, tungsten, and the barrier layer 32 is, for example, a combination of a titanium layer and a titanium nitride layer. The titanium layer is disposed on the sidewalls and bottom of the connection hole 312, and the titanium nitride layer is disposed on the titanium layer. The thickness of the titanium layer is, for example, 8 nm to 10 nm, and the thickness of the titanium nitride layer is, for example, 3 nm to 5 nm. The combination of the titanium layer and the titanium nitride layer can prevent the raw materials from reacting with the titanium layer during the deposition of the conductive structure 33, thereby preventing the conductive structure 33 from falling off. At the same time, the stress of the titanium nitride layer can be alleviated, and the bonding strength between the titanium nitride layer and the interlayer dielectric layer 29 can be improved. The barrier layer 32 enhances the adhesion of the metal material to the sidewalls of the connection hole 312, blocks the diffusion of metal ions, reduces electromigration, and improves the reliability of the semiconductor device.

[0090] See also Figures 16 and 17As shown, in another embodiment of the present invention, the doping concentration in the lightly doped region is determined to meet performance requirements based on wafer acceptance test data from a previous batch of substrates, such as the saturation current IDSat. After forming the compensation epitaxial layer 22, the first etch stop layer 19 is not removed, and a metal silicide layer 23 is directly formed to reduce the subsequent contact resistance with the conductive plug. Specifically, a silicon oxide layer and a silicon nitride layer (not shown) are deposited on the first etch stop layer 19 and the compensation epitaxial layer 22. The area where the metal silicide layer 23 is to be formed is then exposed by etching. A SiCoNi pre-cleaning step is performed to remove possible contaminants on the substrate 10, thereby improving the quality of the formed metal silicide layer 23. A layer of metal material (not shown) is then deposited, such as at least one of titanium, cobalt, or nickel. In this embodiment, a mixture of nickel and titanium is deposited, with a thickness of, for example, 10 nm to 15 nm. A titanium nitride layer (not shown) is formed on the metal material, with a thickness of, for example, 3 nm to 8 nm, to prevent oxidation of the metal material. Through a rapid annealing process, such as annealing at 260°C to 300°C for 30s to 40s, the metal material reacts with the silicon in the exposed substrate 10 and the compensation epitaxial layer 22 to form a high-resistance metal silicide Ni2PtSi. Subsequently, annealing is performed at 400°C to 900°C for 30s to 40s to form a low-resistance NiPtSi2, i.e., a metal silicide layer 23. Finally, the unreacted metal material is removed. In this embodiment, since the first etch stop layer 19 is not removed, the metal material reacts only with the compensation epitaxial layer 22 to form the metal silicide layer 23. The formed metal silicide layer 23 protrudes above the substrate 10 or the gate structure 15.

[0091] See also Figures 17 to 19 As shown, in another embodiment of the present invention, after forming the metal silicide layer 23, an interlayer dielectric layer 29, a hard mask layer 30, and a photolithography mask layer 31 are formed directly on the first etch stop layer 19 and the metal silicide layer 23. The formation method and structure are the same as those of the previous embodiment and will not be elaborated on here. In the process of forming the connection hole 312, the hard mask layer 30, the interlayer dielectric layer 29, and a portion of the metal silicide layer 23 are etched in sequence to form the connection hole 312, and then the barrier layer 32 and the conductive structure 33 are formed. The formation method and structure are the same as those of the previous embodiment and will not be elaborated on here. In this embodiment, the formation process of the metal silicide layer 23 is different from that of the previous embodiment, which can simplify the manufacturing process while having the beneficial effects of the previous embodiment and can improve the performance and yield of the semiconductor device.

[0092] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. By improving the semiconductor device and the method for manufacturing the same, the unexpected technical effect of the present application is that it can ensure that the range of forming the metal silicide layer is larger than the range of forming the connection hole. When forming the connection hole, when problems such as the critical dimension of the connection hole becomes larger, the overlay offset or the connection hole is over-etched occur, damage to the heavily doped and lightly doped regions can be avoided, thereby improving the quality of the device. The difficulty of masking and etching can be reduced, and by adopting a mask plate for subsequently forming the connection hole, the etching of the first etch stop layer can be achieved, which can reduce the development of the mask plate and reduce costs. By forming a compensating epitaxial layer, when forming the metal silicide layer, the height of the active area and the gate structure can be avoided from being consumed, and at the same time, the consumption of doped ions in the heavily doped area and the lightly doped area can be effectively avoided, thereby improving the saturation current and ensuring the performance of the device. The metal silicide layer on the heavily doped area can play the role of voltage and current division, and can eliminate the hot carrier effect. Timely adjustments to the manufacturing process based on wafer acceptance test data can compensate for the loss of lightly doped regions during metal silicide formation, lower the potential barrier between the metal silicide layer and the substrate, and enable bidirectional conduction in the channel. This effectively prevents semiconductor device failure under high supply voltages and high-voltage failures caused by high resistance across the device's channel width. It also reduces stress on the gate structure and gate-to-source / drain leakage. It also reduces the contact hole etch height, thereby simplifying contact hole etching and preventing contact hole shorting, thereby improving semiconductor device performance and yield.

[0093] The above description of the illustrated embodiments of the present invention (including that described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, as those skilled in the art will recognize and appreciate, various equivalent modifications are possible within the spirit and scope of the present invention. As noted, modifications may be made to the present invention in light of the above description of the illustrated embodiments of the present invention, and such modifications will be within the spirit and scope of the present invention.

[0094] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solutions formed by replacing the above features with (but not limited to) technical features with similar functions disclosed in this application. In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be repeated here.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: At least the following steps are included: A substrate is provided, on which a gate structure and sidewall structures on both sides of the gate structure are formed, and a lightly doped region and a heavily doped region are formed in the substrate on both sides of the gate structure; forming a first etch stop layer on the substrate, covering the substrate, the gate structure and the spacer structure; forming an opening in the first etch stop layer by etching, wherein the opening exposes a portion of the heavily doped region and at least a portion of the gate structure; forming a compensation epitaxial layer in the opening, wherein the compensation epitaxial layer covers a portion of the heavily doped region and at least a portion of the gate structure; removing the first etch stop layer; Metallizing at least the compensation epitaxial layer and a portion of the substrate to form a metal silicide layer; the metal silicide layer on the heavily doped region includes a first portion and a second portion, the first portion protruding from the substrate, and the second portion extending from the surface of the substrate into the substrate; The spacer structure includes a stacked first sublayer, a second sublayer, a third sublayer, and a fourth sublayer, starting from a side close to the gate structure. After forming the metal silicide layer, the fourth sublayer and the third sublayer are removed, and a compensating doped region is formed in the substrate at the bottom of the second subsection and between the heavily doped region and the second sublayer. forming an interlayer dielectric layer on the substrate and the metal silicide layer; Etching the interlayer dielectric layer to the metal silicide layer to form a connection hole; as well as A barrier layer and a conductive structure are formed in the connection hole.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The production method further comprises the following steps: forming a bottom anti-reflective layer and a first photoresist layer on the first etch stop layer; exposing and developing the first photoresist layer and the bottom anti-reflective layer through a mask to form a first opening, wherein the first opening exposes a portion of the first etch stop layer; dry-etching the first etch-stop layer at the bottom of the first opening to form a second opening; Laterally etching the first etch-stop layer exposed by the second opening to form a third opening; and The first photoresist layer and the bottom anti-reflection layer are removed to form a fourth opening, wherein the fourth opening exposes a portion of the heavily doped region and at least a portion of the gate structure.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The mask used to form the first opening is the same as the mask used to form the connection hole.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The first section is obtained by metallization treatment of the compensation epitaxial layer and is formed protruding on the substrate. The second section is obtained by metallization treatment of the heavily doped region outside the compensation epitaxial layer and extends from the surface of the substrate into the substrate. The connection between the first section and the second section is in an arc shape.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The depth of the compensating doping region is greater than the depth of the second section.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The production method further comprises: After forming the compensating doped region, forming a second etch stop layer on the substrate; forming the interlayer dielectric layer, the hard mask layer and the photoresist mask layer in sequence on the second etch stop layer, wherein a recess is formed in the photoresist mask layer; and The hard mask layer, the interlayer dielectric layer, the second etch stop layer and a portion of the metal silicide layer exposed in the recess are etched using the photolithography mask layer as a mask to form the connection hole.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The production method further comprises: After forming the metal silicide layer, forming an interlayer dielectric layer, a hard mask layer, and a photolithography mask layer on the substrate and the metal silicide layer, wherein a recess is formed in the photolithography mask layer; and The hard mask layer, the interlayer dielectric layer and a portion of the metal silicide layer exposed in the recess are etched using the photolithography mask layer as a mask to form the connection hole.

8. A semiconductor device, characterized in that: Obtained by the production method according to any one of claims 1 to 7, comprising at least a substrate, on which a gate structure and sidewall structures on both sides of the gate structure are provided, and in which a lightly doped region and a heavily doped region are provided in the substrate on both sides of the gate structure; an etch stop layer, at least disposed on the substrate and the sidewall structure; a metal silicide layer, disposed at least on the heavily doped region and the gate structure, and protruding from surfaces of the substrate and the gate structure; an interlayer dielectric layer, disposed on the substrate and the metal silicide layer; a connection hole, provided in the interlayer dielectric layer; as well as The barrier layer and the conductive structure are arranged in the connection hole.

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