Image sensor

Abstract

An image sensor includes a pad overlapping a pad region of a substrate, and a conductive structure surrounding the pad. The conductive structure includes a conductive layer in contact with the bottom surface of the pad, and a conductive via extending from the bottom surface of the conductive layer toward the bottom surface of the substrate. The conductive layer and the conductive via have the same material. A bottom surface of the conductive via is closer to a bottom surface of the substrate than a bottom surface of the conductive layer. The bottom surface of the pad and the bottom surface of the conductive layer are between the bottom surface of the substrate and the top surface of the substrate.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0012451, filed with the Korean Intellectual Property Office on January 26, 2024, and Korean Patent Application No. 10-2024-0095524, filed with the Korean Intellectual Property Office on July 19, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present inventive concept relates to an image sensor, and more particularly, to an image sensor including a conductive layer. Background Art

[0003] An image sensor is a device that converts an optical image into an electrical signal. Image sensors can be classified into charge-coupled device (CCD) type and complementary metal-oxide-semiconductor (CMOS) type. A CMOS type image sensor is simply referred to as a CIS (CMOS image sensor). The CIS has a plurality of pixels arranged two-dimensionally. Each of the pixels includes a photodiode. The photodiode is used to convert incident light into an electrical signal. Summary of the Invention

[0004] Some embodiments of the present inventive concept provide an image sensor with improved electrical characteristics.

[0005] According to an aspect of the present disclosure, an image sensor includes: a substrate having a pixel array region and a pad region; a microlens stacked on the pixel array region; a pad stacked on the pad region; and a conductive structure surrounding the pad. The conductive structure includes: a conductive layer in contact with a bottom surface of the pad; and a conductive via extending from a bottom surface of the conductive layer toward a bottom surface of the substrate. The material of the conductive layer is the same as the material of the conductive via. A distance between the bottom surface of the substrate and the bottom surface of the conductive via is smaller than a distance between the bottom surface of the substrate and the bottom surface of the conductive layer. The distance between the bottom surface of the substrate and the bottom surface of the conductive layer is smaller than a distance between the bottom surface of the substrate and the bottom surface of the pad. The bottom surface of the pad and the bottom surface of the conductive layer are between the bottom surface and the top surface of the substrate.

[0006] According to an aspect of the present disclosure, an image sensor includes: a substrate including a pixel array region and a pad region; a microlens stacked on the pixel array region; a pad stacked on the pad region; a conductive structure surrounding the pad; and a first connection conductive structure electrically connected to the conductive structure. The conductive structure includes: a conductive layer in contact with a bottom surface of the pad; and a conductive via extending from a bottom surface of the conductive layer toward a bottom surface of the substrate. A bottom surface of the conductive via is in contact with a top surface of the first connection conductive structure. Sidewalls of the conductive via are in contact with the substrate.

[0007] According to one aspect of the present disclosure, an image sensor includes: a first substrate including a pixel array region and a pad region, wherein the pixel array region includes a photoelectric conversion region; a color filter stacked with the photoelectric conversion region; a lens layer on the color filter; a pad stacked with the pad region; a conductive structure surrounding the pad; a second substrate spaced apart from the first substrate; a first dielectric structure and a second dielectric structure in contact with each other between the first substrate and the second substrate; a first bonding pad in the first dielectric structure; a second bonding pad in the second dielectric structure and in contact with the first bonding pad; and a first connecting conductive structure and a second connecting conductive structure electrically connecting the conductive layer to the first bonding pad. The conductive structure includes: a conductive layer in contact with a bottom surface of the pad; and a conductive via between the conductive layer and the first connecting conductive structure. The material of the conductive layer is the same as that of the conductive via. The second connecting conductive structure is surrounded by the first dielectric structure. The first connecting conductive structure includes: a first portion surrounded by the first substrate; and a second portion surrounded by the first dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. shows a block diagram illustrating an image sensor according to some embodiments.

[0009] Figure 2 FIG. shows a circuit diagram illustrating an active pixel sensor array of an image sensor according to some embodiments.

[0010] Figure 3A FIG. shows a plan view illustrating an image sensor according to some embodiments.

[0011] Figure 3B FIG. shows a cross-sectional view taken along line Figure 3A A-A'

[0012] Figure 3C FIG. shows a cross-sectional view taken along line Figure 3A B-B'

[0013] Figure 3D FIG. shows an enlarged view of a portion Figure 3C E

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 5 and Figure 6 FIGS. show diagrams illustrating a method of manufacturing the image sensor depicted in Figures 3A to 3D

[0015] Figure 7 FIG. shows an enlarged cross-sectional view illustrating an image sensor according to some embodiments.

[0016] Figure 8Shows an enlarged cross-sectional view of an image sensor according to some embodiments.

[0017] Figure 9 Shows an enlarged cross-sectional view of an image sensor according to some embodiments.

[0018] Figure 10 Shows an enlarged cross-sectional view of an image sensor according to some embodiments.

[0019] Figure 11 Shows a plan view of a conductive layer and a connecting conductive structure of an image sensor according to some embodiments.

[0020] Figure 12A And Figure 12B Shows a cross-sectional view of an image sensor according to some embodiments.

[0021] Figure 13 Shows an enlarged cross-sectional view of an image sensor according to some embodiments.

[0022] Figure 14A And Figure 14B Shows a cross-sectional view of an image sensor according to some embodiments. Detailed Description

[0023] Figure 1 Shows a block diagram of an image sensor according to some embodiments. Figure 2 Shows a circuit diagram of an active pixel sensor array of an image sensor according to some embodiments.

[0024] Referring to Figure 1 , the image sensor may include an active pixel sensor array 1001, a row decoder 1002, a row driver 1003, a column decoder 1004, a timing generator 1005, a correlated double sampler (CDS) 1006, an analog-to-digital converter (ADC) 1007, and an input / output (I / O) buffer 1008.

[0025] The active pixel sensor array 1001 may include a plurality of unit pixels arranged two-dimensionally, and each of the unit pixels is configured to convert an optical signal into an electrical signal. The active pixel sensor array 1001 may be driven by a plurality of driving signals (such as a pixel selection signal, a reset signal, and a charge transfer signal) from the row driver 1003. The correlated double sampler 1006 may be provided with the converted electrical signal.

[0026] The row driver 1003 may provide a plurality of driving signals for driving a plurality of unit pixels to the active pixel sensor array 1001 according to a decoding result obtained from the row decoder 1002. When the unit pixels are arranged in a matrix shape, driving signals may be provided for each row.

[0027] The timing generator 1005 can provide timing and control signals to the row decoder 1002 and the column decoder 1004.

[0028] The correlated double sampler 1006 can receive the electrical signals generated from the active pixel sensor array 1001, and can hold and sample the received electrical signals. The correlated double sampler 1006 can perform a double sampling operation to sample the specific noise level and signal level of the electrical signals, and then can output a difference level corresponding to the difference between the noise level and the signal level.

[0029] The analog-to-digital converter 1007 can convert the analog signal corresponding to the difference level received from the correlated double sampler 1006 into a digital signal, and then output the converted digital signal.

[0030] The input / output buffer 1008 can latch the digital signal, and then sequentially output the latched digital signal to an image signal processing unit (not shown) in response to the decoding result obtained from the column decoder 1004.

[0031] Reference Figure 1 and Figure 2 As shown in FIGS. 1 and 2, the active pixel sensor array 1001 can include a plurality of unit pixels UP, and the plurality of unit pixels UP can be arranged in a matrix shape. Each unit pixel UP can include a transfer transistor TX. Each unit pixel UP can also include logic transistors RX, SX, and DX. The logic transistors RX, SX, and DX can include a reset transistor RX, a selection transistor SX, and a source follower transistor DX. The transfer transistor TX can include a transfer gate TG. Each unit pixel UP can also include a photoelectric conversion region PD and a floating diffusion region FD. The present disclosure is not limited thereto. In some embodiments, the logic transistors RX, SX, and DX can be shared by a plurality of unit pixels UP.

[0032] The photoelectric conversion region PD can generate and accumulate photo charges in proportion to the amount of external incident light. The photoelectric conversion region PD can include a photodiode, a phototransistor, a photogate, a clamped photodiode, or a combination thereof. The transfer transistor TX can transfer the charges generated in the photoelectric conversion region PD to the floating diffusion region FD. The floating diffusion region FD can accumulate and store the charges generated and transferred from the photoelectric conversion region PD. The source follower transistor DX can be controlled by the amount of photo charges accumulated in the floating diffusion region FD.

[0033] The reset transistor RX can periodically reset the charges accumulated in the floating diffusion region FD. The reset transistor RX can have a drain electrode connected to the floating diffusion region FD and a source electrode connected to the power supply voltage V DD . When the reset transistor RX is turned on, the floating diffusion region FD can be supplied with the power supply voltage V connected to the source electrode of the reset transistor RXDD Therefore, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion region FD can be exhausted (i.e., depleted), so that the floating diffusion region FD can be reset. In one embodiment, the reset transistor RX may include a reset gate electrode RG.

[0034] The source follower transistor DX including the source follower gate SF can be used as a source follower buffer amplifier. The source follower transistor DX can amplify the change in the potential of the floating diffusion region FD and output the amplified potential to the output line V OUT .

[0035] The selection transistor SX including the selection gate electrode SEL can select each row in the unit pixel UP to be read out. When the selection transistor SX is turned on, the power supply voltage V DD can be applied to the drain electrode of the source follower transistor DX.

[0036] Figure 3A FIG. shows a plan view of an image sensor according to some embodiments. Figure 3B FIG. shows a cross-sectional view taken along the line Figure 3A A-A'. Figure 3C FIG. shows a cross-sectional view taken along the line Figure 3A B-B'. Figure 3D FIG. shows an enlarged view of a portion Figure 3C E.

[0037] Referring to Figures 3A to 3C , the image sensor may include a sensor chip 10. The sensor chip 10 may include a first substrate 100. The first substrate 100 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. In one embodiment, the first direction D1 and the second direction D2 may be parallel to the upper surface of the first substrate 100.

[0038] The first substrate 100 may be a semiconductor substrate. For example, the first substrate 100 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The first substrate 100 may include impurities of a first conductivity type. For example, the first substrate 100 may include P-type impurities (such as aluminum (Al), boron (B), indium (In), and gallium (Ga)). In some embodiments, the first substrate 100 may be a silicon-on-insulator (SOI) substrate.

[0039] The first substrate 100 may include a pixel array region APS, an optical black region OBR, and a pad region PDR. The pixel array region APS, the optical black region OBR, and the pad region PDR may be regions distinguished on a plane defined by a first direction D1 and a second direction D2. The optical black region OBR may surround the pixel array region APS, and the pad region PDR may surround the optical black region OBR and the pixel array region APS.

[0040] The first substrate 100 may have a bottom surface 102 and a top surface 101 opposite to each other. The top surface 101 of the first substrate 100 may receive incident light.

[0041] The pixel array region APS of the first substrate 100 may include a plurality of pixel portions PX. The pixel portions PX of the pixel array region APS may output a photoelectric signal from the incident light. The pixel portions PX may be two-dimensionally arranged on the pixel array region APS. In one embodiment, each pixel portion PX may correspond to a unit pixel.

[0042] The pixel array region APS of the first substrate 100 may include a plurality of photoelectric conversion regions PD. The photoelectric conversion regions PD may be disposed between the top surface 101 and the bottom surface 102 of the first substrate 100. The photoelectric conversion regions PD may be correspondingly disposed in the pixel portions PX of the first substrate 100.

[0043] The photoelectric conversion region PD may include an impurity of a second conductivity type. The second conductivity type may be different from the first conductivity type. For example, the photoelectric conversion region PD may include phosphorus, arsenic, bismuth, or antimony as an impurity of the second conductivity type. The photoelectric conversion region PD may be adjacent to the top surface 101 of the first substrate 100.

[0044] The first substrate 100 may include a plurality of floating diffusion regions FD. The floating diffusion regions FD may be correspondingly disposed in the pixel portions PX of the first substrate 100. The floating diffusion regions FD may include an impurity of a second conductivity type. The floating diffusion regions FD may be adjacent to the bottom surface 102 of the first substrate 100.

[0045] The sensor chip 10 may include a pixel isolation pattern 110. The pixel isolation pattern 110 may be disposed in the first substrate 100. The pixel isolation pattern 110 may extend in a third direction D3 to penetrate the first substrate 100. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2. In one embodiment, the third direction D3 may be perpendicular to the upper surface of the first substrate 100. The pixel isolation pattern 110 may define the pixel portions PX. When viewed in a plan view, the pixel isolation pattern 110 may have, for example, a grid shape.

[0046] The pixel isolation pattern 110 may include an isolation conductive layer 111 and an isolation dielectric layer 112. The isolation conductive layer 111 may penetrate the first substrate 100. The isolation dielectric layer 112 may be interposed between the isolation conductive layer 111 and the first substrate 100. The isolation conductive layer 111 may include a conductive material. The isolation dielectric layer 112 may include a dielectric material.

[0047] The sensor chip 10 may include a device isolation pattern 120. The device isolation pattern 120 may be disposed in the first substrate 100. The device isolation pattern 120 may be disposed adjacent to the bottom surface 102 of the first substrate 100. The device isolation pattern 120 may define an active region of the first substrate 100. The device isolation pattern 120 may include a dielectric material.

[0048] The sensor chip 10 may include a first dielectric structure 150 covering the bottom surface 102 of the first substrate 100. The first dielectric structure 150 may cover the active region of the first substrate 100. The first dielectric structure 150 may include a dielectric material. In some embodiments, the first dielectric structure 150 may be a multi-layer structure including a plurality of dielectric layers.

[0049] The sensor chip 10 may include a transmission gate TG and a gate dielectric layer GI. The transmission gate TG may be disposed between the first substrate 100 and the first dielectric structure 150. The transmission gate TG may be disposed to overlap with the photoelectric conversion region PD. The transmission gate TG and the gate dielectric layer GI may penetrate the bottom surface 102 of the first substrate 100. The transmission gate TG may include a conductive material. For example, the transmission gate TG may include polysilicon doped with boron (B), arsenic (As), or phosphorus (P). The gate dielectric layer GI may be disposed between the transmission gate TG and the first substrate 100. The gate dielectric layer GI may include a dielectric material.

[0050] The first dielectric structure 150 may be provided therein with a first contact 130, a first conductive wire 140, and a first bonding pad BP1. At least one of the first contacts 130 may be connected to the floating diffusion region FD. The first conductive wire 140 may be connected to the first contact 130. The first bonding pad BP1 may be connected to the first contact 130. The first contact 130, the first conductive wire 140, and the first bonding pad BP1 may include a conductive material.

[0051] The sensor chip 10 may include a first protective layer 161 on the top surface 101 of the first substrate 100, a fixed charge layer 162 on the first protective layer 161, and a second protective layer 163 on the fixed charge layer 162. The first protective layer 161 and the fixed charge layer 162 may extend from the pixel array region APS to the optical black region OBR. The second protective layer 163 may be disposed on the pixel array region APS. In one embodiment, the first protective layer 161 and the fixed charge layer 162 may be disposed on both the pixel array region APS and the optical black region OBR. In one embodiment, the second protective layer 163 may be disposed only on the pixel array region APS. In other words, the second protective layer 163 may not be disposed on the optical black region OBR.

[0052] The first protective layer 161 and the second protective layer 163 may include a dielectric material. For example, the first protective layer 161 and the second protective layer 163 may include aluminum oxide.

[0053] The fixed charge layer 162 may have a negative fixed charge and may generate hole accumulation. The fixed charge layer 162 may effectively reduce the white dots and dark current of the first substrate 100. In some embodiments, the fixed charge layer 162 may be a multi-layer including multiple layers. For example, the fixed charge layer 162 may include a first layer containing hafnium oxide, a second layer containing silicon oxide, a third layer containing silicon nitride, and a fourth layer containing hafnium oxide.

[0054] The sensor chip 10 may include a fence pattern 164 on the fixed charge layer 162. The fence pattern 164 may be disposed on the pixel array region APS. The fence pattern 164 may separate color filters CF, which will be described later, from each other. For example, the fence pattern 164 may have a grid shape. In some embodiments, the fence pattern 164 may be a single metal layer, a single dielectric layer, or multiple layers including a metal layer and a dielectric layer. The metal layer may include, for example, tungsten. The dielectric layer may include, for example, an oxide. In some embodiments, the fence pattern 164 may further include empty spaces. The empty spaces may be filled with, for example, air.

[0055] The sensor chip 10 may include a light-shielding layer 265 on the fixed charge layer 162. The light-shielding layer 265 may be disposed on the optical black region OBR. The light-shielding layer 265 may include a conductive material. In some embodiments, the light-shielding layer 265 may include the same material as the material of the fence pattern 164. For example, the light-shielding layer 265 may include tungsten.

[0056] The sensor chip 10 may include a connection contact 266. The connection contact 266 may be disposed on the optical black region OBR. The connection contact 266 may be stacked with the pixel isolation pattern 110 in the third direction D3. The connection contact 266 may include a conductive material. For example, the connection contact 266 may include aluminum.

[0057] The sensor chip 10 may include pads 290. The pads 290 may be disposed on the pad region PDR. The pads 290 may be stacked with the pad region PDR in the third direction D3. The pads 290 may include a conductive material. For example, the pads 290 may include aluminum.

[0058] The conductive structure 280, the first material layer 271, and the second material layer 272 may be disposed to separate the pads 290 and the first substrate 100 from each other. At least a portion of each of the conductive structure 280, the first material layer 271, and the second material layer 272 may be disposed between the first substrate 100 and the pads 290. The first material layer 271 and the second material layer 272 may extend from the pad region PDR to the optical black region OBR. The conductive structure 280 may be disposed on the pad region PDR. In one embodiment, the first material layer 271 and the second material layer 272 may be disposed on both the pad region PDR and the optical black region OBR. In one embodiment, the conductive structure 280 may be disposed only on the pixel array region APS. In other words, the conductive structure 280 may not be disposed on the optical black region OBR.

[0059] In some embodiments, the conductive structure 280 may include the same conductive material as the conductive material of the light shielding layer 265. The first material layer 271 and the second material layer 272 may include different dielectric materials from each other. In some embodiments, the first material layer 271 may include the same dielectric material as the dielectric material of the first protective layer 161. In some embodiments, the second material layer 272 may include the same material as the material of the fixed charge layer 162. For example, the second material layer 272 may include a first layer containing hafnium oxide, a second layer containing silicon oxide, a third layer containing silicon nitride, and a fourth layer containing hafnium oxide.

[0060] The sensor chip 10 may include color filters CF. The color filters CF may be disposed on the pixel array region APS. The color filters CF may be stacked with the photoelectric conversion region PD of the pixel array region APS in the third direction D3. The color filters CF may be disposed on the pixel portion PX. Each of the color filters CF may be one of a red color filter, a green color filter, and a blue color filter. The color filters CF may constitute a color filter array. For example, the color filters CF may be arranged two-dimensionally in a Bayer pattern format.

[0061] The sensor chip 10 may include a third protective layer 261. The third protective layer 261 may extend from the optical black region OBR to the pad region PDR. The third protective layer 261 may be disposed on the light shielding layer 265, the connection contacts 266, and the conductive structure 280. The third protective layer 261 may separate the light shielding layer 265 and the conductive structure 280 from each other. In some embodiments, the third protective layer 261 may include the same dielectric material as the dielectric material of the second protective layer 163. For example, the third protective layer 261 may include aluminum oxide.

[0062] The sensor chip 10 may include a filter layer 262 on the third protective layer 261. The filter layer 262 may be disposed on the optical black region OBR. The filter layer 262 may block light having a wavelength different from the wavelength of the light generated from the color filter CF.

[0063] The sensor chip 10 may include a lens layer 170. The lens layer 170 may be disposed on the pixel array region APS. The lens layer 170 may be disposed on the color filter CF. The lens layer 170 may be transparent. The lens layer 170 may allow light to pass therethrough. The lens layer 170 may include an organic material. For example, the lens layer 170 may include a photoresist material or a thermosetting resin.

[0064] The lens layer 170 may include a substrate portion 173 on the color filter CF and microlenses 172 on the substrate portion 173. The microlenses 172 may protrude from the substrate portion 173 in a third direction D3. The microlenses 172 and the substrate portion 173 may be connected without a boundary. The microlenses 172 and the substrate portion 173 may constitute a single integral structure.

[0065] The microlenses 172 may be stacked with the pixel array region APS in the third direction D3. The microlenses 172 may be correspondingly disposed on the pixel portions PX. The microlenses 172 may be disposed at positions corresponding to the photoelectric conversion regions PD.

[0066] The sensor chip 10 may include a coating layer 171 on the lens layer 170. The coating layer 171 may be transparent. The coating layer 171 may conformally cover the top surface of the lens layer 170.

[0067] The sensor chip 10 may include a first cover layer 263 and a second cover layer 264. The first cover layer 263 and the second cover layer 264 may be disposed on the optical black region OBR and the pad region PDR. The first cover layer 263 may be disposed on the filter layer 262 and the third protective layer 261. The first cover layer 263 may include the same material as the material of the lens layer 170.

[0068] The second cover layer 264 may be disposed on the first cover layer 263. The second cover layer 264 may include the same material as the material of the coating layer 171.

[0069] The sensor chip 10 may include a first connecting conductive structure 220 in contact with the conductive structure 280, a second connecting conductive structure 230 correspondingly in contact with the first connecting conductive structure 220, a third connecting conductive structure 240 in contact with the second connecting conductive structure 230, and a fourth connecting conductive structure 250 in contact with the third connecting conductive structure 240. The first connecting conductive structure 220, the second connecting conductive structure 230, the third connecting conductive structure 240, and the fourth connecting conductive structure 250 may be sequentially arranged in a direction opposite to the third direction D3. The first connecting conductive structure 220, the second connecting conductive structure 230, the third connecting conductive structure 240, and the fourth connecting conductive structure 250 may include a conductive material. The first connecting conductive structure 220, the second connecting conductive structure 230, the third connecting conductive structure 240, and the fourth connecting conductive structure 250 may be surrounded by a first dielectric structure 150.

[0070] The sensor chip 10 may include a first dielectric layer 210 between the first dielectric structure 150 and the first substrate 100. The first dielectric layer 210 may surround the first connecting conductive structure 220. The first dielectric layer 210 may include a dielectric material. For example, the first dielectric layer 210 may include an oxide (such as silicon oxide).

[0071] The image sensor may include a sub-chip 30. The sub-chip 30 may include a second substrate 300. The second substrate 300 may be a semiconductor substrate. In some embodiments, the second substrate 300 may be a silicon-on-insulator (SOI) substrate. The second substrate 300 may be spaced apart from the first substrate 100 in the third direction D3.

[0072] The sub-chip 30 may include a second dielectric structure 310 on the second substrate 300. The second dielectric structure 310 may cover the active region of the second substrate 300. The second dielectric structure 310 may include a dielectric material. In some embodiments, the second dielectric structure 310 may be a multi-layer structure including a plurality of dielectric layers.

[0073] The sub-chip 30 may include a first electronic component 320 between the second substrate 300 and the second dielectric structure 310. The first electronic component 320 may include at least one selected from a selection transistor, a reset transistor, and a source follower transistor.

[0074] The sub-chip 30 may include second contacts 330, second conductive wires 340, and second bonding pads BP2 in the second dielectric structure 310. At least one of the second contacts 330 may be connected to the first electronic component 320. The second conductive wires 340 may be connected to the second contacts 330. The second bonding pads BP2 may be connected to the second contacts 330. The second contacts 330, the second conductive wires 340, and the second bonding pads BP2 may include a conductive material.

[0075] The sensor chip 10 can be hybrid bonded to the sub-chip 30. The bottom surface of the first dielectric structure 150 can be in contact with the top surface of the second dielectric structure 310. The first dielectric structure 150 and the second dielectric structure 310 can be disposed between the first substrate 100 and the second substrate 300. The bottom surface of the first bonding pad BP1 can be in contact with the top surface of the second bonding pad BP2.

[0076] The sub-chip 30 can further include a spacer 360 and a through-hole 350. The spacer 360 can be disposed in the second substrate 300. The spacer 360 can penetrate through the second substrate 300 in the third direction D3. The spacer 360 can include a dielectric material. For example, the spacer 360 can include silicon oxide or silicon nitride.

[0077] The through-hole 350 can be disposed in the spacer 360. The through-hole 350 can penetrate through the second substrate 300 and the spacer 360 in the third direction D3. The spacer 360 can surround the through-hole 350. The spacer 360 can separate the through-hole 350 from the second substrate 300. The through-hole 350 can include a conductive material. For example, the through-hole 350 can include copper. The through-hole 350 can be connected to the second contact 330.

[0078] The image sensor can include a circuit chip 50. The circuit chip 50 can include a third substrate 500. The third substrate 500 can be a semiconductor substrate. In some embodiments, the third substrate 500 can be a silicon-on-insulator (SOI) substrate. The third substrate 500 can be spaced apart from the second substrate 300 in the third direction D3.

[0079] The circuit chip 50 can include a third dielectric structure 510 on the third substrate 500. The third dielectric structure 510 can cover the active region of the third substrate 500. The third dielectric structure 510 can include a dielectric material. In some embodiments, the third dielectric structure 510 can be a multi-layer structure including a plurality of dielectric layers.

[0080] The circuit chip 50 can include a second electronic component 520 between the third substrate 500 and the third dielectric structure 510. The second electronic component 520 can include at least one selected from an analog-to-digital converter and a logic circuit.

[0081] The circuit chip 50 can include a third bonding pad BP3, a third contact 530, and a third conductive wire 540 in the third dielectric structure 510. The third contact 530 can be connected to the second electronic component 520. The third bonding pad BP3 can be connected to the through-hole 350 and the third contact 530. The top surface of the third bonding pad BP3 can be in contact with the bottom surface of the through-hole 350. The third conductive wire 540 can be connected to the third contact 530. The third contact 530 and the third conductive wire 540 can include a conductive material.

[0082] The top surface of the third dielectric structure 510 may be in contact with the bottom surface of the second substrate 300. The conductive structure 280 may be electrically connected to the second electronic component 520 through the first connecting conductive structure 220, the second connecting conductive structure 230, the third connecting conductive structure 240, the fourth connecting conductive structure 250, the first contact 130, the first bonding pad BP1, the second bonding pad BP2, the second contact 330, the second conductive wire 340, the vias 350, the third bonding pad BP3, the third contact 530, and the third conductive wire 540.

[0083] Referring to Figure 3D , the first dielectric structure 150 may include a first interlayer dielectric layer 151, a second interlayer dielectric layer 152 on the first interlayer dielectric layer 151, a third interlayer dielectric layer 153 on the second interlayer dielectric layer 152, a fourth interlayer dielectric layer 154 on the third interlayer dielectric layer 153, a fifth interlayer dielectric layer 155 on the fourth interlayer dielectric layer 154, a sixth interlayer dielectric layer 156 on the fifth interlayer dielectric layer 155, and a second dielectric layer 157 on the sixth interlayer dielectric layer 156. The first interlayer dielectric layer 151 to the sixth interlayer dielectric layer 156 and the second dielectric layer 157 may include a dielectric material. The second dielectric layer 157 may include, for example, an oxide (such as silicon oxide) or a nitride (such as silicon nitride).

[0084] The fourth connecting conductive structure 250 may penetrate through the third interlayer dielectric layer 153 and the fourth interlayer dielectric layer 154. The fourth connecting conductive structure 250 may include a barrier layer 251 and a metal layer 252. The barrier layer 251 of the fourth connecting conductive structure 250 may be in contact with the third connecting conductive structure 240. The metal layer 252 of the fourth connecting conductive structure 250 may be in contact with the first contact 130. The barrier layer 251 of the fourth connecting conductive structure 250 may surround the metal layer 252 of the fourth connecting conductive structure 250. The barrier layer 251 and the metal layer 252 of the fourth connecting conductive structure 250 may include different conductive materials. For example, the metal layer 252 of the fourth connecting conductive structure 250 may include copper, and the barrier layer 251 of the fourth connecting conductive structure 250 may include titanium.

[0085] The fourth connecting conductive structure 250 may include a lower portion and a plurality of upper portions. The upper portions of the fourth connecting conductive structure 250 may be connected to the lower portion of the fourth connecting conductive structure 250. The upper portions of the fourth connecting conductive structure 250 may be in contact with the third connecting conductive structure 240. A portion of the third interlayer dielectric layer 153 may be interposed between the upper portions of the fourth connecting conductive structure 250. A portion of the fourth interlayer dielectric layer 154 may be interposed between the upper portions of the fourth connecting conductive structure 250. The lower portion of the fourth connecting conductive structure 250 may have a width that decreases as the distance from the bottom surface 102 of the first substrate 100 decreases in the first direction D1.

[0086] The third connecting conductive structure 240 may penetrate the fifth interlayer dielectric layer 155. The third connecting conductive structure 240 may include a barrier layer 241 and a metal layer 242. The barrier layer 241 of the third connecting conductive structure 240 may be in contact with the second connecting conductive structure 230. The metal layer 242 of the third connecting conductive structure 240 may be in contact with the barrier layer 251 of the fourth connecting conductive structure 250. The barrier layer 241 of the third connecting conductive structure 240 may surround the metal layer 242 of the third connecting conductive structure 240. The barrier layer 241 and the metal layer 242 of the third connecting conductive structure 240 may include different conductive materials. For example, the metal layer 242 of the third connecting conductive structure 240 may include copper, and the barrier layer 241 of the third connecting conductive structure 240 may include titanium. The third connecting conductive structure 240 may have a width that decreases as the distance from the bottom surface 102 of the first substrate 100 decreases in the first direction D1.

[0087] The second connecting conductive structure 230 may penetrate the sixth interlayer dielectric layer 156 and the second dielectric layer 157. The second connecting conductive structures 230 may be arranged spaced apart from each other in the first direction D1. The bottom surface of the second connecting conductive structure 230 may be in contact with the top surface of the third connecting conductive structure 240. The second connecting conductive structure 230 may include a conductive material different from that of the third connecting conductive structure 240. For example, the second connecting conductive structure 230 may include tungsten.

[0088] The width of the second connecting conductive structure 230 in the first direction D1 may decrease as the distance from the bottom surface 102 of the first substrate 100 decreases. The width of the second connecting conductive structure 230 in the first direction D1 may be smaller than the width of the third connecting conductive structure 240 in the first direction D1.

[0089] The first connecting conductive structures 220 may be arranged to be spaced apart from each other in the first direction D1. The first connecting conductive structures 220 may penetrate the bottom surface 102 of the first substrate 100. The first connecting conductive structures 220 may include a portion located at a height lower than the height of the bottom surface 102 of the first substrate 100 and a portion located at a height higher than the height of the bottom surface 102 of the first substrate 100. The first connecting conductive structures 220 may be stacked with the second connecting conductive structures 230 in the third direction D3. The width of the first connecting conductive structures 220 in the first direction D1 may be smaller than the width of the third connecting conductive structures 240 in the first direction D1. In some embodiments, the first connecting conductive structures 220 may include the same conductive material as the second connecting conductive structures 230. For example, the first connecting conductive structures 220 and the second connecting conductive structures 230 may include tungsten. In some embodiments, the first connecting conductive structures 220 may include a different conductive material from the second connecting conductive structures 230. For example, the first connecting conductive structures 220 may include polysilicon doped with boron (B), arsenic (As), or phosphorus (P), and the second connecting conductive structures 230 may include tungsten. In some embodiments, the first connecting conductive structures 220 may include the same conductive material as the conductive material of the transmission gate TG.

[0090] The first connecting conductive structure 220 may include a first portion 222 and a second portion 221 on the first portion 222. The width (e.g., the maximum width) of the first portion 222 included in the first connecting conductive structure 220 in the first direction D1 may be larger than the width (e.g., the maximum width) of the second portion 221 included in the first connecting conductive structure 220 in the first direction D1. The width of the second portion 221 included in the first connecting conductive structure 220 in the first direction D1 may decrease as the distance from the bottom surface 283_B of the third conductive portion 283 decreases, which will be discussed below.

[0091] The second dielectric layer 157 may be in contact with the sidewall 222_S and the bottom surface 222_B of the first portion 222 included in the first connecting conductive structure 220. The first dielectric layer 210 may be in contact with the sidewall 221_S of the second portion 221 included in the first connecting conductive structure 220 and in contact with the top surface 222_T of the first portion 222 included in the first connecting conductive structure 220. The first dielectric layer 210 may be in contact with the bottom surface 102 of the first substrate 100. The top surface 210_T of the first dielectric layer 210 may be in contact with the bottom surface 283_B of the third conductive portion 283. In some embodiments, the first dielectric layer 210 may be spaced apart from the bottom surface 283_B of the third conductive portion 283, and at least a portion of the sidewall 221_S of the second portion 221 in the first connecting conductive structure 220 may be in contact with the first substrate 100. The top surface 221_T of the second portion 221 included in the first connecting conductive structure 220 may be in contact with the bottom surface 283_B of the third conductive portion 283. The width of the top surface 221_T of the second portion 221 included in the first connecting conductive structure 220 in the first direction D1 may be smaller than the width of the bottom surface 283_B of the third conductive portion 283 in the first direction D1. The first portion 222 of the first connecting conductive structure 220 may be surrounded by the second dielectric layer 157 of the first dielectric structure 150. The second portion 221 of the first connecting conductive structure 220 may be surrounded by the first substrate 100 and the first dielectric layer 210.

[0092] The first connecting conductive structure 220 may be located at the same height as the height of the transmission gate TG. The bottom surface 222_B of the first portion 222 included in the first connecting conductive structure 220 may be located at the same height as the height of the bottom surface of the transmission gate TG. The top surface 221_T of the second portion 221 included in the first connecting conductive structure 220 may be located at the same height as the height of the top surface of the transmission gate TG. The width of the first portion 222 included in the first connecting conductive structure 220 in the first direction D1 may be larger than the width of the second connecting conductive structure 230 in the first direction D1.

[0093] The second dielectric layer 157 may include a portion interposed between the first portions 222 of the first connecting conductive structure 220. The sixth interlayer dielectric layer 156 may include a portion interposed between the first portions 222 of the first connecting conductive structure 220.

[0094] The recess RS may be defined in the pad region PDR of the first substrate 100. The recess RS may be defined as being recessed from the top surface 101 of the first substrate 100. The recess RS may be connected to the top surface 101 of the first substrate 100. The recess RS may be located at a height lower than the height of the top surface 101 of the first substrate 100. The bottom surface and the sidewall of the recess RS may be defined by the surface of the first substrate 100.

[0095] The hole HO may be defined on the pad region PDR of the first substrate 100. The hole HO may be connected to the recess RS. The hole HO may be located at a height lower than the height of the recess RS. The sidewall of the hole HO may be defined by the surface of the first substrate 100. The bottom surface of the hole HO may be defined by the surface of the first substrate 100, the top surface 221_T of the second part 221 included in the first connecting conductive structure 220, and the top surface 210_T of the first dielectric layer 210. The width of the hole HO in the first direction D1 may be smaller than the width of the recess RS in the first direction D1.

[0096] The conductive structure 280 may include a first conductive part 281, a second conductive part 282 (i.e., a conductive layer), and a third conductive part 283 (i.e., a conductive via). The second conductive part 282 may be disposed in the recess RS. The second conductive part 282 may be located at a height lower than the height of the top surface 101 of the first substrate 100. The first conductive part 281 may be located at a height higher than the height of the top surface 101 of the first substrate 100. The third conductive part 283 may completely fill the hole HO. The third conductive part 283 may be connected to the second conductive part 282. In some embodiments, the first conductive part 281, the second conductive part 282, and the third conductive part 283 may have the same material. For ease of description, the first conductive part 281, the second conductive part 282, and the third conductive part 283 are explained as being distinct from each other, but the first conductive part 281, the second conductive part 282, and the third conductive part 283 may be connected to have a single integral structure without any boundary therebetween.

[0097] The first material layer 271 may be disposed between the first substrate 100 and the second material layer 272. The first material layer 271 may include a first part P1 in contact with the top surface 101 of the first substrate 100 and a second part P2 in the recess RS. The second material layer 272 may include a first part P3 on the first part P1 of the first material layer 271 and a second part P4 in the recess RS.

[0098] The first conductive portion 281 may be disposed on the first portion P3 of the second material layer 272. The second conductive portion 282 may be disposed in the second portion P4 of the second material layer 272. The bottom surface 282_B and the sidewalls of the second conductive portion 282 may be in contact with the second portion P4 of the second material layer 272. The third conductive portion 283 may penetrate through the second portion P2 of the first material layer 271 and the second portion P4 of the second material layer 272. The sidewalls 283_S of the third conductive portion 283 may be in contact with the second portion P4 of the second material layer 272 and the second portion P2 of the first material layer 271. The first material layer 271 and the second material layer 272 may separate the first conductive portion 281 and the second conductive portion 282 from the first substrate 100. The sidewalls 283_S of the third conductive portion 283 may be in contact with the pad region PDR of the first substrate 100.

[0099] The conductive structure 280 may surround the pad 290. The first conductive portion 281 may be in contact with the sidewall of the pad 290. The second conductive portion 282 may be in contact with the sidewall and the bottom surface 290_B of the pad 290. The third conductive portion 283 may protrude from the bottom surface 282_B of the second conductive portion 282 toward the bottom surface 102 of the first substrate 100. The third conductive portion 283 may be spaced apart from the pad 290.

[0100] The third conductive portions 283 may be arranged spaced apart from each other in the first direction D1. The second portion P2 of the first material layer 271 and the second portion P4 of the second material layer 272 may each include portions interposed between the third conductive portions 283. The third conductive portions 283 may be stacked with the first connection conductive structure 220, the second connection conductive structure 230, and the pad 290 in the third direction D3. The width of the third conductive portion 283 in the first direction D1 may decrease as the distance from the bottom surface 102 of the first substrate 100 decreases. The width of the third conductive portion 283 in the first direction D1 may decrease as the distance from the top surface 221_T of the second portion 221 included in the first connection conductive structure 220 decreases.

[0101] The length of the third conductive portion 283 in the third direction D3 may be greater than the length of each of the first connection conductive structure 220 and the second connection conductive structure 230 in the third direction D3. The third conductive portion 283 may be disposed between the second conductive portion 282 and the first connection conductive structure 220. The width of the third conductive portion 283 in the first direction D1 may be smaller than the width of the third connection conductive structure 240 in the first direction D1.

[0102] The pad 290 may be superimposed on the pad region PDR in the third direction D3. The distance in the third direction D3 between the bottom surface 282_B of the second conductive portion 282 and the bottom surface 102 of the first substrate 100 may be smaller than the distance in the third direction D3 between the bottom surface 290_B of the pad 290 and the bottom surface 102 of the first substrate 100. The distance in the third direction D3 between the bottom surface 283_B of the third conductive portion 283 and the bottom surface 102 of the first substrate 100 may be smaller than the distance in the third direction D3 between the bottom surface 282_B of the second conductive portion 282 and the bottom surface 102 of the first substrate 100.

[0103] The bottom surface 290_B of the pad 290, the bottom surface 282_B of the second conductive portion 282, and the bottom surface 283_B of the third conductive portion 283 may be disposed between the top surface 101 and the bottom surface 102 of the first substrate 100.

[0104] In an image sensor according to some embodiments, the pad 290 and the third connection conductive structure 240 may be connected through the conductive structure 280, the first connection conductive structure 220, and the second connection conductive structure 230. Accordingly, the third conductive portion 283, the first connection conductive structure 220, and the second connection conductive structure 230 may have a relatively large length and improved reliability.

[0105] In an image sensor according to some embodiments, since the third conductive portion 283, the first connection conductive structure 220, and the second connection conductive structure 230 are superimposed on the pad 290 in the third direction D3, a minimized space may be provided to the structure that electrically connects the third connection conductive structure 240 and the pad 290 to each other, and the image sensor may be minimized in size.

[0106] Figure 4A , Figure 4B , Figure 4C , Figure 5 and Figure 6 shows a diagram showing a method of manufacturing Figures 3A to 3D the image sensor depicted in Figure 4A may correspond to Figure 3B correspond. Figure 4B may correspond to Figure 3C correspond. Figure 4C , Figure 5 and Figure 6 may correspond to Figure 3D correspond.

[0107] Referring to Figure 4A , Figure 4B and Figure 4C , the sub-chip 30 may be formed on the circuit chip 50.

[0108] A sensor chip 10 can be formed. The formation of the sensor chip 10 may include: forming a pixel isolation pattern 110 to penetrate the first substrate 100, forming a photoelectric conversion region PD in the pixel array region APS of the first substrate 100, and forming a first dielectric layer 210, a floating diffusion region FD, a gate dielectric layer GI, a transfer gate TG, a first connection conductive structure 220, a second connection conductive structure 230, a third connection conductive structure 240, a fourth connection conductive structure 250, a first contact 130, a first conductive line 140, a first bonding pad BP1, and a first dielectric structure 150 on the bottom surface 102 of the first substrate 100.

[0109] The sensor chip 10 can be hybrid bonded to the sub-chip 30. The top surface 101 of the first substrate 100 can be etched to form a recess RS. A first preliminary layer LA1 can be formed on the first substrate 100. A second preliminary layer LA2 can be formed on the first preliminary layer LA1. A part of each of the first preliminary layer LA1 and the second preliminary layer LA2 can be disposed in the recess RS.

[0110] The first preliminary layer LA1 may include a dielectric material. For example, the first preliminary layer LA1 may include alumina. In some embodiments, the second preliminary layer LA2 may be a multi-layer including multiple layers. For example, the second preliminary layer LA2 may include a first layer containing hafnium oxide, a second layer containing silicon oxide, a third layer containing silicon nitride, and a fourth layer containing hafnium oxide.

[0111] Referring to Figure 5 , a hole HO can be formed. The first preliminary layer LA1, the second preliminary layer LA2, and the first substrate 100 can be etched through the recess RS to form the hole HO. The hole HO can expose the top surface 221_T of the first connection conductive structure 220 and the top surface 210_T of the first dielectric layer 210.

[0112] The length of the hole HO in the third direction D3 can be smaller than the length of the first substrate 100 in the third direction D3.

[0113] Referring to Figure 6 , a conductive structure 280 can be formed. The conductive structure 280 can be formed by, for example, a deposition process. The third conductive part 283 of the conductive structure 280 can completely fill the hole HO. In some embodiments, the third conductive part 283 of the conductive structure 280 can only fill a part of the hole HO.

[0114] Referring to Figures 3A to 3D, the first preliminary layer LA1 can be divided into a first protective layer 161 and a first material layer 271. The second preliminary layer LA2 can be divided into a fixed charge layer 162 and a second material layer 272. A fence pattern 164 and a light-shielding layer 265 can be formed. In some embodiments, the formation of the fence pattern 164, the light-shielding layer 265, and the conductive structure 280 can include forming a preliminary conductive layer and dividing the preliminary conductive layer into the fence pattern 164, the light-shielding layer 265, and the conductive structure 280. A connection contact 266 can be formed on the light-shielding layer 265.

[0115] A second protective layer 163 and a third protective layer 261 can be formed. A color filter CF and a light-filtering layer 262 can be formed. A lens layer 170, a coating layer 171, a first cover layer 263, and a second cover layer 264 can be formed. In some embodiments, the lens layer 170 and the first cover layer 263 can be formed simultaneously. The coating layer 171 and the second cover layer 264 can be formed simultaneously.

[0116] In a method of manufacturing an image sensor according to some embodiments, since the hole HO exposes the first connection conductive structure 220 that does not include copper, there can be a relative improvement in the oxidation of the conductive structure electrically connected to the pad 290.

[0117] In a method of manufacturing an image sensor according to some embodiments, since the hole HO is completely filled with the third conductive portion 283, the hole HO can be prevented from being filled with a process material for forming the color filter CF.

[0118] In a method of manufacturing an image sensor according to some embodiments, since the hole HO has a length smaller than the length of the first substrate 100, there can be an improvement in the process margin of the process of forming the hole HO.

[0119] In a method of manufacturing an image sensor according to some embodiments, only the first preliminary layer LA1, the second preliminary layer LA2, and the first substrate 100 can be etched to form the hole HO, so the manufacturing process can be simplified.

[0120] Figure 7 An enlarged cross-sectional view showing an image sensor according to some embodiments is shown. Except for the following description, Figure 7 the image sensor can be similar to Figures 3A to 3D the image sensor.

[0121] Referring to Figure 7 , the first connection conductive structure 220a can be surrounded by the first dielectric layer 210. The bottom surface 220a_B of the first connection conductive structure 220a can contact the top surface 157a_T of the second dielectric layer 157a included in the first dielectric structure 150a. The second dielectric layer 157a can have a flat top surface 157a_T and a flat bottom surface.

[0122] Each of the first conductive portion 281a, the second conductive portion 282a, and the third conductive portion 283a of the conductive structure 280a may include a barrier layer BL and a metal layer CL. The barrier layer BL and the metal layer CL may include different conductive materials from each other. For example, the metal layer CL may include tungsten, and the barrier layer BL may include titanium.

[0123] The barrier layers BL of the first conductive portion 281a, the second conductive portion 282a, and the third conductive portion 283a may be connected to have a single integral structure without any boundary therebetween. The metal layers CL of the first conductive portion 281a, the second conductive portion 282a, and the third conductive portion 283a may be connected to have a single integral structure without any boundary therebetween.

[0124] The metal layers CL of the third conductive portion 283a may be spaced apart from each other in the first direction D1. The metal layers CL of the third conductive portion 283a may be stacked with the pad 290 in the third direction D3.

[0125] Figure 8 An enlarged cross-sectional view showing an image sensor according to some embodiments is shown. Except as described below, Figure 8 the image sensor may be similar to Figures 3A to 3D the image sensor.

[0126] Referring to Figure 8 , the first dielectric layer 210b may include a first portion 211b, a second portion 212b on the first portion 211b, and a third portion 213b on the second portion 212b.

[0127] The first portion 211b of the first dielectric layer 210b may be in contact with the second dielectric layer 157. The second portion 212b of the first dielectric layer 210b may surround the plurality of first connection conductive structures 220. The third portion 213b of the first dielectric layer 210b may correspondingly surround the first connection conductive structures 220.

[0128] The width of the second portion 212b included in the first dielectric layer 210b in the first direction D1 may be larger than the sum of the widths of the first connection conductive structures 220 in the first direction D1. The width of the second portion 212b included in the first dielectric layer 210b in the first direction D1 may be larger than the sum of the widths of the third portion 213b included in the first dielectric layer 210b in the first direction D1.

[0129] Figure 9 An enlarged cross-sectional view showing an image sensor according to some embodiments is shown. Except as described below, Figure 9 the image sensor may be similar to Figures 3A to 3D the image sensor.

[0130] Reference Figure 9 Referring to Figure 9 , the sidewall 290c_S of the pad 290c can be spaced apart from the conductive structure 280c. The sidewall 290c_S of the pad 290c can be spaced apart from the first conductive portion 281c and the second conductive portion 282c of the conductive structure 280c.

[0131] The pad 290c can be disposed between the third conductive portions 283c of the conductive structure 280c. The third conductive portions 283c can be disposed on opposite sides of the pad 290c. The pad 290c can be disposed between the third conductive portion 283c on one side of the pad 290c and the third conductive portion 283c on the other side of the pad 290c. In one embodiment, when viewed in a plan view, the pad 290c can be disposed in a region between two adjacent conductive vias (i.e., the third conductive portions) 283c among a plurality of conductive vias 283c.

[0132] The pad 290c can be disposed between the first connection conductive structures 220c. The first connection conductive structures 220c can be disposed on opposite sides of the pad 290c. The pad 290c can be disposed between the first connection conductive structure 220c on one side of the pad 290c and the first connection conductive structure 220c on the other side of the pad 290c.

[0133] The pad 290c can be disposed between the second connection conductive structures 230c. The second connection conductive structures 230c can be disposed on opposite sides of the pad 290c. The pad 290c can be disposed between the second connection conductive structure 230c on one side of the pad 290c and the second connection conductive structure 230c on the other side of the pad 290c.

[0134] None of the third conductive portion 283c, the first connection conductive structure 220c, and the second connection conductive structure 230c can be stacked with the pad 290c in the third direction D3. The third conductive portion 283c, the first connection conductive structure 220c, and the second connection conductive structure 230c can be spaced apart from the pad 290c in the first direction D1.

[0135] Figure 10 An enlarged cross-sectional view of an image sensor showing according to some embodiments is shown. Except as described below, Figure 10 the image sensor can be similar to Figures 3A to 3D the image sensor of

[0136] Reference Figure 10 Referring to Figure 10 , a first connection conductive structure 220d can be disposed between a plurality of third conductive portions 283 and a plurality of second connection conductive structures 230. The plurality of third conductive portions 283 can be in contact with the first connection conductive structure 220d. The plurality of second connection conductive structures 230 can be in contact with the first connection conductive structure 220d.

[0137] In some embodiments, the conductive structure 280 may include a third conductive portion 283. In some embodiments, the third connecting conductive structure 240 may be connected to the second connecting conductive structure 230.

[0138] Figure 11 A plan view showing a conductive layer and a connecting conductive structure of an image sensor according to some embodiments is shown. In addition to the following description, Figure 11 the image sensor may be similar to Figures 3A to 3D the image sensor.

[0139] Referring to Figure 11 , the third conductive portion 283e of the conductive structure 280e may have a strip shape extending in the second direction D2. The first connecting conductive structure 220e may have a cylindrical shape. The second connecting conductive structure 230e may include a first portion 231e extending in the first direction D1 and a second portion 232e extending in the second direction D2. The second connecting conductive structure 230e may have a grid shape in which the first portion 231e intersects the second portion 232e.

[0140] In some embodiments, the third conductive portion 283e may have a cylindrical shape or a grid shape. The first connecting conductive structure 220e may have a strip shape or a grid shape. The second connecting conductive structure 230e may have a cylindrical shape or a strip shape.

[0141] Figure 12A and Figure 12B A cross-sectional view showing an image sensor according to some embodiments is shown. In addition to the following description, Figure 12A and Figure 12B the image sensor may be similar to Figures 3A to 3D the image sensor.

[0142] Referring to Figure 12A and Figure 12B , the sensor chip 10 may be hybrid bonded to the circuit chip 30f. The circuit chip 30f may include a second substrate 300f, electronic components 320f, second contacts 330f, second conductive wires 340f, second bonding pads BP2f, and a second dielectric structure 310f. The electronic components 320f may include at least one selected from an analog-to-digital converter, a memory circuit, and a logic circuit. The second bonding pad BP2f may be in contact with the first bonding pad BP1. The second dielectric structure 310f may be in contact with the first dielectric structure 150.

[0143] Figure 13 An enlarged cross-sectional view showing an image sensor according to some embodiments is shown. In addition to the following description, Figure 13 the image sensor may be similar to Figures 3A to 3D the image sensor.

[0144] Reference Figure 13 Referring to Figure 13 , the third conductive portion 283g of the conductive structure 280g can penetrate the bottom surface 102 of the first substrate 100. The third conductive portion 283g of the conductive structure 280g can have a bottom surface 283g_B that contacts the top surface 220g_T of the first connecting conductive structure 220g. The first dielectric layer 210g can contact the bottom surface 102 of the first substrate 100, the sidewall 283g_S of the third conductive portion 283g, and the top surface 220g_T of the first connecting conductive structure 220g. The bottom surface 210g_B of the first dielectric layer 210g can contact the top surface 220g_T of the first connecting conductive structure 220g.

[0145] The first dielectric layer 210g can have a flat bottom surface 210g_B and a flat top surface. The third conductive portion 283g can penetrate the first dielectric layer 210g.

[0146] Figure 14A and Figure 14B shows a cross-sectional view of an image sensor according to some embodiments. Except as discussed below, the image sensor according to Figure 14A and Figure 14B can be substantially the same as or similar to the image sensor according to Figures 3A to 3D .

[0147] Reference Figure 14A and Figure 14B Referring to Figure 14A and Figure 14B , the sub-chip 30h can include a second substrate 300h, a second dielectric structure 310h, a third dielectric structure 311h, a first electronic component 320h, a second contact 330h, a second conductive wire 340h, a via hole 350h, a spacer 360h, a second bonding pad BP2h, and a third bonding pad BP3h.

[0148] The first electronic component 320h can be disposed on the bottom surface of the second substrate 300h. The second dielectric structure 310h can cover the first electronic component 320h. The second dielectric structure 310h can contact the bottom surface of the second substrate 300h.

[0149] The third dielectric structure 311h can contact the top surface of the second substrate 300h. The second substrate 300h can be disposed between the second dielectric structure 310h and the third dielectric structure 311h. The third dielectric structure 311h can include a dielectric material. In some embodiments, the third dielectric structure 311h can be a multi-layer structure including a plurality of dielectric layers.

[0150] The second bonding pad BP2h can be disposed in the third dielectric structure 311h. The top surface of the third dielectric structure 311h can contact the bottom surface of the first dielectric structure 150. The top surface of the second bonding pad BP2h can contact the bottom surface of the first bonding pad BP1.

[0151] The spacer 360h may penetrate through the second substrate 300h in the third direction D3. The spacer 360h may include a dielectric material. The through hole 350h may penetrate through the second substrate 300h and the spacer 360h in the third direction D3. The through hole 350h may be connected to the second bonding pad BP2h and the second conductive line 340h. The through hole 350h may include a conductive material different from the conductive material of the second bonding pad BP2h. For example, the through hole 350h may include tungsten.

[0152] The third bonding pad BP3h may be disposed in the second dielectric structure 310h. The third bonding pad BP3h may be connected to the second contact 330h.

[0153] The circuit chip 50h may include a third substrate 500h, a fourth dielectric structure 510h, a second electronic component 520h, a third contact 530h, a third conductive line 540h, and a fourth bonding pad BP4h.

[0154] The fourth bonding pad BP4h may be connected to the third bonding pad BP3h and the third contact 530h. The top surface of the fourth bonding pad BP4h may be in contact with the bottom surface of the third bonding pad BP3h. The bottom surface of the second dielectric structure 310h may be in contact with the top surface of the fourth dielectric structure 510h.

[0155] In an image sensor according to some embodiments of the inventive concept, minimized space may be provided to structures electrically connected to pads, and the image sensor may be minimized in size.

[0156] In a method of manufacturing an image sensor according to some embodiments of the inventive concept, a process for forming a hole that completely penetrates a substrate may be omitted to improve process margins.

[0157] Those skilled in the art will understand that the inventive concept may be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive. In addition, the embodiments discussed above may be combined with each other.

Claims

1. An image sensor, comprising: A substrate including a pixel array region and a pad region; A microlens stacked with the pixel array region; A pad stacked with the pad region; And A conductive structure surrounding the pad, Wherein, the conductive structure includes: A conductive layer in contact with the bottom surface of the pad, and A conductive via extending from the bottom surface of the conductive layer towards the bottom surface of the substrate, Wherein, the material of the conductive layer is the same as that of the conductive via, Wherein, the distance between the bottom surface of the substrate and the bottom surface of the conductive via is smaller than the distance between the bottom surface of the substrate and the bottom surface of the conductive layer, Wherein, the distance between the bottom surface of the substrate and the bottom surface of the conductive layer is smaller than the distance between the bottom surface of the substrate and the bottom surface of the pad, and Wherein, the bottom surfaces of the pad and the conductive layer are between the bottom surface and the top surface of the substrate.

2. The image sensor according to claim 1, further comprising: A connecting conductive structure penetrating the bottom surface of the substrate, Wherein, the bottom surface of the conductive via is in contact with the top surface of the connecting conductive structure.

3. The image sensor according to claim 2, further comprising: A first dielectric layer in contact with the sidewall of the connecting conductive structure, the bottom surface of the substrate, and the bottom surface of the conductive via.

4. The image sensor according to claim 2, Among them, The connecting conductive structure includes a first part and a second part on the first part, Wherein, the maximum width of the second part of the connecting conductive structure is smaller than the maximum width of the first part of the connecting conductive structure, and Wherein, the second part of the connecting conductive structure has a width decreasing from the bottom surface of the conductive via towards the pad.

5. The image sensor according to claim 2, Among them, The connecting conductive structure includes polysilicon.

6. The image sensor according to claim 1, Among them, The pad region of the substrate defines a depression and a hole, Wherein, the depression is connected to the top surface of the substrate, Wherein, the hole is connected to the depression, Wherein, the width of the hole is smaller than the width of the depression, Wherein, the conductive layer is in the depression, and Wherein, the conductive via completely fills the hole.

7. The image sensor according to any one of claims 1 to 6, Among them, The conductive layer is spaced apart from the substrate, and Wherein, the sidewall of the conductive via is in contact with the substrate.

8. An image sensor, comprising: A substrate including a pixel array region and a pad region; A microlens stacked with the pixel array region; A pad stacked with the pad region; A conductive structure surrounding the pad; And A first connecting conductive structure electrically connected to the conductive structure, Wherein, the conductive structure includes: A conductive layer in contact with the bottom surface of the pad, and A conductive via extending from the bottom surface of the conductive layer towards the bottom surface of the substrate, Wherein, the bottom surface of the conductive via is in contact with the top surface of the first connecting conductive structure, and Wherein, the sidewall of the conductive via is in contact with the substrate.

9. The image sensor according to claim 8, Among them, The conductive via has a width increasing from the top surface of the first connecting conductive structure towards the pad.

10. The image sensor according to claim 8, Among them, The width of the bottom surface of the conductive via is larger than the width of the top surface of the first connecting conductive structure.

11. The image sensor according to claim 8, Among them, The first connecting conductive structure includes a first part and a second part on the first part, Wherein, the maximum width of the second part of the first connecting conductive structure is smaller than the maximum width of the first part of the first connecting conductive structure, and Wherein, the image sensor further includes: A first dielectric layer in contact with the sidewalls of the second part of the first connecting conductive structure and the top surface of the first part of the first connecting conductive structure; and A second dielectric layer in contact with the sidewalls of the first part of the first connecting conductive structure.

12. The image sensor according to claim 11, further including: A second connecting conductive structure that penetrates the second dielectric layer and contacts the first connecting conductive structure.

13. The image sensor according to claim 11, Among them, The substrate further includes a photoelectric conversion region, Wherein, the image sensor further includes a transfer gate stacked with the photoelectric conversion region, Wherein, the top surface of the first connecting conductive structure is at the same height as the top surface of the transfer gate, and Wherein, the bottom surface of the first connecting conductive structure is at the same height as the bottom surface of the transfer gate.

14. The image sensor according to claim 8, Among them, The first connecting conductive structure penetrates the bottom surface of the substrate, Wherein, the image sensor further includes: A second connecting conductive structure in contact with the first connecting conductive structure; A third connecting conductive structure in contact with the second connecting conductive structure; and A dielectric structure surrounding the second connecting conductive structure and the third connecting conductive structure, Wherein, the width of the third connecting conductive structure is larger than the width of the first connecting conductive structure, the width of the second connecting conductive structure, and the width of the conductive via, and Wherein, the second connecting conductive structure includes a conductive material different from the conductive material of the third connecting conductive structure.

15. The image sensor according to claim 14, Among them, The third connecting conductive structure includes copper, Wherein, the second connecting conductive structure includes tungsten, and Wherein, the first connecting conductive structure includes polysilicon.

16. The image sensor according to claim 8, further including: A first material layer in contact with the bottom surface of the conductive layer and the sidewalls of the conductive via, Wherein, the first material layer includes a dielectric material, and Wherein, the conductive via penetrates the first material layer.

17. The image sensor according to claim 16, further including: A second material layer between the first material layer and the substrate, Wherein, the second material layer includes a dielectric material different from the dielectric material of the first material layer, Wherein, the sidewalls of the conductive via are in contact with the second material layer, and Wherein, the conductive via penetrates the second material layer.

18. The image sensor according to any one of claims 8 to 17, Among them, The conductive vias are provided in plurality such that the plurality of conductive vias extend from the bottom surface of the conductive layer towards the bottom surface of the substrate, Wherein, the plurality of conductive vias are spaced apart from each other, and Wherein, when viewed in a plan view, the pad is disposed on a region between two adjacent ones of the plurality of conductive vias.

19. An image sensor, including: A first substrate including a pixel array region and a pad region, wherein the pixel array region includes a photoelectric conversion region; A color filter stacked with the photoelectric conversion region; A lens layer on the color filter; A pad stacked with the pad region; A conductive structure surrounding the pad; A second substrate spaced apart from the first substrate; A first dielectric structure and a second dielectric structure are in contact with each other between a first substrate and a second substrate; A first bonding pad is in the first dielectric structure; A second bonding pad is in the second dielectric structure and in contact with the first bonding pad; and A first connecting conductive structure and a second connecting conductive structure electrically connect the conductive structure to the first bonding pad, wherein the conductive structure includes: A conductive layer in contact with the bottom surface of the pad, and A conductive via between the conductive layer and the first connecting conductive structure, wherein the material of the conductive layer is the same as the material of the conductive via, wherein the second connecting conductive structure is surrounded by the first dielectric structure, and wherein the first connecting conductive structure includes: A first portion surrounded by the first substrate, and A second portion surrounded by the first dielectric structure.

20. The image sensor according to claim 19, further comprising: A material layer separating the conductive layer from the first substrate from each other, wherein the conductive via penetrates the material layer.

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