Display device

Abstract

A display device includes: scan lines extending in a first direction, where the scan lines include write scan lines and offset scan lines; a data line extending in a second direction crossing the first direction; and a pixel connected to the scan line and the data line. The bias scan line includes: a plurality of sub-bias scan lines spaced apart from each other in a first direction; and a connection line connected to the sub-bias scan line.

Description

[0001] This application claims the priority and all rights and interests derived therefrom of Korean Patent Application No. 10-2024-0012605 filed on January 26, 2024 and Korean Patent Application No. 10-2024-0041072 filed on March 26, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display device. Background Art

[0003] Generally, electronic devices such as smart phones, digital cameras, laptop computers, automotive navigation units, and smart TVs that provide images to a user may include a display device for displaying an image. Such a display device may generate an image and provide the generated image to the user through a display screen.

[0004] A display device generally includes a plurality of pixels for generating an image and a driver for driving the pixels. Each of the pixels may include a light-emitting element, a plurality of transistors connected to the light-emitting element, and at least one capacitor connected to the transistors. The transistors are connected to a scan line, a data line, and a light-emitting line. The transistors are driven by a scan signal, a data voltage, and a light-emitting signal applied through the scan line, the data line, and the light-emitting line, respectively. Summary of the Invention

[0005] When manufacturing a transistor of a display device, a doping process may be performed on a semiconductor layer of the transistor. In the doping process, a phenomenon may occur in which charges accumulate on the scan line, and static electricity may be generated from the scan line. The semiconductor layer of the transistor may be damaged by the static electricity. Accordingly, a technique for reducing static electricity is desired.

[0006] Embodiments of the present disclosure provide a display device in which damage to pixels is effectively prevented by reducing static electricity generated from a bias scan line.

[0007] According to an embodiment, a display device includes: a scan line extending in a first direction, wherein the scan line includes a write scan line and a bias scan line; a data line extending in a second direction crossing the first direction; and a pixel connected to the scan line and the data line. In such an embodiment, the bias scan line includes: a plurality of sub-bias scan lines spaced apart from each other in the first direction; and a connection line connected to the sub-bias scan lines.

[0008] According to an embodiment, a display device includes: scan lines extending in a first direction, where the scan lines include write scan lines and bias scan lines; a plurality of data lines extending in a second direction intersecting the first direction; and a plurality of pixels arranged in the first direction and connected to the scan lines and the data lines. In such an embodiment, the bias scan lines include: a plurality of sub-bias scan lines spaced apart from each other for at least one pixel; and a plurality of connection lines connected to the sub-bias scan lines.

[0009] According to an embodiment, a display device includes: scan lines extending in a first direction, where the scan lines include write scan lines and bias scan lines; data lines extending in a second direction intersecting the first direction; and pixels connected to the scan lines and the data lines. In such an embodiment, the bias scan lines include: two sub-bias scan lines spaced apart from each other in the first direction; and a connection line connected to the two sub-bias scan lines. In such an embodiment, the pixels include: a plurality of transistors connected to the data lines, the write scan lines, and the bias scan lines; and a light-emitting element connected to a corresponding one of the transistors. In such an embodiment, the two sub-bias scan lines and the gate electrodes of the transistors are disposed in the same layer, and the connection lines are disposed above the gate electrodes. Description of the Drawings

[0010] The above and other features of the embodiments of the present disclosure will become apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0011] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure;

[0012] Figure 2 is Figure 1 a cross-sectional view of the display device illustrated in ;

[0013] Figure 3 is Figure 2 a cross-sectional view of the display panel illustrated in ;

[0014] Figure 4 is Figure 3 a plan view of the display panel illustrated in ;

[0015] Figure 5 is an illustration of Figure 4 a view of an equivalent circuit of one pixel illustrated in ;

[0016] Figure 6 is for driving Figure 5 a signal timing diagram of signals for the pixels illustrated in ;

[0017] Figure 7 is an illustration of Figure 5Cross-sectional views of the light-emitting element, the first transistor, and the sixth transistor of the pixel illustrated in the figure;

[0018] Figures 8A to 8E is illustrated in a layer-by-layer manner Figure 5 View of the planar structure of the pixel illustrated in the figure;

[0019] Figure 9 is a schematic plan view illustrating pixels and bias scan lines arranged in a row;

[0020] Figure 10 is a view illustrating only multiple bias scan lines in the display panel;

[0021] Figure 11 and Figure 12 is a view illustrating components of the bias scan line according to an embodiment of the present disclosure;

[0022] Figure 13 is along Figure 8D Cross-sectional view taken along line I-I' illustrated in the figure;

[0023] Figure 14 is a view for explaining the doping process of the semiconductor layer;

[0024] Figure 15 is a view illustrating the doping process performed in a state where the sub-bias scan line of the present disclosure is provided on the substrate;

[0025] Figure 16 is a view illustrating the doping process performed in a state where the comparative bias scan line is provided on the substrate; and

[0026] Figures 17 to 19 is a view illustrating components of the bias scan line according to various embodiments of the present disclosure. Detailed Description of the Invention

[0027] Now, the present invention will be more fully described hereinafter with reference to the accompanying drawings showing various embodiments. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0028] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to", or "coupled to" another component, this means that the component can be directly on, directly connected to, or directly coupled to the other component, or a third component may be present between them.

[0029] Like reference numerals refer to like components. Additionally, in the drawings, the thickness, ratios, and dimensions of the components are exaggerated for effective description.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, "a," "the," and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural unless the context clearly dictates otherwise. Thus, a reference to "a" element in a claim followed by a reference to "the" element includes one element and a plurality of elements. For example, "element" has the same meaning as "at least one element" unless the context clearly dictates otherwise. "At least one" should not be construed as limiting "a." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the terms "comprises" and / or "comprising," and variations thereof, specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0031] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings herein.

[0032] Additionally, terms such as "below," "beneath," "above," and "over" are used to describe the relationships of components illustrated in the drawings. The terms are relative concepts and are described based on the orientation illustrated in the drawings.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0034] In this document, embodiments are described with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are anticipated. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein, but rather are to include deviations in shapes, such as those resulting from manufacturing. For example, regions illustrated or described as flat will typically have rough and / or non-linear features. Additionally, sharp corners illustrated may be rounded. Thus, the regions illustrated in the various figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of a region and are not intended to limit the scope of the claims.

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 , embodiments of the display device DD may have a surface on a plane defined by a first direction DR1 and a second direction DR2 that intersect each other. In a plan view or when viewed in a third direction DR3, the display device DD may have a rectangular shape having a long side extending in the first direction DR1 and a short side extending in the second direction DR2. However, and without limitation, the display device DD may have one of various other shapes such as a circular shape and a polygonal shape.

[0038] Hereinafter, a direction that is substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 or the thickness direction of the display device DD is defined as the third direction DR3. Additionally, the expressions “when viewed from above the plane” or “in a plan view” used herein may mean viewing in the third direction DR3.

[0039] The upper surface of the display device DD may be defined as a display surface DS and may be on a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface DS.

[0040] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display an image, and the non-display area NDA may not display any image. The non-display area NDA may surround the display area DA and may define a boundary of the display device DD printed in a specific color.

[0041] The display device DD according to an embodiment may be used in an electronic device such as a smart phone, a digital camera, a notebook computer, a monitor, a smart TV, and a car navigation unit that provides an image to a user.

[0042] Figure 2 is Figure 1 a cross-sectional view of the display device illustrated in the figure.

[0043] In Figure 2 it, a cross-section of the display device DD observed in the first direction DR1 is illustrated.

[0044] Referring Figure 2 , embodiments of the display device DD may include a display panel DP, an input sensing part ISP, an antireflection layer RPL, a window WIN, a panel protection film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2.

[0045] The display panel DP according to an embodiment of the present disclosure may be an emissive display panel. In an embodiment, for example, the display panel DP may be an organic light emitting display panel or an inorganic light emitting display panel. The emission layer of the organic light emitting display panel may include an organic light emitting material. The emission layer of the inorganic light emitting display panel may include quantum dots or quantum rods, etc. Hereinafter, for ease of description, embodiments in which the display panel DP is an organic light emitting display panel will be mainly described, but it is not limited thereto.

[0046] The input sensing part ISP may be disposed on the display panel DP. The input sensing part ISP may include a plurality of sensing parts (not illustrated) for sensing an external input in a capacitive type. In an embodiment, when manufacturing the display device DD, the input sensing part ISP may be directly manufactured on the display panel DP. Alternatively, without being limited thereto, the input sensing part ISP may be manufactured as a panel separated from the display panel DP, and may be attached to the display panel DP through an adhesive layer.

[0047] The antireflection layer RPL may be disposed on the input sensing part ISP. In an embodiment, when manufacturing the display device DD, the antireflection layer RPL may be directly manufactured on the input sensing part ISP. Alternatively, without being limited thereto, the antireflection layer RPL may be manufactured as a separated panel, and may be attached to the input sensing part ISP through an adhesive layer.

[0048] The antireflection layer RPL may be defined as a film for preventing reflection of external light. The antireflection layer RPL may reduce the reflectance of external light incident on the display panel DP from above the display device DD. Due to the antireflection layer RPL, the reflected external light may be invisible to the user.

[0049] When external light propagating toward the display panel DP is reflected from the display panel DP and returned to be provided to the user, the user can visually recognize the external light as if in a mirror. In an embodiment, the anti-reflection layer RPL may include a plurality of color filters that display the same color as the light emitted by the pixels of the display panel DP to prevent such a phenomenon.

[0050] The color filters may filter the external light into the same color as the light emitted by the pixels. In such an embodiment, the external light may be invisible to the user. Alternatively, and not limited thereto, the anti-reflection layer RPL may include a phase retarder and / or a polarizer for reducing the reflectance of the external light.

[0051] The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing part ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0052] The panel protective film PPF may be disposed under the display panel DP. The panel protective film PPF may protect the lower part of the display panel DP. The panel protective film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0053] The first adhesive layer AL1 may be disposed between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF may be joined to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be disposed between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL may be joined to each other through the second adhesive layer AL2.

[0054] Figure 3 is Figure 2 a cross-sectional view of the display panel illustrated.

[0055] In Figure 3 is illustrated a cross-section of the display panel DP observed in the first direction DR1.

[0056] Reference Figure 3 , an embodiment of the display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0057] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include glass or may include a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed on the display area DA.

[0058] Multiple pixels may be provided in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor provided in the circuit element layer DP-CL and a light-emitting element provided in the display element layer DP-OLED and connected to the transistor.

[0059] The thin film encapsulation layer TFE may be provided on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign substances.

[0060] Figure 4 is Figure 3 A plan view of the display panel illustrated in

[0061] Reference Figure 4 , an embodiment of the display device DD may include a display panel DP, a scan driver SDV, a plurality of data drivers DDV, a light-emitting driver EDV, and a plurality of pads PD.

[0062] In the plan view, the display panel DP may have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2. However, the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0063] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, and a plurality of light-emitting lines EL1 to ELm. Here, m and n are natural numbers greater than 0.

[0064] The pixels PX may be provided in the display area DA. The scan driver SDV and the light-emitting driver EDV may be provided in the non-display area NDA adjacent to opposite sides of the display panel DP in the first direction DR1. The data driver DDV may be provided in the non-display area NDA adjacent to one of the opposite sides of the display panel DP in the second direction DR2. When viewed from above the plane or in the plan view, the data driver DDV may be adjacent to the lower end of the display panel DP.

[0065] The scan lines SL1 to SLm may extend in the first direction DR1 and may be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the second direction DR2 and may be connected to the pixels PX and the data driver DDV. The light-emitting lines EL1 to ELm may extend in the first direction DR1 and may be connected to the pixels PX and the light-emitting driver EDV.

[0066] The data drivers DDV can be spaced apart from each other in a first direction DR1. A certain number of data lines can be connected to each of the data drivers DDV. Although two data drivers DDV are illustrated as an example in Figure 4 , the number of data drivers DDV is not limited thereto. In an embodiment, for example, as the left and right regions of the display panel DP increase, the number of data drivers DDV can also be increased.

[0067] The pads PD can be provided in the non-display area NDA adjacent to the lower end of the display panel DP and closer to the lower end of the display panel DP than the data drivers DDV. The data drivers DDV can be connected to the pads PD. The data lines DL1 to DLn can be connected to the data drivers DDV, and the data drivers DDV can be connected to the pads PD corresponding to the data lines DL1 to DLn.

[0068] Although not illustrated, the display device DD can further include a timing controller for controlling the operations of the scan driver SDV, the data driver DDV, and the light-emitting driver EDV. The timing controller can be connected to the pads PD through a printed circuit board.

[0069] The scan driver SDV can generate a plurality of scan signals, and the scan signals can be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV can generate a plurality of data voltages, and the data voltages can be applied to the pixels PX through the data lines DL1 to DLn. The light-emitting driver EDV can generate a plurality of light-emitting signals, and the light-emitting signals can be applied to the pixels PX through the light-emitting lines EL1 to ELm.

[0070] The pixel PX can receive a data voltage in response to the scan signal. The pixel PX can display an image by emitting light having a brightness corresponding to the data voltage in response to the light-emitting signal.

[0071] Figure 5 is a view of an equivalent circuit of one pixel illustrated in Figure 4 .

[0072] Referring to Figure 5 , an embodiment of the pixel PX can include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. Figure 5 The pixel PX illustrated in can be a pixel provided in the i-th row and the j-th column. Here, i is a natural number greater than 0 and less than or equal to m, and j is a natural number greater than 0 and less than or equal to n. The row direction can correspond to the first direction DR1, and the column direction can correspond to the second direction DR2. Figure 4 Each of the pixels PX illustrated in can have Figure 5 the configuration illustrated in.

[0073] The pixel circuit PC can drive the light-emitting element OLED. The light-emitting element OLED can be defined as an organic light-emitting element. The light-emitting element OLED can include an anode AE and a cathode CE.

[0074] The pixel circuit PC can include a plurality of transistors T1 to T9 and a plurality of capacitors C1 and C2. The transistors T1 to T9 and the capacitors C1 and C2 can control the amount of current flowing through the light-emitting element OLED. The light-emitting element OLED can generate light with a specific brightness depending on the amount of current supplied thereto.

[0075] Among the scan lines SL1 to SLm, the i-th scan line can include the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, and the i-th bias scan line GBLi.

[0076] The pixel PX can be connected to the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, the i-th bias scan line GBLi, the i-th first emission line EML1i, the i-th second emission line EML2i, the j-th data line DLj, the first initialization (voltage) line VIL1, the second initialization (voltage) line VIL2, the reference (voltage) line VL, the bias (voltage) line VBL, and the first power supply line PL1 and the second power supply line PL2.

[0077] The i-th write scan line GWLi can receive the i-th write scan signal GWi, and the i-th compensation scan line GCLi can receive the i-th compensation scan signal GCi. The i-th initialization scan line GILi can receive the i-th initialization scan signal GIi, and the i-th bias scan line GBLi can receive the i-th bias scan signal GBi. The i-th first emission line EML1i can receive the i-th first emission signal EM1i, and the i-th second emission line EML2i can receive the i-th second emission signal EM2i.

[0078] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage VAINT. The bias line VBL can receive the bias voltage VBIAS, and the reference line VL can receive the reference voltage VR. The first power supply line PL1 can receive the first voltage ELVDD, and the second power supply line PL2 can receive the second voltage ELVSS.

[0079] Each of the transistors T1 to T9 can include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in Figure 5 for convenience, one of the source electrode and the drain electrode is defined as the first electrode, and the other of the source electrode and the drain electrode is defined as the second electrode. In addition, the gate electrode is defined as the control electrode.

[0080] The transistors T1 to T9 may include a first transistor T1 to a ninth transistor T9. The first transistor T1 to the ninth transistor T9 may be p-channel metal oxide semiconductor (PMOS) transistors. However, not limited thereto, the first transistor T1 to the ninth transistor T9 may be n-channel metal oxide semiconductor (NMOS) transistors. The capacitors C1 and C2 may include a first capacitor C1 and a second capacitor C2.

[0081] The transistors T1 to T9 and the capacitors C1 and C2 may be directly or indirectly connected to the above-mentioned lines GWLi, GCLi, GILi, GBLi, EML1i, EML2i, DLj, VIL1, VIL2, VL, VBL, PL1, and PL2 and the light-emitting element OLED.

[0082] In an embodiment, for example, the second transistor T2 may be directly connected to the j-th data line DLj and the i-th write scan line GWLi, and the first capacitor C1 may be indirectly connected to the j-th data line DLj through the second transistor T2. The eighth transistor T8 may be directly connected to the bias line VBL, and the first transistor T1 may be indirectly connected to the bias line VBL through the eighth transistor T8. The sixth transistor T6 may be directly connected to the light-emitting element OLED, and the first transistor T1 may be indirectly connected to the light-emitting element OLED through the sixth transistor T6.

[0083] The first transistor T1 may be connected to the light-emitting element OLED and the first power supply line PL1, and may be switched by the voltage of the first node N1. In an embodiment, for example, the first transistor T1 may be connected to the anode AE of the light-emitting element OLED through the sixth transistor T6 and may be connected to the first power supply line PL1 through the ninth transistor T9. The first transistor T1 may be disposed between the sixth transistor T6 and the ninth transistor T9 and may be connected to the sixth transistor T6 and the ninth transistor T9.

[0084] The first transistor T1 may include a first electrode connected to the ninth transistor T9, a second electrode connected to the sixth transistor T6, and a control electrode connected to the first node N1. The first transistor T1 may control the amount of current flowing through the light-emitting element OLED depending on the voltage of the first node N1 applied to the control electrode of the first transistor T1. The first transistor T1 may be defined as a driving transistor.

[0085] The second transistor T2 may be disposed between the j-th data line DLj and the second node N2, and may be connected to the j-th data line DLj and the second node N2. The second transistor T2 may be switched by the i-th write scan signal GWi. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the second node N2, and a control electrode connected to the i-th write scan line GWLi. The second transistor T2 may be defined as a switching transistor.

[0086] The first capacitor C1 may be connected to the first node N1 and the second node N2. The first capacitor C1 may be connected to the control electrode of the first transistor T1 through the first node N1, and may be connected to the second electrode of the second transistor T2 through the second node N2. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0087] The second transistor T2 may be turned on by the i-th write scan signal GWi applied through the i-th write scan line GWLi. The turned-on second transistor T2 may receive the data voltage VD through the j-th data line DLj. The data voltage VD may be provided to the first capacitor C1 through the turned-on second transistor T2.

[0088] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0089] The third transistor T3 may be turned on by the i-th compensation scan signal GCi applied through the i-th compensation scan line GCLi, and may connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 may be connected to each other in the form of a diode. The third transistor T3 may be defined as a compensation transistor.

[0090] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi.

[0091] The fourth transistor T4 may be turned on by the i-th initialization scan signal GIi applied through the i-th initialization scan line GILi. The turned-on fourth transistor T4 may provide the first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1. The fourth transistor T4 may be defined as a first initialization transistor.

[0092] The fifth transistor T5 can be disposed between the reference line VL and the second node N2, and can be connected to the reference line VL and the second node N2. The fifth transistor T5 can be switched by the i-th compensation scan signal GCi.

[0093] The fifth transistor T5 can include a first electrode connected to the second node N2, a second electrode connected to the reference line VL, and a control electrode connected to the i-th compensation scan line GCLi. The fifth transistor T5 can be turned on by the i-th compensation scan signal GCi applied through the i-th compensation scan line GCLi. The turned-on fifth transistor T5 can provide the reference voltage VR applied through the reference line VL to the second node N2. The fifth transistor T5 can be defined as a reference transistor.

[0094] The sixth transistor T6 can be connected to the first transistor T1 and the anode AE, and can be switched by the i-th second emission signal EM2i. The sixth transistor T6 can include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th second emission line EML2i.

[0095] The sixth transistor T6 can be turned on by the i-th second emission signal EM2i applied through the i-th second emission line EML2i. The sixth transistor T6 can be defined as a first emission control transistor.

[0096] The seventh transistor T7 can be connected to the anode AE and the second initialization line VIL2, and can be switched by the i-th bias scan signal GBi. The seventh transistor T7 can include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi.

[0097] The seventh transistor T7 can be turned on by the i-th bias scan signal GBi applied through the i-th bias scan line GBLi. The turned-on seventh transistor T7 can provide the second initialization voltage VAINT received through the second initialization line VIL2 to the anode AE of the light-emitting element OLED. The seventh transistor T7 can be defined as a second initialization transistor.

[0098] The eighth transistor T8 can be connected to the first transistor T1 and the bias line VBL, and can be switched by the i-th bias scan signal GBi. The eighth transistor T8 can include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0099] The eighth transistor T8 can be turned on by the i-th bias scan signal GBi applied through the i-th bias scan line GBLi. The turned-on eighth transistor T8 can supply the bias voltage VBIAS received through the bias line VBL to the first electrode of the first transistor T1. The eighth transistor T8 can be defined as a bias transistor.

[0100] The ninth transistor T9 can be connected to the first power supply line PL1 and the first transistor T1, and can be switched by the i-th first emission signal EM1i. The ninth transistor T9 can include a first electrode connected to the first power supply line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th first emission line EML1i.

[0101] The ninth transistor T9 can be turned on by the i-th first emission signal EM1i applied through the i-th first emission line EML1i. The ninth transistor T9 can be defined as a second emission control transistor. When the sixth transistor T6 and the ninth transistor T9 are turned on, the first voltage ELVDD can be supplied to the light-emitting element OLED, and the drive current Id can flow through the light-emitting element OLED. Accordingly, the light-emitting element OLED can emit light.

[0102] The second capacitor C2 can include a first electrode connected to the second node N2 and a second electrode connected to the first power supply line PL1.

[0103] The light-emitting element OLED can be connected to the corresponding sixth transistor T6 among the transistors T1 to T9. The anode AE of the light-emitting element OLED can be connected to the first power supply line PL1 through the sixth transistor T6, the first transistor T1, and the ninth transistor T9. The anode AE of the light-emitting element OLED can receive the first voltage ELVDD through the sixth transistor T6, the first transistor T1, and the ninth transistor T9.

[0104] The cathode CE of the light-emitting element OLED can be connected to the second power supply line PL2. The cathode CE of the light-emitting element OLED can receive a second voltage ELVSS having a level lower than that of the first voltage ELVDD through the second power supply line PL2.

[0105] The pixel PX can substantially include three pixel circuits PC and three light-emitting elements OLED respectively connected to the three pixel circuits PC. The layout diagram of Figures 8A to 8E will illustrate the three pixel circuits PC.

[0106] Figure 6 is a signal timing diagram of the signals for driving the Figure 5 pixels illustrated in

[0107] Hereinafter, in Figure 6In the timing diagram, the activation period of each signal represents a low level, and Figure 6 in the timing diagram, the deactivation period of each signal represents a high level.

[0108] Refer to Figure 5 and Figure 6 , the i-th first light-emitting signal EM1i can be activated and deactivated during the non-light-emitting period NLP. The i-th first light-emitting signal EM1i can be activated during the light-emitting period LP. The i-th second light-emitting signal EM2i can be deactivated during the non-light-emitting period NLP in a frame period, and can be activated during the light-emitting period LP in a frame period.

[0109] In the non-light-emitting period NLP, the i-th initialization scan signal GIi and the i-th compensation scan signal GCi can be repeatedly activated during the activation period of the i-th first light-emitting signal EM1i. First, the i-th initialization scan signal GIi can be activated, and then, the i-th compensation scan signal GCi can be activated. The activation period of the i-th initialization scan signal GIi may not overlap with the activation period of the i-th compensation scan signal GCi.

[0110] In the non-light-emitting period NLP, the i-th initialization scan signal GIi and the i-th compensation scan signal GCi can be deactivated during the deactivation period of the i-th first light-emitting signal EM1i. In the deactivation period of the i-th first light-emitting signal EM1i, the i-th write scan signal GWi can be activated, and thereafter, the i-th bias scan signal GBi can be activated. The i-th bias scan signal GBi can be repeatedly activated during the deactivation period of the i-th first light-emitting signal EM1i.

[0111] In an embodiment, for example, during the non-light-emitting period NLP, the i-th initialization scan signal GIi, the i-th compensation scan signal GCi, and the i-th bias scan signal GBi can each be activated three times. However, the number of activations during the non-light-emitting period NLP is not limited to this. In the light-emitting period LP, the i-th initialization scan signal GIi, the i-th compensation scan signal GCi, the i-th write scan signal GWi, and the i-th bias scan signal GBi can be deactivated.

[0112] In the non-light-emitting period NLP, the i-th first light-emitting signal EM1i that activates the ninth transistor T9 is turned on, and the first voltage ELVDD can be applied to the first electrode (or source) of the first transistor T1.

[0113] During the non-light-emitting period NLP, the fourth transistor T4 can be turned on by the i-th initialization scan signal GIi that is activated. The first initialization voltage VINT can be supplied to the first node N1 through the fourth transistor T4, and the first transistor T1 can be initialized. This operation can be defined as an initialization operation.

[0114] Thereafter, during the non-light-emitting period NLP, the activated i-th compensation scan signal GCi can be applied to the third transistor T3, and the third transistor T3 can be turned on. The first transistor T1 and the third transistor T3 can be turned on and can be connected in the form of a diode. In this case, the compensation voltage (ELVDD - Vth) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first voltage ELVDD can be applied to the control electrode of the first transistor T1. This operation can be defined as a threshold voltage compensation operation.

[0115] During the non-light-emitting period NLP, the activated i-th compensation scan signal GCi can be applied to the fifth transistor T5, and the fifth transistor T5 can be turned on. The reference voltage VR can be applied to the second node N2 through the turned-on fifth transistor T5.

[0116] While the i-th initialization scan signal GIi and the i-th compensation scan signal GCi are repeatedly activated, the above-described initialization operation and compensation operation can be repeatedly executed. As the initialization operation is repeatedly executed, the data written to the first node N1 in the previous frame can be removed more effectively or completely, and the first transistor T1 can be initialized more effectively or completely.

[0117] Parasitic capacitors may exist in the third transistor T3 and the fourth transistor T4. The gate-source voltages of the third transistor T3 and the fourth transistor T4 may be changed by the parasitic capacitors. The second capacitor C2 can have a capacitance larger than that of the parasitic capacitor. The second capacitor C2 having a capacitance larger than that of the parasitic capacitor can be connected to the third transistor T3 and the fourth transistor T4 through the first node N1. The second capacitor C2 having a capacitance larger than that of the parasitic capacitor can suppress the change in the gate-source voltage level of the third transistor T3 and the fourth transistor T4.

[0118] Thereafter, during the non-light-emitting period NLP, the activated i-th write scan signal GWi can be applied to the second transistor T2, and the second transistor T2 can be turned on. The data voltage VD can be supplied to the first capacitor C1 through the second transistor T2. In this case, the data voltage VD can be applied to the second node N2, and the voltage of the first node N1 can be ELVDD - Vth + VD - VR.

[0119] The i-th bias scan signal GBi at which the seventh transistor T7 and the eighth transistor T8 can be activated turns on. The second initialization voltage VAINT can be provided to the anode AE through the seventh transistor T7, and the bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8.

[0120] During the light emission period LP, the activated i-th first light emission signal EM1i and the i-th second light emission signal EM2i can be applied to the ninth transistor T9 and the sixth transistor T6, and the ninth transistor T9 and the sixth transistor T6 can be turned on. The drive current Id can be provided to the light emitting element OLED through the sixth transistor T6, and the light emitting element OLED can emit light.

[0121] The source-gate voltage (Vsg) of the first transistor T1 can be defined as the voltage difference between the first voltage ELVDD and the voltage ELVDD-Vth+VD-VR at the first node N1. When the source-gate voltage (Vsg) of the first transistor T1 is substituted into Equation 1 below, the threshold voltage (Vth) can be eliminated, and the drive current (Id) in Equation 1 can be proportional to (VR-VD)^2, which is the value obtained by subtracting the data voltage VD from the reference voltage VR. 2 Accordingly, the drive current (Id) can be determined without considering the threshold voltage (Vth) of the first transistor T1.

[0122] Id=(1 / 2)μCox(W / L)(Vsg-Vth) 2 Equation 1

[0123] Equation 1 represents the current-voltage relationship of a general transistor.

[0124] Before the light emitting element OLED emits light and after the threshold voltage of the first transistor T1 is compensated, the bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8. The shift of the hysteresis curve of the first transistor T1 can be suppressed by the bias voltage VBIAS. This operation can be defined as a bias operation.

[0125] Figure 7 is a diagram Figure 5 showing a cross-sectional view of the light emitting element, the first transistor, and the sixth transistor of the pixel illustrated in

[0126] Reference Figure 7 , in the embodiment, the light emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and an emission layer EML. The first electrode AE may be Figure 5 the anode AE illustrated in Figure 5The cathode CE illustrated in the figure. The second electrode CE may be disposed over the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the emission layer EML may be disposed between the first electrode AE and the second electrode CE.

[0127] The first transistor T1, the sixth transistor T6, and the light-emitting element OLED may be disposed on the substrate SUB. The display area DA may include an emission area LEA corresponding to the pixel PX and a non-emission area NLEA adjacent to or surrounding the emission area LEA. In a plan view, the light-emitting element OLED may be disposed in the emission area LEA.

[0128] The buffer layer BFL may be disposed on the substrate SUB. The buffer layer BFL may be an inorganic layer. The semiconductor layers S1, A1, and D1 of the first transistor T1 and the semiconductor layers S6, A6, and D6 of the sixth transistor T6 may be disposed on the buffer layer BFL. In an embodiment, the semiconductor layers S1, A1, D1, S6, A6, and D6 may include polysilicon. Alternatively, and not limited thereto, the semiconductor layers S1, A1, D1, S6, A6, and D6 may include amorphous silicon.

[0129] The semiconductor layers S1, A1, D1, S6, A6, and D6 may be doped with an N-type dopant or a P-type dopant. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include a highly doped region and a lightly doped region. The highly doped regions (e.g., source regions and drain regions) may have a higher conductivity than the lightly doped region and may substantially serve as the source electrodes and drain electrodes of the first transistor T1 and the sixth transistor T6. The lightly doped region may substantially correspond to the channel regions (or channels) of the first transistor T1 and the sixth transistor T6.

[0130] The semiconductor layers S1, A1, and D1 of the first transistor T1 may include a first source region S1, a first channel region A1, and a first drain region D1. The semiconductor layers S6, A6, and D6 of the sixth transistor T6 may include a sixth source region S6, a sixth channel region A6, and a sixth drain region D6. The first channel region A1 may be disposed between the first source region S1 and the first drain region D1. The sixth channel region A6 may be disposed between the sixth source region S6 and the sixth drain region D6.

[0131] The first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layers S1, A1, D1, S6, A6, and D6. The first gate electrodes G1 and the sixth gate electrodes G6 (or control electrodes) of the first transistor T1 and the sixth transistor T6 may be disposed on the first insulating layer INS1.

[0132] The first gate electrode G1 may be disposed over the semiconductor layers S1, A1, and D1, and the sixth gate electrode G6 may be disposed over the semiconductor layers S6, A6, and D6. The first gate electrode G1 may be disposed over the first channel region A1 and may overlap the first channel region A1. The sixth gate electrode G6 may be disposed over the sixth channel region A6 and may overlap the sixth channel region A6.

[0133] Although not illustrated, the other transistors T2 to T5 and T7 to T9 may also have substantially the same configuration as the first transistor T1 and the sixth transistor T6.

[0134] The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. The dummy electrode DME may be disposed on the second insulating layer INS2. The dummy electrode DME may be disposed over the first gate electrode G1 and may overlap the first gate electrode G1 when viewed from above in a plane or in a plan view (i.e., when viewed in the thickness direction of the substrate SUB).

[0135] The dummy electrode DME may form the first capacitor C1 together with the first gate electrode G1. The first gate electrode G1 may define the first electrode of the first capacitor C1, and the dummy electrode DME may define the second electrode of the first capacitor C1.

[0136] The third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the dummy electrode DME. The fourth insulating layer INS4 may be disposed on the third insulating layer INS3. The buffer layer BFL and the first insulating layer INS1 to the fourth insulating layer INS4 may include inorganic layers.

[0137] The connection electrode CNE may be disposed between the sixth transistor T6 and the light-emitting element OLED. The connection electrode CNE may electrically connect the sixth transistor T6 and the light-emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 disposed over the first connection electrode CNE1.

[0138] The first connection electrode CNE1 may be disposed on the third insulating layer INS3, and the fourth insulating layer INS4 may be disposed on the first connection electrode CNE1. The first connection electrode CNE1 may be disposed over the dummy electrode DME and may be connected to the corresponding sixth transistor T6. The first connection electrode CNE1 may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first insulating layer INS1 to the third insulating layer INS3.

[0139] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. The second connection electrode CNE2 may be disposed on the fifth insulating layer INS5. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4 and the fifth insulating layer INS5. The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the second connection electrode CNE2. The fifth insulating layer INS5 and the sixth insulating layer INS6 may include an inorganic layer or an organic layer.

[0140] The light-emitting element OLED may be disposed on the sixth insulating layer INS6. The light-emitting element OLED may be disposed on the second connection electrode CNE2 and may be connected to the second connection electrode CNE2. In an embodiment, the first electrode AE may be disposed on the sixth insulating layer INS6. The first electrode AE may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the sixth insulating layer INS6.

[0141] The pixel defining layer PDL exposing a specific portion of the first electrode AE may be disposed on the first electrode AE and the sixth insulating layer INS6. An opening PX_OP for exposing a specific portion of the first electrode AE may be defined in the pixel defining layer PDL.

[0142] The hole control layer HCL may be disposed on the first electrode AE and the pixel defining layer PDL. The hole control layer HCL may be commonly disposed in the light-emitting area LEA and the non-light-emitting area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0143] The emission layer EML may be disposed on the hole control layer HCL. The emission layer EML may be disposed in a region corresponding to the opening PX_OP. The emission layer EML may include an organic material and / or an inorganic material. The emission layer EML may generate one of red light, green light, and blue light.

[0144] The electron control layer ECL may be disposed on the emission layer EML and the hole control layer HCL. The electron control layer ECL may be commonly disposed in the light-emitting area LEA and the non-light-emitting area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0145] The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may be commonly disposed for the pixel PX. That is, the second electrode CE may be commonly disposed over the emission layer EML of the pixel PX.

[0146] The layer from the buffer layer BFL to the sixth insulating layer INS6 may be defined as a circuit element layer DP-CL. The layer in which the light-emitting element OLED is disposed may be defined as a display element layer DP-OLED.

[0147] The thin film encapsulation layer TFE may be disposed on the light emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer sequentially stacked one on top of the other. The inorganic layer may include an inorganic material and may protect the pixel PX from moisture / oxygen. The organic layer may include an organic material and may protect the pixel PX from foreign substances such as dust particles.

[0148] A first voltage ELVDD may be applied to the first electrode AE, and a second voltage EVLSS may be applied to the second electrode CE. Holes and electrons injected into the emission layer EML may combine to form excitons, and when the excitons transition to the ground state, the light emitting element OLED may emit light. When the light emitting element OLED emits light, an image may be displayed.

[0149] Figures 8A to 8E is illustrated in a layer-by-layer manner Figure 5 a view of the planar structure of the pixel illustrated in

[0150] Figures 8A to 8E The plan view illustrated in may be substantially a plan view of the layers defining the first transistor T1 to the ninth transistor T9 and the first capacitor C1 and the second capacitor C2. Figures 8A to 8E The view illustrated in may be defined as a layout diagram. In Figures 8A to 8E the description of, the term "overlap" indicates a state in which components overlap each other when viewed from above the plane or in the plan view (i.e., when viewed in the third direction DR3).

[0151] Reference Figures 8A to 8E , each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may correspond to Figure 5 the pixel circuit PC illustrated in. Each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be connected to Figure 5 and Figure 7 the light emitting element OLED illustrated in.

[0152] The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be arranged in the first direction DR1. The gap in the first direction DR1 between the first pixel circuit PC1 and the second pixel circuit PC2 may be greater than the gap in the first direction DR1 between the second pixel circuit PC2 and the third pixel circuit PC3. Accordingly, the first pixel circuit PC1 and the second pixel circuit PC2 may be spaced farther apart from each other than the second pixel circuit PC2 and the third pixel circuit PC3.

[0153] The above pixel PX may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel may include a first pixel circuit PC1 and a light-emitting element OLED connected to the first pixel circuit PC1. The second sub-pixel may include a second pixel circuit PC2 and a light-emitting element OLED connected to the second pixel circuit PC2. The third sub-pixel may include a third pixel circuit PC3 and a light-emitting element OLED connected to the third pixel circuit PC3.

[0154] In an embodiment, for example, the first sub-pixel may display red, the second sub-pixel may display green, and the third sub-pixel may display blue. The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 have substantially the same structure as each other, and thus, the structure of the first pixel circuit PC1 will be mainly described hereinafter.

[0155] In Figures 8A to 8E the boundaries between the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are illustrated by dotted lines. Each of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be defined as a region forming the first transistor T1 to the ninth transistor T9, and the first capacitor C1 and the second capacitor C2.

[0156] Reference Figure 8A to Figure 8A the semiconductor pattern SMP illustrated in Figure 8A may be disposed on the above substrate SUB. The semiconductor pattern SMP may have various shapes and is not limited to the shape illustrated in

[0157] The first semiconductor layer S1, A1, and D1 of the first transistor T1, the second semiconductor layer S2, A2, and D2 of the second transistor T2, the third semiconductor layer S3, A3, and D3 of the third transistor T3, the fourth semiconductor layer S4, A4, and D4 of the fourth transistor T4, the fifth semiconductor layer S5, A5, and D5 of the fifth transistor T5, the sixth semiconductor layer S6, A6, and D6 of the sixth transistor T6, the seventh semiconductor layer S7, A7, and D7 of the seventh transistor T7, the eighth semiconductor layer S8, A8, and D8 of the eighth transistor T8, and the ninth semiconductor layer S9, A9, and D9 of the ninth transistor T9 may be defined or formed by the semiconductor pattern SMP.

[0158] The first channel region A1 to the ninth channel region A9 can be disposed between the first source region S1 to the ninth source region S9 and the first drain region D1 to the ninth drain region D9. In an embodiment, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can have a double-gate structure. Each of the second channel region A2, the third channel region A3, the fourth channel region A4, and the fifth channel region A5 of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 having the double-gate structure can be formed by two channel regions.

[0159] The second semiconductor layer and the fifth semiconductor layer S2, A2, D2, S5, A5, and D5 can be spaced apart from or disconnected from the first semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the sixth semiconductor layer, the seventh semiconductor layer, the eighth semiconductor layer, and the ninth semiconductor layer S1, A1, D1, S3, A3, D3, S4, A4, D4, S6, A6, D6, S7, A7, D7, S8, A8, D8, S9, A9, and D9.

[0160] The second drain region D2 of the second transistor T2 can extend from the fifth source region S5 of the fifth transistor T5. The third source region S3 of the third transistor T3 can extend from the first drain region D1 of the first transistor T1. The sixth source region S6 of the sixth transistor T6 can extend from the third source region S3 of the third transistor T3.

[0161] The fourth source region S4 of the fourth transistor T4 can extend from the third drain region D3 of the third transistor T3. The seventh source region S7 of the seventh transistor T7 can extend from the sixth drain region D6 of the sixth transistor T6.

[0162] The ninth drain region D9 of the ninth transistor T9 can extend from the first source region S1 of the first transistor T1. The eighth drain region D8 of the eighth transistor T8 can extend from the ninth drain region D9 of the ninth transistor T9.

[0163] Hereinafter, for ease of description, when referring to Figures 8B to 8E the lines illustrated in, the names and symbols "the i-th" and "the j-th" are omitted.

[0164] Referring to Figure 8A and Figure 8B a first gate pattern GPT1 can be disposed on a semiconductor pattern SMP. The first gate pattern GPT1 can include a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, a fourth gate electrode G4, a fifth gate electrode G5, a sixth gate electrode G6, and a ninth gate electrode G9, a bias scan line GBL, and a first dummy electrode DME1.

[0165] The first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, the third gate electrode G3 of the third transistor T3, the fourth gate electrode G4 of the fourth transistor T4, the fifth gate electrode G5 of the fifth transistor T5, the sixth gate electrode G6 of the sixth transistor T6, and the ninth gate electrode G9 of the ninth transistor T9 may be defined or formed by the first gate pattern GPT1.

[0166] The first gate electrode G1 may overlap with the first channel region A1, the second gate electrode G2 may overlap with the second channel region A2, the third gate electrode G3 may overlap with the third channel region A3, the fourth gate electrode G4 may overlap with the fourth channel region A4, the fifth gate electrode G5 may overlap with the fifth channel region A5, the sixth gate electrode G6 may overlap with the sixth channel region A6, and the ninth gate electrode G9 may overlap with the ninth channel region A9.

[0167] In an embodiment, each of the second gate electrodes G2, the third gate electrodes G3, the fourth gate electrodes G4, and the fifth gate electrodes G5 of the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 having a dual-gate structure may be formed by two gate electrodes.

[0168] The bias scan line GBL may extend in the first direction DR1. The bias scan line GBL may be adjacent to the lower side of the first pixel circuit PC1. The bias scan line GBL may be divided into two parts extending in the first direction DR1 to form sub-bias scan lines SBL. Accordingly, the bias scan line GBL may include two sub-bias scan lines SBL spaced apart from each other in the first direction DR1. The sub-bias scan lines SBL may be spaced apart from each other at the area or region between the first pixel circuit PC1 and the second pixel circuit PC2, that is, the ends of the sub-bias scan lines SBL facing and spaced apart from each other in the first direction DR1 are disposed in the area between the first pixel circuit PC1 and the second pixel circuit PC2.

[0169] The bias scan line GBL may extend to cross the semiconductor pattern SMP. The seventh gate electrode G7 and the eighth gate electrode G8 of the seventh transistor T7 and the eighth transistor T8 may be formed by the bias scan line GBL. The portion of the bias scan line GBL overlapping with the semiconductor pattern SMP may be defined as the seventh gate electrode G7 and the eighth gate electrode G8. The seventh gate electrode G7 may overlap with the seventh channel region A7, and the eighth gate electrode G8 may overlap with the eighth channel region A8.

[0170] The first dummy electrode DME1 may be disposed between the first transistor T1, the second transistor T2, and the fifth transistor T5. The first dummy electrode DME1 may extend longer in the first direction DR1 than in the second direction DR2, that is, the length of the first dummy electrode DME1 in the first direction DR1 may be longer than the length of the first dummy electrode DME1 in the second direction DR2.

[0171] In Figures 8C to 8E for ease of description and illustration, the reference numerals of the source regions S1 to S9, the drain regions D1 to D9, the channel regions A1 to A9, and the gate electrodes G1 to G9 of the first transistor T1 to the ninth transistor T9 are omitted, and the reference numerals of the first transistor T1 to the ninth transistor T9 are illustrated. However, for ease of description, only the reference numeral of the first gate electrode G1 is illustrated in Figure 8C In

[0172] In Figures 8C to 8E the omitted reference numerals of the source regions S1 to S9, the drain regions D1 to D9, the channel regions A1 to A9, and the gate electrodes G1 to G9 refer to the reference numerals illustrated in Figure 8A and Figure 8B illustrated in

[0173] Referring to Figures 8A to 8C a second gate pattern GPT2 may be disposed on the first gate pattern GPT1. The second gate pattern GPT2 may include a dummy electrode DME, a second dummy electrode DME2, a first emission line EML1, a first initialization line VIL1, a second emission line EML2, a repair line RL, and a bias line VBL.

[0174] The dummy electrode DME may overlap with the first gate electrode G1. The dummy electrode DME may form a first capacitor C1 together with the first gate electrode G1. A first opening OP1 may be defined in the dummy electrode DME. A part of the first gate electrode G1 may be exposed by the first opening OP1.

[0175] The second dummy electrode DME2 may overlap with the first dummy electrode DME1. The second dummy electrode DME2 may form a second capacitor C2 together with the first dummy electrode DME1. A second opening OP2 may be defined in the second dummy electrode DME2. A part of the first dummy electrode DME1 may be exposed by the second opening OP2.

[0176] The second dummy electrode DME2 may extend toward the third transistor T3 and the fourth transistor T4. The second dummy electrode DME2 may overlap with a portion of the semiconductor pattern SMP between the third channel regions A3 and a portion of the semiconductor pattern SMP between the fourth channel regions A4.

[0177] The dummy electrode DME and the second dummy electrode DME2 can be adjacent to each other in the second direction DR2. The dummy electrode DME and the second dummy electrode DME2 can be closer to the upper side of the first pixel circuit PC1 than the first emission line EML1, the first initialization line VIL1, the second emission line EML2, the repair line RL, and the bias line VBL.

[0178] The first emission line EML1, the first initialization line VIL1, the second emission line EML2, the repair line RL, and the bias line VBL can extend in the first direction DR1 and can be arranged in the second direction DR2. The first emission line EML1, the first initialization line VIL1, the second emission line EML2, the repair line RL, and the bias line VBL can be closer to the lower side of the first pixel circuit PC1 than the dummy electrode DME and the second dummy electrode DME2.

[0179] The first emission line EML1, the first initialization line VIL1, the second emission line EML2, and the repair line RL can be disposed between the dummy electrode DME and the bias line VBL. The first emission line EML1 can be disposed between the dummy electrode DME and the first initialization line VIL1. The first initialization line VIL1 can be disposed between the first emission line EML1 and the second emission line EML2.

[0180] The second emission line EML2 can be disposed between the first initialization line VIL1 and the repair line RL. The bias scan line GBL can be disposed between the repair line RL and the bias line VBL. The bias line VBL can be closer to the lower side of the first pixel circuit PC1 than the bias scan line GBL.

[0181] In Figure 8D and Figure 8E the reference numerals of the first capacitor C1 and the second capacitor C2, the dummy electrode DME, and the first dummy electrode DME1 and the second dummy electrode DME2 are omitted, and the omitted reference numerals of the first capacitor C1 and the second capacitor C2, the dummy electrode DME, and the first dummy electrode DME1 and the second dummy electrode DME2 refer to Figure 8C the reference numerals shown in

[0182] Referring to Figures the first connection pattern SDP1 can be disposed on the second gate pattern GPT2. The first connection pattern SDP1 can be defined as a first source-drain pattern.

[0183] The first connection pattern SDP1 can include a plurality of first connection electrodes CNE1 and CE1-1 to CE1-9, a connection line CL, a write scan line GWL, a compensation scan line GCL, a reference line VL, an initialization scan line GIL, and a second initialization line VIL2. The first connection electrode CNE1 can be ​The first connection electrode CNE1 illustrated in the figure. The write scan line GWL, the compensation scan line GCL, the reference line VL, the initialization scan line GIL, and the second initialization line VIL2 can extend in the first direction DR1 and can be arranged in the second direction DR2.

[0184] The write scan line GWL, one compensation scan line GCL, and the reference line VL can be adjacent to the upper side of the first pixel circuit PC1. The one compensation scan line GCL can be provided between the write scan line GWL and the reference line VL. The write scan line GWL can be closer to the upper side of the first pixel circuit PC1 than the one compensation scan line GCL.

[0185] The initialization scan line GIL, another compensation scan line GCL, and the second initialization line VIL2 can be closer to the lower side of the first pixel circuit PC1 than the write scan line GWL, the one compensation scan line GCL, and the reference line VL.

[0186] The initialization scan line GIL can be adjacent to the dummy electrode DME. The another compensation scan line GCL can be provided between the initialization scan line GIL and the first emission line EML1. One second initialization line VIL2 can be provided between the repair line RL and the bias scan line GBL. Another second initialization line VIL2 can be provided between the bias scan line GBL and the bias line VBL.

[0187] The first connection electrodes CE1-1 to CE1-9, the connection line CL, the write scan line GWL, the compensation scan line GCL, the reference line VL, the initialization scan line GIL, and the second initialization line VIL2 can be provided in the same layer as the first connection electrode CNE1 (or directly provided in the same layer). The first connection electrodes CE1-1 to CE1-9, the connection line CL, the write scan line GWL, the compensation scan line GCL, the reference line VL, the initialization scan line GIL, and the second initialization line VIL2 can be patterned simultaneously with the same material as the material of the first connection electrode CNE1.

[0188] A plurality of contact holes H and a plurality of first contact holes CH1 and H1-1 to H1-16 can be defined in the first connection pattern SDP1. The first contact hole CH1 can be ​ the first contact hole CH1 illustrated in the figure. The contact hole H and the first contact holes H1-1 to H1-16 can be formed similarly to the first contact hole CH1.

[0189] The first connection electrode CNE1 can be connected to the sixth drain region D6 of the sixth transistor T6 through the first contact hole CH1. The first connection electrode CNE1 can be connected to ​ the second connection electrode CNE2 illustrated in the figure.

[0190] A part of the repair line RL may overlap with a part of the first connection electrode CNE1. When the first pixel circuit PC1 is damaged and not driven, the repair line RL can be laser-connected to the first connection electrode CNE1. Although not shown, dummy pixel circuits may be provided in the non-display area NDA described above. The dummy pixel circuits can be connected to the repair line RL. Accordingly, when the first pixel circuit PC1 is damaged, the dummy pixel circuits connected to the repair line RL can be used.

[0191] The bias scan line GBL may include a connection line CL. The connection line CL may extend in the first direction DR1. The connection line CL may be provided between the first pixel circuit PC1 and the second pixel circuit PC2. The connection line CL can be connected to the sub-bias scan line SBL through a contact hole H overlapping with the connection line CL. The separated sub-bias scan lines SBL can be electrically connected to each other through the connection line CL.

[0192] The first connection electrode CE1-1 can be connected to the fifth source region S5 of the fifth transistor T5, the dummy electrode DME, and the first dummy electrode DME1 through a first contact hole H1-1 overlapping with the first connection electrode CE1-1. The first connection electrode CE1-1 can be connected to the first dummy electrode DME1 through a first contact hole H1-1 overlapping with the second opening OP2.

[0193] Since the second drain region D2 of the second transistor T2 extends from the fifth source region S5, the second transistor T2 can also be connected to the first dummy electrode DME1 through the first connection electrode CE1-1.

[0194] The first connection electrode CE1-2 can be connected to the second dummy electrode DME2 through a first contact hole H1-2 overlapping with the first connection electrode CE1-2. The first connection electrode CNE1-3 can be connected to the second source region S2 of the second transistor T2 through a first contact hole H1-3 overlapping with the first connection electrode CE1-3.

[0195] The first connection electrode CE1-4 can be connected to the first gate electrode G1 of the first transistor T1 and the fourth source region S4 of the fourth transistor T4 through a first contact hole H1-4 overlapping with the first connection electrode CE1-4. The first connection electrode CE1-4 can be connected to the first gate electrode G1 through a first contact hole H1-4 overlapping with the first opening OP1. The first transistor T1 and the fourth transistor T4 can be connected to each other through the first connection electrode CE1-4.

[0196] Since the third drain region D3 of the third transistor T3 extends from the fourth source region S4, the third transistor T3 can also be connected to the first transistor T1 through the first connection electrode CE1-4.

[0197] The first connection electrode CE1-5 can be connected to the ninth gate electrode G9 of the ninth transistor T9 and the first emission line EML1 through a first contact hole H1-5 overlapping with the first connection electrode CE1-5. The first connection electrode CE1-6 can be connected to the fourth drain region D4 of the fourth transistor T4 and the first initialization line VIL1 through a first contact hole H1-6 overlapping with the first connection electrode CE1-6.

[0198] The first connection electrode CE1-7 can be connected to the ninth source region S9 of the ninth transistor T9 through a first contact hole H1-7 overlapping with the first connection electrode CE1-7. The first connection electrode CE1-8 can be connected to the sixth gate electrode G6 of the sixth transistor T6 and the second emission line EML2 through a first contact hole H1-8 overlapping with the first connection electrode CE1-8. The first connection electrode CE1-9 can be connected to the eighth source region S8 of the eighth transistor T8 and the bias line VBL through a first contact hole H1-9 overlapping with the first connection electrode CE1-9.

[0199] The write scan line GWL can be connected to the second gate electrode G2 of the second transistor T2 through the first contact hole H1-10. A compensation scan line GCL can be connected to the fifth gate electrode G5 of the fifth transistor T5 through the first contact hole H1-11.

[0200] The reference line VL can be connected to the fifth drain region D5 of the fifth transistor T5 through the first contact hole H1-12. The initialization scan line GIL can be connected to the fourth gate electrode G4 of the fourth transistor T4 through the first contact hole H1-13. Another compensation scan line GCL can be connected to the third gate electrode G3 of the third transistor T3 through the first contact hole H1-14.

[0201] The second initialization line VIL2 provided between the bias scan line GBL and the bias line VBL can be connected to the seventh drain region D7 of the seventh transistor T7 through the first contact hole H1-15. The second initialization line VIL2 provided between the repair line RL and the bias scan line GBL can be connected to the seventh drain region D7 of the seventh transistor T7 of the second pixel circuit PC2 through the first contact hole H1-16.

[0202] In ​ the reference numerals of the first connection electrodes CNE1 and CE1-1 to CE1-9, the first contact holes CH1 and H1-1 to H1-16, the contact hole H, and the first opening OP1 and the second opening OP2 are omitted, and the omitted reference numerals of the first connection electrodes CNE1 and CE1-1 to CE1-9, the first contact holes CH1 and H1-1 to H1-16, the contact hole H, and the first opening OP1 and the second opening OP2 refer to ​ the reference numerals shown in

[0203] Reference ​ , the second connection pattern SDP2 may be disposed on the first connection pattern SDP1. The second connection pattern SDP2 may be defined as a second source-drain pattern.

[0204] The second connection pattern SDP2 may include a second connection electrode CNE2, a data line DL, a first power line PL1, a reference line VL', and a second initialization line VIL2'. The second connection electrode CNE2 may be ​ the second connection electrode CNE2 illustrated in. The data line DL, the first power line PL1, the reference line VL', and the second initialization line VIL2' may extend in a second direction DR2 and may be arranged in a first direction DR1.

[0205] The data line DL, the first power line PL1, the reference line VL', and the second initialization line VIL2' may be disposed in the same layer as (or directly in the same layer as) the second connection electrode CNE2. The data line DL, the first power line PL1, the reference line VL', and the second initialization line VIL2' may be patterned simultaneously with the same material as the material of the second connection electrode CNE2.

[0206] The first power line PL1 may be disposed between the data line DL and the reference line VL'. The second initialization line VIL2' may overlap with the third pixel circuit PC3.

[0207] A plurality of second contact holes CH2 and H2-1 to H2-5 may be defined in the second connection pattern SDP2. The second contact hole CH2 may be ​ the second contact hole CH2 illustrated in. The second contact holes H2-1 to H2-5 may be formed similarly to the second contact hole CH2.

[0208] The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through the second contact hole CH2. The second connection electrode CNE2 may be connected to ​ the first electrode AE illustrated in. For ease of illustration, the first electrode AE is omitted in the layout diagram of the pixel PX. The first electrode AE may be connected to the sixth transistor T6 through the first connection electrode CNE1 and the second connection electrode CNE2.

[0209] The sixth semiconductor layers S6, A6, and D6 of the sixth transistor T6 may extend to the first drain region D1, and the sixth drain region D6 may be connected to the first electrode AE. Accordingly, the first drain region D1 may be connected to the light-emitting element OLED.

[0210] The data line DL can be connected to the first connection electrode CE1-3 through the second contact hole H2-1. The data line DL can be connected to the second transistor T2 through the first connection electrode CE1-3.

[0211] The first power line PL1 can be connected to the first connection electrode CE1-2 through the second contact hole H2-2. The first power line PL1 can be connected to the second dummy electrode DME2 through the first connection electrode CE1-2. The first power line PL1 can be connected to the first connection electrode CE1-7 through the second contact hole H2-3. The first power line PL1 can be connected to the ninth transistor T9 through the first connection electrode CE1-7. Accordingly, the ninth transistor T9 and the second capacitor C2 can be connected to the first power line PL1.

[0212] The first voltage can be applied to the second dummy electrode DME2 through the first power line PL1. That is, a constant voltage can be applied to the second dummy electrode DME2. As described above, the second dummy electrode DME2 can partially overlap the semiconductor pattern SMP of the third transistor T3 and the fourth transistor T4. When a constant voltage is applied to the second dummy electrode DME2, the threshold voltage Vth of each of the third transistor T3 and the fourth transistor T4 overlapping with the second dummy electrode DME2 can be maintained without change.

[0213] The reference line VL’ can be defined as a vertical reference line. The reference line VL’ can be connected to the reference line VL through the second contact hole H2-4. The reference voltage VR can be applied to the reference line VL through the reference line VL’.

[0214] The second initialization line VIL2’ can be connected to the second initialization line VIL2 adjacent to the lower side of the first pixel circuit PC1 through the second contact hole H2-5. The second initialization voltage VAINT can be applied to the second initialization line VIL2’ and the second initialization line VIL2.

[0215] ​ is a schematic plan view showing pixels and bias scan lines arranged in a row. ​ is a view showing only multiple bias scan lines in the display panel.

[0216] In ​ the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 are shown in a rectangular shape, and the pixels PX are separated by a rectangular dotted line.

[0217] Refer to ​ and ​, in an embodiment of the display panel DP, the bias scan line GBL can extend in a first direction DR1 and can be arranged in a second direction DR2. In each of the bias scan lines GBL, a plurality of connection lines CL and more than two sub-bias scan lines SBL can be provided. That is, each of the bias scan lines GBL can include a plurality of connection lines CL and a plurality of sub-bias scan lines SBL.

[0218] The pixels PX can be arranged in the first direction DR1. The connection lines CL and the sub-bias scan lines SBL can extend in the first direction DR1 and can be arranged in the first direction DR1.

[0219] Each of the pixels PX can include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 can be ​ corresponding to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 illustrated in

[0220] In an embodiment, one connection line CL can be provided for every three pixels PX. The sub-bias scan lines SBL can be spaced apart from each other for every three pixels PX and can be connected by the connection lines CL. That is, the connection line CL can be provided in each of the h-th pixel PX and the h+3-th pixel PX, and in each of the h-th pixel PX and the h+3-th pixel PX, the sub-bias scan lines SBL can be spaced apart from each other and can be connected by the connection line CL. Here, h is a natural number greater than 0.

[0221] ​ and ​ are views illustrating components of a bias scan line according to an embodiment of the present disclosure.

[0222] ​ and ​ are ​ corresponding plan views. Hereinafter, the description will focus on the differences from the components illustrated in ​ to describe the components illustrated in ​ and ​ .

[0223] Referring to ​ , in an embodiment, one connection line CL can be provided for every two pixels PX. The sub-bias scan lines SBL can be spaced apart from each other for every two pixels PX and can be connected by the connection lines CL. That is, the connection line CL can be provided in each of the h-th pixel PX and the h+2-th pixel PX, and in each of the h-th pixel PX and the h+2-th pixel PX, the sub-bias scan lines SBL can be spaced apart from each other and can be connected by the connection line CL.

[0224] Reference ​ In another embodiment, a connection line CL may be provided for each pixel PX. The sub-bias scan lines SBL may be spaced apart from each other for each pixel PX and may be connected by the connection line CL.

[0225] Reference ​ 、 ​ and ​ In an embodiment, the sub-bias scan lines SBL may be spaced apart from each other for a predetermined number of pixels PX, and each of the connection lines CL may be provided for a predetermined number of pixels PX and may connect the sub-bias scan lines SBL.

[0226] Embodiments of the present disclosure are not limited to ​ 、 ​ and ​ the configurations illustrated in. In another embodiment, for example, the sub-bias scan lines SBL may be spaced apart from each other for every four or more pixels PX, and each of the connection lines CL may be provided for every four or more pixels PX to connect the sub-bias scan lines SBL.

[0227] ​ is a cross-sectional view taken along line I-I' illustrated in ​ .

[0228] Reference ​ In reference, a seventh channel region A7 and an eighth channel region A8 may be provided on the buffer layer BFL. A first insulating layer INS1 may be provided on the seventh channel region A7, the eighth channel region A8, and the buffer layer BFL.

[0229] The sub-bias scan lines SBL may be provided on the first insulating layer INS1 and may be spaced apart from each other at a region or area between the seventh channel region A7 and the eighth channel region A8. A second insulating layer INS2 and a third insulating layer INS3 may be provided on the sub-bias scan lines SBL and the first insulating layer INS1.

[0230] The connection line CL may be provided on the third insulating layer INS3. The connection line CL may be connected to the sub-bias scan lines SBL through contact holes H defined in the second insulating layer INS2 and the third insulating layer INS3. A fourth insulating layer INS4 and a fifth insulating layer INS5 may be provided on the connection line CL and the third insulating layer INS3.

[0231] The connection line CL may be provided in a layer different from the layer in which the sub-bias scan line SBL is provided (or directly provided in a layer different from the layer in which the sub-bias scan line SBL is provided), and may be connected to the sub-bias scan line SBL. In an embodiment, for example, the connection line CL may be provided above the sub-bias scan line SBL and may be connected to the sub-bias scan line SBL. Accordingly, ​ and ​ the connection line CL illustrated in may be provided above the sub-bias scan line SBL and may be connected to the sub-bias scan line SBL.

[0232] Reference ​ and ​ , the connection line CL may be provided in the same layer as the first connection electrode CNE1 (or directly provided in the same layer). The sub-bias scan line SBL may be provided in the same layer as the gate electrodes G1 and G6 (or directly provided in the same layer). Accordingly, the connection line CL may be provided above the gate electrodes G1 and G6.

[0233] ​ is a view for explaining the doping process of the semiconductor layer.

[0234] ​ The gate electrode G and the semiconductor layers S, A, and D illustrated in may be the gate electrode and the semiconductor layers of one of the first transistor T1 to the ninth transistor T9.

[0235] Reference ​ , in an embodiment, after the gate electrode G is provided (or formed) on the first insulating layer INS1, a doping process may be performed on the semiconductor layers S, A, and D. The dopant DOT may be provided to the source region S and the drain region D using the gate electrode G as a mask. Accordingly, the source region S and the drain region D may be formed as highly doped regions.

[0236] ​ is a view illustrating the doping process performed in a state where the sub-bias scan line of the present disclosure is provided on the substrate. ​ is a view illustrating the doping process performed in a state where the comparison bias scan line is provided on the substrate.

[0237] Reference ​ and ​ , according to an embodiment, the comparison bias scan line GBL' may be formed of a single line and is not divided into sub-bias scan lines SBL like the bias scan line GBL.

[0238] In the doping process, a phenomenon may occur in which charges accumulate in the bias scan line GBL and the comparison bias scan line GBL'. For example, in ​ and ​ the charges are illustrated in a circular shape.

[0239] When a single line such as a comparison bias scan line GBL’ is provided on a substrate SUB, more charges may accumulate on the comparison bias scan line GBL’. Depending on the accumulation of charges, static electricity may be generated. The static electricity may damage the seventh channel region A7 and the eighth channel region A8 that are semiconductor layers. For example, the seventh channel region A7 and the eighth channel region A8 that are semiconductor layers may be burned out by the static electricity generated due to the accumulation of charges. Accordingly, the transistors T7 and T8 may be damaged, and thus the pixel PX may be damaged.

[0240] In an embodiment of the present disclosure, the bias scan line GBL may be divided into a plurality of sub-bias scan lines SBL, and thus, the accumulation of charges may be dispersed to the sub-bias scan lines SBL during a doping process. Accordingly, the static electricity generated from the bias scan line GBL may be reduced, and damage to the pixel PX may be effectively prevented.

[0241] ​ FIG. is a view showing components of a bias scan line according to various embodiments of the present disclosure.

[0242] ​ is related to ​ a corresponding cross-sectional view. Hereinafter, components shown in ​ will be described focusing on differences from the components shown in ​ .

[0243] Referring to ​ and ​ , in an embodiment, the bias scan line GBL-1 may include a plurality of sub-bias scan lines SBL and a connection line CL-1. The connection line CL-1 may be provided on a fifth insulating layer INS5. Accordingly, the connection line CL-1 may be in the same layer as (or directly in the same layer as) a second connection electrode CNE2. The connection line CL-1 may be connected to the sub-bias scan line SBL through a contact hole H-1 defined in the second insulating layer INS2 to the fifth insulating layer INS5.

[0244] Referring to ​ and ​ , in another embodiment, the bias scan line GBL-2 may include a plurality of sub-bias scan lines SBL and a connection line CL-2. The connection line CL-2 may be provided on a second insulating layer INS2. Accordingly, the connection line CL-2 may be in the same layer as (or directly in the same layer as) a dummy electrode DME. The connection line CL-2 may be connected to the sub-bias scan line SBL through a contact hole H-2 defined in the second insulating layer INS2.

[0245] Referring to ​ and ​, in another embodiment, the bias scan line GBL-3 may include a plurality of sub-bias scan lines SBL1 and SBL2 and a connection line CL. The connection line CL may be disposed on the third insulating layer INS3.

[0246] The sub-bias scan lines SBL1 and SBL2 may be respectively disposed in different layers (or directly disposed in different layers). In an embodiment, for example, the sub-bias scan lines SBL1 and SBL2 may include a first sub-bias scan line SBL1 disposed in the same layer as (or directly disposed in the same layer as) the gate electrodes G1 and G6, and a second sub-bias scan line SBL2 disposed in the same layer as (or directly disposed in the same layer as) the dummy electrode DME.

[0247] The connection line CL may be connected to the first sub-bias scan line SBL1 through a contact hole H-3 defined in the second insulating layer INS2 and the third insulating layer INS3. The connection line CL may be connected to the second sub-bias scan line SBL2 through a contact hole H-4 defined in the third insulating layer INS3.

[0248] According to an embodiment of the present disclosure, the bias scan line may be divided into a plurality of sub-bias scan lines, and thus, the accumulation of charges may be dispersed to the sub-bias scan lines during the doping process. Accordingly, the static electricity generated from the bias scan line may be reduced, and damage to the pixels may be effectively prevented.

[0249] The present invention should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the concept of the present invention to those skilled in the art.

[0250] Although the present invention has been specifically shown and described with reference to embodiments of the present invention, those of ordinary skill in the art will understand that various changes in form and details may be made therein without departing from the spirit or scope of the present invention as defined by the claims.

Claims

1. A display device, comprising: Scan lines extending in a first direction, wherein the scan lines include write scan lines and bias scan lines; Data lines extending in a second direction intersecting the first direction; and Pixels connected to the scan lines and the data lines, wherein the bias scan lines include: a plurality of sub-bias scan lines spaced apart from each other in the first direction; and connection lines connected to the sub-bias scan lines.

2. The display device according to claim 1, wherein, The connection lines are disposed in a layer different from the layer in which the sub-bias scan lines are disposed.

3. The display device according to claim 2, wherein, The connection lines are disposed above the sub-bias scan lines.

4. The display device according to claim 1, wherein, The pixels include: A first pixel circuit, a second pixel circuit, and a third pixel circuit, the first pixel circuit, the second pixel circuit, and the third pixel circuit being arranged in the first direction; and Light-emitting elements respectively connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit.

5. The display device according to claim 4, wherein, A gap in the first direction between the first pixel circuit and the second pixel circuit is greater than a gap in the first direction between the second pixel circuit and the third pixel circuit.

6. The display device according to claim 5, wherein, The connection lines are disposed between the first pixel circuit and the second pixel circuit.

7. The display device according to claim 1, wherein, The data lines are provided in a plurality of numbers, The pixels are provided in a plurality of numbers, The connection lines are provided in a plurality of numbers, and The sub-bias scan lines include three or more sub-bias scan lines, and wherein a plurality of pixels, a plurality of connection lines, and the three or more sub-bias scan lines are arranged in the first direction.

8. The display device according to claim 7, wherein, One of the plurality of connection lines is provided for every three pixels, and The three or more sub-bias scan lines are spaced apart from each other for every three pixels and are connected to each other through the connection lines.

9. The display device according to claim 7, wherein, One of the plurality of connection lines is provided for every two pixels, and The three or more sub-bias scan lines are spaced apart from each other for every two pixels and are connected to each other through the connection lines.

10. The display device according to claim 7, wherein, One of the plurality of connection lines is provided for each pixel, and The three or more sub-bias scan lines are spaced apart from each other for each pixel and are connected to each other through the connection lines.

11. The display device according to claim 1, wherein, The pixels include: A plurality of transistors connected to the data lines, the write scan lines, and the bias scan lines; and Light-emitting elements connected to corresponding ones of the transistors, wherein each of the transistors includes: a semiconductor layer including a source region, a channel region, and a drain region; and a gate electrode disposed above the semiconductor layer, and wherein the sub-bias scan lines and the gate electrodes are disposed in the same layer.

12. The display device according to claim 11, wherein, The connection lines are disposed above the gate electrodes.

13. The display device according to claim 11, wherein, The pixels further include: Dummy electrodes disposed above the gate electrodes; First connection electrodes disposed above the dummy electrodes and connected to corresponding ones of the transistors; and A second connection electrode, disposed on top of the first connection electrode and connected to the first connection electrode, and wherein, the light-emitting element is disposed on top of the second connection electrode and connected to the second connection electrode.

14. The display device according to claim 13, wherein, The connection line and the first connection electrode are disposed in the same layer.

15. The display device according to claim 13, wherein, The connection line and the second connection electrode are disposed in the same layer.

16. The display device according to claim 13, wherein, The connection line and the dummy electrode are disposed in the same layer.

17. The display device according to any one of claims 1 to 16, wherein, The sub-bias scan lines are respectively disposed in different layers.

18. A display device, comprising: Scan lines extending in a first direction, wherein the scan lines include write scan lines and bias scan lines; A plurality of data lines extending in a second direction intersecting the first direction; and A plurality of pixels arranged in the first direction and connected to the scan lines and the data lines, wherein, the bias scan lines include: a plurality of sub-bias scan lines spaced apart from each other for at least one pixel; and a plurality of connection lines connected to the sub-bias scan lines.

19. The display device according to claim 18, wherein, The connection lines are disposed above the sub-bias scan lines.

20. A display device, comprising: Scan lines extending in a first direction, wherein the scan lines include write scan lines and bias scan lines; Data lines extending in a second direction intersecting the first direction; and Pixels connected to the scan lines and the data lines, wherein, the bias scan lines include: two sub-bias scan lines spaced apart from each other in the first direction; and a connection line connected to the two sub-bias scan lines, wherein, the pixels include: a plurality of transistors connected to the data lines, the write scan lines and the bias scan lines; and a light-emitting element connected to a corresponding one of the transistors, and wherein, the two sub-bias scan lines and the gate electrodes of the transistors are disposed in the same layer, and the connection line is disposed above the gate electrodes.

Images