Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first display area; the second display area is at least located on one side of the first display area; the plurality of sub-pixels are located in the first display area and the second display area; the plurality of pixel groups are located in the first display area, and at least one pixel group in the plurality of pixel groups comprises at least two sub-pixels; a first power line configured to provide a first voltage signal to the pixel circuit, the first power line including a plurality of first conductive lines and a plurality of second conductive lines; at least one of the first wires comprises a first sub-wire extending in the first direction and a second sub-wire extending in the second direction, and the second sub-wire is electrically connected with at least one of the second wires. According to the display panel, the net-shaped structure of the first power line can be more stable, and the voltage drop on the first power line is reduced, so that the brightness uniformity of the display panel is better.

Description

[0001] This application is a divisional application of the Chinese patent application No. 202010621890.3, filed on June 30, 2020, with the invention title of "Display Panel and Display Device". Technical Field

[0002] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0003] Based on the design of an under-screen camera, a display panel usually includes a high pixel density (Pixels Per Inch, PPI) region and a low PPI region. However, in a conventional display panel, the light transmittance in the low PPI region is relatively low, which is not conducive to improving the display effect of the camera in the imaging region. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display panel, including: a first display area; a second display area at least on one side of the first display area; a plurality of sub-pixels located in the first display area and the second display area, the density of the sub-pixels in the first display area being less than the density of the sub-pixels in the second display area, the sub-pixels including pixel circuits; a plurality of pixel groups located in the first display area, at least one pixel group of the plurality of pixel groups including at least two sub-pixels; and a first power supply line configured to provide a first voltage signal to the pixel circuits, the first power supply line including a plurality of first conductors and a plurality of second conductors, the plurality of first conductors extending from the second display area to the first display area and electrically connecting the plurality of pixel groups, the plurality of second conductors being located in the first display area and between adjacent first conductors, the plurality of second conductors extending in a first direction, adjacent second conductors being spaced apart from each other in the first direction, the plurality of second conductors electrically connecting the plurality of pixel groups; at least one of the plurality of first conductors includes a first sub-wire extending in the first direction and a second sub-wire extending in a second direction, the first direction and the second direction intersecting, and the second sub-wire electrically connecting at least one of the plurality of second conductors.

[0005] For example, in the display panel provided by at least one embodiment of the present disclosure, the at least two sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel are arranged in the first direction, at least one of the plurality of second conductors electrically connects the first sub-pixel and the second sub-pixel, and the second sub-wire is located in a different layer from the plurality of second conductors.

[0006] For example, in the display panel provided by at least one embodiment of the present disclosure, the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is respectively connected to the second transistor, the second transistor is connected to the light-emitting element, the first transistor includes a first active portion and a second active portion, and the first active portion and the second active portion are connected by a conductive portion.

[0007] For example, in the display panel provided by at least one embodiment of the present disclosure, the second wire further includes a connecting arm, the connecting arm is spaced from the conductive portion of a sub-pixel overlapping the second wire in the pixel group in a third direction, and partially overlaps in the third direction, the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0008] For example, in the display panel provided by at least one embodiment of the present disclosure, the shape of the connecting arm includes a C shape.

[0009] For example, in the display panel provided by at least one embodiment of the present disclosure, the plurality of pixel groups include a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and adjacent first pixel groups and second pixel groups are connected by a plurality of traces.

[0010] For example, the display panel provided by at least one embodiment of the present disclosure further includes a connecting wire, and the positive projections of at least two of the plurality of traces between the adjacent first pixel group and the second pixel group on the substrate fall within the positive projection of the connecting wire on the substrate.

[0011] For example, in the display panel provided by at least one embodiment of the present disclosure, there are a plurality of gaps between the plurality of traces, and the positive projection of at least one of the plurality of gaps on the substrate at least partially overlaps the positive projection of the connecting wire on the substrate.

[0012] For example, in the display panel provided by at least one embodiment of the present disclosure, the pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light-emitting control signal line, and an initialization signal line to respectively provide a first reset signal, a second reset signal, a gate scanning signal, a light-emitting control signal, and an initialization signal for the pixel circuit; the plurality of traces are selected from at least two of the first reset signal line, the second reset signal line, the gate line, the light-emitting control signal line, the initialization signal line, and the first wire.

[0013] For example, in the display panel provided by at least one embodiment of the present disclosure, the connection wire has a stopper, and the stopper is disposed on the same layer as the connection wire and integrally formed; the sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is respectively connected to the second transistor and the storage capacitor, the second transistor is connected to the light-emitting element, the first transistor includes a first active portion and a second active portion, and the first active portion and the second active portion are connected by a conductive portion; the stopper and the conductive portion of a pixel unit in the pixel group that overlaps the first wire are spaced apart from each other in the third direction and partially overlap in the third direction.

[0014] For example, in the display panel provided by at least one embodiment of the present disclosure, at least a part of the orthographic projection of the connection wire on the substrate is located between the orthographic projections of the adjacent first pixel group and second pixel group on the substrate.

[0015] For example, in the display panel provided by at least one embodiment of the present disclosure, the first reset signal line, the second reset signal line, the gate line, the light-emitting control signal line, the initialization signal line, and the second wire of the first pixel group are respectively connected to the first reset signal line, the second reset signal line, the gate line, the light-emitting control signal line, the initialization signal line, and the second wire of the second pixel group through the plurality of traces.

[0016] For example, in the display panel provided by at least one embodiment of the present disclosure, the connection wire and the second wire are located on the same layer and integrally formed; or the connection wire and the initialization signal line are located on the same layer and integrally formed; or the connection wire and the first wire are located on the same layer.

[0017] For example, in the display panel provided by at least one embodiment of the present disclosure, the at least two sub-pixels further include a third sub-pixel and a fourth sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged along the first direction and are located on one side of the first sub-pixel and the second sub-pixel along the second direction, the third sub-pixel and the fourth sub-pixel are electrically connected to another one of the plurality of second wires, and the second sub-trace is electrically connected to at least one of the plurality of second wires.

[0018] For example, in the display panel provided by at least one embodiment of the present disclosure, the second sub-trace has a stopper, the stopper is located on a different layer from the second sub-trace and is connected through a via, the stopper and the conductive portion of a pixel unit in the pixel group that overlaps the first wire are spaced apart from each other in the third direction and partially overlap in the third direction.

[0019] For example, in the display panel provided by at least one embodiment of the present disclosure, the first direction is perpendicular to the second direction.

[0020] For example, in the display panel provided by at least one embodiment of the present disclosure, the plurality of second conductors are arranged in sequence along the first direction.

[0021] For example, in the display panel provided by at least one embodiment of the present disclosure, the adjacent second conductors are not directly connected.

[0022] For example, in the display panel provided by at least one embodiment of the present disclosure, the first conductor and the second conductor are connected through a via hole penetrating the insulating layer.

[0023] For example, in the display panel provided by at least one embodiment of the present disclosure, the first power supply line further includes a third conductor and a fourth conductor. The third conductor extends along the second direction, and the third conductor extends from the second display area to the first display area, and the second conductor is electrically connected to the third conductor; the fourth conductor extends along the second direction, the second conductor is electrically connected to the fourth conductor, and the length of the fourth conductor in the second direction is less than or equal to the length of the third conductor in the second direction.

[0024] For example, in the display panel provided by at least one embodiment of the present disclosure, it includes a plurality of fourth conductors. The plurality of fourth conductors are located between adjacent third conductors. The plurality of fourth conductors are arranged in sequence along the second direction, and adjacent fourth conductors are spaced apart from each other in the second direction.

[0025] For example, in the display panel provided by at least one embodiment of the present disclosure, the first conductor and the third conductor are located on the same layer, and the fourth conductor and the third conductor are located on the same layer.

[0026] For example, in the display panel provided by at least one embodiment of the present disclosure, the first display area includes a plurality of light-transmitting areas, which are located between adjacent pixel groups.

[0027] For example, in the display panel provided by at least one embodiment of the present disclosure, the plurality of pixel groups and the traces connected to adjacent pixel groups surround the plurality of light-transmitting areas.

[0028] At least one embodiment of the present disclosure further provides a display device, including the display panel provided by any embodiment of the present disclosure.

[0029] For example, the display device provided by at least one embodiment of the present disclosure further includes a sensor; the sensor is disposed on one side of the display panel, and the orthographic projection of the sensor on the substrate at least partially overlaps with the first display area. Description of the Drawings

[0030] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0031] Figures 1A to 1C Schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0032] Figure 2 Schematic diagram of a second display area of a display panel provided by at least one embodiment of the present disclosure;

[0033] Figure 3 Schematic diagram of a first display area of a display panel provided by at least one embodiment of the present disclosure;

[0034] Figure 4 Schematic diagram of sub-pixels in a display panel and signal lines for providing signals to the sub-pixels provided by at least one embodiment of the present disclosure;

[0035] Figure 5 Schematic diagram of a display panel provided by at least one embodiment of the present disclosure;

[0036] Figures 6A to 6F A pixel circuit and its stacked structure diagram provided by some embodiments of the present disclosure;

[0037] Figure 7 Schematic diagram of a display panel provided by at least one embodiment of the present disclosure;

[0038] Figure 8A For Figure 7 An enlarged schematic diagram of the area A11 shown in;

[0039] Figure 8B For Figure 7 An enlarged schematic diagram of the area A12 shown in;

[0040] Figure 8C For Figure 7 A plan view of the semiconductor pattern of the display panel shown;

[0041] Figure 9 For Figure 7 A plan view of the first conductive pattern layer of the display panel shown;

[0042] Figure 10 For Figure 7 A plan view of the second conductive pattern layer of the display panel shown;

[0043] Figure 11 For Figure 7 A plan view of the third conductive pattern layer of the display panel shown;

[0044] Figure 12 A plan view of another display panel provided by at least one embodiment of the present disclosure;

[0045] Figure 13 is Figure 12 An enlarged schematic view of the area A21 shown in;

[0046] Figure 14 is Figure 12 A plan view of the semiconductor pattern of the display panel shown in;

[0047] Figure 15 is Figure 12 A plan view of the first conductive pattern layer of the display panel shown in;

[0048] Figure 16 is Figure 12 A plan view of the second conductive pattern layer of the display panel shown in;

[0049] Figure 17 is Figure 12 A plan view of the third conductive pattern layer of the display panel shown in;

[0050] Figure 18 A schematic view of another display panel provided by at least one embodiment of the present disclosure;

[0051] Figure 19 is Figure 18 A plan view of the semiconductor pattern of the display panel shown in;

[0052] Figure 20 is Figure 18 A plan view of the first conductive pattern layer of the display panel shown in;

[0053] Figure 21 is Figure 18 A plan view of the second conductive pattern layer of the display panel shown in;

[0054] Figure 22 is Figure 18 A plan view of the third conductive pattern layer of the display panel shown in;

[0055] Figure 23 A cross-sectional schematic view of a pixel circuit of a display panel provided by at least one embodiment of the present disclosure;

[0056] Figure 24 A cross-sectional schematic view of a display panel provided by at least one embodiment of the present disclosure; and

[0057] Figure 25 A schematic view of a display device provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0058] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0059] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second" and similar words used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. The terms "connect" or "couple" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0060] Due to people's preference for selfies, a front camera hole must exist, and the front camera hole and sensors will occupy a certain amount of space. Currently, the methods for placing the front camera hole are as follows: using a notch screen or a waterdrop screen; or using an AA hole (Active Area), that is, digging a hole within the AA area and placing the entire camera hole and sensors within the AA area. However, neither of these two methods can meet the requirements of a full-screen design. Therefore, we choose to adopt the under-screen camera technology, which improves the aperture ratio of the screen by changing the pixel density and places the camera under the screen, thus not damaging the integrity of the entire screen display.

[0061] To achieve a borderless full-screen design, the under-screen camera technology must be adopted, which requires increasing the aperture ratio of the display panel. Therefore, on the premise of meeting the above requirements, how to arrange the structure of the display panel to ensure the display effect of the display panel has become an urgent problem to be solved.

[0062] At least one embodiment of the present disclosure provides a display panel, including: a first display area; a second display area at least on one side of the first display area; a plurality of sub-pixels located in the first display area and the second display area, the density of the sub-pixels in the first display area being less than the density of the sub-pixels in the second display area, and the sub-pixels including pixel circuits; a plurality of pixel groups located in the first display area, at least one pixel group in the plurality of pixel groups including at least two sub-pixels; and a first power line configured to provide a first voltage signal to the pixel circuits, the first power line including a plurality of first conductors and a plurality of second conductors, the plurality of first conductors extending from the second display area to the first display area and electrically connecting the plurality of pixel groups, the plurality of second conductors being located in the first display area and between adjacent first conductors, the plurality of second conductors extending in a first direction, adjacent second conductors being spaced from each other in the first direction, and the plurality of second conductors electrically connecting the plurality of pixel groups; at least one of the plurality of first conductors includes a first sub-wire extending in the first direction and a second sub-wire extending in a second direction, the first direction and the second direction intersecting, and the second sub-wire electrically connecting at least one of the plurality of second conductors.

[0063] The display panel provided by the embodiment of the present disclosure can make the mesh structure of the first power line more stable, reduce the voltage drop on the first power line, so that the brightness uniformity of the display panel is better, thereby improving the display effect of the camera in the imaging area.

[0064] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0065] In a conventional display panel, whether in a high PPI area or a low PPI area, the first power line adopts a mesh structure. In order to make the mesh structure of the first power line more stable, reduce the voltage drop on the first power line, so that the brightness uniformity of the display panel is better, and thereby improve the display effect of the camera in the imaging area, the display panel provided by the embodiment of the present disclosure optimizes the signal lines in the low PPI area. For example, the embodiment of the present disclosure optimizes the horizontally and vertically arranged conductors of the mesh first power line.

[0066] Figures 1A to 1C Schematic diagram of a display panel provided for some embodiments of the present disclosure. As Figures 1A to 1C shown, the display panel includes a first display area R1 and a second display area R2. The first display area R1 is a low pixel density (Pixels Per Inch, PPI) area, and the second display area R2 is a high PPI area. The first display area R1 is a partial light transmission area. As Figures 1A to 1C shown, the second display area R2 is at least on one side of the first display area R1. Figure 1A and Figure 1BThe display panel shown also includes a third region R3. A sensor, such as a camera, may be disposed in the first display region R1 (as Figure 1C shown), or may be disposed in the first display region R1 and the third region R3 (as Figure 1A and Figure 1B shown). Figure 1A and Figure 1B The third region R3 shown in and may be a hole-digging region, that is, the material at the position corresponding to the third region R3 is removed to form a through hole. The sensor can receive ambient light. Taking the sensor as a camera as an example, an under-screen camera is implemented, so that when the screen is normally used, the first display region corresponding to the sensor can display the picture normally, and when the camera takes a picture, the first display region can transmit ambient light to support normal use. For example, the sensor is disposed on the non-display side of the display panel. The sensor may also be referred to as an under-screen device.

[0067] Figure 1A Also shown are a plurality of gate lines 113 and a plurality of data lines 313. The plurality of gate lines 113 includes a first gate line GL1, and the plurality of data lines 313 includes a first data line DL1. The first gate line GL1 extends from the second display region R2 to the first display region R1. The first data line DL1 extends from the first display region R1 to the second display region R2. In an embodiment of the present disclosure, that a certain element extends from the first display region R1 to the second display region R2 can be understood that the element is located in the first display region R1 and the second display region R2, or it can also be said that a certain element extends from the second display region R2 to the first display region R1. For the sake of clear illustration, Figure 1A several gate lines 113 and several data lines 313 are schematically shown, and the number of the gate lines 113 and the data lines 313 can be determined according to needs. The plurality of gate lines 113 and the plurality of data lines 313 intersect each other and are insulated from each other.

[0068] Figure 2 It is a schematic diagram of the second display region of the display panel provided by at least one embodiment of the present disclosure. Figure 3 It is a schematic diagram of the first display region of the display panel provided by at least one embodiment of the present disclosure. As Figure 2 and Figure 3 shown, the display panel includes a plurality of sub-pixels P0, and the plurality of sub-pixels P0 includes a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. For example, the display panel includes a plurality of pixel groups P1, located in the first display region R1, and at least one pixel group P1 in the plurality of pixel groups P1 includes at least two sub-pixels. For example, in some examples, one pixel group P1 may include 4 sub-pixels. For example, as Figure 3As shown, a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104 form a pixel group P1; for example, in some other examples, a pixel group P1 may include 2 sub-pixels. For example, as Figure 5 shown, a first sub-pixel 101 and a second sub-pixel 102 form a pixel group P1; for example, a pixel group P1 may also include three sub-pixels (as Figure 18 shown), and the embodiments of the present disclosure are not limited thereto. For example, a pixel group P1 is a repeating unit and is arranged in an array in the second display area R2. As Figure 3 shown, in the first display area R1, a pixel group P1 is also referred to as a pixel island P1. The same applies to the following embodiments and will not be repeated. The first display area R1 includes a plurality of light-transmitting areas R0; the light-transmitting areas R0 are located between adjacent pixel islands P1. The light-transmitting areas R0 can transmit ambient light. For example, the light-transmitting areas R0 may include a substrate and a transparent insulating layer located on the substrate. The light-transmitting areas R0 do not have a light-blocking structure, for example, do not have metal traces. For example, the light-transmitting areas R0 are located in the area surrounded by four adjacent pixel islands P1, but are not limited thereto. For example, as Figure 3 shown, adjacent pixel islands P1 are spaced apart.

[0069] For example, the length of each of the plurality of light-transmitting areas R0 is substantially the same as the length of a sub-pixel. For example, the pixel group and the traces connected to adjacent pixel groups surround the plurality of light-transmitting areas R0.

[0070] For example, in Figure 7 the example shown, a pixel island may also include two sub-pixels, for example, including a first sub-pixel 101 and a second sub-pixel 102. For example, the first sub-pixel 101 is a red sub-pixel and the second sub-pixel 102 is a green sub-pixel; for example, in Figure 18 the embodiment shown, a pixel island P1 may also include three sub-pixels, for example, including a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel. For example, the three sub-pixels are located in a row; for example, in Figure 12In the illustrated example, a pixel island may further include four sub-pixels. For example, it includes a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, the third sub-pixel 103 is a blue sub-pixel, and the fourth sub-pixel 104 is a green sub-pixel. In other embodiments, the pixel units in the pixel group may also use pixel units of other colors. Of course, in other embodiments, the arrangement of multiple sub-pixels P0 in the display panel is not limited to Figure 2 and Figure 3 as shown. Embodiments of the present disclosure do not limit this.

[0071] Referring to Figure 2 and Figure 3 , multiple sub-pixels P0 are located in the first display area R1 and the second display area R2. The density of the pixel units in the first display area R1 is less than the density of the pixel units in the second display area R2. Or rather, the density of the sub-pixels in the first display area R1 is less than the density of the sub-pixels in the second display area R2. Figure 3 As shown, the density of the pixel units in the first display area R1 is one-fourth of the density of the pixel units in the second display area R2. That is, Figure 3 as shown, the density of the sub-pixels in the first display area R1 is one-fourth of the density of the sub-pixels in the second display area R2. The arrangement of the light-transmitting area R0 and the pixel units within the first display area R1 is not limited to Figure 3 as shown and can be set as needed. For example, in other embodiments, the density of the sub-pixels in the first display area R1 is one-half, one-third, one-sixth, or one-eighth, etc., of the density of the sub-pixels in the second display area R2, which are other values different from one-fourth. Embodiments of the present disclosure do not limit this.

[0072] For example, as Figure 1A and Figure 3 shown, the display panel further includes gate lines 113 and data lines 313. The gate lines 113 and the data lines 313 are insulated from each other. Each gate line 113 connects a row of sub-pixels, and each data line 313 connects a column of sub-pixels. For example, the gate lines 113 are configured to provide a scan signal to a row of sub-pixels.

[0073] For example, as Figure 1A and Figure 3 shown, the data line 313 includes a first data line DL1. The first data line DL1 is at least located in the first display area R1. For example, the first data line DL1 extends from the first display area R1 to the second display area R2.

[0074] For example, as Figure 1A and Figure 3As shown, the gate line includes a first gate line GL1, and the first gate line GL1 extends from the second display area R2 to the first display area R1. As Figure 3 shown, the light-transmitting area R0 is formed by enclosing two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.

[0075] Figure 4 It is a schematic diagram of sub-pixels in a display panel provided by an embodiment of the present disclosure and signal lines for providing signals to the sub-pixels. As Figure 4 shown, the display panel includes: a plurality of sub-pixels P0, each sub-pixel P0 includes a light-emitting element EMC and a pixel circuit 10 for providing a driving current to the light-emitting element EMC. The light-emitting element EMC can be an electroluminescent element, for example, an organic electroluminescent element, such as an organic light-emitting diode (OLED).

[0076] As Figure 4 shown, the display panel further includes an initialization signal line 210, a light-emitting control signal line 110, a data line 313, a first power supply line 311, and a second power supply line 312. For example, the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The light-emitting control signal line 110 is configured to provide a light-emitting control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10. The first power supply line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10. The second power supply line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its magnitude can be, for example, between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint can be less than or equal to the second voltage signal ELVSS. For example, the pixel circuit 10 outputs a driving current under the control of signals such as the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, and the light-emitting control signal EM to drive the light-emitting element EMC to emit light. As Figure 4 shown, the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2. The pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power supply line 312.

[0077] Figure 5 It is a schematic diagram of a display panel provided by some embodiments of the present disclosure. It should be noted that, Figure 5Taking a pixel island P1 including two sub-pixels as an example for illustration, each pixel island P1 may also include 3 or 4 sub-pixels, and their specific connection relationships are similar thereto, which will not be elaborated herein. The embodiments of the present disclosure are not limited thereto.

[0078] As Figure 5 shown, the first power supply line 311 includes a plurality of first conductors L1 and a plurality of second conductors L2. For example, the first power supply line 311 may also include a plurality of third conductors L3. For example, the first conductor L1 extends from the second display area R2 to the first display area R1 and is electrically connected to a plurality of pixel groups (i.e., pixel islands) P1. The plurality of second conductors L2 are located in the first display area R1 and are located between adjacent first conductors L1. Each second conductor L2 extends along the first direction D1, and the plurality of second conductors L2 are electrically connected to a plurality of pixel groups P1. For example, the third conductor L3 is at least located in the first display area R1. For example, the third conductor L3 extends from the second display area R2 to the first display area R1, the third conductor L3 extends along the second direction D2, the first direction D1 intersects the second direction D2, and adjacent second conductors L2 are spaced apart from each other along the first direction D1. The adjacent second conductors L2 are connected by the first conductor L1 and are connected to the third conductor L3 to receive the first voltage signal ELVDD. For example, the first direction D1 is perpendicular to the second direction D2, but is not limited thereto. For example, the first conductor L1 extends along the first direction D1. For example, in the embodiments of the present disclosure, the second conductor L2 is only located in the first display area R1. In the embodiments of the present disclosure, an element extending along a certain direction is not necessarily a straight line and may also have a curved or broken line portion. For example, the extending direction of an element refers to the general extending trend of the element. For example, each part of the element does not necessarily extend along this direction.

[0079] For example, as Figure 5 shown, the first conductor L1 and the second conductor L2 are respectively connected to the sub-pixels located in the corresponding rows of two adjacent pixel islands P1, but are not limited thereto. In other embodiments, the pixel island P1 may also include two rows or more of sub-pixels. For example, as Figures 6A to 6E shown, the pixel island P1 includes at least two pixel units in one row, and the second conductor L2 overlaps with the two pixel units in this one row. For example, as Figure 5 shown, the first conductor L1 is located between two adjacent pixel islands P1, and the second conductors L2 that overlap with the two adjacent pixel islands P1 respectively are connected by the first conductor L1.

[0080] For example, as Figure 5 shown, the plurality of second conductors L2 are arranged in sequence along the first direction D1. For example, as Figure 5As shown, adjacent second conductors L2 are not directly connected, for example, connected by a jumper wire, that is, connected by a first conductor L1 located on different layers, so that the mesh structure of the first power supply line can be more stable, reducing the voltage drop on the first power supply line, so that the brightness uniformity of the display panel is better. Of course, adjacent second conductors L2 can also be directly connected, and the embodiments of the present disclosure do not limit this.

[0081] For example, as Figure 5 shown, in order to improve the light transmittance of the first display area, the length of the part of the first conductor L1 located in the first display area R1 in the first direction D1 is greater than the length of the second conductor L2 in the first direction D1.

[0082] For example, as Figure 5 shown, the first power supply line 311 further includes a fourth conductor L4, the fourth conductor L4 extends along the second direction D2, the second conductor L2 is connected to the fourth conductor L4 to receive the first voltage signal ELVDD, and the length of the fourth conductor L4 in the second direction D2 is less than or equal to the length of the third conductor L3 in the second direction D2. In Figure 5 the shown display panel, the length of the fourth conductor L4 in the second direction D2 is less than the length of the third conductor L3 in the second direction D2.

[0083] For example, as Figure 5 shown, in order to further improve the light transmittance of the first display area, a plurality of fourth conductors L4 are provided, the plurality of fourth conductors L4 are arranged in sequence along the second direction D2, and adjacent fourth conductors L4 are spaced from each other in the second direction D2. For example, as Figure 5 shown, a plurality of fourth conductors L41 are located between the third conductor L31 and the third conductor L32, and the third conductor L31 and the third conductor L32 are adjacent third conductors L3. Figure 5 5 fourth conductors L41 are shown, but the number of fourth conductors L4 located between adjacent third conductors L3 is not limited to that shown in the figure and can be determined according to needs. Because the plurality of fourth conductors L4 are spaced from each other in the second direction D2, it is equivalent to removing a part of the first power supply line arranged along the second direction in a normal display panel, thereby reducing wiring, optimizing the routing space, and improving the light transmittance.

[0084] For example, as Figure 5 shown, the first power supply line 311 further includes a fifth conductor L5, the fifth conductor L5 extends along the first direction D1, the fifth conductor L5 is located in the second display area R2, and the fifth conductor L5 and the adjacent second conductor L2 are spaced from each other along the first direction D1. Thus, at the junction position between the first display area and the second display area, the wiring is reduced and the light transmittance is improved.

[0085] In the embodiments of the present disclosure, the number of pixel units included in each pixel island and the arrangement manner of the pixel units are not limited.

[0086] As Figure 5 shown, in the display panel, the first power line 311 further includes a plurality of sixth conductors L6, the sixth conductors L6 are located in the second display area R2, and the sixth conductors L6 extend along the second direction D2. In the second display area R2, a plurality of fifth conductors L5 and a plurality of sixth conductors L6 are arranged in a crosswise manner. In the embodiments of the present disclosure, both the fifth conductors L5 and the sixth conductors L6 are only located in the second display area R2.

[0087] As Figure 5 shown, the same gate line 113 connects the sub-pixels in the second display areas on both sides of the first display area R1 and the sub-pixels in the first display area R1 to form a row of sub-pixels. The embodiments of the present disclosure do not limit the form of the first conductor, as long as it can extend from the second display area R2 to the first display area R1. Figure 5 The first power line in Figure 5 can also be replaced with the first power line in other embodiments of the present disclosure. Moreover, the extending manner of the gate line 113 is not limited to

[0088] shown, as long as the arrangement manner of the gate line 113 can connect the pixels in the second display area R2 and the pixels in the first display area R1. For example, in the first display area R1, the gate lines of the sub-pixels in the corresponding rows between two adjacent pixel islands are connected through the seventh conductors L7 (i.e., in the way of jumpers). Of course, the gate lines of the sub-pixels in the corresponding rows between two adjacent pixel islands can also be directly connected, and the embodiments of the present disclosure do not limit this.

[0088] For example, the corresponding relationship between the remaining signal lines (such as the initialization signal line providing the initialization signal Vint and the light emission control signal line providing the light emission control signal EM) and a pixel island P1 is as Figure 5 shown, and the embodiments of the present disclosure do not limit this and will not be elaborated herein.

[0089] For example, in Figure 5 the shown display panel, the first conductor is in contact with two adjacent second conductors through vias penetrating the insulating layer.

[0090] For example, in an embodiment of the present disclosure, a row of sub-pixels are sub-pixels connected to the same gate line 113, and a column of sub-pixels are sub-pixels connected to the same data line 313. In an embodiment of the present disclosure, the first wire L1, the second wire L2, and the fifth wire L5 all extend along the row direction (i.e., the first direction D1), and the third wire L3, the fourth wire L4, and the sixth wire L6 extend along the column direction (i.e., the second direction D2) as an example for illustration, but it is not limited thereto. In other embodiments, the first wire L1, the second wire L2, and the fifth wire L5 may all extend along the column direction, and the third wire L3, the fourth wire L4, and the sixth wire L6 extend along the row direction. Correspondingly, the second direction D2 and the first direction D1 are also replaced with each other.

[0091] Figure 5 Taking the pixel island including two sub-pixels (for example, a row of sub-pixels) as an example, in other embodiments, the pixel island may further include three or more (for example, two rows of sub-pixels) sub-pixels. In this case, the above-mentioned multiple second wires can be understood as the second wires connected to the same row of sub-pixels in a pixel island. When the first wire L1, the second wire L2, and the fifth wire L5 all extend along the column direction, and the third wire L3, the fourth wire L4, and the sixth wire L6 extend along the row direction, the above-mentioned multiple second wires can be understood as the second wires connected to the same column of sub-pixels in a pixel island.

[0092] The following combines Figures 6A to 24 to describe some embodiments of the present disclosure. Figures 6A to 24 Taking the pixel circuit of 7T1C as an example for illustration.

[0093] Figure 6A It is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present disclosure. Figure 6B It is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the present disclosure. Figure 6C It is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 6D It is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure. Figure 23 It is a cross-sectional schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 24 It is a cross-sectional schematic diagram of a display panel provided by an embodiment of the present disclosure. In the embodiment of the present disclosure, for clear illustration, in the plan view, the insulating layer is shown in the form of a via hole, and the insulating layer itself is made transparent.

[0094] It should be noted that Figures 6B - 6F respectively show the hierarchical structure diagrams of pixel circuits including two sub-pixels. It should be noted that it may also include more or fewer sub-pixels, and the structure of its pixel circuit can adoptFigures 6B - 6F design the layout of one of the pixels shown in this disclosure, and the embodiments of the present disclosure do not limit this. For example, Figure 6F Taking the pixel structure of the first sub-pixel 101 as an example for introduction, the pixel structures of the remaining sub-pixels, such as the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, are similar thereto and will not be elaborated herein.

[0095] For example, referring to Figure 6A , the gate line 113 is configured to provide a scan signal SCAN to the pixel circuit 10. The light emission control signal line 110 is configured to provide a light emission control signal EM to the sub-pixel P0. The data line 313 is configured to provide a data signal DATA to the pixel circuit 10, the first power supply line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10, the second power supply line 312 is configured to provide a constant second voltage signal ELVSS to the pixel circuit 10, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS. The initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10. The initialization signal Vint is a constant voltage signal, and its magnitude can, for example, be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint can be less than or equal to the second voltage signal ELVSS. For example, the pixel circuit outputs a driving current under the control of signals such as the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, and the light emission control signal EM to drive the light emitting element 20 to emit light. The light emitting element 20 emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit 10.

[0096] As Figure 6A shown, the pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The driving transistor T1 is electrically connected to the light emitting element 20 and outputs a driving current to drive the light emitting element 20 to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, and the second voltage signal ELVSS.

[0097] For example, the display panel provided by the embodiments of the present disclosure further includes: a data driving circuit and a scan driving circuit. The data driving circuit is configured to provide a data signal DATA to the sub-pixel P0 according to the instruction of the control circuit; the scan driving circuit is configured to provide a light emission control signal EM, a scan signal SCAN, a first reset control signal RST1, a second reset signal RST2, and other signals to the sub-pixel P0 according to the instruction of the control circuit. For example, the control circuit includes an external integrated circuit (IC), but is not limited thereto. For example, the scan driving circuit is a GOA (Gate driver On Array) structure mounted on the display panel, or a driving chip (IC) structure bonded to the display panel. For example, different driving circuits may also be used to respectively provide the light emission control signal EM and the scan signal SCAN. For example, the display panel further includes a power supply (not shown in the figure) to provide the above voltage signals, which may be a voltage source or a current source as needed, and the power supply is configured to provide a first voltage signal ELVDD, a second voltage signal ELVSS, and an initialization signal Vint to the sub-pixel P0 through a first power line 311, a second power line 312, and an initialization signal line 210, respectively.

[0098] As Figure 6A shown, the second pole C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first pole C11 of the storage capacitor C1 is electrically connected to the second pole T32 of the threshold compensation transistor T3. The gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first pole T21 and the second pole T22 of the data writing transistor T2 are respectively electrically connected to the data line 313 and the first pole T11 of the driving transistor T1. The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1.

[0099] For example, as Figure 6A shown, the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110.

[0100] For example, as Figure 6AAs shown, the first pole T41 and the second pole T42 of the first light-emitting control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the driving transistor T1, respectively. The first pole T51 and the second pole T52 of the second light-emitting control transistor T5 are electrically connected to the second pole T12 of the driving transistor T1 and the pixel electrode E1 (which can be the anode of the OLED) of the light-emitting element 20, respectively. The common electrode E2 (which can be the common electrode of the OLED, such as the cathode) of the light-emitting element 20 is electrically connected to the second power line 312.

[0101] For example, as Figure 6A shown, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first pole T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (the first initialization signal line 211), and the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (the second initialization signal line 212), and the second pole T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0102] Figure 6B shows the semiconductor pattern SCP, Figure 6C shows the first conductive pattern layer LY1. A first gate insulating layer is provided between the first conductive pattern layer LY1 and the semiconductor pattern SCP. The semiconductor pattern SCP is doped using the first conductive pattern layer LY1 as a mask, such that the region of the semiconductor pattern SCP not covered by the first conductive pattern layer LY1 retains semiconductor characteristics to form the channel of the thin-film transistor, while the region of the semiconductor pattern SCP covered by the first conductive pattern layer LY1 is conductorized to form the source or drain of the thin-film transistor. As Figure 6A shows the active layer ALT formed after the semiconductor pattern SCP is partially conductorized.

[0103] As Figure 6C shown, the first conductive pattern layer LY1 includes the first reset control signal line 111, the second reset control signal line 112, the light-emitting control signal line 110, the gate line 113, and the first pole C11 of the storage capacitor C1. Figure 6C Also shown is the first part DL11 (the wire 114) of the first data line DL1. For example, referring to Figure 7 , in the embodiment of the present disclosure, the current row gate line 113 is also connected to the second reset control signal line 112 in the same row.

[0104] Figure 6DThe second conductive pattern layer LY2 is shown. A second gate insulating layer is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1. The second conductive pattern layer LY2 includes a stopper BK0, a stopper BK1, an initialization signal line 210, and a second pole C12 of the storage capacitor C1. The second poles C12 of the storage capacitors C1 of two sub-pixels of a pixel island are integrally formed as the second wire L2. The second pole C12 of the storage capacitor C1 has an opening OPN. An interlayer insulating layer is located between the second conductive pattern layer LY2 and the third conductive pattern layer LY3. Regarding the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3, reference can be made to the introduction in the art and will not be elaborated here.

[0105] Figure 6E The third conductive pattern layer LY3 is shown. The third conductive pattern layer LY3 includes a first wire L1, a third wire L3 (a part of the first power supply line 311), a fourth wire L4 (a part of the first power supply line 311), a second part DL12 of the data line (a part of the data line 313), a first connection electrode 31a, a second connection electrode 31b, a third connection electrode 31c, and a fourth connection electrode 31d.

[0106] For example, as Figure 6E shown, at least one of the plurality of first wires L1 includes a first sub-wire L111 extending along a first direction D1 and a second sub-wire L112 extending along a second direction D2, and the second sub-wire L112 is electrically connected to at least one of the plurality of second wires L2. For example, as Figure 11 shown, the second sub-wire L112 is electrically connected to the second wires L2 of the corresponding rows in adjacent pixel islands. For example, as Figure 13 and Figure 17 shown, the second sub-wire L112 is electrically connected to two second wires L2 in a pixel island and two second wires L2 in a pixel island adjacent to the pixel island. The embodiments of the present disclosure are not limited thereto.

[0107] For example, the second sub-wire L112 is connected to the stopper BK0 through a via hole penetrating the interlayer insulating layer and is connected to the second wire L2 through a via hole penetrating the interlayer insulating layer.

[0108] Figure 6F is Figures 6B - 6E a stacked structure diagram. Refer to Figures 6B - 8A, the data line 313 is electrically connected to the first pole T21 of the data writing transistor T2 through a via hole, the first power supply line 311 is electrically connected to the first pole T41 of the first light-emitting control transistor T4 through a via hole, the first power supply line 311 is electrically connected to the second pole C12 of the storage capacitor C1 through a via hole, and the first power supply line 311 is electrically connected to the conductive block BK1 through a via hole. One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 through a via hole, and the other end of the first connection electrode 31a is connected to the first pole T61 of the first reset transistor T6 through a via hole, so that the first pole T61 of the first reset transistor T6 is electrically connected to the first initialization signal line 211. One end of the second connection electrode 31b is electrically connected to the second pole T62 of the first reset transistor T6 through a via hole, and the other end of the second connection electrode 31b is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole C11 of the storage capacitor C1) through a via hole, so that the second pole T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (i.e., the first pole C11 of the storage capacitor C1). One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 through a via hole, and the other end of the third connection electrode 31c is connected to the first pole T71 of the second reset transistor T7 through a via hole, so that the first pole T71 of the second reset transistor T7 is electrically connected to the second initialization signal line 212. The fourth connection electrode 31d is electrically connected to the second pole T52 of the second light-emitting control transistor T5 through a via hole. The fourth connection electrode 31d can be used to be electrically connected to the pixel electrode E1 of the light-emitting element 20 formed subsequently (refer to Figure 6A ). For example, the positional relationship between the first connection electrode 31a and the third connection electrode 31c can refer to Figure 6E in the figure. For the sake of clarity and conciseness, it is not shown again in Figure 6F .

[0109] It should be noted that the transistors used in some embodiments of the present disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The source and drain of the transistors used here can be symmetric in structure, so there is no difference between the source and drain in structure. In an embodiment of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other as the second pole. Therefore, the first pole and the second pole of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed. For example, the first pole of the transistor described in the embodiments of the present disclosure can be the source, and the second pole can be the drain; or, the first pole of the transistor is the drain, and the second pole is the source.

[0110] In addition, transistors can be classified into N-type and P-type transistors according to their characteristics. In the embodiments of the present disclosure, P-type transistors are used as an example for illustration. Based on the description and teaching of the present disclosure for this implementation manner, those of ordinary skill in the art can easily think of using at least some of the transistors in the pixel circuit of the embodiments of the present disclosure as N-type transistors, that is, using N-type transistors or an implementation manner combining N-type transistors and P-type transistors. Therefore, these implementation manners are also within the protection scope of the present disclosure.

[0111] Figures 6A to 6F Taking the pixel circuit of 7T1C as an example for illustration, the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display substrate may also have a structure including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, and the embodiments of the present disclosure do not limit this.

[0112] Figure 23 It is a cross-sectional schematic diagram of the pixel circuit of the display panel provided by some embodiments of the present disclosure. For example, as Figure 23As shown, the display panel includes a thin film transistor 50 and a storage capacitor C1. The thin film transistor 50 includes an active layer ATL1 located on a substrate BS, a first gate insulating layer GI1 on a side of the active layer ATL1 away from the substrate BS, and a gate electrode GE on a side of the first gate insulating layer GI1 away from the substrate BS. The display panel further includes a second gate insulating layer GI2 on a side of the gate electrode GE away from the substrate BS, an interlayer insulating layer ILD on a side of the second gate insulating layer GI2 away from the substrate BS, and a source or drain CNE1 on a side of the interlayer insulating layer ILD away from the substrate BS. For example, when the thin film transistor 50 is implemented as an N-type transistor, CNE1 represents the source of the thin film transistor 50, and CNE2 represents the drain of the thin film transistor 50. When the thin film transistor 50 is implemented as a P-type transistor, CNE1 represents the drain of the thin film transistor 50, and CNE2 represents the source of the thin film transistor 50. The active layer ATL1 includes a channel CN11 and a first electrode ET1 and a second electrode ET2 respectively located on both sides of the channel CN11. The connection electrode CNE1 is connected to the second electrode ET2 through a via hole penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD. The storage capacitor C1 includes a first electrode C11 and a second electrode C12. The first electrode C11 and the gate electrode GE are on the same layer, both located in the first conductive pattern layer LY1. The second electrode C12 is between the second gate insulating layer GI2 and the interlayer insulating layer ILD, located in the second conductive pattern layer LY2. One of the first electrode ET1 and the second electrode ET2 is the source, and the other of the first electrode ET1 and the second electrode ET2 is the drain. The connection electrode CNE1 is located in the third conductive pattern layer LY3. The display panel further includes a passivation layer PVX and a planarization layer PLN. For example, the source or drain CNE1 is the first part of the fourth connection electrode 31d shown in Figure 6E or 6F, and the thin film transistor 50 can be the second light-emitting control transistor T5 as described above.

[0113] As Figure 23 shown, the display panel further includes a light-emitting element EMC. The light-emitting element EMC includes a pixel electrode E1, a light-emitting functional layer EML, and a common electrode E2. The pixel electrode E1 is connected to the connection electrode CNE1 through a via hole penetrating the passivation layer PVX and the planarization layer PLN. The display panel further includes a packaging layer CPS. The packaging layer CPS includes a first packaging layer CPS1, a second packaging layer CPS2, and a third packaging layer CPS3. For example, the first packaging layer CPS1 and the third packaging layer CPS3 are inorganic material layers, and the second packaging layer CPS2 is an organic material layer. For example, the pixel electrode E1 is an anode and the common electrode E2 is a cathode, but it is not limited thereto.

[0114] For example, the light-emitting element EMC includes an organic light-emitting diode. The light-emitting functional layer is located between the common electrode E2 and the pixel electrode E1. The light-emitting functional layer EML includes at least a light-emitting layer, and may further include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

[0115] As Figure 23 shown, the display panel further includes a pixel definition layer PDL and spacers PS. The pixel definition layer PDL has openings configured to define the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit, and the spacers PS are configured to support a fine metal mask when forming the light-emitting functional layer EML. Figure 23 It is shown that spacers PS are provided on both opposite sides of the light-emitting element, but it is not limited thereto.

[0116] For example, a data line is configured to input a data signal to the pixel unit, a first power line is configured to input a first voltage signal to the driving transistor. A second power line is configured to input a second voltage signal to the sub-pixel. The first voltage signal is a constant voltage, and the second voltage signal is a constant voltage. For example, the first voltage signal is a positive voltage and the second voltage signal is a negative voltage, but it is not limited thereto. For example, in some embodiments, the first voltage signal is a positive voltage and the second power line is grounded.

[0117] Referring Figure 23 to, in an embodiment of the present disclosure, the first insulating layer ISL1 includes at least one of a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization layer PLN.

[0118] For example, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel definition layer PDL, and the spacers PS are all made of insulating materials. For example, the materials of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX include at least one of SiOx and SiNx, but it is not limited thereto. For example, the planarization layer PLN, the pixel definition layer PDL, and the spacers PS can be made of an organic insulating material, for example, resin, but it is not limited thereto.

[0119] Referring Figure 6F to, the threshold compensation transistor T3 includes a first active portion CN1 and a second active portion CN2, and the first active portion CN1 and the second active portion CN2 are connected by a conductive portion CP. Referring Figure 8B and Figure 10, the second conductive line L2 also includes a connecting arm L21. The threshold compensation transistor T3 is a dual-gate transistor. When the threshold compensation transistor T3 is turned off, the conductive portion CP is in a floating state and is easily affected by the surrounding line voltage and jumps. The voltage jump of the conductive portion CP will affect the leakage current of the threshold compensation transistor T3, and further affect the luminous brightness of the pixel unit. Therefore, it is necessary to keep the voltage of the conductive portion CP stable. A block can be designed to form a capacitor with the conductive portion CP. The block can have a constant voltage signal so that the voltage of the conductive portion CP in the floating state is also kept stable. The block BK0 and block BK1 mentioned in the embodiments of the present disclosure and the connecting arm mentioned later all play a role in stabilizing the voltage of the conductive portion CP.

[0120] Figure 7 A schematic diagram of a display panel provided by at least one embodiment of the present disclosure; Figure 8A for Figure 7 An enlarged schematic diagram of the area A11 shown in FIG; Figure 8B for Figure 7 An enlarged schematic diagram of the area A12 shown in FIG. Figure 8C for Figure 7 A plan view of a semiconductor pattern of a display panel shown; Figure 9 for Figure 7 A plan view of the first conductive pattern layer of the display panel shown; Figure 10 for Figure 7 A plan view of the second conductive pattern layer of the display panel shown; Figure 11 for Figure 7 A plan view of the third conductive pattern layer of the display panel is shown.

[0121] For example, Figure 7 As shown, the at least two sub-pixels include a first sub-pixel 101 and a second sub-pixel 102, and the first sub-pixel 101 and the second sub-pixel 102 are arranged along a first direction D1. Figure 8A As shown, at least one of the plurality of second conductive lines L2 is electrically connected to the first sub-pixel 101 and the second sub-pixel 102 , and the second sub-line L112 and the plurality of second conductive lines L2 are located in different layers.

[0122] For example, Figure 6A As shown, the sub-pixel P0 further includes a light emitting element 20, and the pixel circuit includes a first transistor (eg, a threshold compensation transistor T3) and a second transistor (eg, Figure 6A The first transistor T3 is connected to the second transistor T5, and the second transistor T5 is connected to the light emitting element 20, for example, Figure 6F As shown, the first transistor T3 includes a first active portion CN1 and a second active portion CN2 , and the first active portion CN1 and the second active portion CN2 are connected via a conductive portion CP.

[0123] For example, as Figure 8B and Figure 10 shown, the second wire L2 further includes a connection arm L21. The connection arm L21 and the conductive part CP of a sub-pixel in the pixel group that overlaps with the second wire L2 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3 (refer to Figure 24 ). The third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2.

[0124] For example, as Figure 8B and Figure 10 shown, the shape of the connection arm L21 includes a C shape. It should be noted that the connection arm L21 is generally in a C shape. Of course, the connection arm L21 can also adopt other shapes as long as it can play a role in stabilizing the threshold compensation transistor T3.

[0125] Refer to Figure 24 , the connection arm L21 and the conductive part CP of the threshold compensation transistor T3 partially overlap to form a capacitor C0. A first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connection arm L21 and the conductive part CP. Figure 24 The second active part CN2 is also shown. The capacitor C0 can be called a stabilizing capacitor, and the connection arm L21 and the conductive part CP are two plates of the capacitor C0. As Figure 24 shown, the gate GE2 and the second active part CN2 overlap in a direction perpendicular to the substrate BS. The gate GE2 is a gate of the threshold compensation transistor T3. As Figure 24 shown, a part of the second connection electrode 31b (as shown in Figure 6E ) serves as the second pole T32 (for example, the drain) of the threshold compensation transistor T3.

[0126] For example, the third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2. The third direction D3 is a direction perpendicular to the substrate BS. A first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connection arm L21 and the conductive part CP. For example, the first direction D1 and the second direction D2 are directions parallel to the main surface of the substrate BS, and the third direction D3 is a direction perpendicular to the main surface of the substrate BS. Various elements are fabricated on the main surface of the substrate BS.

[0127] Refer to Figure 6F , Figure 8A and Figure 24 , the stopper BK0 and the conductive part of a sub-pixel in the pixel island that overlaps with the first wire L1 are spaced apart from each other in the third direction D3 and partially overlap in the third direction D3. Refer to Figure 6F , Figure 8A and Figure 24, the stopper BK0 and the conductive part CP of a sub-pixel ( Figure 8A the bottom-right sub-pixel in

[0128] For example, referring to Figure 6A , Figure 6F , Figure 8B and Figure 24 , the second wire L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive part CP of a sub-pixel ( Figure 7 the upper-right sub-pixel in Figure 8B the sub-pixel in

[0129] For example, as Figure 6D shown, the initialization signal line 210 includes a plurality of hollow areas HP, the second wire L2 is located within a hollow area HP, and is surrounded by the part of the initialization signal line that encloses the hollow area HP, and the second wire L2 does not overlap with the part of the initialization signal line that encloses the hollow area HP. That is, the second wire L2 is completely surrounded by the part of the initialization signal line that encloses the hollow area HP. In the embodiment of the present disclosure, the hollow area HP is the position corresponding to the part of the thin film removed when manufacturing the initialization signal line 210.

[0130] For example, referring to FIG. Figure 8A , the first wire L1 includes a first sub-wire L111 and a second sub-wire L112, the first sub-wire L111 of the first wire L1 is not on the same layer as the second wire L2, and the second sub-wire L112 of the first wire L1 is not on the same layer as the second wire L2. Referring to Figure 8A , Figure 10 and Figure 11 , the second wire L2 is located in the second conductive pattern layer LY2, and the first wire L1 is located in the third conductive pattern layer LY3.

[0131] For example, referring to Figure 3 , the data line 313 includes a first data line DL1, and the first data line DL1 extends from the first display area R1 to the second display area R2. For example, as Figure 8AAs shown, a first part DL11 of the first data line DL1 overlaps a part of the positive projection of the third conductor L3 on the substrate base BS. This setting method is conducive to reducing the wiring area and improving the light transmittance.

[0132] For example, referring to Figure 6C , Figure 6D , Figure 7 and Figure 8A , the first data line DL1 includes a first part DL11 and a second part DL12. The first part DL11 of the first data line DL1 partially overlaps the third conductor L3, and the second part DL12 of the first data line DL1 does not overlap the third conductor L4. The first part DL11 and the second part DL12 of the first data line DL1 are located in different layers respectively. For example, Figure 8A in the left side, the first part DL11 (conductor 214) of the first data line DL1 is located in the second conductive pattern layer, and the second part DL12 of the left-side first data line DL1 is located in the third conductive pattern layer. Figure 8A In the right side, the first part DL11 (conductor 114) of the first data line DL1 is located in Figure 9 the first conductive pattern layer shown in Figure 8A , and the second part DL12 of the first data line DL1 on the right side is located in Figure 11 the third conductive pattern layer shown in Figure 3 . Figure 19 and Figure 23 , the first part DL11 of the first data line DL1 is located between adjacent pixel islands P1.

[0133] For example, referring to Figure 3 , two first data lines DL1 are provided, and the two first data lines DL1 are respectively connected to adjacent columns of sub-pixels. For example, as Figure 8A shown, the first parts DL11 of the two first data lines overlap a part of the positive projection of the same third conductor L3 on the substrate base BS. This setting method enables the data lines between the pixel islands in adjacent columns of sub-pixels to be hidden under the third conductor, thereby reducing the wiring area and improving the light transmittance.

[0134] For example, the first conductor L1 and the second conductor L2 are located in different layers and are connected by vias penetrating the insulating layer. Referring to Figure 8A and Figure 11 , the first conductor L1 is located in the third conductive pattern layer LY3, and the second conductor is located in the second conductive pattern layer LY2. Referring to Figure 23 and Figure 24, an interlayer dielectric layer ILD is disposed between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, that is, the second sub-wire L112 of the first wire L2 and the second wire L2 are connected through vias penetrating the interlayer dielectric layer ILD.

[0135] For example, referring to Figure 11 , the first wire and the third wire L3 are on the same layer, both on the third conductive pattern layer LY3. The fourth wire L4 and the third wire L3 are on the same layer, both on the third conductive pattern layer LY3.

[0136] For example, a plurality of pixel groups include a plurality of first pixel groups (i.e., pixel islands) and a plurality of second pixel groups (i.e., pixel islands) arranged at intervals. Adjacent first pixel groups and second pixel groups are connected by a plurality of traces (for example, including the trace L11 between gate lines connecting adjacent pixel islands, the trace L13 (i.e., 210) between initialization signal lines connecting adjacent pixel islands, the trace L14 between light emission control signal lines connecting adjacent pixel islands, and the first wire L1, etc.).

[0137] For example, as Figure 8A and Figure 10 shown, the display panel 1 further includes a connection wire Ld. The orthographic projections of at least two of the plurality of traces between adjacent first pixel groups and second pixel groups on the substrate fall within the orthographic projection of the connection wire Ld on the substrate. For example, in some examples, there are a plurality of gaps between the plurality of traces, and at least one of the plurality of gaps overlaps at least partially with the orthographic projection of the connection wire Ld on the substrate, so as to prevent light leakage from the gaps between the traces.

[0138] For example, as Figures 6A - 6F shown, the pixel circuit 10 includes a first reset signal line 111, a second reset signal line 112, a gate line 113, a light emission control signal line 110, and an initialization signal line 210 to respectively provide a first reset signal, a second reset signal, a gate scan signal, a light emission control signal, and an initialization signal for the pixel circuit; the plurality of traces are selected from at least two of the first reset signal line 111, the second reset signal line 112, the gate line 113, the light emission control signal line 110, the initialization signal line 210, and the first wire. For example, the first reset signal line 111, the second reset signal line 112, the gate line 113, the light emission control signal line 110, the initialization signal line 21, and the second wire of the first pixel group are respectively connected to the second reset signal line 112, the gate line 113, the light emission control signal line 110, the initialization signal line 210, and the second wire of the second pixel group through a plurality of traces.

[0139] For example, as Figure 8A and Figure 10As shown, at least a part of the orthographic projection of the connection wire Ld on the substrate is located between the orthographic projections of the adjacent first pixel group and the second pixel group on the substrate, and the connection wire Ld and the initialization signal wire are on the same layer and integrally formed.

[0140] Figure 18 FIG. is a schematic diagram of a display panel in which one pixel island includes three sub-pixels according to at least one embodiment of the present disclosure. For example, one pixel island includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. Figure 19 is Figure 18 a plan view of the semiconductor pattern of the display panel shown in;

[0141] Figure 20 is Figure 18 a plan view of the first conductive pattern layer of the display panel shown in; Figure 21 is Figure 18 a plan view of the second conductive pattern layer of the display panel shown in; Figure 22 is Figure 18 a plan view of the third conductive pattern layer of the display panel shown in.

[0142] For example, Figure 18 the display panel shown in is substantially the same as the connection structure of the display panel shown in, except that: Figure 7 the adjacent pixel islands shown in are in the same row, Figure 18 and the adjacent pixel islands shown in are staggered. For the relevant description of, reference can be made to the relevant description of, which will not be elaborated here. Figure 7 is Figure 18 reference can be made to Figures 7 - 11 the relevant description of, which will not be elaborated here.

[0143] For example, as shown in Figure 18 and Figure 21 the connection wire Ld and the second wire L2 are on the same layer and integrally formed. It should be noted that the connection wire Ld can also be on the same layer and integrally arranged with the first wire L1, and the embodiments of the present disclosure are not limited thereto.

[0144] For example, in this embodiment, as shown in Figure 21 the connection wire Ld has a stopper BK0, and the stopper BK0 is on the same layer as the connection wire Ld and integrally formed. The stopper and the conductive part of a pixel unit in the BK0 pixel group that overlaps with the first wire L1 are spaced from each other in the third direction D1 and partially overlap in the third direction D3, so as to ensure the stability of the threshold compensation transistor T3. For the specific description, reference can be made to the above introduction, which will not be elaborated here.

[0145] Figure 12Schematic diagram of a display panel provided by at least one embodiment of the present disclosure, where one pixel island includes 4 sub-pixels. For example, one pixel island includes a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. Figure 13 is Figure 12 An enlarged schematic diagram of the area A21 shown in Figure 14 is Figure 12 A plan view of the semiconductor pattern of the display panel shown in Figure 15 is Figure 12 A plan view of the first conductive pattern layer of the display panel shown in Figure 16 is Figure 12 A plan view of the second conductive pattern layer of the display panel shown in Figure 17 is Figure 12 A plan view of the third conductive pattern layer of the display panel shown in

[0146] For example, in some embodiments of the present disclosure, as Figure 12 shown, at least two sub-pixels further include a third sub-pixel 103 and a fourth sub-pixel 104. The third sub-pixel 103 and the fourth sub-pixel 104 are arranged along a first direction D1 and are located on one side of the first sub-pixel 101 and the second sub-pixel 102 along a second direction D2. The third sub-pixel 103 and the fourth sub-pixel 104 are electrically connected to another one of a plurality of second wires L2 (for example, the second wire L21 located below the layout as shown in Figure 16 ), and the second sub-wire L112 is electrically connected to at least one of the plurality of second wires. For example, it is electrically connected to the second wire L2 of the first row of pixels (i.e., the first sub-pixel 101 and the second sub-pixel 102) and / or the second wire L21 of the second row of pixels (i.e., the third sub-pixel 103 and the fourth sub-pixel 104).

[0147] For example, Figure 12 the display panel shown in Figure 7 is substantially the same as the display panel shown in Figure 15 , except that the layers where the traces connecting adjacent two pixel groups are located are different. Specifically, for example, as Figure 7 shown, the trace L11 of the gate line connecting adjacent two pixel islands is located in the first conductive pattern layer LY2, while in Figure 16 it is located in the third conductive pattern layer LY3; the initialization signal line 111 extends from the second display area R2 to the first display area R1 in the first conductive pattern layer; as Figure 16 shown, the initialization signal line 111 can also be connected through the trace Lrest located in the second conductive pattern layer.

[0148] For example, as Figure 16 and Figure 10As shown, the second sub-trace L112 has a stopper BK0. The stopper BK0 and the second sub-trace L112 are located on different layers and are connected by vias. For example, with reference to Figure 24 , the stopper BK0 is located on the second conductive pattern layer, and the second sub-trace L112 is located on Figure 17 and Figure the third conductive pattern layer LY3 shown. Therefore, in this embodiment, the stopper BK0 is connected to the second sub-trace L112 through a via penetrating the insulating layer to ensure the stability of the threshold compensation transistor T3.

[0149] It should be noted that for the remaining structures of the display panel (such as the stopper BK0), the first wire L1, etc., reference can be made to ​ for the introduction, which will not be elaborated here.

[0150] At least one embodiment of the present disclosure further provides a display device, including any of the above display panels. For example, the display device can be a display device such as an Organic Light-Emitting Diode (OLED) display, as well as any product or component with a display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, navigator, etc., including these display devices.

[0151] ​ is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. As ​ shown, the display device 2 includes a display panel 1 and a sensor 3. For example, the sensor 3 is disposed on one side of the display panel 1.

[0152] For example, as ​ shown, the sensor 3 is disposed on the second side of the display panel 1, and the sensor 3 is configured to receive light from the first side of the display panel. For example, the first side of the display panel 1 is used for display, and the first display area R1 allows light from the first side of the display panel to at least partially transmit to the second side of the display panel.

[0153] For example, the orthographic projection of the sensor 3 on the substrate substrate at least partially overlaps with the first display area R1.

[0154] It should be noted that for the sake of clarity and conciseness, the embodiments of the present disclosure do not show all the constituent units of the display device. To achieve the basic functions of the display device, those skilled in the art can provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0155] Regarding the technical effects of the display device 2 provided in the above embodiments, reference can be made to the technical effects of the display panel 1 provided in the embodiments of the present disclosure, which will not be elaborated here.

[0156] The following points need to be noted:

[0157] (1) Unless otherwise defined, in the embodiments of the present disclosure and the accompanying drawings, the same reference numerals represent the same meaning.

[0158] (2) In the accompanying drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0159] (3) For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be intermediate elements.

[0160] (4) Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0161] As described above, the above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: A first display area; A second display area, at least located on one side of the first display area; Multiple sub-pixels, located in the first display area and the second display area, the density of the sub-pixels in the first display area being less than the density of the sub-pixels in the second display area, and the sub-pixels including pixel circuits; Multiple pixel groups, located in the first display area, at least one pixel group in the multiple pixel groups including at least two sub-pixels; And A first power supply line, configured to provide a first voltage signal to the pixel circuits, and the first power supply line extends from the first display area to the second display area; Multiple data lines, configured to be connected to the multiple pixel groups to provide data signals to the multiple pixel groups; Wherein, between adjacent pixel groups, a partial segment of at least one data line among the multiple data lines has a positive projection on the substrate falling within the positive projection of the first power supply line on the substrate.

2. The display panel according to claim 1, wherein Between adjacent pixel groups, a partial segment of each of two adjacent data lines has a positive projection on the substrate falling within the positive projection of the same first power supply line on the substrate.

3. The display panel according to claim 1, wherein, The partial segment of the at least one data line extends along the direction in which adjacent pixel groups face each other.

4. The display panel according to claim 1, wherein, The first power supply line includes multiple first conductors and multiple second conductors, the multiple first conductors extending from the second display area to the first display area and electrically connecting the multiple pixel groups, the multiple second conductors being located in the first display area and between adjacent first conductors, the multiple second conductors extending along a first direction, adjacent second conductors being spaced apart from each other along the first direction, and the multiple second conductors electrically connecting the multiple pixel groups; Wherein, at least one of the multiple first conductors includes a first sub-wire extending along a first direction and a second sub-wire extending along a second direction, the first direction and the second direction intersecting, and the second sub-wire electrically connecting at least one of the multiple second conductors.

5. The display panel according to claim 4, wherein, The at least two sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel being arranged along the first direction, at least one of the multiple second conductors electrically connecting the first sub-pixel and the second sub-pixel, and the second sub-wire being in a different layer from the multiple second conductors.

6. The display panel according to claim 5, wherein, The sub-pixels further include light-emitting elements, the pixel circuits include a first transistor, a second transistor, and a storage capacitor, the first transistor being connected to the second transistor and the storage capacitor respectively, the second transistor being connected to the light-emitting elements, the first transistor including a first active portion and a second active portion, and the first active portion and the second active portion being connected by a conductive portion.

7. The display panel according to claim 6, wherein, The second conductor further includes a connecting arm, the connecting arm being spaced apart from and partially overlapping with the conductive portion of a sub-pixel in the pixel group that overlaps with the second conductor in a third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction.

8. The display panel according to claim 7, wherein, The shape of the connecting arm includes a C shape.

9. The display panel according to claim 4, wherein, The multiple pixel groups include a plurality of first pixel groups and a plurality of second pixel groups arranged at intervals, and are connected by a plurality of wirings between adjacent first pixel groups and second pixel groups.

10. The display panel according to claim 9, further comprising a connection wire, and at least two of the plurality of wirings between the adjacent first pixel group and the second pixel group fall within the orthographic projection of the connection wire on the substrate.

11. The display panel according to claim 9, wherein, There are a plurality of gaps between the plurality of wirings, and at least one of the plurality of gaps at least partially overlaps with the orthographic projection of the connection wire on the substrate.

12. The display panel according to any one of claims 9-11, wherein, The pixel circuit includes a first reset signal line, a second reset signal line, a gate line, a light emission control signal line, and an initialization signal line to respectively provide a first reset signal, a second reset signal, a gate scanning signal, a light emission control signal, and an initialization signal for the pixel circuit; The plurality of wirings are selected from at least two of the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the first wire.

13. The display panel according to claim 10, wherein, The connection wire has a stopper, and the stopper is provided on the same layer as the connection wire and integrally formed; The sub-pixel further includes a light-emitting element, the pixel circuit includes a first transistor, a second transistor, and a storage capacitor, the first transistor is respectively connected to the second transistor and the storage capacitor, the second transistor is connected to the light-emitting element, the first transistor includes a first active portion and a second active portion, and the first active portion and the second active portion are connected by a conductive portion; The stopper and the conductive portion of a pixel unit in the pixel group that overlaps with the first wire are spaced apart from each other in the third direction and partially overlap in the third direction.

14. The display panel according to claim 12, wherein, The orthographic projection of the connection wire on the substrate is at least partially located between the orthographic projections of the adjacent first pixel group and second pixel group on the substrate.

15. The display panel according to claim 14, wherein, The first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the second wire of the first pixel group are respectively connected to the first reset signal line, the second reset signal line, the gate line, the light emission control signal line, the initialization signal line, and the second wire of the second pixel group through the plurality of wirings.

16. The display panel according to claim 15, wherein, The connection wire and the second wire are located on the same layer and integrally formed; or the connection wire and the initialization signal line are located on the same layer and integrally formed; or the connection wire and the first wire are located on the same layer.

17. The display panel according to claim 6, wherein, The at least two sub-pixels further include a third sub-pixel and a fourth sub-pixel, the third sub-pixel and the fourth sub-pixel are arranged along the first direction and are located on one side of the first sub-pixel and the second sub-pixel along the second direction, the third sub-pixel and the fourth sub-pixel are electrically connected to another one of the plurality of second wires, and the second sub-wiring is electrically connected to at least one of the plurality of second wires.

18. The display panel according to claim 6 or 17, wherein, The second sub-wiring has a stopper, the stopper is on a different layer from the second sub-wiring, and is connected by a via hole. The stopper and the conductive part of a pixel unit in the pixel group that overlaps with the first wire are spaced apart from each other in the third direction and partially overlap in the third direction.

19. The display panel according to claim 4, wherein, The first direction is perpendicular to the second direction.

20. The display panel according to claim 4, wherein, The multiple second wires are arranged in sequence along the first direction.

21. The display panel according to claim 4, wherein, The adjacent second wires are not directly connected.

22. The display panel according to claim 4, wherein, The first wire and the second wire are connected through a via hole penetrating the insulating layer.

23. The display panel according to claim 4, wherein The first power supply line further includes a third wire and a fourth wire. The third wire extends along the second direction, the third wire extends from the second display area to the first display area, and the second wire is electrically connected to the third wire. The fourth wire extends along the second direction, the second wire is electrically connected to the fourth wire, and the length of the fourth wire in the second direction is less than or equal to the length of the third wire in the second direction.

24. The display panel according to claim 4, including multiple fourth wires, the multiple fourth wires are located between adjacent third wires, the multiple fourth wires are arranged in sequence along the second direction, and adjacent fourth wires are spaced apart from each other in the second direction.

25. The display panel according to claim 23, wherein, The first wire and the third wire are on the same layer, and the fourth wire and the third wire are on the same layer.

26. The display panel according to claim 1, wherein, The first display area includes multiple light-transmitting areas located between adjacent pixel groups.

27. The display panel according to claim 25, wherein, The multiple pixel groups and the traces connecting adjacent pixel groups surround the multiple light-transmitting areas.

28. A display device, including the display panel according to any one of claims 1-27.

29. The display device according to claim 28, further including a sensor, wherein The sensor is disposed on one side of the display panel, and the orthographic projection of the sensor on the substrate at least partially overlaps with the first display area.

Images