Memory device capable of sensing memory cells without bit line pre-charging

Abstract

The disclosure relates to systems, methods, and apparatus related to memory devices. In one method, a memory device controls a power supply to a detector for sensing a voltage of a bit line coupled to a memory cell. An output of the detector indicates a logic state of the selected memory cell. By controlling the voltage of the power supply, a detection threshold of the detector may increase as the voltage on the bit line increases. This allows the detector to be used without the need to pre-charge the bit line.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 536,098, filed on Dec. 11, 2023, which claims priority to U.S. Provisional Patent Application No. 63 / 476,911, filed on Dec. 22, 2022, the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] At least some of the embodiments disclosed herein generally relate to memory devices, and more particularly (but not limited to) memory devices that sense the state of memory cells without precharging bit lines or other access lines used to detect whether a memory cell has reached a threshold. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states typically represented by a logic “1” or a logic “0”. In other systems, more than two states can be stored. To access the stored information, components of an electronic device can read or sense the stored state in the memory device. To store information, components of an electronic device can write or program a state in the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic state for an extended period even in the absence of an external power source. Volatile memory cells may lose their stored state over time unless they are periodically refreshed by an external power source.

[0006] Storage devices are examples of memory devices. A typical computer storage device has a controller that receives data access requests from a host computer and performs programming and computational tasks to implement the requests in a manner that may be specific to the media and architecture configured in the storage device. In one example, a memory controller manages data stored in memory and communicates with a computer device. In some instances, memory controllers are used in solid state drives used in mobile devices or laptop computers or in media used in digital cameras.

[0007] Firmware can be used to operate the memory controller of a specific storage device. In one instance, when a computer system or device reads data from or writes data to a memory device, it communicates with the memory controller.

[0008] Memory devices typically store data in memory cells. In some cases, the memory cells exhibit non-uniform, variable electrical characteristics, which may originate from various factors, including statistical process variations, cycling events (e.g., read or write operations to the memory cells), or drift (e.g., change in resistance of a chalcogenide alloy), among others.

[0009] In one instance, reading a set of data is performed by determining the read voltage (e.g., estimated median of the threshold voltage) of the memory cells storing the set of data. In some cases, the memory device may include an array of PCM cells arranged in a 3D architecture, such as a cross-point architecture for storing the set of data. The PCM cells in the cross-point architecture can represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages, or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages. In some cases, coding (e.g., error correction coding (ECC)) can be used to store data to recover data from errors in the data stored in the memory cells.

[0010] For resistive variable memory cells (e.g., PCM cells), one of several states (e.g., resistance states) can be set. For example, a single-level cell (SLC) can be programmed to one of two states (e.g., logic 1 or 0), which can depend on whether the cell is programmed to a resistance above or below a specific level. As an additional example, each resistive variable memory cell can be programmed to one of multiple different states corresponding to multiple data states (e.g., 10, 01, 00, 11, 111, 101, 100, 1010, 1111, 0101, 0001, etc.). Such cells can be referred to as multi-state cells, multi-digit cells, and / or multi-level cells (MLC).

[0011] The state of a resistive variable memory cell can be determined (e.g., read) by sensing the current passing through the cell in response to an applied interrogation voltage. The sensed current, which varies based on the resistance of the cell, can indicate the state of the cell (e.g., the binary data stored by the cell). The resistance of a programmed resistive variable memory cell can drift over time (e.g., shift). Resistance drift can lead to incorrect sensing of the resistive variable memory cell (e.g., determining that the cell is in a state different from the state to which it was programmed, and other issues).

[0012] For example, a PCM cell can be programmed to a reset state (amorphous state) or a set state (crystalline state). A reset pulse (e.g., a pulse used to program a cell to the reset state) can include a relatively high current pulse applied to the cell for a relatively short period of time, causing the cell's phase change material to melt and cool rapidly, resulting in a relatively small amount of crystallization. Conversely, a set pulse (e.g., a pulse used to program a cell to the set state) can include a relatively low current pulse applied to the cell for a relatively long time interval and at a slower quenching rate, which results in increased crystallization of the phase change material.

[0013] A program signal can be applied to a selected memory cell to program the cell to a target state. A read signal can be applied to a selected memory cell to read the cell (e.g., determine the state of the cell). For example, the program signal and the read signal can be current and / or voltage pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0015] Figure 1 A memory device is shown that varies power to a detector when sensing the state of a memory cell in a memory array in accordance with some embodiments.

[0016] Figure 2 Exemplary current-voltage (IV) curves are shown for memory cells according to some embodiments.

[0017] Figure 3 A circuit is shown for sensing a memory cell using a detector for which a ramp voltage is used to control a supply voltage to the detector, according to some embodiments.

[0018] Figure 4 exhibit Figure 3 Exemplary voltage waveforms of the circuit.

[0019] Figure 5 Shown is a circuit for sensing positive polarity memory cells using a detector for which a ramp voltage is used to control positive and negative supply voltages to the detector, according to some embodiments.

[0020] Figure 6 exhibit Figure 5 Exemplary voltage waveforms of the circuit.

[0021] Figure 7 A circuit is shown for sensing negative polarity memory cells using a detector for which a ramp voltage is used to control positive and negative supply voltages to the detector, according to some embodiments.

[0022] Figure 8 Show Figure 7 Exemplary voltage waveforms of the circuit.

[0023] Figure 9 Show an exemplary three-dimensional memory array structure including memory cells sensed by a detector according to some embodiments.

[0024] Figure 10 Show a method for controlling a detection threshold when sensing a memory cell according to some embodiments. Detailed Description

[0025] The following disclosure describes various embodiments of a memory device that senses memory cells in a memory array by using a detector. During this sensing, the memory device uses a ramp voltage to control the power supply to the detector. The memory device may store data used by a host device (e.g., a computing device of an autonomous vehicle, or another computing device that accesses data stored in the memory device), for example. In one instance, the memory device is a solid state drive installed in an electric vehicle.

[0026] In some existing memory devices, it is necessary to use high-performance sensing to read memory cells in order to detect the switching of the cells in a timely manner. This is desirable while maintaining a low readout time and reducing the current drawn. In one instance, the memory cell is a phase change memory cell (e.g., a chalcogenide cell), which exhibits snap-back behavior when switching.

[0027] There are several different types of detectors that can be used to sense the state of a cell by sensing the voltage on a bit line. For example, the detector may use a cascade-based architecture, a sense amplifier-based architecture, or an inverter-based architecture. One limitation shared by such architectures is that they require precharging the bit line (or digital line) used to sense the cell. This precharging may take up to 30 to 40 ns, which significantly reduces the read access time. For example, the sense amplifier cannot be activated to start sensing the memory cell until this precharging is complete. Additionally, this precharging is an important part of the power consumption of the memory device.

[0028] To address the above and other technical problems, the memory device controls the power supply to the detector that senses the bit line coupled to the memory cell. For example, by controlling the voltage of the power supply, the detection threshold of the detector increases as the voltage on the bit line increases. This allows the use of the detector without precharging the bit line.

[0029] In one embodiment, the sensing architecture uses the IV characteristics of chalcogenide or other memory cells that exhibit favorable snapback behavior during sensing. The leakage current of such memory cells is a monotonic function of the voltage applied across the cell. As the voltage applied to the cell increases, the leakage current through the cell only gradually increases. However, when the threshold voltage of the cell is reached, the current through the cell increases sharply and significantly. Due to snapback, the cell current does not vary according to its voltage.

[0030] The sensing architecture applies a voltage to the bit line of a selected memory cell. The voltage is applied through a cascade transistor whose gate is coupled to a ramp voltage (e.g., a voltage that increases at a constant slope). A reference current is provided from a current source (e.g., a current generator) coupled to the cascade transistor to the bit line through the cascade transistor. The reference current is provided to the bit line in an exact manner.

[0031] If the ramp slope of the gate voltage is equal to or higher than the RC time constant of the bit line, then the voltage across the memory cell ramps up in a manner that follows the ramp voltage, but no snapback occurs as long as the voltage applied across the cell is below its threshold voltage. This allows the sensing of the memory cell to start without waiting for the pre-charging of the bit line.

[0032] When the memory cell exhibits snapback, the current through the cell exceeds the reference current, which allows the detection of cell switching. In one example, the detector is an inverter having an input coupled to the bit line. When the cell switches, the bit line is pulled to a lower voltage, causing the inverter to switch.

[0033] In one embodiment, the memory device includes a memory array having chalcogenide memory cells in a three-dimensional cross-point architecture. Word lines and bit lines are each biased to access at least one memory cell in the array.

[0034] A current source (e.g., a current generator) provides a reference current for the sensing operation of reading the memory cell. A first transistor (e.g., M1) couples the current source to the bit line. The magnitude of the gate voltage of the first transistor is increased during the sensing of the memory cell. In one example, the gate voltage is a ramp voltage with a constant slope. Initially, the bit line voltage increases as the ramp voltage increases.

[0035] The detector (e.g., inverter 308) has an input coupled to the bit line. The detector detects whether the memory cell has reached a threshold (e.g., the cell has snapped back). When the cell snaps back (exhibits snapback), then the bit line voltage drops below the detection threshold of the detector.

[0036] A second transistor (e.g., M2) supplies a supply voltage (e.g., insup) to the detector. The magnitude of the gate voltage of the second transistor is increased during sensing of the first memory cell. In one example, the gate voltage is a ramp voltage with a constant slope (e.g., V ramp ). The gate voltage of the second transistor can be the same ramp voltage as that applied to the gate of the first transistor, or can be a different ramp voltage. The detection threshold of the detector increases as the gate voltage of the second transistor increases.

[0037] The sensing architecture embodiments described herein provide various advantages. In one advantage, the sensing architecture has a reduced readout time due to avoiding the need for a precharge phase as used in existing detectors. Also, the provided sensing architecture has higher area efficiency and power efficiency (e.g., due to no or low DC consumption). Additionally, the sensing architecture can be implemented for faster or slower read operations (e.g., read operations from 10 nanoseconds to 1 microsecond).

[0038] Additionally, for some cases, the sensing architecture can reduce leakage problems. For example, the bias of each memory cell when being sensed is adapted to the switching behavior of a particular cell. This avoids overbiasing the memory cell with a high fixed voltage as used in existing methods. This generally reduces the leakage current through the memory cell. For example, due to this adaptive biasing, the leakage current of the cell with a lower threshold voltage is lower.

[0039] Figure 1 A memory device 101 is shown that changes the power supply to a detector 130 when sensing the state of a memory cell 110 in a memory array 102 according to some embodiments. In one example, the memory cell 110 is a chalcogenide memory cell.

[0040] A sensing circuit system 122 senses the state of the memory cell 110. The sensing circuit system 122 includes a detector 130. In one example, the detector 130 is an inverter. An access line 140 is used to select the memory cell 110. In one example, the access line 140 includes word lines and bit lines in a cross-point memory array. A bias circuit system 124 biases the selected one of the access lines 140 to select a portion of the memory cell 110 to be sensed. The bias circuit system 124 also supplies power to the sensing circuit system 122, including supplying power to the detector 130.

[0041] A memory controller 120 controls various operations of the memory device 101, including read and write operations of the memory cell 110. The memory controller 120 includes a processing device 116 and a memory 118. Some operations are controlled by the controller 120 in response to various commands received from a host device 126 on a communication interface 150.

[0042] In one embodiment, communication interface 150 receives a read command from host device 126. In response to receiving the read command, controller 120 initiates a read operation. As part of the read operation, memory cell 110 is selected such that its logical state is determined by sense circuitry 122.

[0043] Biasing circuitry 124 drives the voltage on access line 140 to select the memory cell, including driving the voltage on the bit lines for selecting the memory cell. To sense the state of the memory cell, detector 130 monitors the voltage on the bit lines. During the read operation, biasing circuitry 124 applies a reference current to the bit lines. A ramped voltage (sometimes referred to herein as a ramp voltage) is used to control the current.

[0044] During the read operation, the voltage on the bit lines increases as the ramp voltage increases. When the memory cell reaches its threshold voltage, the current through the memory cell exceeds the reference current, which causes the voltage on the bit lines to rapidly decrease. Detector 130 detects this voltage change. The output of detector 130 is used by sense circuitry 122 to determine the logical state (e.g., 1 or 0) of the memory cell that has been read.

[0045] During the read operation, biasing circuitry 124 increases the power supply to detector 130. This causes the detection threshold of detector 130 to increase (see, e.g., Figure 4 V th inv). In one embodiment, a ramped voltage is used to control the power supply to detector 130. In one instance, this ramp voltage is the same as the ramp voltage used to control the above-mentioned reference current. In one instance, the magnitude of the ramp voltage is different, but it is controlled to have an equal rate of change (slope).

[0046] In one embodiment, memory cell 110 stores user data of host device 126. Memory cell 110 stores data in a first logical state or a second logical state. In one instance, biasing circuitry 124 includes word line and bit line drivers (not shown) to bias the word lines and bit lines of memory array 102.

[0047] Sense circuitry 122 may include sense amplifiers for sensing characteristics associated with the memory cells of memory array 102. The characteristics may be, for example, voltages and / or currents associated with the selected memory cell. The detection threshold of the sense amplifier may be changed during a read operation generally as described herein.

[0048] In one embodiment, the controller 120 causes the bias circuit system 124 to apply a voltage to the selected memory cell 110. In one instance, the voltage is an incremental value of voltage values separated by a step (e.g., a 0.5V step), such as +2, +2.5, +3, +3.5, +4, +4.5, +5V.

[0049] In one embodiment, the memory controller 120 includes one or more processing devices 116 and memory 118. In one instance, the memory 118 stores firmware executed by the processing device 116 to select and apply read voltages. The memory controller 120 can use the bias circuit system 124 to generate voltages for applying read and other voltages (e.g., initial read and read retry). As part of a programming operation, the bias circuit system 124 can also generate a voltage for applying a write voltage to the memory cell 110.

[0050] In one embodiment, if the sense circuit system 122 determines that the current of the memory cell is greater than a fixed threshold (e.g., a predetermined current level), then the memory controller 120 determines that the memory cell has switched (e.g., snapped back).

[0051] In one embodiment, the memory controller 120 receives a write command from the host device 126. The write command is accompanied by data to be written to the memory array 102 (e.g., user data of a user of the host device 126). In response to receiving the write command, the controller 120 initiates a programming operation.

[0052] In one instance, the polarity of the read or write pulse can be a first polarity or a second polarity. For example, a write pulse can apply a voltage (e.g., bit line at 6V and word line at 0V) to the memory cell with the first polarity.

[0053] In one instance, the circuit coupled to the access line to which the memory cell can be coupled is used to provide a read pulse (e.g., an access line driver included in the decoder circuit). The circuit can be controlled by an internal control signal provided by control logic (e.g., the controller 120). The read voltage or pulse can be a voltage applied to the memory cell over a period of time (e.g., 10 to 50 ns, 1 to 100 ns, 1 ns to 1 microsecond). In some embodiments, the read pulse can be a square pulse. In some embodiments, the read pulse can be a ramp, i.e., a linearly increasing voltage can be applied across the memory cell.

[0054] In one example, after being accessed (e.g., selected), a memory cell can be read or sensed by a sensing component (e.g., sensing circuitry 122) to determine the stored state of the memory cell. For example, a voltage can be applied to the memory cell (using a word line and a bit line), and the presence of a resulting current can depend on the applied voltage and the threshold voltage of the memory cell. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not result in current flow, other voltages can be applied until a current is detected by the sensing component.

[0055] By evaluating the voltage that causes current flow, the stored logic state of the memory cell can be determined. In some cases, the magnitude of the voltage can be ramped up until current flow is detected (e.g., the memory cell conducts, turns on, conducts current, or is activated). A current can be applied to the memory cell, and the magnitude of the voltage that produces the current can depend on the resistance or threshold voltage of the memory cell.

[0056] In some cases, a memory cell (e.g., a PCM cell) includes a material that changes its crystal configuration (e.g., between a crystalline phase and an amorphous phase), which in turn determines the threshold voltage of the memory cell to store information. In other cases, the memory cell includes a material that remains in a crystal configuration (e.g., amorphous phase), which can exhibit a variable threshold voltage to store information.

[0057] The sensing component can include various transistors or amplifiers to detect and amplify differences in signals. The detected logic state of the memory cell can then be output as an output by a column decoder. In some cases, the sensing component can be part of a column decoder or a row decoder.

[0058] At least some embodiments herein relate to a memory device that uses bipolar operation for a memory array (e.g., for multi-level memory cells). In one example, a bipolar select voltage is used to select memory cells of a memory array. In one example, the memory cells are arranged in a cross-point architecture. In one example, a single select device is used to form each memory cell. In one example, the select device includes a chalcogenide material that switches (e.g., snaps back) when a sufficient voltage is applied across the memory cell.

[0059] In some cases, the memory device can include an array of memory cells arranged in a three-dimensional (3D) architecture (e.g., cross-point architecture) to store the set of data. The memory cells in the cross-point architecture can represent, for example, a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages, or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages.

[0060] In other embodiments, the memory cells may be arranged in a three-dimensional (3D) vertical architecture. The 3D vertical architecture may include memory cells located at intersections between vertical access lines (e.g., bit line struts) formed in horizontal planes or levels parallel to each other and each of a plurality of second access lines (e.g., word lines).

[0061] More generally, integrated circuit memory cells (e.g., memory cells in a cross-point memory or 3D vertical array) may be programmed to store data by their state under a voltage applied across the memory cell. For example, if a memory cell is configured or programmed such that a large amount of current is allowed to pass through the state of the memory cell at a voltage in a predefined voltage region, then the memory cell is considered to be configured or programmed to store a first bit value (e.g., 1 or 0); otherwise, the memory cell stores a second bit value (e.g., 0 or 1).

[0062] Optionally, by being configured or programmed to have a threshold voltage in one of more than two separate voltage regions, the memory cells may be configured or programmed to store more than one data bit.

[0063] In one example, the threshold voltage of a memory cell is such that when the voltage applied across the memory cell increases above the threshold voltage, the memory cell switches by rapidly or suddenly changing, snap-back (e.g., for chalcogenide memory cells), or jumping from a non-conductive state to a conductive state. The non-conductive state allows a small leakage current to pass through the memory cell; and in contrast, the conductive state allows more than a threshold amount of current to pass through. Thus, the memory device may use a detector (e.g., a sense amplifier) to detect the change, or determine the conductive / non-conductive state of the memory device under one or more applied voltages, to evaluate or classify the level of the threshold voltage of the memory cell and thus the data it stores.

[0064] The threshold voltages of memory cells configured / programmed to be in different voltage regions may be used to represent different data values stored in the memory cells. For example, the threshold voltage of a memory cell may be programmed to be in any of four predefined voltage regions; and each of the regions may be used to represent the bit values of different two-bit data items. Thus, when a given two-bit data item is provided, one of the four voltage regions may be selected based on the mapping between the two-bit data item and the voltage regions; and the threshold voltage of the memory cell may be adjusted, programmed, or configured to be in the selected voltage region to represent or store the given two-bit data item.

[0065] To retrieve, determine, or read a data item from a memory cell, one or more read voltages may be applied across the memory cell to determine which of the four voltage regions contains the threshold voltage of the memory cell. Identification of the voltage region containing the threshold voltage of the memory cell provides the two-bit data item that has been stored, programmed, or written to the memory cell.

[0066] For example, a memory cell may be configured or programmed to store one data item of one bit in a single-level cell (SLC) mode, or two data items of two bits in a multi-level cell (MLC) mode, or three data items of three bits in a three-level cell (TLC) mode, or four data items of four bits in a quad-level cell (QLC) mode.

[0067] Figure 2 Exemplary current-voltage (IV) curves of a memory cell according to some embodiments are shown. As illustrated, as the voltage V applied across the memory cell increases, the current I through the memory cell increases monotonically (in the leakage region).

[0068] The current increases as the voltage increases until the threshold voltage of the memory cell is reached. At this time, the memory cell exhibits snapback behavior as illustrated, where the current through the memory cell rapidly increases. For example, as discussed above, this current through the memory cell after snapback pulls down the voltage on the selected bit line, such that the detector 130 detects that the memory cell has reached the threshold and snapped back.

[0069] As an example, the illustrated IV curves are for a chalcogenide memory cell. Other types of phase change memory cells exhibit similar snapback behavior. In one example, the illustrated IV curves are for one of the memory cells 110.

[0070] Figure 3 A circuit for sensing a memory cell using a detector according to some embodiments is shown, for which a ramp voltage is used to control the supply voltage to the detector. The detector includes an inverter 308. The input of the inverter 308 is coupled to the bit line at node 306. The memory cell to be read is coupled to the bit line. The output of the inverter 308 provides a signal detection, which corresponds to the logical state of the memory cell coupled to the bit line.

[0071] The supply voltage insup is provided to the inverter 308 through a transistor M2. The transistor M2 is coupled to a positive supply voltage 304 (e.g., Vpp). A gate voltage Vramp is applied to the gate of the transistor M2 to control the power supply to the inverter 308. The inverter 308 is also connected to a negative supply voltage 310 (e.g., ground).

[0072] A transistor M1 couples a positive supply voltage 302 (e.g., Vpp) to node 306. A current source Iref (e.g., a current generator) provides a reference current to node 306. A gate voltage Vramp is applied to the gate of the transistor M1 to control the supply of current from the current source Iref to node 306.

[0073] In one example, each of the transistors M1 and M2 is an n-channel MOSFET. In one example, the gate voltages of transistors M1 and M2 increase as a ramp voltage Vramp during a read operation.

[0074] In one example, during an initial portion of a read operation (e.g., as discussed above for Figure 1 ), the memory cell selected by the bit line is non-conductive. Thus, the current provided by the current source Iref increases the voltage at node 306. This voltage is higher than the threshold voltage of the inverter 308. Thus, the output signal sense remains at a low voltage (e.g., logic 0).

[0075] Later during the read operation, if the selected memory cell coupled to the bit line snaps back, then the voltage at node 306 is pulled low. This causes the output signal sense to switch to a high voltage (e.g., logic 1).

[0076] Figure 4 Shows Figure 3 exemplary voltage waveforms of the circuit. The sensing operation begins at an initial time 408 (e.g., under the control of the controller 120). The ramp voltage Vramp begins increasing at a steady rate (constant slope) from time 408. The ramp voltage is applied to the gates of both transistors M1 and M2.

[0077] As time progresses, the supply voltage insup provided to the inverter 308 increases, as illustrated. Also, as illustrated, due to the current source Iref driving the voltage higher (and being able to overcome leakage current of the selected memory cell and / or other non-selected cells on the bit line), the voltage on the bit line increases. Initially, in portion 402 of the bit line waveform, the bit line voltage and the supply voltage insup are nearly the same.

[0078] Later, at portion 404 of the bit line waveform, the leakage current through the selective memory cell increases. This causes the slope of the bit line waveform to decrease (before the snap back).

[0079] As time progresses, the threshold voltage of the inverter 308 also increases, as illustrated. The bit line voltage remains higher than the inverter threshold voltage until the memory cell snaps back, at which point the bit line voltage drops below the inverter threshold voltage at point 406. At point 406, the inverter 308 switches such that the signal sense output from the inverter 308 changes state (e.g., from low to high). In one example, the threshold voltage of the inverter 308 is approximately halfway between the positive and negative supply voltages 304, 310. In one example, the switching point 406 is reached between 10 and 500 nanoseconds after sensing begins at time 408.

[0080] Note that the threshold voltage of the inverter 308 is adapted to the bias voltage applied across the selected memory cell. This is an advantage because the threshold voltages of the memory cells in a memory array can vary drastically from one memory cell to another (e.g., some memory cells are quite high and some memory cells are quite low). Thus, memory cells with lower threshold voltages will experience less stress, which increases the durability of those memory cells. In contrast, existing systems require the threshold voltage of the inverter to be set to a high constant value. This results in applying a higher voltage than necessary to those memory cells with lower threshold voltages.

[0081] In one example, as the voltage on the bit line increases, the leakage through the memory cell increases, thus reducing the slope of the bit line. This occurs prior to the memory cell snapback. The same voltage Vramp used to control the transistor M1 is used to control the power supply to the inverter 308 such that the inverter 308 remains off. This reduces the power consumption of the memory device. Later during the sense operation, when the memory cell snapbacks, the bit line goes low and the inverter 308 switches. In one example, the threshold voltage of the inverter is within plus or minus 20% of the voltage Vramp / 2.

[0082] In one example, the same ramp voltage Vramp is applied to the gates of the transistors M1 and M2. The voltage insup = Vramp - Vth2 (the threshold voltage of the transistor M2). The voltage insup is approximately equal to the voltage of the selected bit line. The bit line voltage is equal to Vramp - Vth1 (the threshold voltage of the transistor M1). Thus, the inverter 308 is off at the start of the sense operation at time 408.

[0083] Later during the sense operation, the voltage of the bit line drops below the voltage insup - |Vthp| = Vramp - Vth1 - |Vthp|. |Vthp| is the magnitude of the threshold voltage of the internal p-type transistor (e.g., p-type MOSFET; not shown) of the inverter 308. Thus, the inverter 308 conducts.

[0084] Figure 5 A circuit for sensing a positive-polarity memory cell using a detector is shown, for which a ramp voltage is used to control the positive and negative supply voltages to the detector. Figure 5 The circuit is similar to the above Figure 3 circuit, except that a transistor M3 is added to couple the negative supply voltage 310 (e.g., ground) to the negative supply voltage inmin provided to the inverter 308. In one example, the transistor M3 is a p-type MOSFET. In one example, the negative supply voltage inmin is coupled to the internal n-type MOSFET (not shown) of the inverter 308.

[0085] The transistor M3 controls the provision of a negative supply voltage inmin to the inverter 308. A ramp voltage is applied to the gate of the transistor M3. In one embodiment, the slope of the voltage applied to the gate of the transistor M3 is the same as the slope of the ramp voltage applied to the transistors M1 and M2.

[0086] In one example, the gate voltage applied to the transistor M3 has a magnitude given by Vramp - 2V th - ΔV. Vramp is the magnitude of the ramp voltage applied to the transistors M1 and M2. 2V th is the sum of the threshold voltages of the transistors M2 and M3, which is expressed as 2V th = |Vt(M2)| + |Vt(M3)|.

[0087] ΔV is an arbitrary voltage selected according to the needs of a particular design. For example, ΔV can be selected to configure the difference between the voltage insup and the voltage inmin, or between the voltage of the bit line and the voltage inmin (see, e.g., Figure 6 ).

[0088] In one embodiment, the threshold voltage of the inverter 308 increases at the same rate as the voltages insup and inmin. The voltages insup and inmin increase at the same rate as the voltage Vramp applied to the gates of the transistors M1 and M2. Thus, the threshold voltage of the inverter 308 increases at the same rate as the voltage Vramp.

[0089] By restricting the negative or lower supply range of the internal NMOS device (not shown) in the inverter 308, performance can be improved. In Figure 3 the previous architecture, the switching or threshold voltage of the inverter 308 was defined only by the positive or top power supply of the inverter 308 (since the lower supply was fixed to ground). Configuring the lower supply allows the inverter threshold to be closer to the snap-back point of the memory cell to reduce power consumption and / or the current flowing through the selected memory cell.

[0090] The addition of the PMOS transistor M3 controls the negative supply voltage to increase the actual lower supply voltage provided to the inverter 308. Thus, the switching threshold of the inverter 308 is closer to the snap-back voltage of the selected memory cell.

[0091] Figure 6 Shows Figure 5 an exemplary voltage waveform of the circuit. The sensing operation starts at time 604. A ramp voltage Vramp is applied to the gates of the transistors M1 and M2. The upper and lower supply voltages insup and inmin are provided to the inverter 308, and these upper and lower supply voltages increase at the same rate as Vramp. Thus, the threshold voltage V of the inverter 308 thThe inv increases at the same rate as the ramp voltage Vramp (except for the initial part of the waveform), as illustrated.

[0092] The voltage of the bit line initially increases almost the same as the voltage insup. As the leakage through the selected memory cell increases, the rate of increase of the voltage of the bit line slows down. Eventually, at time 602, the memory cell snaps back, and the voltage of the bit line at node 306 drops below the threshold voltage of the inverter 308, as illustrated.

[0093] In one embodiment, the slew rate reduction of the voltage inmin reduces the range of the area for conduction of the inverter 308 (e.g., voltage insup – voltage inmin). This reduces power consumption. For the gate voltage applied to the transistor M3, ΔV can be arbitrarily selected to adjust the shape of the waveforms of the voltages insup and inmin (e.g., the vertical voltage distance). This defines the width of the window between insup and inmin.

[0094] In one embodiment, for all memory cells being read, the difference between the voltage insup and the inverter threshold is the same. Therefore, each memory cell must produce the same voltage drop on the bit line. Note that this is independent of the bias point of a particular memory cell. Therefore, for each cell read, the switching of the inverter has the same delay because when the cell switches, it draws the same current (removes charge from the bit line). Therefore, the response of the inverter is the same regardless of the bias point of the cell.

[0095] Figure 7 A circuit for sensing a negative-polarity memory cell using a detector is shown, for which a ramp voltage is used to control the positive and negative supply voltages to the detector. Figure 7 The circuit is similar to the above Figure 5 positive-polarity circuit, except that the polarity of its operation becomes the opposite negative polarity.

[0096] In one embodiment, a read operation is performed on multi-level cells (more than one bit of data is stored in each cell). In some cases, it is necessary to read such memory cells of both positive and negative polarities. For example, during a read operation, a cell can snap back in the positive polarity, snap back in the negative polarity, or not snap back at all. The controller can select a specific sensing circuitry suitable for the desired polarity during the read operation.

[0097] Node 706 is coupled to the bit line for selecting the memory cell to be sensed by the inverter 708. The transistor M1 couples the negative voltage supplier 702 (e.g., Vnn) to node 706. The transistor M2 is coupled to the negative voltage supplier 704 (e.g., Vnn) to provide a negative or lower power supply voltage to the inverter 708.

[0098] Transistor M3 is coupled to a positive or upper supply 710 (e.g., ground) to provide a positive or upper power supply voltage to inverter 708, similar to that discussed above, except with opposite polarities.

[0099] In one embodiment, transistors M1 and M2 cannot have their body voltages biased to a negative supply voltage (e.g., Vss or Vnn). Instead, a higher voltage (e.g., Vpp) is used to bias the body. Using a high positive voltage in the case where transistors M1 and M2 operate in the negative range results in a significant body effect, which would increase the threshold of the transistors. However, there is compensation between the voltage inmin and the bitline voltage because the two PMOS transistors M1 and M2 see the same body effect. This is because the two transistors will be affected by the same threshold voltage variation without affecting the inverter operation.

[0100] Figure 8 Shown Figure 7 are exemplary voltage waveforms of the circuit. The sense operation starts at time 804. The ramp voltage Vramp decreases at a constant rate. The voltages inmin and insup decrease at the same rate as the ramp voltage Vramp.

[0101] The threshold voltage V th inv of inverter 708 decreases at the same rate as the ramp voltage Vramp (except for the initial part of the waveform), as illustrated. The bitline voltage remains below the threshold voltage of inverter 708 until the selected memory cell snaps back at time 802. Due to the memory cell snap-back, the bitline voltage increases and reaches the threshold voltage of inverter 708. This causes inverter 708 to switch and provide an output signal detection, which indicates that the selected memory cell has switched.

[0102] Figure 9 Shown is an exemplary three-dimensional memory array structure including memory cells sensed by a detector according to some embodiments. In one example, the memory cells are memory cells 110 sensed by Figure 1 detector 130.

[0103] The memory arrays and memory cells described herein are not limited to use in a planar architecture (e.g., cells at the intersections of word lines (WL) and bit lines (BL) on different levels). Instead, the method can also be used for a vertical architecture (e.g., vertical BL pillars intersecting horizontal WL planes).

[0104] Figure 9Illustrates an example of a vertical architecture that can be used in conjunction with the embodiments described in this disclosure. As illustrated, the memory array includes memory cells 1102, 1103. The memory array is formed over a semiconductor substrate 902. In one example, the semiconductor substrate 902 includes logic circuitry. In one example, the logic circuitry provides at least a portion of the bias circuitry 124 and / or the sense circuitry 122.

[0105] Each memory cell 1102, 1103 can be selected using word lines (e.g., 1106, 1107, or 1108) and digit lines (e.g., 1110). Each digit line is coupled to a bit line pillar (e.g., 1104) through a selection transistor (selector). The memory cells 1102, 1103 are Figure 1 instances of the memory cell 110 of

[0106] In one embodiment, each word line extends in one of a plurality of horizontal planes of word lines 1106, 1107, 1108 vertically stacked over the semiconductor substrate 902. Each digit line (e.g., 1110) is coupled to a bit line pillar 1104. Each bit line pillar 1104 extends vertically away from the semiconductor substrate 902. Each memory cell 1102, 1103 is located on a side of one of the bit line pillars 1104.

[0107] In one embodiment, the memory array has a vertical array architecture that includes vertical bit lines (e.g., vertical pillars 1104) intersecting a plurality of horizontal word line levels (e.g., even word lines 1106 and odd word lines 1107). Each level is configured as two interleaved word line combs such that each bit line forms two cells 1102, 1103 at each of the levels. In one example, the even word lines 1106 and the odd word lines 1107 are interleaved in a comb structure as illustrated.

[0108] Figure 10 Shows a method for controlling a detection threshold when sensing a memory cell according to some embodiments. For example, Figure 10 the method of Figure 1 can be implemented in a

[0109] Figure 10 system. In one example, the detection threshold is the threshold voltage of an inverter 308 or 708. Figure 10 The method of Figure 1 can be executed by processing logic that can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, Figure 10 the method of Figure 1 is executed at least in part by one or more processing devices (e.g., Figure 1 the controller 120 of

[0110] Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, all processes are not required in every embodiment. Other process flows are possible.

[0111] At block 1001, a voltage is applied to a word line to access a memory cell. In one example, the voltage is driven by a bias circuit system 124 on a selected word line of an access line 140.

[0112] At block 1003, a voltage is applied to a bit line to access a memory cell. In one example, the voltage is driven by a bias circuit system 124 on a selected bit line of an access line 140.

[0113] At block 1005, when reading a memory cell, a ramp voltage is increased. In one example, the ramp voltage is the gate voltage Vramp applied to Figure 3 transistors M1 and M2.

[0114] At block 1007, the ramp voltage is used to control the voltage applied to the bit line. In one example, the gate voltage Vramp applied to transistor M1 controls the voltage applied to node 306.

[0115] At block 1009, the logical state of a memory cell is detected while using the ramp voltage to control a detection threshold. In one example, the logical state of a memory cell selected by a bit line is detected by an inverter 308. The threshold voltage of the inverter 308 is controlled by the gate voltage Vramp applied to transistor M2. Figure 3 The logical state of a memory cell selected by a bit line is detected by an inverter 308. The threshold voltage of the inverter 308 is controlled by the gate voltage Vramp applied to transistor M2.

[0116] At block 1011, an output indicating the logical state of the memory cell is provided. In one example, the inverter 308 provides an output signal detect to indicate the logical state of a memory cell coupled to node 306.

[0117] In one embodiment, an apparatus includes: a memory array (e.g., 102) having memory cells; bit lines (e.g., Figure 3 bit lines) coupled to at least one first memory cell; a current source (e.g., I ref), which is configured to provide a reference current; a first transistor (e.g., M1) that couples a current source to a bit line, wherein a magnitude of a first gate voltage of the first transistor is increased during sensing of a first memory cell; a detector (e.g., 130) having an input coupled to the bit line, wherein the detector is configured to detect whether the first memory cell has reached a threshold (e.g., the cell has snapped back or exhibits snap-back behavior); and a second transistor (e.g., M2) that supplies a supply voltage to the detector, wherein a magnitude of a second gate voltage of the second transistor is increased during sensing of the first memory cell.

[0118] In one embodiment, the detector is an inverter.

[0119] In one embodiment, the first and second gate voltages are the same ramp voltage (e.g., Vramp).

[0120] In one embodiment, the first and second gate voltages ramp at the same rate (e.g., different voltage magnitudes but ramp at the same rate).

[0121] In one embodiment, the supply voltage has a first polarity (e.g., a positive voltage from Vpp), and the device further includes a third transistor (e.g., a PMOS device) that supplies a supply voltage of a second polarity (e.g., a low or negative voltage from Vnn or ground) to the detector.

[0122] In one embodiment, a magnitude of a third gate voltage of the third transistor ramps at the same rate as the first and second gate voltages during sensing.

[0123] In one embodiment, the first and second transistors are n-type, and the third transistor is p-type.

[0124] In one embodiment, the memory array is a cross-point array, the bit lines are pillars (e.g., Figure 9 bit line pillar 1104) that extend vertically above the semiconductor substrate, and the memory cells are chalcogenide memory cells.

[0125] In one embodiment, a system includes: a sensing circuit system (e.g., 122) configured to sense memory cells of a memory device; a biasing circuit system (e.g., 124) configured to bias an access line coupled to at least a first memory cell and supply power to the sensing circuit system; and a controller (e.g., 120) configured to: receive a read command from a host device; initiate a read operation in response to receiving the read command; increase a magnitude of at least one ramp voltage (e.g., Vramp) during the read operation; apply a current (e.g., Iref) to the access line using the biasing circuit system during the read operation, wherein applying the current to the access line is controlled by the ramp voltage; and sense the first memory cell using the sensing circuit system to determine whether the first memory cell has reached a threshold, wherein power supply to the sensing circuit system is controlled by the ramp voltage.

[0126] In one embodiment, the sensing circuit system is configured to sense the first memory cell using a first polarity or an opposite second polarity, wherein the first or second polarity is selected by the controller.

[0127] In one embodiment, the sensing circuit system includes an inverter, and a threshold voltage of the inverter increases as the magnitude of the ramp voltage increases.

[0128] In one embodiment, a leakage current of the first memory cell increases as a voltage on the access line increases.

[0129] In one embodiment, the biasing circuit system includes a transistor (e.g., an n-type MOSFET) coupled to the access line; and applies the ramp voltage to a gate of the transistor.

[0130] In one embodiment, the biasing circuit system supplies power to the sensing circuit system using a first supply voltage of a first polarity (e.g., Vpp for a positive polarity, or ground for a negative polarity) and a second supply voltage of an opposite second polarity (e.g., ground for a positive polarity, or Vnn for a negative polarity), wherein the ramp voltage controls magnitudes of the first and second supply voltages.

[0131] In one embodiment, a detection threshold (e.g., an inverter threshold) of the sensing circuit system increases at the same rate as an increase in the magnitude of the ramp voltage.

[0132] In one embodiment, at least one ramp voltage includes a first and a second ramp voltage; the magnitude of the second ramp voltage is lower than the magnitude of the first ramp voltage; the bias circuit system includes an n-type transistor and a p-type transistor; a first supply voltage is coupled to the sense circuit system (e.g., an inverter) through the n-type transistor, and the first ramp voltage is applied to the gate of the n-type transistor during a read operation; and a second supply voltage is coupled to the sense circuit system through the p-type transistor, and the second ramp voltage is applied to the gate of the p-type transistor during a read operation.

[0133] In one embodiment, a method includes: applying a first voltage to a word line (e.g., 1106) to access at least one memory cell in a three-dimensional cross-point memory array, where the word line extends horizontally above a semiconductor substrate; applying a second voltage to a bit line (e.g., pillar 1104) to access the memory cell, where the bit line extends vertically above the semiconductor substrate; increasing the magnitude of at least one gate voltage (e.g., Vramp) during a sense operation to read the memory cell; controlling the second voltage using the gate voltage; detecting the logic state of the memory cell, where the detection threshold (e.g., inverter threshold) is controlled using the gate voltage; and providing an amplified output indicative of the logic state of the memory cell.

[0134] In one embodiment, the magnitude of the detection threshold increases as the magnitude of the gate voltage increases.

[0135] In one embodiment, the method further includes limiting the current passing through the memory cell during the sense operation (e.g., using current source I ref Limiting current).

[0136] In one embodiment, at least one memory cell is a self-selecting memory cell (e.g., a chalcogenide memory cell), and the magnitude of the bias voltage applied across the memory cell during the sense operation corresponds to the threshold voltage of the memory cell.

[0137] The present disclosure includes various apparatuses that perform the methods described above and implement the systems described above, including a data processing system that executes these methods, and a computer-readable medium containing instructions that, when executed on the data processing system, cause the system to execute these methods.

[0138] The description and the figures are illustrative and should not be construed as restrictive. Numerous specific details are described to provide a thorough understanding. However, in some instances, well-known or conventional details are not described so as not to obscure the description. References in the present disclosure to one or an embodiment are not necessarily references to the same embodiment; and such references mean at least one.

[0139] As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0140] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The phrase "in one embodiment" appearing in various places in the specification does not necessarily all refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Additionally, various features may be described that are presented by some embodiments but not by other embodiments. Similarly, various requirements may be described that are required by some embodiments but not by other embodiments.

[0141] In this description, various functions and / or operations may be described as being performed by or caused by software code to simplify the description. However, those skilled in the art will recognize that such expressions mean that the functions and / or operations are derived from the execution of code by one or more processing devices, such as a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit, and / or a field programmable gate array (FPGA). Alternatively, or in combination, the functions and operations may be implemented using dedicated circuitry (e.g., logic circuitry) in the case of software instructions or without software instructions. Embodiments may be implemented using hardwired circuitry without software instructions or in combination with software instructions. Thus, the technology is neither limited to any particular combination of hardware circuitry and software nor to any particular source of the instructions executed by a computing device.

[0142] Although some embodiments may be implemented in full - fledged computers and computer systems, various embodiments can be distributed as computing products in various forms and can be applied regardless of the specific type of computer - readable medium used for actual implementation of the distribution.

[0143] At least some aspects of the disclosed subject matter may be embodied, at least in part, in software. That is, the technology may be practiced in a computing device or other system in response to its processing device (e.g., a microprocessor) executing a sequence of instructions contained in a memory (e.g., ROM, volatile RAM, non - volatile memory, cache, or remote storage device).

[0144] The routines for implementing the embodiments may be implemented as part of an operating system, middleware software, a service delivery platform, an SDK (software development kit) component, a network service, or other specific applications, components, programs, objects, modules, or sequences of instructions (sometimes referred to as a computer program). The call interfaces of these routines may be exposed to the software development community as an API (application programming interface). A computer program typically includes one or more instructions that are set at various times in various memories and storage devices in a computer and, when read and executed by one or more processors in the computer, cause the computer to perform the operations required for implementing the elements involved in various aspects.

[0145] Computer-readable media can be used to store software and data that, when executed by a computing device, cause the device to perform various methods. The executable software and data can be stored in various locations including, for example, ROM, volatile RAM, non-volatile memory, and / or cache. Portions of this software and / or data can be stored in any of these storage devices. Additionally, data and instructions can be obtained from a centralized server or a peer-to-peer network. Different portions of the data and instructions can be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions or the same communication session. The data and instructions can be obtained in their entirety before an application is executed. Alternatively, only portions of the data and instructions can be obtained dynamically just in time as needed for execution. Thus, it is not required that the data and instructions be entirely on a computer-readable media at a particular moment.

[0146] Examples of computer-readable media include (but are not limited to) recordable and non-recordable media such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state drive storage media, removable disks, magnetic disk storage media, optical storage media (e.g., compact disc read-only memory (CD ROM), digital versatile disk (DVD), etc.), and the like. A computer-readable media can store instructions. Other examples of computer-readable media include (but are not limited to) non-volatile embedded devices using NOR flash or NAND flash architectures. The media used in these architectures can include unmanaged NAND devices and / or managed NAND devices including, for example, eMMC, SD, CF, UFS, and SSD.

[0147] Generally, a non-transitory computer-readable media includes any mechanism that provides (e.g., stores) information in a form accessible by a computing device (e.g., a computer, a mobile device, a network device, a personal digital assistant, a manufacturing tool having a controller, any device having a set of one or more processors, etc.). As used herein, "computer-readable media" can include a single media or multiple media (e.g., storing one or more instruction sets).

[0148] In various embodiments, hardwired circuitry may be combined with software and firmware instructions to implement techniques. Accordingly, the techniques are not limited to any specific combination of hardware circuitry and software, nor to any particular source of the instructions executed by a computing device.

[0149] A wide variety of different types of computing devices may be used to implement the various embodiments set forth herein. As used herein, examples of "computing device" include, but are not limited to, servers, centralized computing platforms, systems of multiple computing processors and / or components, mobile devices, user terminals, vehicles, personal communication devices, wearable digital devices, electronic kiosks, general purpose computers, electronic document readers, tablet computers, laptop computers, smartphones, digital cameras, household appliances, televisions, or digital music players. Additional examples of computing devices include devices that are part of what is known as the "Internet of Things" (IoT). Such "things" may have occasional interactions with their owners or administrators who may monitor the things or modify the settings of these things. In some cases, such owners or administrators act as users of the "thing" devices. In some instances, a user's primary mobile device (e.g., an iPhone) may be an administrative server for a paired "thing" device (e.g., an Apple Watch) worn by the user.

[0150] In some embodiments, the computing device may be a computer or host system implemented, for example, as a desktop computer, laptop computer, network server, mobile device, or other computing device that includes a memory and a processing device. The host system may include or be coupled to a memory subsystem such that the host system can read data from or write data to the memory subsystem. The host system may be coupled to the memory subsystem via a physical host interface. Generally, the host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0151] In some embodiments, the computing device is a system that includes one or more processing devices. Examples of processing devices may include a microcontroller, a central processing unit (CPU), application specific logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), a system on a chip (SoC), or another suitable processor.

[0152] In one example, the computing device is a controller of a memory system. The controller includes a processing device and a memory that contains instructions executed by the processing device to control various operations of the memory system.

[0153] Although some of the figures illustrate several operations in a particular order, operations that are not order-dependent can be reordered and other operations can be combined or broken down. While some reorderings or other groupings are specifically mentioned, other reorderings or groupings will be apparent to those skilled in the art and thus do not represent an exhaustive list of alternatives. In addition, it should be recognized that the stages can be implemented in hardware, firmware, software, or any combination thereof.

[0154] Unless otherwise specifically stated, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood in the context usually used to present items, terms, etc. that can be X, Y, or Z or any combination thereof (e.g., X, Y, and / or Z). Thus, this disjunctive language is generally not intended to, nor should it, imply that certain embodiments require the presence of at least one of each of X, at least one of Y, or at least one of Z.

[0155] In the foregoing specification, the disclosure has been described with reference to specific exemplary embodiments of the disclosure. It should be understood that various modifications can be made to the disclosure without departing from the broader spirit and scope set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. An apparatus comprising: A memory array having memory cells; Bit lines coupled to at least one first memory cell; A current source configured to provide a reference current; A first transistor coupling the current source to the bit line, wherein a magnitude of a first gate voltage of the first transistor is increased during sensing of the first memory cell; A detector having an input coupled to the bit line, wherein the detector is configured to detect whether the first memory cell has reached a threshold; And A second transistor supplying a supply voltage to the detector, wherein a magnitude of a second gate voltage of the second transistor is increased during the sensing of the first memory cell.

2. The apparatus according to claim 1, wherein the detector is an inverter.

3. The apparatus according to claim 1, wherein the first and second gate voltages are the same ramp voltage.

4. The apparatus according to claim 1, wherein the first and second gate voltages ramp at the same rate.

5. The apparatus according to claim 1, wherein the supply voltage has a first polarity, and the apparatus further comprises a third transistor supplying a supply voltage of a second polarity to the detector.

6. The apparatus according to claim 5, wherein a magnitude of a third gate voltage of the third transistor ramps at the same rate as the first and second gate voltages during the sensing.

7. The apparatus according to claim 5, wherein the first and second transistors are n-type, and the third transistor is p-type.

8. The apparatus according to claim 1, wherein the memory array is a cross-point array, the bit lines are pillars extending vertically above a semiconductor substrate, and the memory cells are chalcogenide memory cells.

9. A system comprising: Sensing circuitry configured to sense memory cells of a memory device; Bias circuitry configured to bias an access line coupled to at least one first memory cell and supply power to the sensing circuitry; And A controller configured to: Receive a read command from a host device; In response to receiving the read command, initiate a read operation; Increase a magnitude of at least one ramp voltage during the read operation; During the read operation, apply a current to the access line using the bias circuitry, wherein application of the current to the access line is controlled using the ramp voltage; And Sense the first memory cell using the sensing circuitry to determine whether the first memory cell has reached a threshold, wherein power supply to the sensing circuitry is controlled using the ramp voltage.

10. The system according to claim 9, wherein the sensing circuitry is configured to sense the first memory cell using a first polarity or an opposite second polarity, and the first or second polarity is selected by the controller.

11. The system according to claim 9, wherein the sensing circuitry includes an inverter, and a threshold voltage of the inverter increases as a magnitude of the ramp voltage increases.

12. The system according to claim 9, wherein a leakage current of the first memory cell increases as the voltage on the access line increases.

13. The system according to claim 9, wherein: the bias circuit system includes a transistor coupled to the access line; and the ramp voltage is applied to a gate of the transistor.

14. The system according to claim 9, wherein the bias circuit system supplies power to the sense circuit system using a first supply voltage of a first polarity and a second supply voltage of an opposite second polarity, and wherein the ramp voltage controls magnitudes of the first and second supply voltages.

15. The system according to claim 14, wherein a detection threshold of the sense circuit system increases at a same rate as an increase in the magnitude of the ramp voltage.

16. The system according to claim 14, wherein: the at least one ramp voltage includes a first and a second ramp voltage; a magnitude of the second ramp voltage is lower than a magnitude of the first ramp voltage; the bias circuit system includes an n-type transistor and a p-type transistor; the first supply voltage is coupled to the sense circuit system through the n-type transistor, and the first ramp voltage is applied to a gate of the n-type transistor during the read operation; and the second supply voltage is coupled to the sense circuit system through the p-type transistor, and the second ramp voltage is applied to a gate of the p-type transistor during the read operation.

17. A method, comprising: applying a first voltage to a word line to access at least one memory cell in a three-dimensional cross-point memory array, wherein the word line extends horizontally above a semiconductor substrate; applying a second voltage to a bit line to access the memory cell, wherein the bit line extends vertically above the semiconductor substrate; increasing a magnitude of at least one gate voltage during a sense operation to read the memory cell; controlling the second voltage using the gate voltage; detecting a logic state of the memory cell, wherein a detection threshold is controlled using the gate voltage; and providing an amplified output indicative of the logic state of the memory cell.

18. The method according to claim 17, wherein a magnitude of the detection threshold increases as a magnitude of the gate voltage increases.

19. The method according to claim 17, further comprising restricting a current through the memory cell during the sense operation.

20. The method according to claim 17, wherein the at least one memory cell is a self-selecting memory cell, and a magnitude of a bias voltage applied across the memory cell during the sense operation corresponds to a threshold voltage of the memory cell.

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