Hybrid HSync transmission for video mode display panels

Abstract

A mobile communication device includes a first physical layer circuit, a second physical layer circuit, a selector circuit, and a display driver coupled to a display panel. The first physical layer circuit is configured to communicate packets of data at a first data rate over a first serial bus when the first physical layer circuit is operating in a high speed mode, and to suppress communication over the first serial bus when the first physical layer circuit is operating in a low power mode. The second physical layer circuit is configured to transmit or receive display-related information through a second serial bus according to a clock signal transmitted through the second serial bus. The selector circuit is configured to provide a row synchronization signal to the display panel by selecting between a synchronization signal generated by the display driver in a high speed mode and the clock signal in the low power mode.

Description

Technical Field

[0001] The present disclosure generally relates to serial communication via a serial bus in a wireless communication device, and more particularly to a low power mode for communication of a display subsystem interface. Background Art

[0002] Mobile communication devices typically include various components such as circuit boards, integrated circuit (IC) devices, application specific integrated circuit (ASIC) devices, and / or system on a chip (SoC) devices. The types of these components can include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus can operate according to a standardized protocol or a proprietary protocol. In one example, the serial bus can operate according to the inter-integrated circuit (I2C or I 2 C) communication protocol. The I2C bus is configured as a multi-drop bus and is developed for connecting low-speed peripheral devices to a processor. The two wires of the I2C bus include a serial data line (SDA) that carries a data signal and a serial clock line (SCL) that carries a clock signal.

[0003] In another example, the serial bus can operate according to the serial peripheral interface (SPI) communication protocol, where a clock signal controls synchronous serial data exchange between a master device and subordinate devices. The SPI protocol enables the use of two or more data lines of the serial bus to convey data and allows the serial bus to be configured for multi-drop operation. Since one or more of the data lines can be shared by receiving devices, a select signal provided to devices coupled to the bus is used to control access to the shared data lines.

[0004] In another example, the serial bus may operate according to a multi-master protocol such that one or more devices may be designated as bus master or host devices for the serial bus. A device may act as a bus master or host in some transmissions and as a slave or subordinate device in other transmissions. In one example, an improved Inter-Integrated Circuit (I3C) protocol may be used to control operations on the serial bus. The I3C protocol is defined by the Mobile Industry Processor Interface (MIPI) Alliance and derives certain implementation aspects from the I2C protocol. In another example, the Radio Frequency Front-End (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PAs), low noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices may be co-located in a single IC device or provided in multiple IC devices. Multiple antennas and radio transceivers may be provided in a mobile communication device to support multiple concurrent RF links. In another example, the System Power Management Interface (SPMI) defined by the MIPI Alliance provides a hardware interface that may be implemented between a baseband or application processor and peripheral components. The SPMI may be used to support power management and other operations within a device or system.

[0005] Multiple standards have been defined for interconnecting certain types of components in a mobile communication device. For example, there are various types of interfaces defined for communication between an application processor and a display or camera component in a mobile communication device. Some components employ interfaces that conform to one or more standards or protocols specified by the MIPI Alliance, including standards or protocols for the Camera Serial Interface (CSI) and the Display Serial Interface (DSI).

[0006] The MIPI Alliance DSI, DSI-2 (collectively and individually referred to herein as DSI), and CSI and CSI-2 (collectively and individually referred to herein as CSI) standards define wired interfaces that may be deployed within an IC or between a certain combination of IC devices and SoC devices. The CSI protocol may be used to couple a camera and an application processor. The DSI protocol may be used to couple an application processor and a display subsystem. The low-level physical layer (PHY) interfaces in each of these applications may be implemented according to the MIPI Alliance C-PHY or D-PHY standards and protocols. High-speed and low-power modes of communication are defined for the C-PHY interface and the D-PHY interface. The C-PHY high-speed mode uses low-voltage multi-phase signals transmitted in different phases on a 3-wire link. The D-PHY high-speed mode uses multiple 2-wire channels to carry low-voltage differential signals. The low-power modes of the C-PHY interface and the D-PHY interface provide lower rates than the high-speed modes and transmit signals at higher voltages.

[0007] As device technology improves, the combination of the need for higher data rates on serial buses and the use of multi-mode display panels tends to increase power consumption. The display subsystem and associated circuitry exchange data at high data rates and consume a significant portion of the power available in mobile communication devices and other portable devices. There is a continuing need to improve power savings in mobile communication devices and other portable devices. SUMMARY OF THE INVENTION

[0008] Certain aspects of the present disclosure relate to systems, apparatuses, methods, and techniques that enable mobile communication devices and other portable devices to idle data communication links between and within a processor and a display subsystem, and enable a greater portion of the mobile communication devices and other portable devices to enter a sleep mode when the display is dormant.

[0009] In various aspects of the present disclosure, a mobile communication device includes: a first physical layer circuit powered by a first power supply and configured to: convey data packets to a display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and inhibit conveyance via the first serial bus when the first physical layer circuit operates in a low-power mode; a second physical layer circuit powered by a second power supply and configured to transmit or receive display-related information via a second serial bus in accordance with a clock signal transmitted via the second serial bus; and a selector circuit configured to provide a line synchronization signal to the display panel by selecting: a synchronization signal generated by the display driver when the first physical layer circuit operates in the high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low-power mode.

[0010] In various aspects of the present disclosure, a method for operating a display in a mobile communication device includes: configuring a first physical layer circuit powered by a first power supply to: convey data packets to a display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and inhibit conveyance via the first serial bus when the first physical layer circuit operates in a low-power mode; configuring a second physical layer circuit powered by a second power supply to transmit or receive display-related information via a second serial bus in accordance with a clock signal transmitted via the second serial bus; and configuring a selector circuit to provide a line synchronization signal to the display panel by selecting a synchronization signal generated by the display driver when the first physical layer circuit operates in the high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low-power mode.

[0011] In various aspects of the present disclosure, an apparatus includes: means for communicating with a display driver, the means including a first physical layer circuit powered by a first power supply, the first physical layer circuit being configured to convey packets of data to the display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and being further configured to inhibit conveyance via the first serial bus when the first physical layer circuit operates in a low-power mode; means for communicating with a touch panel interface, the means including a second physical layer circuit powered by a second power supply, the second physical layer circuit being configured to transmit or receive display-related information via the second serial bus in accordance with a clock signal transmitted via the second serial bus; and means for selecting between a synchronization signal generated by the display driver and the clock signal transmitted via the second serial bus to provide a line synchronization signal to a display panel. When the first physical layer circuit operates in the high-speed mode, the synchronization signal generated by the display driver is selectable, and when the first physical layer circuit operates in the low-power mode, the clock signal transmitted via the second serial bus is selected.

[0012] In various aspects of the present disclosure, a processor-readable storage medium includes code for: configuring a first physical layer circuit powered by a first power supply to convey packets of data to a display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and to inhibit conveyance via the first serial bus when the first physical layer circuit operates in a low-power mode; configuring a second physical layer circuit powered by a second power supply to transmit or receive display-related information via the second serial bus in accordance with a clock signal transmitted via the second serial bus; and configuring a selector circuit to provide a line synchronization signal to a display panel by selecting a synchronization signal generated by the display driver when the first physical layer circuit operates in the high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low-power mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An apparatus that exemplifies the use of a data link between IC devices and selectively operates according to a standard or proprietary protocol is illustrated.

[0014] Figure 2 An example of an interface circuit that can be adapted according to certain aspects of the present disclosure is illustrated.

[0015] Figure 3 A system architecture of an apparatus that exemplifies the use of a data link between IC devices is illustrated.

[0016] Figure 4 An example of a C-PHY interface that can be adapted according to certain aspects disclosed herein is illustrated.

[0017] Figure 5 Illustrates an example of a D-PHY interface that can be adapted according to certain aspects disclosed herein.

[0018] Figure 6 Illustrates certain aspects of a two-data-line serial peripheral interface that can be adapted according to certain aspects disclosed herein.

[0019] Figure 7 Illustrates a system that includes a display subsystem interface and can be adapted according to certain aspects of the present disclosure.

[0020] Figure 8 Illustrates certain aspects of the operation of a display panel in a system that includes a DSI interface.

[0021] Figure 9 Illustrates a system that operates in a low-power mode according to certain aspects of the present disclosure.

[0022] Figure 10 Illustrates Figure 9 certain aspects of the high-speed mode operation of the system illustrated in

[0023] Figure 11 Illustrates an example of an apparatus that employs processing circuitry that can be adapted according to certain aspects disclosed herein.

[0024] Figure 12 Is a flowchart that illustrates a method for operating a display in a mobile communication device according to certain aspects disclosed herein.

[0025] Figure 13 Illustrates a first example of a hardware implementation of a communication device that is adapted according to certain aspects disclosed herein. Detailed Description

[0026] The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. For the purpose of providing a thorough understanding of the various concepts, the detailed description includes specific details. It will be apparent, however, to one of ordinary skill in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0027] Aspects of the present invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various boxes, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0028] Data communication links employed by an SoC and other IC devices to connect a processor to a modem and other peripherals can operate according to industry or proprietary standards or protocols associated with certain functions or types of devices. In the example of a display panel, display subsystem, and display driver, communication standards and protocols defined by the MIPI Alliance are often used. For example, the Display Serial Interface provides the C-PHY and D-PHY standards and protocols for defining, configuring, and controlling a high-speed serial interface between a host processor and a display module. Control and management protocols can be used to operate other serial buses coupling the host processor and the display module, and these protocols may include SPMI, I2C, I3C, and / or other protocols.

[0029] Mobile communication handsets typically support low-power operation modes that can be initiated when the handset is idle. In conventional handsets that use the DSI protocol to manage certain serial data links, there is little difference between the high-speed mode and the low-power operation mode of the serial data link. Thus, when the handset is idle and using the DSI protocol to manage the serial data link, it may be difficult or impossible to allow the processor in the host device including the serial data link or related circuits to enter the low-power mode. According to certain aspects of the present disclosure, when the low-power mode is activated, data communication between the host device and the display driver can be transferred to a low-power serial data link. The DSI physical layer circuit can be idle, and the processor in the host device can enter the sleep mode.

[0030] Example of an apparatus using a serial data link

[0031] In accordance with certain aspects of the present disclosure, a serial data link can be used to interconnect electronic devices that are sub-components of devices such as cellular telephones, smart phones, session initiation protocol (SIP) telephones, laptop computers, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, global positioning system (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, gaming devices, entertainment devices, vehicle components, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0032] Figure 1 An example of an apparatus 100 employing a data communication bus is illustrated. The apparatus 100 can include processing circuitry 102 having a plurality of circuits or devices 104, 106, and / or 108, which can be implemented in one or more application specific integrated circuits (ASICs) or in a system on a chip (SoC). In one example, the apparatus 100 can be a communication device, and the processing circuitry 102 can include processing devices provided in an ASIC 104, one or more peripherals 106, and a transceiver 108 that enables the apparatus to communicate with a radio access network, a core access network, the Internet, and / or another network via an antenna 124.

[0033] The ASIC 104 may have one or more processors 112, one or more modems 110, on-board memory 114, bus interface circuitry 116, and / or other logic circuits or functions. The processing circuitry 102 may be controlled by an operating system, which may provide an application programming interface (API) layer that enables one or more processors 112 to execute software modules resident in the on-board memory 114 provided on the processing circuitry 102 or other processor-readable storage devices 122. The software modules may include instructions and data stored in the on-board memory 114 or the processor-readable storage devices 122. The ASIC 104 may access its on-board memory 114, processor-readable storage devices 122, and / or storage devices external to the processing circuitry 102. The on-board memory 114, processor-readable storage devices 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device usable in processing systems and computing platforms. The processing circuitry 102 may include, implement, or access a local database or other parameter storage device, which may maintain operating parameters and other information for configuring and operating the device 100 and / or the processing circuitry 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks, or hard disks, etc. The processing circuitry 102 is also operatively coupled to external devices such as an antenna 124, a display 126, operator controls (such as switches or buttons 128, 130, and / or an integrated or external keypad 132), and other components. The user interface module may be configured to operate with the display 126, external keypad 132, etc. via a dedicated communication link or via one or more serial data interconnections.

[0034] The processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable two or more devices 104, 106, and / or 108 to communicate. In one example, the ASIC 104 may include one or more bus interface circuits 116, which include a combination of circuitry, counters, timers, control logic components, and other configurable circuits or modules. In one example, the bus interface circuit 116 may be configured to operate according to a communication specification or protocol defined by a standard. The processing circuitry 102 may include or control power management functions that configure and manage the operation of the device 100.

[0035] Figure 2Illustrates an example of an interface circuit that can be adopted or adapted according to certain aspects of the present disclosure. The first interface circuit is configured as a camera subsystem 200, and the second interface circuit is configured as a display subsystem 250. For example, the interface circuit can be deployed in a mobile communication device. The camera subsystem 200 can include a CSI-2 defined communication link between an image sensor 202 and an application processor 212. The communication link can include a high data rate data transmission link 210 used by the image sensor 202 to transmit image data to the application processor 212 using a transmitter 206. The high data rate data transmission link 210 can be configured and operated according to the D-PHY or C-PHY protocol. The application processor 212 can include a crystal oscillator (XO 214) or other clock source to generate a clock signal 222 that controls the operation of the transmitter 206. The clock signal 222 can be processed by a phase locked loop (PLL) 204 in the image sensor 202. In some cases, the clock signal 222 can also be used by a D-PHY or C-PHY receiver 216 in the application processor 212. The communication link can include a camera control interface (CCI), which is essentially similar to an inter-integrated circuit (I2C) interface. The CCI bus can include a serial clock (SCL) line that carries the clock signal and a serial data (SDA) line that carries the data. The CCI link 220 can be bidirectional and can operate at a lower data rate than the high data rate data transmission link 210. The application processor 212 can use the CCI link 220 to exchange control and configuration information with the image sensor 202. The application processor 212 can include a CCI bus master PHY 218, and the image sensor 202 can include a CCI slave PHY 208.

[0036] The display subsystem 250 can include a unidirectional data link 258 that can be configured and operated according to the D-PHY or C-PHY protocol. In the application processor 252, a clock source such as a PLL 254 can be used to generate a bit clock signal used by the D-PHY or C-PHY receiver 256 to control transmissions on the data link 258. At the display driver 260, the D-PHY or C-PHY receiver 262 can extract embedded clock information from the symbol sequence transmitted on the data link or from the clock channel provided in the data link 258.

[0037] Certain aspects disclosed herein relate to systems, devices, and methods that support a wide range of interface protocols and can operate using different physical media. As Figure 2As shown, for example, camera subsystem 200 and / or display subsystem 250 may use D-PHY or C-PHY protocols to convey high data rate information. In some configurations, camera subsystem 200 and / or display subsystem 250 may communicate using a reverse channel (e.g., CCI link 220) for configuring image sensor 202 or other devices. In some cases, a low power operation mode may be defined for links using either the D-PHY or C-PHY protocol.

[0038] Figure 3 An example of apparatus 300 incorporating a data link that may be used to communicatively couple two or more devices, subcomponents, or circuits is illustrated. Here, apparatus 300 includes a plurality of devices 302 and 3220 - 322 coupled to a two-wire serial bus 320 N Devices 302 and 3220 - 322 N may be implemented in one or more semiconductor IC devices such as an application processor, SoC, or ASIC. In various embodiments, some of devices 302 and 3220 - 322 N may include, support, operate as, or otherwise include a modem, signal processing device, display driver, camera, user interface, sensor, sensor controller, media player, transceiver, and / or other such components or devices. In some examples, one or more of devices 3220 - 322 N may be used to control, manage, or monitor sensor devices. Communication between devices 302 and 3220 - 322 N over serial bus 320 is controlled by host device 302. Certain types of buses may support multiple bus masters 302.

[0039] In one example, host device 302 may include interface controller 304, which may manage access to the serial bus, configure dynamic addresses for subordinate devices, and / or generate a clock signal 328 to be sent on clock line 318 of serial bus 320. Host device 302 may include configuration register 306 or other storage 324 and other control logic 312 configured to handle protocols and / or higher level functions. Control logic 312 may include processing circuitry such as a state machine, sequencer, signal processor, or general purpose processor. Host device 302 includes transceiver 310 and line drivers / receivers 314a and 314b. Transceiver 310 may include a receiver, transmitter, and common circuitry, where the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on the timing in clock signal 328 provided by clock generation circuit 308. Control logic 312 and other functions, circuits, or modules may use other timing clocks 326.

[0040] At least one device 3220-322 N may be configured to operate as a subordinate device on serial bus 320 and may include circuitry and modules that support a display, an image sensor, and / or one or more sensors that control and communicate with measurement environmental conditions. In one example, device 3220 configured to operate as a subordinate device may provide control functions, a physical layer circuit 332 that includes circuitry and modules that support a display, an image sensor, and / or one or more sensors that control and communicate with measurement environmental conditions. In this example, device 3220 may include a configuration register 334 or other storage device 336, control logic 342, a transceiver 340, and line drivers / receivers 344a and 344b. Control logic 342 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 340 may include a receiver, a transmitter, and common circuitry, where the common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 348 provided by clock generation and / or recovery circuitry 346. In some instances, clock signal 348 may be derived from a signal received from clock line 318. Control logic 342 and other functions, circuitry, or modules may use other timing clocks 338.

[0041] Serial bus 320 may operate according to RFFE, I2C, I3C, SPI, SPMI, or another suitable protocol. In some cases, two or more devices 302, 3220-322 N may be configured to operate as host devices on serial bus 320. In some cases, apparatus 300 includes multiple serial buses 320, 352a, and / or 352b that couple two or more of devices 302, 3220-322 N or one of devices 302, 3220-322 N and a peripheral device such as a display or camera 350 or a radio frequency integrated circuit (RFIC). In some examples, one subordinate device 3220 is configured to operate as a display or camera coupled to display or camera 350. The latter subordinate device 3220 may include a physical layer circuit 332 configured to operate as a C-PHY or D-PHY interface controller that communicates with display or camera 350 via serial bus 352a or 352b operating according to the C-PHY protocol or D-PHY protocol.

[0042] In certain aspects of the present disclosure, systems and devices may employ a multi-phase data encoding and decoding interface method to communicate between IC devices. A multi-phase encoder may drive multiple conductors (i.e., 3 conductors). Each conductor may be referred to as a wire, but the conductor may include conductive traces on a circuit board or traces or interconnects within a conductive layer of a semiconductor IC device. In one example, a physical layer interface (i.e., C-PHY interface) implemented using the C-PHY technology and protocol defined by the MIPI Alliance may be used to connect a camera or a display to an application processor. The C-PHY interface employs three-phase symbol encoding to transmit data symbols over a 3-wire channel or "trio", where each trio includes an embedded clock. The trio may be referred to herein as a channel. Multiple trios may be used to establish a multi-channel C-PHY communication channel to carry data exchanged between a pair of devices, where each channel includes one trio that carries a portion of the data, and the data may be independently encoded according to the C-PHY protocol.

[0043] The C-PHY interface provides a three-phase encoding scheme for a three-wire system, which can define three phase states and two polarities, thus providing 6 states and 5 possible transitions for each state. Deterministic voltage and / or current changes can be detected and decoded to extract data from the three wires.

[0044] Figure 4 Illustrated is a C-PHY interface 400 that may be used to implement certain aspects of the serial buses 352a or 352b depicted in Figure 3 The illustrated example may relate to a three-wire link configured to carry three-phase polarity-encoded data according to the DSI protocol. The use of 3-phase polarity encoding provides high-speed data transmission and may consume half or less power of other interfaces at a desired operating frequency, since fewer than 3 drivers are active at any time in a C-PHY link. The C-PHY interface uses 3-phase polarity encoding to encode multiple bits for each symbol transition on the three-wire link. In one example, a combination of three-phase encoding and polarity encoding may be used to support a wide video graphics array (WVGA), a liquid crystal display driver IC at 80 frames per second, without a frame buffer, delivering pixel data at 810 Mbp over three or more wires for display refresh.

[0045] In the depicted C-PHY interface 400, three-phase polarity coding is used to control the signaling states of connectors, wires, traces, and other interconnects that provide communication channels. In the illustrated example, a combination of three wires (triplet 420) is used to provide a single unidirectional channel or lane. Each wire of the triplet 420 can be undriven, positively driven, or negatively driven during any symbol transmission interval. In some cases, the undriven signal wire of the triplet 420 can be in a high impedance state. In some cases, the undriven signal wire of the triplet 420 can be driven or pulled to a voltage level that is substantially intermediate between the positive voltage level and the negative voltage level provided on the driven signal wires. In some cases, no current can flow through the undriven signal wire of the triplet 420. The driver 408 that controls the signal wires coupled to the triplet 420 is such that only one wire of the triplet 420 is in each of three states (represented as +1, -1, or 0) during each symbol interval.

[0046] In one example, the driver 408 can include a unit-level current mode driver. In another example, the driver 408 can drive opposite polarity voltages on two signals transmitted on two signal wires of the triplet 420 while the third signal wire is in a high impedance and / or pulled to ground. For each transmission symbol interval, at least one signal is in an undriven (0) state while one signal is driven positive (+1 state) and one signal is driven negative (-1 state) such that the sum of the currents flowing to the receiver is always zero. For each symbol, the state of at least one signal wire of the triplet 420 changes from the symbol transmitted in the previous transmission interval.

[0047] In the C-PHY interface 400, the mapper 402 can receive a 16-bit input data word 418, and the mapper 402 can map the input data word 418 to seven symbols 412 for sequential transmission over the signal wires of the triplet 420. The M-wire, N-phase encoder 406, configured for three-wire, three-phase coding, receives the seven symbols 412 produced by the mapper one input symbol 414 at a time and calculates the state of each signal wire of the triplet 420 for each symbol interval based on the immediately preceding state of the signal wires of the triplet 420. The seven symbols 412 can be serialized using, for example, a parallel-to-serial converter 404. The encoder 406 provides a control signal 416 to define the output of the driver 408. The encoder 406 selects the state of the signal wires of the triplet 420 based on the input symbol 414 and the previous state of the signal wires of the triplet 420 and can provide the control signal 416 to cause the driver 408 to produce the desired signaling state on the triplet 420.

[0048] The use of three-wire, three-phase encoding allows multiple bits to be encoded in multiple symbols, where the bits per symbol are not integers. In an example of a three-wire, three-phase system, there are 3 available combinations of 2 wires that can be driven simultaneously, and 2 possible polarity combinations on a pair of wires that are driven simultaneously, resulting in 6 possible states. Since each transition starts from the current state, 5 of the 6 states are available for each transition. For 5 states, each symbol transition can encode a fractional bit. Thus, the mapper can accept a 16-bit word and convert it into 7 symbols, since 7 symbols with 2.32 bits per symbol can encode 16.24 bits. In other words, the combination of seven symbols encoding five states has 5 7 (78,125) permutations. Thus, 7 symbols can be used to encode 2 16 (65,536) permutations of 16 bits.

[0049] The receiver in the C-PHY interface 400 includes a comparator 422 and a decoder 424 that are configured to provide a digital representation of the state of each of the three signal lines of the three-wire group 420, and the change in the state of the three signal lines compared to the state transmitted in the previous symbol period. Seven consecutive states are combined by the serial-to-parallel converter 426 to produce a set of 7 symbols to be processed by the demapper 428 to obtain 16-bit data that can be buffered in a first-in, first-out (FIFO) storage device 430, which can be implemented using, for example, registers.

[0050] In accordance with certain aspects disclosed herein, systems and devices can employ some combination of differential encoding and single-ended encoding to communicate between IC devices. In one example, the "D-PHY" physical layer interface technology defined by the MIPI Alliance can be used to connect a camera and a display device to an application processor. The D-PHY interface can switch between differential (high-speed) mode and single-ended low-power (LP) mode in real time as needed to facilitate the transfer of large amounts of data or to conserve power and extend battery life. The D-PHY interface is capable of operating in a simplex or duplex configuration with a single data channel or multiple data channels with a unidirectional clock channel driven by the host device. In one example, a single wire is used to implement the data channel. The single-wire channel can be used at a lower data rate that is used to generate a data signal that can be transmitted with limited loss such that the receiver can easily decode the data carried on the data channel. The two-wire channel carrying differential-encoded clock and data signals provides common-mode rejection of electromagnetic interference and can limit the attenuation of higher frequency components in the signals transmitted on the channel.

[0051] Figure 5Illustrates a generalized example of a D-PHY interface 500 that includes a host device 502 and a subordinate device 504 coupled using a set of wires 510 for providing a clock channel 506 and one or more data channels 5081-508 N For high-speed operation, the clock channel 506 and data channels 5081-508 N can each be set up to carry differential signals using a pair of wires. In one example, the subordinate device 504 is provided in a display driver IC (DDIC) associated with a display panel, and the host device 502 is included in an application processor or provided by another processing circuit.

[0052] In the illustrated example, a clock signal is transmitted on the clock channel 506, and data is transmitted on one or more data channels 5081-508 N The host device 502 includes a clock generation circuit 512 that can be configured to generate a clock signal 514 that is transmitted on the clock channel 506 to control the transmission on the data channels 5081-508 N The frequency of the clock signal 514 can be configured during system initialization or configuration and / or can be dynamically configured based on the operating mode of the D-PHY interface 500, application requirements, amount of data to be transmitted, and power savings requirements. The number of data channels 5081-508 N set or active in the device can be configured during system initialization or configuration and / or can be dynamically configured based on the operating mode of the D-PHY interface 500, application requirements, amount of data to be transmitted, and power savings requirements.

[0053] According to certain aspects of the present disclosure, a serial bus operating according to the SPI protocol can be used to provide a simple, low-power communication interface. In one example, the SPI interface can be primarily used to exchange data between a processing circuit and a touch panel of a display. The SPI interface can be coupled to a serial bus that has a clock line, two data lines (Master In Slave Out (MISO) line, Master Out Slave In (MOSI) line), and Chip Select (CS) for each subordinate device. The presence of the MISO and MOSI lines enables full-duplex operation. Figure 6Illustrates certain aspects related to the operation of a two - wire SPI 600. In some cases, the master device 602 may be incorporated into a SoC that acts as an application processor, a host processor, or other functional components of a device or system. The master device 602 is coupled to a plurality of subordinate devices 604, 606, 608 using a multi - wire bus 610. The master device 602 drives data to the subordinate devices 604, 606, 608 via the master - out - slave - in (MOSI) line 616 of the multi - wire bus 610. The subordinate devices 604, 606, 608 may each drive data to the master device 602 via the shared master - in - slave - out (MISO) line 614 of the multi - wire bus 610.

[0054] The multi - wire bus 610 includes at least one slave - select line 618, 620, 622 for each of the subordinate devices 604, 606, 608. As illustrated, the first slave - select line 618 (SS1) controls the bus access of the first subordinate device 604, the second slave - select line 620 (SS2) controls the bus access of the second subordinate device 606, and the third slave - select line 622 (SS3) controls the bus access of the third subordinate device 608. The master device 602 may assert the slave - select lines 618, 620, 622 to cause the corresponding subordinate devices 604, 606, 608 to receive data via the MOSI line 616, and / or to grant permission to the corresponding subordinate devices 604, 606, 608 to transmit on the MISO line 614.

[0055] In one example, when a low voltage level is applied to the slave - select lines 618, 620, 622, the slave - select lines 618, 620, 622 are not asserted, and the slave - select lines 618, 620, 622 are asserted by driving them to a high voltage level (e.g., towards the power level). In another example, when a high voltage level (e.g., the power level) is applied to the slave - select lines 618, 620, 622, the slave - select lines 618, 620, 622 are not asserted, and the slave - select lines 618, 620, 622 are asserted by driving them to a low voltage level. For each of the slave - select lines 618, 620, 622, a driver in the master device 602 is operable to charge and discharge the slave - select lines 618, 620, 622 based on the desired assertion state of the slave - select lines 618, 620, 622.

[0056] Data is transmitted between the master device 602 and the subordinate devices 604, 606, 608 according to a clock signal provided on the clock line 612 of the multi-line bus 610. The data signaling is unidirectional on the MISO line 614 and on the MOSI line 616. The direction of data transmission on the MISO line 614 is opposite to the direction of data transmission on the MOSI line 616. The data transmission on the MISO line 614 and the MOSI line 616 is synchronized with the clock signal provided on the clock line 612.

[0057] Figure 7 Illustrated is a system 700 that includes a display subsystem interface and may be adapted in accordance with certain aspects of the present disclosure. The illustrated system 700 includes an SoC 702 and a display subsystem 704 communicatively coupled using a high-speed serial bus 706 and a low-power serial bus 708. In the illustrated example, the SoC 702 includes multiple processors, the multiple processors including a central processing unit or a display processing unit (display controller 712) and a digital signal processor (DSP 716). For purposes of the present disclosure, an example of a high-speed serial data link may be described as being controlled and managed using the DSI protocol, while an example of a low-speed serial data link may be described as being controlled and managed using the SPI protocol. In other examples, other types of communication protocols may be used to control or manage the high-speed serial data link and the low-speed serial data link. In the illustrated example, the SoC 702 includes a DSI physical interface (DSIPHY 714) and an SPI physical interface (SPIPHY 718).

[0058] In one aspect of the present disclosure, at least two power domains are defined for the SoC 702, including a high-speed power domain and a low-power power domain, wherein the low-power power domain may be implemented as a low-power island 710. The high-speed power domain may support, supply, and / or include a section of an IC or an SoC that performs various functions, the various functions including storing data (memory), managing the stored data, performing certain logic functions, processing specific functions, encryption, image processing, wireless and wired communication, and the like. More than one section of the IC may operate as the high-speed power domain. In the illustrated example, the display controller 712 and the DSIPHY 714 operate within the high-speed power domain.

[0059] In many examples, the devices and / or circuits in the high-speed power domain may be configured to support operation at the highest possible operating frequency enabled by the process technology. In some examples, the operating frequency of the circuits in the high-speed power domain may be power budget constrained, and the operating frequency of some circuits may be configured to operate at the highest frequency supportable under the power budget. Lower power consumption in the high-speed circuits may be achieved by reducing the operating voltage of the high-speed power domain.

[0060] In some examples, the low-power island 710 may support, supply, and / or be included in a section of an IC or SoC that performs real-time, low-frequency, and / or low-data rate communications and includes processing circuitry associated with the performance of real-time, low-frequency, and / or low-data rate communication tasks and functions. In one example, the low-power island 710 may power circuitry and devices for communication and processing functions associated with certain types of sensors. In another example, the low-power island may power circuitry and devices for low-data rate communication and processing.

[0061] In some conventional systems, a dedicated display processing unit (DPU) or central processing unit for configuring, controlling, and managing the display subsystem 704 is deployed within a high-speed power domain. In some cases, support circuitry for an “always-on” camera may operate at least partially within the low-power island 710. Circuits within the high-speed power domain may be used to provide a communication link for the camera, as the camera typically transmits image data when the user is actively interacting with the portable device or mobile device and the system 700 has entered a high-speed operation mode. In a conventional implementation, when the portable device or mobile device is in a sleep state, the DSIPHY and associated circuitry for communicating with the camera may be idle.

[0062] The display subsystem 704 includes display driver circuitry that may be implemented in a display driver IC (DDIC 722) to drive the display panel 730. The display subsystem 704 may include a touch panel interface 732 associated with the display panel 730. In some cases, the touch panel interface 732 is included in the DDIC 722. The DDIC 722 includes a DSI physical interface (DSIPHY 724) configured as a receive interface coupled to the high-speed serial bus 706. The illustrated DDIC 722 also includes a low-power serial bus 708.

[0063] The SPI physical interface (SPIPHY 728) in the display subsystem 704 is coupled to the SPIPHY 718 in the SoC 702 via the low-power serial bus 708 and may be configured to support bi-directional full-duplex operation. The SPIPHY 728 in the display subsystem 704 is used to communicatively couple the touch panel interface 732 to the DSP 716 in the SoC 702. The DSP 716 may be configured to support a user interface. For example, the DSP 716 may be configured to detect user contacts, multi-touch contacts, and movements on the display panel 730 that can be decoded as user gestures. The DSP 716 may be configured to wake up the system 700 from an idle or sleep mode when an active or new user contact or movement is detected.

[0064] In a conventional mobile device or portable device, when the display subsystem 704 is in an idle or other static mode, the display subsystem maintains an active high-speed data communication link between the SoC 702 and the display subsystem 704. The circuitry that implements and supports the active high-speed data communication link is not suitable for inclusion in the low-power island 710. The operation of the DSIPHY 724 in the low-power display mode remains substantially the same as its operation in the high-speed mode. The continued operation of the DSIPHY 724 prevents the display controller 712 from entering the deep sleep mode. The level of power consumption attributable to the DSIPHY 724, the display controller 712, and associated circuitry during the static mode may make it infeasible to include them in the low-power island 710 due to cost and complexity.

[0065] In one example, the high-speed data communication link is used to convey the timing and synchronization information required to operate a low-temperature polycrystalline oxide (LPTO) organic light-emitting diode (OLED) display panel without RAM. The DDIC 722 may use the timing and synchronization information to generate or synchronize the horizontal sync signal (HSync 734) required for the video mode operation of the LPTO OLED display panel without RAM. In one example, the DSIPHY 724 includes circuitry 726 that is configured to generate the HSync 734 by detecting or decoding the synchronization information received over the high-speed serial bus 706.

[0066] In many portable devices or mobile devices, the display subsystem consumes a significant portion of the power budget defined for the device. For example, the power budget of a cellular phone may be defined with the goal of maximizing the available operating time between battery charging events to minimize heat generation and limit the need for thermal mitigation. The power budget may be defined based on a trade-off between the power requirements associated with wireless communication scheduling and the requirements for maintaining a responsive user interface.

[0067] Using an LPTO OLED display panel without RAM can exacerbate problems associated with high levels of continuous power demand associated with the DSI interface. When the display is blanked, idle, or operating at a low frame rate, certain components of the display subsystem 704 in a portable device or mobile device, including the LPTO OLED display panel 730 without RAM, continue to operate in high-speed mode. When the display panel 730 is constructed using LPTO OLED technology without RAM and operating in video mode, the SoC 702 needs to provide host timing, reference clock information, and state machine control to the DDIC 722 and the display panel 730 at all times. Therefore, when the portable device or mobile device is operating in an active mode (e.g., "always-on display") or at a low frame rate, or in a static mode (such as "sleep", "hibernate", "display idle", or "smartwatch display" mode), the DSI circuit and associated circuits can consume similar power levels. When the DSI circuit operates continuously in high-speed mode, it is usually necessary to operate other circuits in the SoC or IC in high-speed mode, thereby increasing power consumption when the portable device or mobile device is operating in a static mode.

[0068] Figure 8 Including timing diagram 800, which illustrates certain aspects of the operation of an LPTO OLED display panel without RAM in a system including a DSI interface for communication between the SoC and the display subsystem. The display content 802 can change rapidly or remain unchanged for a long period of time, and the operating mode of the display can be changed to optimize power consumption in each mode and limit processing and communication overhead.

[0069] A variety of operation modes 808a, 808b, 808c, and 808d are shown by way of example. The display operates at a full refresh rate (60 Hz) in a first operation mode 808a, which may be related to the interaction between the user and the display. In the first operation mode 808a, pixel data is sent in a large number of partial packets 804 transmitted over the DSI link. The display operates at a full refresh rate (60 Hz) in a second operation mode 808b, which may be related to the display of video or other rapidly changing images. In the second operation mode 808b, pixel data is sent in a large number of partial packets 804 transmitted over the DSI link. When the displayed image changes slowly, for example, the display operates at a reduced refresh rate (40 Hz) in a third operation mode 808c. In the third operation mode 808c, compared to the full refresh rate modes 808a, 808b, pixel data is sent in a reduced number of packets 804 transmitted over the DSI link. The displayed image remains unchanged or changes slowly in a fourth operation mode 808d, and the display may operate at a low refresh rate, which may be 1 Hz in some examples. In the fourth operation mode 808d, pixel data is sent in a small number of packets 804 transmitted over the DSI link.

[0070] Display line synchronization (HSync) is implemented using the HSync signal 806. In each of the operation modes 808a, 808b, 808c, and 808d, the HSync signal 806 is provided to the display panel at full rate. The SoC can control the HSync signal 806 through the DSI interface. In one example, the SoC inserts certain synchronization event indicators into the packet 804a that also carries the pixel data stream. The synchronization event indicators may include HSync_Start and HSync_End indicators. The packets 804 are framed and transmitted according to the C-PHY or D-PHY protocol.

[0071] Figure 8 An example of signaling associated with the transmission of packets on a data communication link 812 operating according to the DSI protocol is illustrated. Although the timing diagram 810 illustrates the transmission according to the C-PHY protocol, some general concepts also apply to the D-PHY protocol. A high-speed transaction is illustrated. Starting at a first time 814, an SoT sequence 818 is sent to switch the C-PHY interface to a low-voltage, high-speed mode 830 for transmitting data packets. In the high-speed mode 830, low-voltage differential signaling is used. The C-PHY protocol defines a three-phase differential signaling scheme.

[0072] The illustrated high-speed data transmission includes data packet 824 and control signaling, which includes training, synchronization, and termination signaling. According to the C-PHY protocol, for example, preamble 820 and sync word 822 are sent prior to data packet 824 during transmission, and the data transmission is terminated by POST mode 826. The EoT sequence 828 is sent to terminate the transmission. POST mode 826 is provided at the end of the high-speed data transmission to provide a reliable notification of the end of the high-speed burst to the receiver.

[0073] Certain aspects of the present disclosure relate to a display subsystem that can operate in a low-power mode (including when the display subsystem is constructed using a RAM-less LPTO OLED display panel technology) and in a video mode that requires a continuous HSync signal. During the active mode and when the display refresh is not being performed, certain host timing, synchronization, and reference clock information is provided to the display panel. The display subsystem can continuously generate the HSync signal required by the display panel. The HSync signal can be used as a reference for the internal state machine of the DDIC.

[0074] When the display is in a static, sleep, or idle mode, certain aspects of the present disclosure can reduce the power consumption attributable to the display subsystem. In one aspect, HSync can be signaled in a high-speed, active mode via a high-speed data link operating according to the DSI protocol, the high-speed data link can be idle in a low frame rate, static, sleep, or idle mode, and the HSync signaling can be sent via a low-power SPI data link. The physical interface and other circuits associated with the low-power data link can be located in a low-power power domain or low-power island of the SoC or IC, thereby allowing other circuits in the SoC or IC to be idle or placed in a sleep mode. In one example, the SoC or IC provides a high-speed power domain and a low-power island, where the high-speed power domain can operate at a reduced power level during static, sleep, or idle cycles. The clock generator that provides the high-frequency (1.5 GHz - 2.5 GHz) DSI clock signal can be disabled or made idle, thereby achieving a reduction in the voltage of the associated power supply.

[0075] Compared to a conventional display subsystem, the idling of the DSI interface can provide a significant reduction in power consumption. Power savings can be obtained by disabling the DSI PHY during low-power or low-refresh rate operation modes. The high-speed processor can be relieved of the responsibility of servicing the DSI PHY and can enter a deep sleep mode. The display subsystem can be managed or synchronized via a secondary low-power communication link and can be serviced by a low-power processor. The low-power communication link and the low-power processor can reside in the low-power island.

[0076] Figure 9 and Figure 10 Illustrated is the operation of a display interface in a system configured according to certain aspects of the present disclosure. Figure 9Illustrates a first configuration 900 of the system, where the display subsystem operates in a low-power mode. Figure 10 Illustrates a second configuration 1000 of the system, where the display subsystem operates in a normal high-speed mode.

[0077] Figure 9 and Figure 10 The illustrated system corresponds in some aspects to Figure 7 the illustrated system 700. For example, the SoC 902 and the display subsystem 904 are communicatively coupled using a high-speed serial bus 906 and a low-speed serial bus 908. The SoC 902 includes a plurality of processors, which include a CPU or a DPU (display controller 912) and a digital signal processor (DSP 916). For the purposes of this disclosure, an example of a high-speed serial data link may be described as being controlled and managed using the DSI protocol, while an example of a low-speed serial data link may be described as being controlled and managed using the SPI protocol. In other examples, other types of communication protocols may be used to control or manage high-speed serial data links and low-speed serial data links. In the illustrated example, the SoC 902 includes a DSI physical layer interface (DSIPHY 914) and an SPI physical layer interface (SPIPHY 918).

[0078] In one aspect of the present disclosure, at least two power domains are defined for the SoC 902, including a high-power domain and a low-power domain, where the low-power domain is referred to herein as the low-power island 910. The high-power domain may support, supply, and / or include a section of an IC or SoC that performs various functions, including storing data (memory), managing the stored data, performing certain logical functions, processing specific functions, encryption, image processing, wireless and wired communication, etc. More than one section of the IC may operate as the high-power domain. In the illustrated example, the display controller 912 and the DSIPHY 914 operate within the high-power domain.

[0079] In certain examples, the low-power island 910 may support, supply, and / or include a section of an IC or SoC that performs real-time, low-frequency, and / or low-data-rate communication and includes associated processing circuitry. In one example, the low-power island 910 may power circuits and devices for communication and processing functions associated with certain types of sensors. In another example, the low-power island may power circuits and devices for low-data-rate communication and processing. In some examples, the display controller 912a is deployed within the high-power domain. In some cases, the display controller 912a is implemented using dedicated devices that configure, control, and manage the display subsystem 904.

[0080] The display subsystem 904 includes display driver circuitry that may be implemented in a display driver IC (DDIC 922) to drive a display panel 930. The display subsystem 904 may include a touch panel interface 932 associated with the display panel 930. In some embodiments, the touch panel interface 932 is integrated with or included in the DDIC 922.

[0081] The DDIC 922 includes a DSI physical interface (DSIPHY 924), an SPI physical interface (SPI PHY 928), and a selection circuit represented by a selector 940. The selector 940 may be implemented using a switch, a multiplexer, or some combination of logic gates or drivers. The DSIPHY 924 is configured as a receive interface and is coupled to a high-speed serial bus 906. In high-speed mode, the DDIC 722 may use the timing and synchronization information received via the high-speed serial bus 906 to provide the line synchronization signal (HSync 934) required for video mode operation of a RAM-less LPTO OLED display panel. The DDIC 922 may include a decoder circuit 926 that generates HSync 934 in response to HSync_Start and HSync_End indicators received via the high-speed serial bus 906.

[0082] The SPI physical interface (SPIPHY 928) is coupled to the SPIPHY918 in the SoC 902 via a low-speed serial bus 908 and may be configured to support bidirectional full-duplex operation. In some cases, the SPIPHY 928 is shared by the DDIC 922 and the touch panel interface 932. The SPIPHY 928 in the display subsystem 904 is used to communicatively couple the touch panel interface 932 to the DSP 916 in the SoC 902. The DSP 916 may be configured to support a user interface. For example, the DSP 916 may be configured to detect user contact, multi-touch, and movement on the display panel 930 that can be decoded as user gestures. The DSP 916 may be configured to wake the system 900 from an idle or sleep mode when a new user contact or movement is detected.

[0083] According to certain aspects of the present disclosure, the high-speed serial bus 906 may be idle when the display is active low or during system sleep mode. As Figure 9As illustrated, selector 940 can be configured to select the clock output derived from SPI_Clock of SPIPHY 928 to drive HSync 934 when the high-speed serial bus 906 is idle. In one specific implementation, SoC 902 can configure the SPI clock signal (SPI_Clock) to match the DSI line synchronization frequency defined by the specifications defined by the MIPI Alliance. In one example, SPI_Clock can be sent at a frequency of 400 KHz. SPIPHY 928 includes a receiver circuit that can output a signal (SPI_Clk 938) that is provided as an input to selector 940. As Figure 10 As illustrated, in high-speed configuration 1000, selector 940 can be configured to select the output of decoder circuit 926 in DDIC 922 to drive HSync 934 when the high-speed serial bus 906 is active.

[0084] Selector 940 can select between inputs based on the state of the low-power / high-speed selection signal (LP / HS 936). For example, LP / HS 936 can be driven by DSIPHY 924 or controlled by a register in the display subsystem, which is written by SoC902 using commands transmitted over the low-speed serial bus 908. In some cases, LP / HS 936 can be configured via an inter-process communication channel (IPCC) that carries messages between the processor in SoC 902 and the display subsystem 904. In some specific implementations, SoC 902 can transmit a notification to DDIC 922 that the source of HSync 934 needs to be switched. DDIC 922 can be configured to configure various components 922, 924, 926, 926, 940 of the display subsystem 904 before the line synchronization changes. In some specific implementations, commands can be sent over the low-speed serial bus 908 to configure SPIPHY 928 and / or LP / HS 936 before the operating mode of the high-speed serial bus 906 changes.

[0085] In some specific implementations, the source of HSync 934 can be automatically selected. For example, LP / HS 936 can drive HSync 934 by selecting decoder circuit 926 in DDIC922 in response to the detection of high-speed transmission of pixel data over the high-speed serial bus 906. In another example, LP / HS 936 can drive HSync 934 by selecting SPIPHY 928 in response to the detection of the high-speed serial bus 906 entering the low-power mode or the activity on the high-speed serial bus 906 stopping.

[0086] According to one aspect of the present disclosure, when HSync 934 is driven by SPIPHY 928, DSIPHY 914 in SoC 902 and DSIPHY 924 in DDIC 922 can be disabled or placed in a low-power, sleep, or static mode. When DSIPHY 914 in SoC 902 is not operating, the display controller 912 can also be disabled or placed in a low-power, sleep, or static mode.

[0087] In the low-speed mode, components residing in the low-power island 910 and the low-speed serial bus 908 can be used to implement the management and control of the display panel 930. In some examples, the DSP 916 can transmit display data and commands to the DDIC 922 via the low-speed serial bus 908. In some embodiments, the display data can be sent via the low-speed serial bus 908. The display data can be provided in any suitable format and can define pixel settings within a display frame. In one example, the display data is stored in a frame buffer in the low-power island 910 of the SoC 902. In another example, the display data can be retrieved from a cache residing in the low-power island 910 or otherwise accessible in the low-power mode.

[0088] The cache can be implemented in a storage device and can be used to store and supply display data generated by the display controller or another high-speed processor. In one example, when the display subsystem 904 operates in the low-speed mode, the cached display data can be retrieved in each frame refresh cycle. In some embodiments, the cache is filled before entering the low-power mode. In some embodiments, the DSP 916 can update the cache during the low-power mode. In some embodiments, the DSP 916 can merge the display data received from the cache with the data generated by the DSP 916 during the low-power mode. For example, the DSP 916 can cause date or time information, battery charge level, and / or other status information to be displayed during the low-power mode.

[0089] In the low-power mode, in addition to transmitting display data, the low-speed serial bus 908 can also be used to manage the touch panel interface 932. In a conventional system, a full touch interface is not supported in the low-power mode. Detection of a touch event causes the DSP 916 to notify the event to the display controller 912 or another processor or controller in the SoC 902 and thereby initiate a switch to the high-speed mode.

[0090] Example of a processing circuit and method

[0091] Figure 11FIG. is an illustration of an example of a hardware implementation for apparatus 1100. In some examples, apparatus 1100 may perform one or more functions disclosed herein. In accordance with various aspects of the present disclosure, the elements disclosed herein, any part of an element, or any combination of elements may be implemented using processing circuitry 1102. Processing circuitry 1102 may include one or more processors 1104 controlled by some combination of hardware modules and software modules. Examples of processors 1104 include microprocessors, microcontrollers, digital signal processors (DSPs), system on a chip (SoCs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. The one or more processors 1104 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1116. The one or more processors 1104 may be configured by a combination of software modules 1116 loaded during initialization and may be further configured by loading or unloading one or more software modules 1116 during operation.

[0092] In the illustrated example, processing circuitry 1102 may be implemented with a bus architecture, generally represented by bus 1110. Depending on the particular application of processing circuitry 1102 and overall design constraints, bus 1110 may include any number of interconnecting buses and bridges. Bus 1110 links together various circuits, including one or more processors 1104 and a storage device 1106. Storage device 1106 may include memory devices and mass storage devices and may be referred to herein as computer readable medium and / or processor readable medium. Bus 1110 may also link various other circuits, such as a timing source, a timer, peripherals, voltage regulators, and power management circuits. Bus interface 1108 may provide an interface between bus 1110 and one or more transceivers 1112a, 1112b. Transceivers 1112a, 1112b may be provided for each networking technology supported by the processing circuitry. In some instances, multiple networking technologies may share some or all of the circuits or processing modules found in transceivers 1112a, 1112b. Each of transceivers 1112a, 1112b provides means for communicating with various other devices over a transmission medium. In one example, transceiver 1112a may be used to couple apparatus 1100 to a multi-wire bus. In another example, transceiver 1112b may be used to connect apparatus 1100 to a radio access network. Depending on the nature of apparatus 1100, a user interface 1118 (e.g., keypad, display, speaker, microphone, joystick) may also be provided and the user interface may be coupled to bus 1110 either directly or through bus interface 1108 in a communicative manner.

[0093] The processor 1104 may be responsible for managing the bus 1110 and for general processing, which may include executing software stored in a computer-readable medium that may include the storage device 1106. In this regard, the processing circuitry 1102 (including the processor 1104) may be used to implement any of the methods, functions, and techniques disclosed herein. The storage device 1106 may be used to store data manipulated by the processor 1104 when executing the software, and the software may be configured to implement certain methods disclosed herein.

[0094] One or more processors 1104 in the processing circuitry 1102 may execute software. Software should be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, algorithms, etc., regardless of whether it is called software, firmware, middleware, microcode, hardware description language, or other names. The software may reside in the storage device 1106 in a computer-readable form or in an external computer-readable medium. The external computer-readable medium and / or the storage device 1106 may include a non-transitory computer-readable medium. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives", cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM) including EEPROM, registers, removable disks, and any other suitable medium for storing software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or the storage device 1106 may also, for example, include a carrier wave, a transmission line, and any other suitable medium for transmitting software and / or instructions that can be accessed and read by a computer. The computer-readable medium and / or the storage device 1106 may reside within the processing circuitry 1102, within the processor 1104, external to the processing circuitry 1102, or be distributed across multiple entities including the processing circuitry 1102. The computer-readable medium and / or the storage device 1106 may be embodied as a computer program product. By way of example, the computer program product may include a computer-readable medium in a packaging material. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure, depending on the particular application and the overall design constraints imposed on the overall system.

[0095] The storage device 1106 may maintain software that is maintained and / or organized in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software modules 1116. Each software module in the software modules 1116 may include instructions and data that, when installed or loaded into the processing circuitry 1102 and executed by one or more processors 1104, contribute to the runtime image 1114 that controls the operation of the one or more processors 1104. Certain instructions, when executed, may cause the processing circuitry 1102 to perform functions in accordance with certain methods, algorithms, and processes described herein.

[0096] Some of the software modules in the software modules 1116 may be loaded during initialization of the processing circuitry 1102, and these software modules 1116 may configure the processing circuitry 1102 to enable the execution of various functions disclosed herein. For example, some software modules 1116 may configure the internal devices and / or logic circuitry 1122 of the processor 1104 and may manage access to external devices such as transceivers 1112a, 1112b, bus interface 1108, user interface 1118, timers, math coprocessors, etc. The software modules 1116 may include control programs and / or operating systems that interact with interrupt processors and device drivers and control access to various resources provided by the processing circuitry 1102. Resources may include memory, processing time, access to transceivers 1112a, 1112b, user interface 1118, etc.

[0097] One or more processors 1104 of the processing circuitry 1102 may be multifunctional, whereby some of the software modules 1116 are loaded and configured to perform different functions or different instances of the same function. The one or more processors 1104 may additionally be adapted to manage background tasks initiated in response to inputs from, for example, the user interface 1118, the transceivers 1112a, 1112b, and device drivers. To support the execution of multiple functions, the one or more processors 1104 may be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be serviced by the one or more processors 1104 as needed or desired. In one example, a time-sharing program 1120 that transfers control of the processor 1104 between different tasks may be used to implement the multitasking environment, whereby each task returns control of the one or more processors 1104 to the time-sharing program 1120 upon completion of any outstanding operations and / or in response to an input such as an interruption. When a task controls the one or more processors 1104, the processing circuitry is effectively specialized for the purpose of being resolved by the function associated with the control task. The time-sharing program 1120 may include an operating system, a main loop that transfers control on a cyclic basis, a function that assigns control of the one or more processors 1104 according to the priority of the function, and / or an interrupt-driven main loop that provides control of the one or more processors 1104 to a processing function in response to an external event.

[0098] Figure 12 FIG. 1200 is a flowchart of a method for operating a display subsystem configured in accordance with certain aspects of the present disclosure. The method may be implemented in a mobile communication device that includes the display subsystem. In one example, the mobile communication device includes a first serial data link operating according to the DSI protocol and a second serial data link operating according to the SPI protocol. Other combinations of protocols may be used to operate the serial data links. For example, the second serial data link may operate according to a camera control interface (CCI) protocol, an inter-integrated circuit (I2C) protocol, an improved inter-integrated circuit (I3C) protocol, or a system power management interface (SPMI) protocol. The method may be executed using a display controller that is implemented using a combination of a CPU, a DPU, or a suitable processor such as a controller, a finite state machine, a digital signal processor.

[0099] At block 1202 in the illustrated method, a first physical layer circuit powered by a first power supply may be configured to communicate data packets to a display driver at a first data rate via a first serial bus when the first physical layer circuit is operating in a high-speed mode, and to inhibit communication via the first serial bus when the first physical layer circuit is operating in a low-power mode. At block 1204 in the illustrated method, a second physical layer circuit powered by a second power supply may be configured to transmit or receive display-related information via a second serial bus in accordance with a clock signal transmitted via the second serial bus. At block 1206 in the illustrated method, a selector circuit may be configured to provide a line synchronization signal to a display panel by selecting a synchronization signal generated by the display driver when the first physical layer circuit is operating in a high-speed mode and a clock signal transmitted via the second serial bus when the first physical layer circuit is operating in a low-power mode.

[0100] In some examples, the display driver is configured to generate a synchronization signal using a synchronization event indicator transmitted in a data packet. The second physical layer circuit may be configured to provide a clock signal at a frequency defined by a display panel specification when the first physical layer circuit is operating in a low-power mode.

[0101] In some implementations, the first power supply supplies power at a voltage higher than a voltage at which the second power supply supplies power in a high-speed mode. When the first physical layer circuit is operating in a low-power mode, the voltage at which the first power supply supplies power may be reduced. The first physical layer circuit may be configured to enter a sleep mode when the first physical layer circuit is operating in a low-power mode.

[0102] In some implementations, a touch panel interface coupled to the display panel is configured to contribute to display-related information transmitted via the second serial bus. The first physical layer circuit may be configured to exit the low-power mode when the touch panel interface generates a message.

[0103] In some examples, the selector circuit is configured to provide a line synchronization signal to the display panel by selecting a synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

[0104] In some implementations, the first physical layer circuit may be configured to operate in accordance with the MIPI Alliance DSI protocol. The second physical layer circuit may be configured to operate in accordance with the SPI protocol, CCI protocol, I2C protocol, I3C protocol, or SPMI protocol.

[0105] Figure 13FIG. 0 is a diagram illustrating a first example of a hardware implementation of apparatus 1300 employing processing circuitry 1302. The processing circuitry generally includes one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines, and is generally represented by processor 1316. The processing circuitry 1302 may be implemented with a bus architecture, which is generally represented by bus 1320. Depending on the particular application of the processing circuitry 1302 and overall design constraints, bus 1320 may include any number of interconnect buses and bridges. Bus 1320 links together various circuits including a plurality of processors 1316, modules or circuits 1304, 1306, and 1308, and processor-readable storage medium 1318. Bus interface circuitry and / or module 1314 may be provided to support communication on a plurality of serial data links 1312. Bus 1320 may also link various other circuits, such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein.

[0106] Processor 1316 may be responsible for general processing, which includes executing software, code, and / or instructions stored on processor-readable storage medium 1318. Processor-readable storage medium 1318 may include non-transitory storage medium. The software, when executed by processor 1316, causes the processing circuitry 1302 to perform the various functions described above for any particular apparatus. The processor-readable storage medium may be used to store data manipulated by processor 1316 when executing the software. The processing circuitry 1302 also includes at least one of modules 1304, 1306, and 1308. Modules 1304, 1306, and 1308 may be software modules that run in processor 1316, reside / stored in processor-readable storage medium 1318, one or more hardware modules coupled to processor 1316, or some combination thereof. Modules 1304, 1306, and 1308 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0107] In one configuration, apparatus 1300 includes module and / or circuit 1304 adapted to generate a line synchronization signal using a synchronization event indicator transmitted in a packet of data. Apparatus 1300 may include module and / or circuit 1306 adapted to cause a selector circuit to select between different potential sources of the line synchronization signal. Apparatus 1300 may include module and / or circuit 1308 adapted to manage transitions between operating modes, including a high-speed mode and a low-power mode.

[0108] The apparatus 1300 may include components for communicating with a display driver, the components including a first physical layer circuit powered by a first power supply, the first physical layer circuit being configured to convey packets of data to the display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and being further configured to inhibit conveyance via the first serial bus when the first physical layer circuit operates in a low-power mode; components for communicating with a touch panel interface, the components including a second physical layer circuit powered by a second power supply, the second physical layer circuit being configured to transmit or receive display-related information via the second serial bus in accordance with a clock signal transmitted via the second serial bus; and components for selecting between a synchronization signal generated by the display driver and the clock signal transmitted via the second serial bus to provide a line synchronization signal to a display panel. When the first physical layer circuit operates in the high-speed mode, the synchronization signal generated by the display driver may be selected, and when the first physical layer circuit operates in the low-power mode, the clock signal transmitted via the second serial bus is selected.

[0109] In some specific implementations, the display driver is configured to generate a synchronization signal using a synchronization event indicator transmitted in a packet of data. The second physical layer circuit may be further configured to provide a clock signal at a frequency defined by a display panel specification when the first physical layer circuit operates in the low-power mode.

[0110] In some examples, the first physical layer circuit is configured to exit the low-power mode when the touch panel interface generates a message. The components for selection may be configured to provide a line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

[0111] In one aspect, the apparatus 1300 is configured to operate as a mobile communication device having a display driver coupled to a display panel; the first physical layer circuit is powered by a first power supply and is configured to: convey packets of data to the display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and inhibit conveyance via the first serial bus when the first physical layer circuit operates in the low-power mode. The apparatus 1300 has a second physical layer circuit, the second physical layer circuit being powered by a second power supply and being configured to transmit or receive display-related information via the second serial bus in accordance with a clock signal transmitted via the second serial bus; and a selector circuit, the selector circuit being configured to provide a line synchronization signal to the display panel by selecting: the synchronization signal generated by the display driver when the first physical layer circuit operates in the high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low-power mode.

[0112] In some specific implementations, the display driver is configured to generate a synchronization signal using a synchronization event indicator sent in a packet of data. The second physical layer circuit may be configured to provide a clock signal at a frequency defined by the display panel specification when the first physical layer circuit is operating in a low power mode.

[0113] In certain specific implementations, the first power supply supplies power at a voltage higher than the voltage at which the second power supply supplies power in a high speed mode. When the first physical layer circuit is operating in a low power mode, the voltage at which the first power supply supplies power may be reduced. The first physical layer circuit may be further configured to enter a sleep mode when the first physical layer circuit is operating in a low power mode.

[0114] In certain specific implementations, the apparatus 1300 has a touch panel interface that is coupled to the display panel and is configured to contribute to display-related information sent via a second serial bus. The first physical layer circuit may be configured to exit the low power mode when the touch panel interface generates a message. The selector circuit may be further configured to provide a line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high speed data transmission is received from the first serial bus.

[0115] The first physical layer circuit may be further configured to operate according to the MIPI Alliance DSI protocol. The second physical layer circuit may be further configured to operate according to the SPI protocol, CCI protocol, I2C protocol, I3C protocol, or SPMI protocol.

[0116] The processor-readable storage medium 1318 may include instructions that cause the processing circuit 1302 to configure the first physical layer circuit powered by the first power supply to: convey packets of data to the display driver via the first serial bus at a first data rate when the first physical layer circuit is operating in a high speed mode, and inhibit conveyance via the first serial bus when the first physical layer circuit is operating in a low power mode; configure the second physical layer circuit powered by the second power supply to send or receive display-related information via the second serial bus according to a clock signal sent via the second serial bus; and configure the selector circuit to provide a line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when the first physical layer circuit is operating in a high speed mode and the clock signal sent via the second serial bus when the first physical layer circuit is operating in the low power mode. The display driver may be configured to generate a synchronization signal using a synchronization event indicator sent in a packet of data.

[0117] The processor-readable storage medium 1318 maintains instructions that cause the processing circuitry 1302 to configure the second physical layer circuitry to provide a clock signal at a frequency defined by the display panel specification when the first physical layer circuitry operates in a low-power mode.

[0118] The processor-readable storage medium 1318 may include instructions that cause the processing circuitry 1302 to configure the first physical layer circuitry to exit the low-power mode when the touch panel interface generates a message. The processor-readable storage medium 1318 may include instructions that cause the processing circuitry 1302 to configure the selector circuitry to provide a line synchronization signal to the display panel by selecting a synchronization signal generated by the display driver when high-speed data is transmitted from the first serial bus.

[0119] Some specific implementation examples are described in the following numbered clauses:

[0120] 1. A mobile communication device, the mobile communication device comprising: a display driver coupled to a display panel; a first physical layer circuitry powered by a first power supply and configured to: convey packets of data to the display driver at a first data rate via a first serial bus when the first physical layer circuitry operates in a high-speed mode, and inhibit conveyance via the first serial bus when the first physical layer circuitry operates in a low-power mode; a second physical layer circuitry powered by a second power supply and configured to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; and a selector circuitry configured to provide a line synchronization signal to the display panel by selecting: a synchronization signal generated by the display driver when the first physical layer circuitry operates in a high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuitry operates in the low-power mode.

[0121] 2. The mobile communication device according to clause 1, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the packets of data.

[0122] 3. The mobile communication device according to clause 1 or clause 2, wherein the second physical layer circuitry is configured to provide the clock signal at a frequency defined by the display panel specification when the first physical layer circuitry operates in the low-power mode.

[0123] 4. The mobile communication device according to any one of clauses 1 to 3, wherein the first power supply supplies power at a voltage higher than the voltage at which the second power supply supplies power in the high-speed mode, and wherein when the first physical layer circuit operates in the low-power mode, the voltage at which the first power supply supplies power decreases.

[0124] 5. The mobile communication device according to any one of clauses 1 to 4, wherein the first physical layer circuit is further configured to enter a sleep mode when the first physical layer circuit operates in the low-power mode.

[0125] 6. The mobile communication device according to any one of clauses 1 to 5, the mobile communication device further comprising: a touch panel interface, the touch panel interface being coupled to the display panel and configured to contribute to the display-related information transmitted through the second serial bus.

[0126] 7. The mobile communication device according to clause 6, wherein the first physical layer circuit is configured to exit the low-power mode when the touch panel interface generates a message.

[0127] 8. The mobile communication device according to any one of clauses 1 to 7, wherein the selector circuit is further configured to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

[0128] 9. The mobile communication device according to any one of clauses 1 to 8, wherein the first physical layer circuit is further configured to operate according to the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

[0129] 10. The mobile communication device according to any one of clauses 1 to 9, wherein the second physical layer circuit is further configured to operate according to the Serial Peripheral Interface (SPI) protocol, the Camera Control Interface (CCI) protocol, the Inter-Integrated Circuit (I2C) protocol, the Improved Inter-Integrated Circuit (I3C) protocol, or the System Power Management Interface (SPMI) protocol.

[0130] 11. A method for operating a display in a mobile communication device, the method comprising: configuring a first physical layer circuit powered by a first power supply to communicate data packets to a display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and suppressing communication via the first serial bus when the first physical layer circuit operates in a low-power mode; configuring a second physical layer circuit powered by a second power supply to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; and configuring a selector circuit to provide a line synchronization signal to a display panel by selecting a synchronization signal generated by the display driver when the first physical layer circuit operates in the high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low-power mode.

[0131] 12. The method according to clause 11, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the data packets.

[0132] 13. The method according to clause 11 or clause 12, the method further comprising: configuring the second physical layer circuit to provide the clock signal at a frequency defined by a display panel specification when the first physical layer circuit operates in the low-power mode.

[0133] 14. The method according to any one of clauses 11 to 13, wherein the first power supply provides power at a voltage higher than a voltage at which the second power supply provides power in the high-speed mode, and wherein when the first physical layer circuit operates in the low-power mode, the voltage at which the first power supply provides power decreases.

[0134] 15. The method according to any one of clauses 11 to 13, the method further comprising: configuring the first physical layer circuit to enter a sleep mode when the first physical layer circuit operates in the low-power mode.

[0135] 16. The method according to any one of clauses 11 to 13, wherein a touch panel interface coupled to the display panel is configured to contribute to the display-related information transmitted via the second serial bus.

[0136] 17. The method according to clause 16, the method further comprising: configuring the first physical layer circuit to exit the low-power mode when the touch panel interface generates a message.

[0137] 18. The method according to any one of clauses 11 to 17, the method further comprising: configuring the selector circuit to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when receiving high-speed data transmission from the first serial bus.

[0138] 19. The method according to any one of clauses 11 to 18, wherein the first physical layer circuit is further configured to operate according to the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

[0139] 20. The method according to any one of clauses 11 to 19, wherein the second physical layer circuit is further configured to operate according to a Serial Peripheral Interface (SPI) protocol, a Camera Control Interface (CCI) protocol, an Inter-Integrated Circuit (I2C) protocol, an Improved Inter-Integrated Circuit (I3C) protocol, or a System Power Management Interface (SPMI) protocol.

[0140] 21. An apparatus, the apparatus comprising: means for communicating with a display driver, the means including a first physical layer circuit powered by a first power supply, the first physical layer circuit being configured to convey packets of data to the display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and being further configured to inhibit conveyance via the first serial bus when the first physical layer circuit operates in a low-power mode; means for communicating with a touch panel interface, the means including a second physical layer circuit powered by a second power supply, the second physical layer circuit being configured to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; and means for selecting between a synchronization signal generated by the display driver and the clock signal transmitted via the second serial bus to provide a line synchronization signal to the display panel, wherein the synchronization signal generated by the display driver is selected when the first physical layer circuit operates in the high-speed mode, and the clock signal transmitted via the second serial bus is selected when the first physical layer circuit operates in the low-power mode.

[0141] 22. The apparatus according to clause 21, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the packets of data.

[0142] 23. The apparatus according to clause 21 or clause 22, wherein the second physical layer circuit is further configured to provide the clock signal at a frequency defined by a display panel specification when the first physical layer circuit operates in the low-power mode.

[0143] 24. The apparatus according to any one of clauses 21 to 23, wherein the first physical layer circuit is configured to exit the low power mode when the touch panel interface generates a message.

[0144] 25. The apparatus according to any one of clauses 21 to 24, wherein the component for selection is configured to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

[0145] 26. A processor-readable storage medium including code for the following operations: configuring a first physical layer circuit powered by a first power supply to communicate data packets to a display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and suppressing communication via the first serial bus when the first physical layer circuit operates in a low power mode; configuring a second physical layer circuit powered by a second power supply to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; and configuring a selector circuit to provide a line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when the first physical layer circuit operates in the high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low power mode.

[0146] 27. The storage medium according to clause 25, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the data packet.

[0147] 28. The storage medium according to clause 25 or clause 26, further including code for the following operation: configuring the second physical layer circuit to provide the clock signal at a frequency defined by a display panel specification when the first physical layer circuit operates in the low power mode.

[0148] 29. The storage medium according to any one of clauses 26 to 28, further including code for the following operation: configuring the first physical layer circuit to exit the low power mode when the touch panel interface generates a message.

[0149] 30. The storage medium according to any one of clauses 26 to 29, further including code for the following operation: configuring the selector circuit to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

[0150] It should be understood that the specific order or hierarchy of steps in the disclosed process is an illustration of the exemplary method. It should be understood that, according to design preferences, the specific order or hierarchy of steps in these processes can be rearranged. Additionally, some steps can be combined or omitted. The appended method claims present the elements of the various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0151] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, where the elements recited in the singular are not intended to mean "one and only one" unless specifically so stated, but rather "one or more". Unless specifically stated otherwise, the term "some" refers to one or more. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or later will be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public, whether or not such disclosure is explicitly recited in the claims. No claim element can be construed as a means-plus-function unless the element is expressly recited using the phrase "means for".

Claims

1. A mobile communication device, the mobile communication device comprising: A display driver, the display driver being coupled to a display panel; A first physical layer circuit, the first physical layer circuit being powered by a first power supply and configured to: When the first physical layer circuit operates in a high-speed mode, convey packets of data to the display driver at a first data rate via a first serial bus, and When the first physical layer circuit operates in a low-power mode, inhibit conveyance via the first serial bus; A second physical layer circuit, the second physical layer circuit being powered by a second power supply and configured to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; And A selector circuit, the selector circuit being configured to provide a line synchronization signal to the display panel by selecting: A synchronization signal generated by the display driver when the first physical layer circuit operates in a high-speed mode, and The clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low-power mode.

2. The mobile communication device according to claim 1, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the packets of data.

3. The mobile communication device according to claim 1, wherein the second physical layer circuit is configured to provide the clock signal at a frequency defined by a display panel specification when the first physical layer circuit operates in the low-power mode.

4. The mobile communication device according to claim 1, wherein the first power supply supplies power at a voltage higher than a voltage at which the second power supply supplies power in the high-speed mode, and wherein when the first physical layer circuit operates in the low-power mode, the voltage at which the first power supply supplies power decreases.

5. The mobile communication device according to claim 1, wherein the first physical layer circuit is further configured to enter a sleep mode when the first physical layer circuit operates in the low-power mode.

6. The mobile communication device according to claim 1, the mobile communication device further comprising: A touch panel interface, the touch panel interface being coupled to the display panel and configured to contribute to the display-related information transmitted via the second serial bus.

7. The mobile communication device according to claim 6, wherein the first physical layer circuit is configured to exit the low-power mode when the touch panel interface generates a message.

8. The mobile communication device according to claim 1, wherein the selector circuit is further configured to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

9. The mobile communication device according to claim 1, wherein the first physical layer circuit is further configured to operate according to the Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

10. The mobile communication device according to claim 1, wherein the second physical layer circuit is further configured to operate according to a Serial Peripheral Interface (SPI) protocol, a Camera Control Interface (CCI) protocol, an Inter-Integrated Circuit (I2C) protocol, an Improved Inter-Integrated Circuit (I3C) protocol, or a System Power Management Interface (SPMI) protocol.

11. A method for operating a display in a mobile communication device, the method comprising: Configuring a first physical layer circuit powered by a first power supply to: When the first physical layer circuit operates in a high-speed mode, convey a packet of data to a display driver at a first data rate via a first serial bus, and When the first physical layer circuit operates in a low-power mode, inhibit conveyance via the first serial bus; Configuring a second physical layer circuit powered by a second power supply to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; And Configuring a selector circuit to provide a line synchronization signal to a display panel by selecting a synchronization signal generated by the display driver when the first physical layer circuit operates in a high-speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low-power mode.

12. The method according to claim 11, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the packet of data.

13. The method according to claim 11, the method further comprising: Configuring the second physical layer circuit to provide the clock signal at a frequency defined by a display panel specification when the first physical layer circuit operates in the low-power mode.

14. The method according to claim 11, wherein the first power supply supplies power at a voltage higher than a voltage at which the second power supply supplies power in the high-speed mode, and wherein when the first physical layer circuit operates in the low-power mode, the voltage at which the first power supply supplies power decreases.

15. The method according to claim 11, the method further comprising: Configuring the first physical layer circuit to enter a sleep mode when the first physical layer circuit operates in the low-power mode.

16. The method according to claim 11, wherein a touch panel interface coupled to the display panel is configured to contribute to the display-related information transmitted via the second serial bus.

17. The method according to claim 16, the method further comprising: Configuring the first physical layer circuit to exit the low-power mode when the touch panel interface generates a message.

18. The method according to claim 11, the method further comprising: Configuring the selector circuit to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

19. The method according to claim 11, wherein the first physical layer circuit is further configured to operate according to a Mobile Industry Processor Interface (MIPI) Alliance Display Serial Interface (DSI) protocol.

20. The method according to claim 11, wherein the second physical layer circuit is further configured to operate according to a Serial Peripheral Interface (SPI) protocol, a Camera Control Interface (CCI) protocol, an Inter-Integrated Circuit (I2C) protocol, an Improved Inter-Integrated Circuit (I3C) protocol, or a System Power Management Interface (SPMI) protocol.

21. An apparatus, the apparatus comprising: means for communicating with a display driver, the means including a first physical layer circuit powered by a first power supply, the first physical layer circuit being configured to convey data packets to the display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and being further configured to inhibit conveyance via the first serial bus when the first physical layer circuit operates in a low-power mode; means for communicating with a touch panel interface, the means including a second physical layer circuit powered by a second power supply, the second physical layer circuit being configured to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; and means for selecting between a synchronization signal generated by the display driver and the clock signal transmitted via the second serial bus to provide a line synchronization signal to a display panel, wherein the synchronization signal generated by the display driver is selected when the first physical layer circuit operates in the high-speed mode, and the clock signal transmitted via the second serial bus is selected when the first physical layer circuit operates in the low-power mode.

22. The apparatus according to claim 21, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the data packets.

23. The apparatus according to claim 21, wherein the second physical layer circuit is further configured to provide the clock signal at a frequency defined by a display panel specification when the first physical layer circuit operates in the low-power mode.

24. The apparatus according to claim 21, wherein the first physical layer circuit is configured to exit the low-power mode when the touch panel interface generates a message.

25. The apparatus according to claim 21, wherein the means for selecting is configured to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high-speed data transmission is received from the first serial bus.

26. A processor-readable storage medium, the processor-readable storage medium including code for: configuring a first physical layer circuit powered by a first power supply to: convey data packets to a display driver at a first data rate via a first serial bus when the first physical layer circuit operates in a high-speed mode, and When the first physical layer circuit operates in the low power mode, communication via the first serial bus is inhibited; Configure a second physical layer circuit powered by a second power supply to transmit or receive display-related information via the second serial bus according to a clock signal transmitted via the second serial bus; and Configure a selector circuit to provide a line synchronization signal to the display panel by selecting a synchronization signal generated by the display driver when the first physical layer circuit operates in the high speed mode and the clock signal transmitted via the second serial bus when the first physical layer circuit operates in the low power mode.

27. The processor-readable storage medium according to claim 26, wherein the display driver is configured to generate the synchronization signal using a synchronization event indicator transmitted in the packet of data.

28. The processor-readable storage medium according to claim 26, the processor-readable storage medium further comprising code for the following operation: Configure the second physical layer circuit to provide the clock signal at a frequency defined by the display panel specification when the first physical layer circuit operates in the low power mode.

29. The processor-readable storage medium according to claim 26, the processor-readable storage medium further comprising code for the following operation: Configure the first physical layer circuit to exit the low power mode when a touch panel interface generates a message.

30. The processor-readable storage medium according to claim 26, the processor-readable storage medium further comprising code for the following operation: Configure the selector circuit to provide the line synchronization signal to the display panel by selecting the synchronization signal generated by the display driver when high speed data transmission is received from the first serial bus.

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