Preparation method of MX2 / MX2 heterojunction with regulated gate voltage
Through the combination of mechanical peeling method, heat release dry transfer and vacuum annealing, high-quality MX2 heterojunctions were prepared, which solved the limitations of the preparation method in the prior art, realized the valley polarization regulation of MX2 heterojunctions at room temperature, and promoted the development of valley electronic devices.
Patent Information
- Application Number
- CN202510480328.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-17
- Publication Date
- 2025-08-01
AI Technical Summary
In the prior art, the preparation method of MX2 heterojunction has problems such as difficult to accurately control the number of material layers, uneven interface quality and possible introduction of impurities, and there is a lack of effective gate voltage regulation methods to achieve room temperature valley polarization.
The MX2/MX2 heterojunction was prepared by mechanical peeling method combined with heat release dry transfer and vacuum annealing method, and the room temperature valley polarization of the heterojunction was achieved by applying gate pressure regulation. The specific steps include cleaning the silicon wafer substrate, surface treatment of block crystals, peeling two-dimensional materials with tape, heat release transfer and vacuum annealing treatment.
The high-quality MX2 heterojunction was successfully prepared, which achieved effective regulation of valley polarization at room temperature, and provided a new structural platform for high-performance valley electronic devices.
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Abstract
Description
Technical Field
[0001] The present invention belongs to the field of preparation and property regulation of two-dimensional materials. Specifically, it relates to a preparation method of a gate voltage-regulated MX2 / MX2 heterojunction. Background Art
[0002] Since the successful exfoliation of graphene, the field of two-dimensional materials has attracted extensive attention. Two-dimensional transition metal dichalcogenides (TMDs) are a type of graphene-like two-dimensional layered material that has been widely concerned in recent years. Their chemical formula is generally expressed as MX2, where M represents transition metal elements such as Mo, W, Re, etc., and X represents chalcogen elements such as S, Se, Te, etc. TMDs have a unique layered crystal structure. Each layer consists of transition metal atoms M and chalcogen atoms X connected by covalent bonds to form a hexagonal two-dimensional plane. The layers are interacted by relatively weak van der Waals forces. This structure endows them with different properties from bulk materials, thus exhibiting excellent electrical, optical, and quantum properties. Through in-depth research on two-dimensional TMDs, quantum physical phenomena in low-dimensional material systems can be further revealed, and new electronics and optoelectronics applications can be explored.
[0003] Two-dimensional TMDs have valleys near the K point in the Brillouin zone similar to graphene. Due to the broken spatial inversion symmetry and time-reversal symmetry in odd-layer TMDs, there are two inequivalent types of valleys, K and K' valleys. Due to spin-orbit splitting, the valley spins split in the K and K' valleys are opposite. Thus, a special optical selection rule appears in monolayer TMDs, enabling the manipulation of valley degrees of freedom. When excited by circularly polarized light, left-handed (SCP) and right-handed (OCP) polarized light can selectively inject carriers into the K valley and K' valley, respectively. This valley-dependent light absorption property provides a physical basis for valley degree-of-freedom regulation. Therefore, the valley polarization of monolayer MX2 can be manipulated by chiral circularly polarized light, making it an ideal carrier for studying valleytronics. Among various methods for regulating the valley polarization of two-dimensional TMDs, electrical regulation has become the focus of researchers' attention due to its advantages such as simple operation, fast response speed, and integrability. By applying gate voltage regulation, the electronic structure of the material can be effectively changed. On the one hand, the vertical electric field can induce changes in the band structure, causing a shift in the energy difference between the K / K' valleys. On the other hand, the in-plane electric field can enhance the asymmetry of inter-valley scattering. Secondly, by constructing an MX2 heterojunction, the charge transfer at the interface can lead to a significant shortening of the exciton lifetime in a semiconductor material with a higher conduction band position, and reducing the exciton lifetime of MX2 will be beneficial to improving the valley polarization degree. Therefore, by combining gate voltage regulation and constructing a heterojunction, the room-temperature valley polarization of MX2 can be effectively regulated, providing a new structural platform for realizing high-performance valleytronic devices.
[0004] In the reported studies, the preparation methods of MX2 heterojunctions usually include chemical vapor deposition, mechanical exfoliation, etc. However, these methods often have some limitations that are difficult to overcome. For example, it is difficult to precisely control the number of layers of materials during the chemical vapor deposition growth process, the interface quality is uneven, and impurities may be introduced during the preparation process of the mechanical exfoliation method. In addition, for the research on regulating the room-temperature valley polarization of MX2 heterojunctions through gate voltage, there is currently no perfect and unique preparation method. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a preparation method for a gate voltage-regulated MX2 / MX2 heterojunction to achieve room-temperature valley polarization of the heterojunction.
[0006] To solve the above technical problems, the technical solution adopted by the present invention is as follows: A preparation method for a gate voltage-regulated MX2 / MX2 heterojunction includes the following steps: Step 1, clean the silicon wafer substrate to remove impurities on the silicon wafer substrate; Step 2, select two types of MX2 bulk crystals and natural graphite bulk crystals, and perform surface cleaning treatment on the above bulk crystals to remove impurities, oxides, and adsorbed substances on the surface of the bulk crystals; Step 3, obtain two-dimensional materials by mechanical exfoliation: repeatedly bond and peel the surfaces of MX2 bulk crystals and natural graphite bulk crystals with tape, and a thin layer of MX2 and a thin layer of graphite are adhered to the tape; then attach PDMS to the thin-layer sample on the tape and peel off the thin-layer sample to obtain PDMS with a thin layer of MX2 and a thin layer of graphite; Step 4, utilize the thermal release property of PDMS to transfer the first thin layer of MX2 to the upper surface of the silicon wafer substrate in sequence, transfer the second thin layer of MX2 to the upper surface of the first thin layer of MX2 to build an MX2 / MX2 heterojunction, and finally transfer the thin layer of graphite to the edge of the MX2 / MX2 heterojunction; Step 5, perform annealing treatment; Step 6, drop silver glue onto the thin layer of graphite and connect a copper wire to cure it, and drop silver glue at the bottom of the silicon wafer substrate to connect the copper wire and cure it.
[0007] As a preferred embodiment, in Step 1, ultrasonically clean the silicon wafer substrate, use acetone, absolute ethanol, and high-purity water as cleaning agents in sequence, and blow dry with a nitrogen gun after cleaning.
[0008] As a preferred embodiment, in Step 2, the MX2 bulk crystals are selected from any two of WS2, ReS2, and MoS2.
[0009] As a preferred embodiment, in step two, the bulk crystal is cleaned by ultrasonic waves. The bulk crystal is immersed in an absolute ethanol solution, with the vibration frequency set at 80 kHz and the cleaning time at 30 min. Then it is repeatedly rinsed with deionized water and finally dried with a nitrogen gun.
[0010] As a preferred embodiment, in step three, tape is pasted on the surface of the cleaned bulk crystal. After standing for 5 minutes, the tape is torn off. By bonding and tearing two tapes to each other, the number of layers of the bulk crystal is reduced.
[0011] As a preferred embodiment, in step three, the PDMS with a thin layer of MX2 and a thin layer of graphite is placed under an optical microscope to observe the thin layer samples on the PDMS, and the thin layer of MX2 and the thin layer of graphite with the ideal number of layers are selected.
[0012] As a preferred embodiment, in step four, the PDMS film with the first thin layer of MX2 is pasted on a transparent glass slide, and then the transparent glass slide is placed upside down on the transfer rack of the transfer platform. The cleaned silicon wafer substrate is placed on the lower transfer rack of the transfer platform. The MX2 target compound on the PDMS film is located using a microscope. Finally, the PDMS film with the first thin layer of MX2 on the upper transfer rack is lowered onto the silicon wafer substrate on the lower transfer rack and bonded by using the displacement screw rod in the vertical direction. After heating to 80 °C for 15 - 30 min, the upper transfer rack is lifted. At this time, the first thin layer of MX2 is separated from the PDMS and bonded to the silicon wafer substrate. Using the same transfer process, the second thin layer of MX2 is transferred onto the first thin layer of MX2, and the thin layer of graphite is transferred to the edge of the heterojunction.
[0013] As a preferred embodiment, in step five, during the annealing treatment, the vacuum degree of the vacuum annealing tube furnace is 10 -5 Pa, and it is kept warm for 50 - 70 minutes under the condition of a temperature of 180 - 220 °C.
[0014] As a preferred embodiment, it is kept warm for 60 minutes under the condition of a temperature of 200 °C.
[0015] As a preferred embodiment, the heating rate is 20 °C / min.
[0016] The present invention combines the methods of mechanical exfoliation, thermal release dry transfer, and vacuum annealing. First, the mechanically exfoliated MX2 sample is sequentially transferred onto a silicon wafer substrate, transferred onto a heterojunction using thin-layer graphite as an electrode, then the silicon wafer substrate with the sample is annealed in a vacuum annealing tube furnace or the silicon wafer substrate is directly blown clean. Finally, silver paste is dropped onto the graphite using a micromanipulation robotic arm and connected to a copper wire for curing, and silver paste is also dropped at the bottom of the silicon wafer to connect the copper wire and cure, successfully obtaining an MX2 heterojunction and realizing the sample preparation with gate voltage regulation. By applying a gate voltage to the MX2 heterojunction sample, carriers are injected into the heterojunction, making the carrier distribution in the K / K' valleys in the heterojunction uneven, resulting in a larger valley momentum difference and achieving valley polarization. Description of the Drawings
[0017] Figure 1 It is the device schematic diagram of the MX2 (WS2 / ReS2) heterojunction regulated by gate voltage prepared in Example 1 of the present invention; in the figure, 1 - silicon wafer substrate, 2 - WS2, 3 - ReS2, 4 - graphite, 5 - silver paste, 6 - copper wire; Figure 2 It is the fluorescence picture of the MX2 (WS2 / ReS2) heterojunction after annealing after dry transfer prepared in Example 1 of the present invention; Figure 3 It is the optical microscope photo of the sample on the silicon wafer substrate after dropping silver paste and connecting copper wire prepared in Example 1 of the present invention; Figure 4 It is the Raman spectrum test picture of the MX2 (WS2 / ReS2) heterojunction prepared in Example 1 of the present invention; Figure 5 It is the fluorescence spectrum test picture of the MX2 (WS2 / ReS2) heterojunction prepared in Example 1 of the present invention; Figure 6 It is the fluorescence spectrum test picture of the MX2 (WS2 / ReS2) heterojunction regulated by gate voltage prepared in Example 1 of the present invention under different positive gate voltages; Figure 7 It is the fluorescence spectrum test picture of the MX2 (WS2 / ReS2) heterojunction regulated by gate voltage prepared in Example 1 of the present invention under different negative gate voltages; Figure 8 It is the transient absorption spectra of SCP and OCP at different delay times of the MX2 (WS2 / ReS2) heterojunction regulated by gate voltage prepared in Example 1 of the present invention without applying a gate voltage; Figure 9 It is the transient absorption spectra of SCP and OCP at different delay times of the MX2 (WS2 / ReS2) heterojunction regulated by gate voltage prepared in Example 1 of the present invention under a 20V gate voltage; Figure 10It is a picture of the valley polarization lifetime of the MX2 (WS2 / ReS2) heterojunction regulated by gate voltage prepared in Comparative Example 1 of the present invention without applying a gate voltage; Figure 11 It is a picture of the valley polarization lifetime of the MX2 (WS2 / ReS2) heterojunction regulated by gate voltage prepared in Example 1 of the present invention under the application of a 20V gate voltage; Figure 12 It is a fluorescence picture of the MX2 (WS2 / ReS2) heterojunction without annealing after dry transfer prepared in Example 2 of the present invention. Detailed implementation manners
[0018] The basic concept of the present invention is to combine the methods of mechanical exfoliation, thermal release dry transfer and vacuum annealing to prepare a MX2 / MX2 two-dimensional van der Waals heterojunction. By combining gate voltage regulation and heterojunction construction, the room-temperature valley polarization of MX2 can be effectively regulated, which provides a new structural platform for realizing high-performance valley electronic devices.
[0019] A preparation method of a gate voltage-regulated MX2 / MX2 heterojunction provided by a typical embodiment of the present invention includes the following steps 1 to 6.
[0020] Step 1, substrate cleaning.
[0021] The silicon wafer substrate is cleaned multiple times to remove impurities on the silicon wafer substrate.
[0022] Specifically, a beaker is placed in an ultrasonic cleaner, and the cut silicon wafer substrate is laid flat in the beaker. The size of the silicon wafer substrate is 1.5 cm in length and 0.7 cm in width. A cleaning agent is added to the beaker, and the cleaning is carried out in the order of acetone → absolute ethanol → high-purity water. The cleaning time for each time is set to 10 min, and finally the cleaned substrate is dried with a nitrogen gun.
[0023] Step 2, pretreatment of bulk samples.
[0024] Two types of MX2 bulk crystals and natural graphite bulk crystals are selected, and the above bulk crystals are subjected to surface cleaning treatment to remove impurities, oxides and adsorbed substances on the surface of the bulk crystals. Ensure that the crystal surface is flat and has good chemical activity, laying a foundation for subsequent exfoliation operations.
[0025] The two different MX2 bulk crystals are selected from any two of WS2, ReS2, and MoS2, for example: WS2 / ReS2, MoS2 / ReS2, MoS2 / WS2. MX2 bulk crystal samples with a purity of more than 99.9% are selected.
[0026] The bulk MX2 crystals and bulk natural graphite crystals were respectively immersed in an absolute ethanol solution and placed in an ultrasonic cleaner with a vibration frequency of 80 kHz for 30 min of ultrasonic treatment. Subsequently, they were repeatedly rinsed with deionized water and finally dried with a nitrogen gun.
[0027] Step three, mechanical exfoliation of two-dimensional materials.
[0028] The two-dimensional materials were obtained by mechanical exfoliation: the surfaces of the bulk MX2 crystals and bulk natural graphite crystals were repeatedly adhered and peeled off with tape. A thin layer of MX2 and a thin layer of graphite were adhered to the tape. The thickness of the thin layer of MX2 and the thin layer of graphite was approximately about 2.2 nm, being a bilayer or trilayer structure. Then, PDMS was attached to the thin-layer sample on the tape and the thin-layer sample was peeled off to obtain PDMS with the thin layer of MX2 and the thin layer of graphite.
[0029] More specifically, 3M tape was adhered to the surfaces of the cleaned bulk MX2 crystals and bulk natural graphite crystals. After standing for five minutes, the tape was torn off. Then, two tapes were adhered to each other and torn apart to reduce the number of layers of the bulk crystal material. Next, a PDMS film was torn open with a pair of sharp tweezers and attached to the tape with the sample for 15 min. The PDMS was removed, and the side with the sample was placed under an optical microscope for observation to select thin-layer MX2 and thin-layer graphite samples with the desired number of layers.
[0030] Step four, construction of heterojunctions.
[0031] Utilizing the thermal release property of PDMS, the first type of thin-layer MX2 was successively transferred to the upper surface of the silicon wafer substrate, and the second type of thin-layer MX2 was transferred to the upper surface of the first type of thin-layer MX2 to construct an MX2 / MX2 heterojunction. Finally, the thin-layer graphite was transferred to the edge of the MX2 / MX2 heterojunction.
[0032] Taking the transfer of the first type of thin-layer MX2 to the silicon wafer substrate as an example. The PDMS film with the first type of thin-layer MX2 was attached to a transparent glass slide, and then the transparent glass slide was placed upside down on the transfer rack of the transfer platform. The cleaned silicon wafer substrate was placed on the lower transfer rack of the transfer platform. The MX2 target compound on the PDMS film was located with a microscope. Finally, the PDMS film with the first type of thin-layer MX2 on the upper transfer rack was lowered onto the silicon wafer substrate on the lower transfer rack and attached by using the displacement screw rod in the vertical direction. After heating to 80 °C for 15 - 30 min, the upper transfer rack was lifted. At this time, the first type of thin-layer MX2 was separated from the PDMS and attached to the silicon wafer substrate.
[0033] The methods for transferring the second type of thin-layer MX2 to the first type of thin-layer MX2 and for transferring the thin-layer graphite to the edge of the heterojunction are the same as the above process and will not be elaborated further.
[0034] Step five, annealing treatment.
[0035] Put the sample with heterojunction into a vacuum annealing tube furnace. During the annealing process, the vacuum degree of the vacuum annealing tube furnace is 10 -5 Pa, and keep it at a temperature of 180 - 220 °C for 50 - 70 minutes.
[0036] Preferably, the above annealing process is carried out under a vacuum degree of 10 -5 Pa, with a heating rate of 20 °C / min to 200 °C, and keep it for 60 minutes.
[0037] Step six, drop silver paste and connect copper wires.
[0038] Drop silver paste onto the thin-layer graphite and connect copper wires to cure. Drop silver paste at the bottom of the silicon wafer substrate to connect copper wires and cure.
[0039] More specifically, place the annealed heterojunction sample under an optical microscope and fix it with tape. Locate the position of the sample, take a small amount of silver paste with a tungsten needle, and then apply the silver paste on the thin-layer graphite through a micromanipulation robotic arm. Then connect a copper wire with a diameter of 3 mm and a length of 5 cm to the silver paste and let it stand for 30 min to cure. Repeat the above operation to drop silver paste at the bottom of the silicon wafer substrate to connect copper wires and cure.
[0040] The following further illustrates the technical solutions claimed in the present invention through some embodiments. However, the embodiments are used to explain the implementation solutions of the present invention and do not exceed the scope of the present invention's theme. The protection scope of the present invention is not limited by the described embodiments. Unless otherwise specified, the materials and reagents used in the present invention can be obtained from commercial products in the art. Example 1
[0041] (1) Substrate cleaning: Place a beaker in an ultrasonic cleaner, lay the cut silicon wafers flat in the beaker. The size of the silicon wafers is 1.5 cm in length and 0.7 cm in width. Then add a cleaning agent to the beaker. The cleaning agent is used to clean in the order of acetone → absolute ethanol → high-purity water, and the cleaning time for each time is set to 10 min. Finally, blow dry the cleaned substrate with a nitrogen gun.
[0042] (2) Select WS2, ReS2 bulk crystals and natural graphite bulk crystals.
[0043] Immerse the above bulk crystals in an absolute ethanol solution and put them into an ultrasonic cleaner with a set vibration frequency of 80 kHz for cleaning for 30 min. Then rinse repeatedly with deionized water, and finally blow dry the cleaned crystals with a nitrogen gun.
[0044] (3) Use 3M tape to stick on the surface of the crystal after cleaning, let it stand for five minutes, then tear off the tape. Then, fold two tapes in half with each other to reduce the number of layers of graphite, two-dimensional WS2, and ReS2. Next, use a pair of sharp tweezers to tear the PDMS film and attach it to the tape with the sample for 15 minutes. Remove the PDMS and place the side with the sample under an optical microscope. Observe the WS2 sample using a fluorescence microscope objective lens. Monolayer WS2 will have strong luminescence. Observe ReS2 and graphite under bright field, and select thinner samples.
[0045] (4) Stick the PDMS film with the ReS2 sample on a transparent glass slide, then place the transparent glass slide upside down on the transfer rack of the transfer platform. Place the cleaned silicon wafer on the lower transfer rack of the transfer platform. Use a microscope to find the ReS2 target compound on the PDMS film. Finally, use the displacement screw rod in the vertical direction to lower the PDMS film with the ReS2 sample on the upper transfer rack onto the silicon wafer on the lower transfer rack for bonding. Then heat to 80 °C. After 15 - 30 minutes, carefully and slowly lift the upper transfer rack. At this time, ReS2 on the solution film separates from the PDMS and bonds to the silicon wafer. Repeat the above process to transfer the selected monolayer WS2 onto the ReS2 sample to build a WS2 / ReS2 heterojunction. Finally, transfer the thin-layer graphite to the edge of the heterojunction.
[0046] (5) Place the substrate with the heterojunction sample into a vacuum annealing tube furnace. Under the condition of a vacuum degree of 10 -5 Pa, heat it to 200 °C at a heating rate of 20 °C / min and keep it warm for 60 minutes.
[0047] (6) Place the annealed heterojunction sample substrate under an optical microscope and fix it with tape. Locate the position of the sample. Use a tungsten needle to pick up a small amount of silver paste and then apply the silver paste on the thin-layer graphite through a micromanipulation robotic arm. Then connect a copper wire with a diameter of 3 mm and a length of 5 cm to the silver paste and let it stand for 30 minutes to cure. Repeat the above operation to also drip silver paste and connect copper wires at the bottom of the silicon wafer and cure.
[0048] Through the above experimental steps, on the silicon wafer substrate with the sample after annealing treatment, and by connecting copper wires through an optical microscope, a WS2 / ReS2 heterojunction was successfully obtained and a sample preparation with gate voltage regulation was achieved.
[0049] The device schematic diagram of the WS2 / ReS2 heterojunction prepared in this embodiment is as Figure 1 shown.
[0050] The fluorescence picture of the WS2 / ReS2 heterojunction after annealing after dry transfer prepared in this embodiment is as Figure 2 shown, with a flat surface and weakened luminescence in the heterojunction region.
[0051] The optical picture of the sample on the silicon wafer substrate after dropping silver glue and connecting copper wires prepared in this embodiment is as follows Figure 3 shown
[0052] The Raman spectrum test picture of the WS2 / ReS2 heterojunction prepared in this embodiment is as follows Figure 4 shown, where the vibration peak at 520 cm -1 is the peak value of the silicon wafer. The two vibration peaks of monolayer WS2 are at 360 cm -1 and 420 cm -1 respectively, which is consistent with the Raman spectrum of monolayer WS2 reported previously. The three vibration peaks of ReS2 are at 150 cm -1 , 210 cm -1 and 310 cm -1 respectively, which is consistent with the Raman spectrum of ReS2 reported previously, proving that the coupling between monolayer WS2 and ReS2 is very good
[0053] The fluorescence spectrum test picture of the WS2 / ReS2 heterojunction prepared in this embodiment is as follows Figure 5 shown, where 646 nm is the photoluminescence peak of the heterojunction. In previous reports, the photoluminescence peak of mechanically exfoliated monolayer WS2 is around 620 nm. It can be seen that the characteristic photoluminescence peak of WS2 in the heterojunction after transfer is significantly shifted, indicating that the luminescence performance of monolayer WS2 in the formed heterojunction after building ReS2 has changed significantly
[0054] The fluorescence spectrum test pictures of the WS2 / ReS2 heterojunction prepared in this embodiment by gate voltage regulation at different positive gate voltages are as follows Figure 6 shown. It can be observed that as the positive gate voltage increases from 0 V to +20 V, the photoluminescence peak in the heterojunction region moves from 646 nm to around 648 nm, and the photoluminescence intensity of the heterojunction also changes with the increase of the gate voltage. It can be seen that the luminescence performance of monolayer WS2 built on ReS2 has been significantly enhanced
[0055] The fluorescence spectrum test pictures of the WS2 / ReS2 heterojunction prepared in this embodiment by gate voltage regulation at different negative gate voltages are as follows Figure 7 shown. It can be observed that as the negative gate voltage increases from 0 V to -20 V, the photoluminescence peak in the heterojunction region moves from 646 nm to around 642 nm, and the photoluminescence intensity of the heterojunction also changes with the increase of the gate voltage. It can be seen that the luminescence performance of monolayer WS2 in the formed heterojunction after building ReS2 has been significantly enhanced
[0056] The transient absorption spectra of SCP and OCP at different delay times without applying gate voltage for the WS2 / ReS2 heterojunction prepared in this embodiment by gate voltage regulation are as follows Figure 8As shown, it can be observed that without applying a gate voltage, the SCP and OCP of the WS2 / ReS2 heterojunction coincide very quickly, and there is almost no valley polarization.
[0057] The transient absorption spectra of the WS2 / ReS2 heterojunction regulated by gate voltage prepared in this embodiment at different delay times under the application of a 20V gate voltage are as Figure 9 shown. It can be observed that when a gate voltage is applied, the SCP and OCP of the WS2 / ReS2 heterojunction approach coincidence only at 1 ps, indicating that the application of a gate voltage enhances the valley polarization of the WS2 / ReS2 heterojunction.
[0058] The valley polarization lifetime diagram of the WS2 / ReS2 heterojunction regulated by gate voltage prepared in this embodiment without applying a gate voltage is as Figure 10 shown. It can be observed that without applying a gate voltage, the lifetime of the WS2 / ReS2 heterojunction is only about 180 fs, and the lifetime is very short.
[0059] The valley polarization lifetime diagram of the WS2 / ReS2 heterojunction regulated by gate voltage prepared in this embodiment under the application of a 20V gate voltage is as Figure 11 shown. It can be observed that as the gate voltage increases from 0V to 20V, the lifetime of the WS2 / ReS2 heterojunction is about 934 fs, indicating that the application of a gate voltage makes the valley polarization lifetime of the single-layer WS2 in the heterojunction formed after building ReS2 longer. Example 2
[0060] The difference from Example 1 is only in step (5). The substrate with the heterojunction sample is placed in a vacuum annealing tube furnace. Under the condition of a vacuum degree of 10 -5 Pa, it is heated to 180°C at a heating rate of 20°C / min and kept warm for 70 minutes. Example 3
[0061] The difference from Example 1 is only in step (5). The substrate with the heterojunction sample is placed in a vacuum annealing tube furnace. Under the condition of a vacuum degree of 10 -5 Pa, it is heated to 220°C at a heating rate of 20°C / min and kept warm for 50 minutes. Example 4
[0062] (1) Substrate cleaning: A beaker is placed in an ultrasonic cleaner. The cut silicon wafers are laid flat in the beaker. The size of the silicon wafers is 1.5 cm in length and 0.7 cm in width. Then, a cleaning agent is added to the beaker. The cleaning agent is cleaned in the order of acetone → absolute ethanol → high-purity water, and the cleaning time for each time is set to 10 min. Finally, the cleaned substrate is dried with a nitrogen gun.
[0063] (2) Select MoS2, ReS2 bulk crystals and natural graphite bulk crystals.
[0064] The bulk crystal was immersed in an absolute ethanol solution and placed in an ultrasonic cleaner with a set vibration frequency of 80 kHz for 30 min. Subsequently, it was repeatedly rinsed with deionized water and finally dried with a nitrogen gun.
[0065] (3)Use 3M tape to stick on the surface of the cleaned crystal, let it stand for five minutes, then tear off the tape. Then, fold two tapes against each other to reduce the number of layers of graphite, two-dimensional MoS2, and ReS2. Next, use a pair of sharp tweezers to tear the PDMS film and attach it to the tape with the sample for 15 min. Remove the PDMS and place the side with the sample under an optical microscope. Observe the MoS2 sample using a fluorescence microscope lens. Monolayer MoS2 will have strong luminescence, while ReS2 and graphite are observed under bright field. Select thinner samples.
[0066] (4)Attach the PDMS film with the ReS2 sample to a transparent glass slide, then place the transparent glass slide upside down on the transfer rack of the transfer platform. Place the cleaned silicon wafer on the lower transfer rack of the transfer platform. Locate the target compound ReS2 on the PDMS film using a microscope. Finally, use the displacement screw rod in the vertical direction to lower the PDMS film with the ReS2 sample on the upper transfer rack onto the silicon wafer on the lower transfer rack for attachment. Then heat it to 80 °C. After 15 - 30 min, carefully and slowly lift the upper transfer rack. At this time, ReS2 on the solution film separates from the PDMS and attaches to the silicon wafer. Repeat the above process to transfer the selected monolayer MoS2 onto the ReS2 sample to build the MoS2 / ReS2 heterojunction. Finally, transfer the thin-layer graphite to the edge of the heterojunction.
[0067] (5)Place the substrate with the heterojunction sample into a vacuum annealing tube furnace. Under the condition of a vacuum degree of 10 -5 Pa, raise the temperature to 200 °C at a heating rate of 20 °C / min and keep it warm for 60 minutes.
[0068] (6)Place the substrate of the unannealed heterojunction sample under an optical microscope and fix it with tape. Locate the position of the sample. Take a small amount of silver paste with a tungsten needle and apply the silver paste onto the thin-layer graphite through a micromanipulation robotic arm. Then connect a copper wire with a diameter of 3 mm and a length of 5 cm to the silver paste and let it stand for 30 min to cure. Repeat the above operation to also drip silver paste and connect the copper wire at the bottom of the silicon wafer and cure it. Comparative Example 1
[0069] (1)Substrate cleaning: Place a beaker in an ultrasonic cleaner. Lay the cut silicon wafers flat in the beaker. The size of the silicon wafers is 1.5 cm in length and 0.7 cm in width. Add a cleaning agent to the beaker and clean the wafers in the order of acetone → absolute ethanol → high-purity water. Set the cleaning time for each step to 10 minutes. Finally, use a nitrogen gun to blow dry the cleaned substrate.
[0070] (2)Select bulk WS2, ReS2 crystals and bulk natural graphite crystals.
[0071] Immerse the bulk crystals in an absolute ethanol solution and place them in an ultrasonic cleaner with a set vibration frequency of 80 kHz for 30 minutes. Then rinse them repeatedly with deionized water and finally use a nitrogen gun to blow dry the cleaned crystals.
[0072] (3)Use 3M tape to stick on the surface of the cleaned bulk crystals. Let it stand for five minutes, then tear off the tape. Then use two tapes to bond with each other to reduce the number of layers of graphite and two-dimensional WS2 and ReS2. Then use a pair of sharp tweezers to tear the PDMS film and attach it to the tape with the sample for 15 minutes. Remove the PDMS and place the side with the sample under an optical microscope for observation. Observe the WS2 sample using a fluorescence microscope lens. Monolayer WS2 will have strong luminescence. Observe ReS2 and graphite under bright field and select thinner samples.
[0073] (4)Attach the PDMS film with the ReSe2 sample to a transparent glass slide, then place the transparent glass slide upside down on the transfer rack of the transfer platform. Place the cleaned silicon wafer substrate on the lower transfer rack of the transfer platform. Use a microscope to find the target compound ReSe2 on the PDMS film. Finally, use the displacement screw rod in the vertical direction to lower the PDMS film with the ReSe2 sample on the upper transfer rack onto the silicon wafer on the lower transfer rack for attachment. Then heat it to 80 °C. After 15 - 30 minutes, carefully and slowly lift the upper transfer rack. At this time, ReSe2 on the solution film separates from the PDMS and attaches to the silicon wafer substrate. Repeat the above process to transfer the selected monolayer WS2 onto the ReSe2 sample to build the WS2 / ReS2 heterojunction. Finally, transfer the thin-layer graphite to the edge of the heterojunction.
[0074] (5)Do not anneal the substrate with the heterojunction sample in a vacuum annealing tube furnace. Directly use a nitrogen gun to blow the substrate clean.
[0075] (6)Place the substrate of the unannealed heterojunction sample under an optical microscope and fix it with tape. Locate the position of the sample. Use a tungsten needle to pick up a small amount of silver paste and then apply the silver paste on the thin-layer graphite through a micromanipulation robotic arm. Then connect a copper wire with a diameter of 3 mm and a length of 5 cm to the silver paste and let it stand for 30 minutes to cure. Repeat the above operation to also drip silver paste at the bottom of the silicon wafer to connect the copper wire and cure it.
[0076] The fluorescence image of the MX2 (WS2 / ReS2) heterojunction after dry transfer and before annealing prepared in this example is as Figure 12 shown. It can be observed that compared with the Figure 2 fluorescence image of the annealed sample in Comparative Example 2
[0077] (1) Substrate cleaning: Place a beaker in an ultrasonic cleaner, lay the cut silicon wafers flat in the beaker. The size of the silicon wafers is 1.5 cm in length and 0.7 cm in width. Add a cleaning agent to the beaker and clean it in the order of acetone → absolute ethanol → high-purity water. Set the cleaning time to 10 minutes each time, and finally blow dry the cleaned substrate with a nitrogen gun.
[0078] (2) Select bulk crystals of MoS2, ReS2, and natural graphite.
[0079] Immerse the bulk crystals in an absolute ethanol solution and place them in an ultrasonic cleaner with a set vibration frequency of 80 kHz for 30 minutes. Then rinse them repeatedly with deionized water, and finally blow dry the cleaned crystals with a nitrogen gun.
[0080] (3) Use 3M tape to stick to the surface of the cleaned crystals, let it stand for five minutes, then tear off the tape. Then fold two tapes against each other to reduce the number of layers of graphite, two-dimensional MoS2, and ReS2. Then use a pair of pointed tweezers to tear the PDMS film and attach it to the tape with the sample for 15 minutes. Remove the PDMS and place the side with the sample under an optical microscope. Observe the MoS2 sample with a fluorescence microscope lens. Monolayer MoS2 will have strong luminescence. Observe ReS2 and graphite under bright field and select thinner samples.
[0081] (4) Attach the PDMS film with the ReS2 sample to a transparent glass slide, then place the transparent glass slide upside down on the transfer rack of the transfer platform. Place the cleaned silicon wafer on the lower transfer rack of the transfer platform. Use a microscope to find the ReS2 target compound on the PDMS film. Finally, use the displacement screw rod in the vertical direction to lower the PDMS film with the ReS2 sample on the upper transfer rack onto the silicon wafer on the lower transfer rack for bonding. Then heat it to 80 °C. After 15 - 30 minutes, carefully and slowly lift the upper transfer rack. At this time, ReS2 on the solution film separates from the PDMS and bonds to the silicon wafer. Repeat the above process to transfer the selected monolayer MoS2 onto the ReS2 sample to build the MoS2 / ReS2 heterojunction. Finally, transfer the thin-layer graphite to the edge of the heterojunction.
[0082] (5) Do not anneal the substrate with the heterojunction sample in a vacuum annealing tube furnace, and directly blow dry the substrate with a nitrogen gun.
[0083] (6) Place the substrate of the unannealed heterojunction sample under an optical microscope and fix it with tape. Locate the position of the sample. Take a small amount of silver paste with a tungsten needle and then apply the silver paste onto the thin-layer graphite through a micromanipulation robotic arm. Then connect a copper wire with a diameter of 3 mm and a length of 5 cm to the silver paste and let it stand for 30 min to cure. Repeat the above operation to similarly drip silver paste at the bottom of the silicon wafer to connect the copper wire and cure it.
[0084] The scope of protection claimed in the present invention is not limited to the above specific embodiments. For those skilled in the art, the present invention can have various deformations and modifications. Any modification, improvement, and equivalent replacement made within the concept and principle of the present invention should be included within the scope of protection of the present invention.
Claims
1. A preparation method of a gate voltage-regulated MX2 / MX2 heterojunction, characterized in that, It includes the following steps: Step 1: Clean the silicon wafer substrate to remove impurities on the silicon wafer substrate; Step 2: Select two types of MX2 bulk crystals and natural graphite bulk crystals, and perform surface cleaning treatment on the above bulk crystals to remove impurities, oxides and adsorbates on the surface of the bulk crystals; Step 3: Obtain two-dimensional materials by mechanical exfoliation method: repeatedly bond and peel the surfaces of MX2 bulk crystals and natural graphite bulk crystals with tape, and a thin layer of MX2 and a thin layer of graphite are adhered to the tape; then bond PDMS with the thin layer sample on the tape and peel off the thin layer sample to obtain PDMS with a thin layer of MX2 and a thin layer of graphite; Step 4: Utilize the thermal release property of PDMS to transfer the first type of thin layer MX2 to the upper surface of the silicon wafer substrate in sequence, transfer the second type of thin layer MX2 to the upper surface of the first type of thin layer MX2 to build an MX2 / MX2 heterojunction, and finally transfer the thin layer graphite to the edge of the MX2 / MX2 heterojunction; Step 5: Perform annealing treatment; Step 6: Drop silver glue onto the thin layer of graphite and connect copper wires to cure it, and drop silver glue at the bottom of the silicon wafer substrate to connect copper wires and cure it.
2. The method according to claim 1, characterized in that: In Step 1, ultrasonically clean the silicon wafer substrate, successively use acetone, absolute ethanol, and high-purity water as cleaning agents, and blow dry with a nitrogen gun after cleaning.
3. The method according to claim 1 or 2, characterized in that: In Step 2, the MX2 bulk crystals are selected from any two of WS2, ReS2, and MoS2.
4. The method according to claim 3, characterized in that: In Step 2, ultrasonically clean the bulk crystals, immerse the bulk crystals in an absolute ethanol solution, set the vibration frequency to 80 kHz and the cleaning time to 30 min, then repeatedly rinse with deionized water, and finally blow dry with a nitrogen gun.
5. The method according to claim 1 or 4, characterized in that: In Step 3, stick the tape on the surface of the cleaned bulk crystals, wait for 5 minutes and then tear off the tape, and use two tapes to bond and tear each other to reduce the number of layers of the bulk crystals.
6. The method according to claim 5, characterized in that: In Step 3, place the PDMS with a thin layer of MX2 and a thin layer of graphite under an optical microscope to observe the thin layer samples on the PDMS, and select the thin layer MX2 and thin layer graphite with the ideal number of layers.
7. The method according to claim 1 or 6, characterized in that: In Step 4, stick the PDMS film with the first type of thin layer MX2 on a transparent glass slide, then place the transparent glass slide upside down on the transfer rack of the transfer platform, place the cleaned silicon wafer substrate on the lower transfer rack of the transfer platform, find the MX2 target compound on the PDMS film with a microscope, and finally use the displacement screw rod in the vertical direction to drop the PDMS film with the first type of thin layer MX2 on the upper transfer rack onto the silicon wafer substrate on the lower transfer rack to fit, heat to 80 °C, after 15 - 30 min, lift the upper transfer rack, at this time, the first type of thin layer MX2 is separated from the PDMS and adheres to the silicon wafer substrate; adopt the same transfer process to transfer the second type of thin layer MX2 to the first type of thin layer MX2, and transfer the thin layer graphite to the edge of the heterojunction.
8. The method according to claim 7, characterized in that: In Step 5, during the annealing treatment, the vacuum degree of the vacuum annealing tube furnace is 10 -5 Pa, and it is kept warm for 50 - 70 minutes under the condition of a temperature of 180 - 220°C.
9. The method according to claim 8, characterized in that: Keep it at a temperature of 200 °C for 60 minutes.
10. The method according to claim 8 or 9, characterized in that: The heating rate is 20 °C / min.