Semiconductor defect detection method
By combining medium and low frequency and high frequency transducer scanning and back-side processing technology, the problem of defect identification in flip-chip-level packaging structures is solved, and efficient and accurate defect analysis and evaluation are achieved.
Patent Information
- Application Number
- CN202510311489.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-08-01
AI Technical Summary
The prior art is difficult to effectively identify defects such as layering and hollowing in flip chip-level packaging structures, especially in the case of high integration, and traditional scanning methods cannot meet the identification requirements.
The medium and low frequency transducer is used for preliminary scanning, combining transmission and reflection scanning, and then scanning the bumps and interfaces are scanned through the high frequency transducer, combining back treatment and corrosion liquid to expose the chip surface, and detailed defect analysis is performed using X-ray fluoroscopy and laser open-closing technology.
It realizes accurate identification and type judgment of defects in flip chip-level packaging structures, and improves the efficiency and accuracy of quality control and reliability evaluation.
Smart Images
Figure CN120404942A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of defect detection of integrated circuits, and particularly to a semiconductor defect detection method. Background Art
[0002] Flip-Chip Chip Scale Packaging (FCCSP packaging) technology is an advanced microelectronic packaging technology. In the case of using the flip-chip process, the active surface of the chip is directly mounted on the substrate facing downwards, and electrical interconnection is achieved with the substrate through bumps. Compared with the traditional wire bonding (WB) method, the distance between the chip and the substrate in flip-chip chip scale packaging is smaller, signal loss is reduced, I / O density is high, and it is more suitable for large-scale integrated circuits. At the same time, flip-chip chip scale packaging has the characteristics of small packaging size, fast signal processing speed, thin packaging thickness, and can achieve multi-chip side-by-side or stacked packaging, etc., and has been widely used in mobile devices, automotive electronics, communication devices, artificial intelligence and other fields.
[0003] However, with the increasing integration and complexity of flip-chip chip scale packaging, higher requirements are put forward for the quality and reliability of the packaging. In the case of increasing packaging complexity and increasing difficulty in identifying packaging defects, the packaging process defects of flip-chip chip scale packaging are one of the important factors affecting its reliability. Summary of the Invention
[0004] Based on this, it is necessary to provide a semiconductor defect detection method, which realizes effective identification of defects such as delamination, voids, and cracks inside flip-chip chip scale packaging devices.
[0005] The present application provides a semiconductor defect detection method for detecting defects in a flip-chip chip scale packaging structure, including:
[0006] Providing a flip-chip chip scale packaging structure, including a plastic package body and a chip and a substrate encapsulated in the plastic package body, wherein the active surface of the chip faces the substrate, and a filler layer is filled between the chip and the substrate, and the chip and the substrate are connected by bumps penetrating through the filler layer;
[0007] Scanning the flip-chip chip scale packaging structure with a medium-low frequency transducer, and analyzing the defects of the plastic package body and the substrate according to the scanning results;
[0008] Performing backside processing on the flip-chip chip scale packaging structure to remove part of the plastic package body to expose the surface of the chip on the side away from the substrate;
[0009] A high-frequency transducer is used to scan the first interface between the filling adhesive layer and the chip and the second interface between the filling adhesive layer and the substrate, so as to perform defect analysis on the bumps, the first interface and the second interface.
[0010] In one embodiment, a medium-low frequency transducer is used to scan the flip-chip level package structure, and defect analysis is performed on the plastic package body and the substrate according to the scanning results, including:
[0011] Perform a transmission scan on the flip-chip level package structure, and perform defect analysis according to the transmission scan image. When there is a black shadow area in the transmission scan image, the flip-chip level package structure has a defect, and the position of the defect is the position where the black shadow area is located;
[0012] Focus on the surface of the chip away from the substrate side and perform a planar scan, and perform defect analysis according to the changes in the phase and amplitude of the planar scan waveform. When the planar scan waveform is inverted and / or the amplitude decays, there is a defect in the plastic package body;
[0013] Focus on the substrate and perform a C-scan, and perform defect analysis according to the change in the image gray level of the C-scan image. When the change in the image gray level of the C-scan image is abnormal, there is a defect in the substrate.
[0014] In one embodiment, when there is a black shadow area in the transmission scan image, focus on the position where the defect is located and perform an A-scan, and judge whether the defect is an internal defect of the flip-chip level package structure according to the A-scan waveform.
[0015] In one embodiment, when there is a defect in the plastic package body, the position where the planar scan waveform is inverted and / or the amplitude decays is the position where the defect is located. Focus on the position where the defect is located and perform an A-scan, and judge the type of the defect according to the A-scan waveform.
[0016] In one embodiment, when the A-scan waveform is inverted, there is a defect of interface delamination at the position where the defect is located;
[0017] When the A-scan waveform has an amplitude decay, there is a void or foreign matter at the position where the defect is located.
[0018] In one embodiment, the back processing of the flip-chip level package structure includes:
[0019] Use an X-ray fluoroscopy system to position the chip to determine the size and position of the chip;
[0020] Use a laser opening machine to perform laser thinning on the flip-chip level package structure, forming a groove on the surface of a part of the plastic package body on the side of the chip away from the substrate, and the projection of the surface of the chip facing the substrate falls within the projection of the surface of the groove facing the substrate;
[0021] Perform a preheating treatment on the flip-chip level package structure, and drop an etching solution into the groove to expose the surface of the chip on the side away from the substrate.
[0022] In one embodiment, after performing the preheating treatment on the flip-chip level package structure, dropping the etching solution into the groove to expose the surface of the chip on the side away from the substrate, the semiconductor defect detection method further includes:
[0023] Perform a cleaning treatment on the flip-chip level package structure, and detect whether the surface of the chip on the side away from the substrate is completely exposed;
[0024] If the surface of the chip on the side away from the substrate is not completely exposed, perform the preheating treatment again, drop the etching solution into the groove again, and perform the cleaning treatment again until the surface of the chip on the side away from the substrate is completely exposed.
[0025] In one embodiment, the etching solution includes a mixed acid formed by mixing fuming nitric acid and concentrated sulfuric acid.
[0026] In one embodiment, the scanning of the first interface and the second interface using a high-frequency transducer includes:
[0027] Focus on the first interface and the second interface respectively and perform C-scans respectively, and judge whether there are defects in the first interface and the second interface according to the C-scan images of the first interface and the second interface;
[0028] In the case where the image gray-scale change of the C-scan images of the first interface and the second interface is abnormal, perform an A-scan on the abnormal area. If the waveform amplitude of the A-scan waveform increases, there is a defect of interface delamination in the filling glue layer. If the waveform amplitude of the A-scan waveform decays, there are voids or foreign objects in the filling glue layer.
[0029] In one embodiment, the frequency range of the medium and low-frequency transducer includes 5 MHz to 100 MHz, and the frequency range of the high-frequency transducer includes 110 MHz to 230 MHz.
[0030] In summary, the semiconductor defect detection method provided by the present application is used to detect defects in a flip-chip level package structure. The flip-chip level package structure is scanned by a medium-low frequency transducer to analyze defects in the encapsulant and the substrate. Part of the encapsulant is removed by backside processing of the flip-chip level package structure to expose the surface of the chip away from the substrate. The first interface and the second interface are scanned by a high-frequency transducer to analyze defects in the bumps, the first interface, and the second interface, thereby effectively identifying the types and positions of defects at the bumps and the filling glue layer, which helps to improve the efficiency and accuracy of quality control, failure analysis, and reliability assessment of the flip-chip level package structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0032] Figure 1 It is a flowchart of the semiconductor defect detection method provided by one embodiment of the present application.
[0033] Figure 2 It is a flowchart block diagram of the semiconductor defect detection method provided by one embodiment of the present application.
[0034] Figure 3 It is a schematic structural diagram of a flip-chip level package structure in the semiconductor defect detection method provided by one embodiment of the present application.
[0035] Figure 4 It is a schematic structural diagram of a flip-chip level package structure corresponding to the step of backside processing in the semiconductor defect detection method provided by one embodiment of the present application.
[0036] Description of the reference numerals: 100 - flip-chip level package structure; 110 - encapsulant; 120 - chip; 121 - filling glue layer; 122 - bump; 130 - substrate; M1 - first interface; M2 - second interface. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0037] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.
[0039] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0040] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0041] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising", "including" or "having", etc., specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0042] Acoustic scanning detection technology is a technology that uses the differences in acoustic impedance of different materials to determine the size and location of defects. It has the advantages of large detection depth, accurate positioning, high detection sensitivity, low cost, convenient use, fast detection speed, etc., and can effectively detect various defects (such as voids, delaminations, cracks, etc.) at any part inside the sample. Therefore, acoustic scanning detection technology is of great significance for defect detection and reliability evaluation of components.
[0043] Generally, in a plastic-encapsulated device chip using the wire bonding method, the active surface of the chip is mounted upward. At this time, acoustic scanning of the front and back of the semiconductor device respectively can effectively evaluate the internal defect situation of the semiconductor device.
[0044] However, in a flip-chip chip scale packaging (FCCSP packaging) device, the chip is flip-chip mounted on the substrate and wrapped by a plastic encapsulant, with the characteristics of complex structure and high packaging density. When evaluating the defects related to bumps and underfill in a flip-chip chip scale packaging device, although using a low-frequency transducer for acoustic scanning has strong penetration ability, it is limited by low resolution, and this scanning method cannot achieve defect identification of the highly integrated internal interconnection structure in a flip-chip chip scale packaging device. At this time, a high-frequency transducer needs to be used for acoustic scanning so that the resolution can meet the requirement of identifying the defects related to bumps and underfill. However, the penetration ability of the high-frequency transducer is weak, and it is difficult to penetrate the plastic encapsulant and chip material of the semiconductor device to detect the defects of the internal structure.
[0045] To solve the above problems, the present application provides a semiconductor defect detection method, which realizes effective identification of defects such as delamination, voids, cracks, etc. inside a flip-chip chip scale packaging device.
[0046] Figure 1 The flowchart of the semiconductor defect detection method provided by one embodiment of the present application. Refer to Figure 1, a semiconductor defect detection method provided by one embodiment of the present application is used for defect detection of a flip-chip level package structure, including the following steps S01 to S04.
[0047] Step S01: Provide a flip-chip level package structure, including a plastic package body and a chip and a substrate encapsulated in the plastic package body. Among them, the active surface of the chip faces the substrate, and a filling glue layer is filled between the chip and the substrate, and the chip and the substrate are connected by bumps passing through the filling glue layer.
[0048] It should be noted that the filling glue layer fills the voids existing between the chip and the substrate by using the capillary action principle to play a role in strengthening and protecting the flip-chip level package structure.
[0049] Step S02: Scan the flip-chip level package structure with a medium and low frequency transducer, and perform defect analysis on the plastic package body and the substrate according to the scanning results.
[0050] It should be noted that scanning the flip-chip level package structure with a medium and low frequency transducer can initially check whether there are defects inside the structure and provide a reference for subsequent defect analysis. Optionally, the defect detection and analysis can be carried out by combining transmission scanning and reflection scanning to improve the accuracy of the defect analysis results. Among them, the results of transmission scanning mainly help to judge whether there are abnormal conditions such as delamination and cracking at the substrate, and the results of reflection scanning mainly help to evaluate whether there are defects such as cracks and voids inside the plastic package body, and at the same time help to evaluate whether there is interface delamination at the part where the plastic package body contacts the chip.
[0051] Step S03: Perform backside treatment on the flip-chip level package structure to remove part of the plastic package body to expose the surface of the chip on the side away from the substrate.
[0052] Step S04: Scan the first interface between the filling glue layer and the chip and the second interface between the filling glue layer and the substrate with a high frequency transducer to perform defect analysis on the bumps, the first interface and the second interface.
[0053] As described above, the semiconductor defect detection method scans the flip-chip level package structure with a medium and low frequency transducer to perform defect analysis on the plastic package body and the substrate; scans the first interface and the second interface with a high frequency transducer to perform defect analysis on the bumps, the first interface and the second interface, so as to effectively identify the defect types and positions at the bumps and the filling glue layer, which helps to improve the efficiency and accuracy of quality control, failure analysis and reliability evaluation of the flip-chip level package structure.
[0054] Refer to Figure 2 and Figure 3 In one embodiment, a mid - low frequency transducer is used to scan the flip - chip level package structure. The specific process of defect analysis on the plastic package body and the substrate according to the scanning results (i.e., step S02) includes: performing a transmission scan on the flip - chip level package structure 100, and performing defect analysis based on the transmission scan image. When there is a black shadow area in the transmission scan image, the flip - chip level package structure 100 has a defect, and the position of the defect is the position where the black shadow area is located; focusing on the surface of the chip 120 away from the substrate 130 side and performing a planar scan, and performing defect analysis based on the changes in the phase and amplitude of the planar scan waveform. When the planar scan waveform undergoes an in - phase inversion and / or amplitude attenuation, there is a defect in the plastic package body 110; focusing on the substrate 130 and performing a C - scan, and performing defect analysis based on the image gray - level change of the C - scan image. When the image gray - level change of the C - scan image is abnormal, there is a defect in the substrate 130.
[0055] It should be noted that in the transmission scan mode, ultrasonic waves cannot penetrate stratification or cavities that appear in the transmission scan path. At the same time, since the acoustic impedance of air is zero, sound waves will be totally reflected when encountering air, resulting in the receiving probe below the flip - chip level package structure being unable to receive the acoustic wave signal, thus making the image of the defect position display black. Therefore, if there is a black shadow in the transmission scan image, it indicates that there is a defect at the corresponding position of the flip - chip level package structure. In addition, to ensure the accuracy of the inspection structure, the position of the defect can be marked first, and then a comprehensive judgment can be made in combination with the subsequent reflection scan results.
[0056] Continue to refer to Figure 2 In one embodiment, when there is a black shadow area in the transmission scan image, it is possible to focus on the position where the defect is located and perform an A - scan, and determine whether the defect is an internal defect of the flip - chip level package structure based on the A - scan waveform.
[0057] In one embodiment, when there is a defect in the plastic package body, the position where the planar scan waveform undergoes an in - phase inversion and / or amplitude attenuation is the position where the defect is located. It is possible to focus on the position where the defect is located and perform an A - scan, and determine the type of the defect based on the A - scan waveform.
[0058] In one embodiment, when there is a defect in the substrate, it is possible to perform an A - scan on the area with abnormal image change in the substrate, and determine the type of the defect based on the A - scan waveform. Optionally, when the A - scan waveform undergoes an in - phase inversion, there is a defect of interface stratification at the position where the defect is located; when the A - scan waveform undergoes amplitude attenuation, there is a cavity or foreign object at the position where the defect is located.
[0059] Refer to Figures 2 to 4, in one embodiment, the backside processing of the flip-chip level package structure 100 (i.e., step S03) includes: using an X-ray fluoroscopy system to position the chip 120 to determine the size and position of the chip 120; using a laser dicing machine to perform laser thinning on the flip-chip level package structure 100 to form a groove (not shown in the figure) on the surface of a part of the encapsulant 110 on the side of the chip 120 away from the substrate 130, and the projection of the surface of the chip 120 facing the substrate 130 falls within the projection of the groove facing the substrate 130; performing a preheating treatment on the flip-chip level package structure 100, dropping an etching solution into the groove to expose the surface of the chip 120 on the side away from the substrate 130.
[0060] It should be noted that during the above backside processing, the projection of the surface of the chip facing the substrate falls within the projection of the groove facing the substrate, in order to make the range of laser thinning at least larger than the size of the chip, so as to ensure that the surface of the chip on the side away from the substrate can be completely exposed after the backside processing is completed, facilitating the subsequent defect analysis process. At the same time, it should be emphasized that the depth of the groove needs to be less than the thickness of the part of the encapsulant on the side of the chip away from the substrate to avoid damaging the chip.
[0061] In one embodiment, the flip-chip level package structure 100 can be placed on a heating stage for preheating to improve the processing effect of subsequently removing the remaining encapsulant on the chip with the etching solution. Optionally, the preheating temperature of the heating stage can be adjusted according to actual needs, for example, it can be set to 60 °C.
[0062] In one embodiment, after performing a preheating treatment on the flip-chip level package structure, dropping an etching solution into the groove to expose the surface of the chip on the side away from the substrate, the semiconductor defect detection method further includes: performing a cleaning treatment on the flip-chip level package structure and detecting whether the surface of the chip on the side away from the substrate is completely exposed; if the surface of the chip on the side away from the substrate is not completely exposed, then perform the preheating treatment again, drop the etching solution into the groove again and perform the cleaning treatment again until the surface of the chip on the side away from the substrate is completely exposed.
[0063] In one embodiment, the etching solution includes a mixed acid composed of fuming nitric acid and concentrated sulfuric acid. It should be noted that during the process of dropping the etching solution into the groove, attention should be paid to the acid dropping flow rate and the etching rate to prevent over-etching from damaging the structures of parts such as the chip, the filler layer, and the substrate, thereby avoiding damage to the flip-chip level package structure.
[0064] In one embodiment, the specific process of the cleaning treatment includes: first washing the surface of the flip-chip level package structure with water to remove the residual etching solution, and then putting the flip-chip level package structure into an acetone solution for ultrasonic cleaning to improve the cleaning effect.
[0065] Continuing to refer to Figure 2 and Figure 4 In one embodiment, the specific process of using the high-frequency transducer to scan the first interface M1 and the second interface M2 (i.e., step S04) includes: focusing on the first interface M1 and the second interface M2 respectively and performing C-scans respectively, and judging whether there are defects on the first interface M1 and the second interface M2 according to the C-scan images of the first interface M1 and the second interface M2; in the case where the image gray-scale change of the C-scan images of the first interface M and the second interface M2 is abnormal, performing an A-scan on the abnormal area. If the waveform amplitude of the A-scan waveform increases, there is a defect of interface delamination in the underfill layer 121. If the waveform amplitude of the A-scan waveform decays, there are voids or foreign objects in the underfill layer 121. In addition, in the case where the image gray-scale change of the C-scan image of the first interface M is abnormal, it may also be that there are defects such as cracking and poor soldering in the bumps 122.
[0066] In one embodiment, the frequency range of the medium-low frequency transducer includes 5 MHz to 100 MHz, and the frequency range of the high-frequency transducer includes 110 MHz to 230 MHz.
[0067] In summary, the semiconductor defect detection method provided by this application is used to detect defects in the flip-chip level package structure. The flip-chip level package structure is scanned by the medium-low frequency transducer to perform defect analysis on the plastic package and the substrate; the back surface of the flip-chip level package structure is processed to remove part of the plastic package so that the surface on the side of the chip away from the substrate is exposed; the first interface and the second interface are scanned by the high-frequency transducer to perform defect analysis on the bumps, the first interface and the second interface, so as to effectively identify the types and positions of defects at the bumps and the underfill layer, which helps to improve the efficiency and accuracy of quality control, failure analysis and reliability evaluation of the flip-chip level package structure.
[0068] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0069] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.
[0070] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A semiconductor defect detection method for detecting defects in a flip chip level package structure, characterized in that, Including: Provided is a flip-chip level package structure, including a plastic package body, a chip and a substrate encapsulated in the plastic package body. Wherein, the active surface of the chip faces the substrate, and a filling glue layer is filled between the chip and the substrate, and the chip and the substrate are connected by bumps penetrating through the filling glue layer; Using a medium-low frequency transducer to scan the flip-chip level package structure, and performing defect analysis on the plastic package body and the substrate according to the scanning result; Performing backside processing on the flip-chip level package structure to remove part of the plastic package body to expose the surface of the chip on the side away from the substrate; Using a high-frequency transducer to scan the first interface between the filling glue layer and the chip and the second interface between the filling glue layer and the substrate, so as to perform defect analysis on the bumps, the first interface and the second interface.
2. The semiconductor defect detection method according to claim 1, wherein The step of using a medium-low frequency transducer to scan the flip-chip level package structure and performing defect analysis on the plastic package body and the substrate according to the scanning result includes: Performing transmission scanning on the flip-chip level package structure, and performing defect analysis according to the transmission scanning image. When there is a black shadow area in the transmission scanning image, the flip-chip level package structure has a defect, and the position of the defect is the position where the black shadow area is located; Focusing on the surface of the chip on the side away from the substrate and performing planar scanning, and performing defect analysis according to the changes in the phase and amplitude of the planar scanning waveform. When the planar scanning waveform undergoes phase inversion and / or amplitude attenuation, there is a defect in the plastic package body; Focusing on the substrate and performing C-scanning, and performing defect analysis according to the change in the image gray level of the C-scanning image. When the change in the image gray level of the C-scanning image is abnormal, there is a defect in the substrate.
3. The semiconductor defect detection method according to claim 2, wherein When there is a black shadow area in the transmission scanning image, focusing on the position where the defect is located and performing A-scanning, and judging whether the defect is an internal defect of the flip-chip level package structure according to the A-scanning waveform.
4. The semiconductor defect detection method according to claim 2, wherein When there is a defect in the plastic package body, the position where the planar scanning waveform undergoes phase inversion and / or amplitude attenuation is the position where the defect is located. Focusing on the position where the defect is located and performing A-scanning, and judging the type of the defect according to the A-scanning waveform.
5. The semiconductor defect detection method according to claim 4, wherein, When the A-scanning waveform undergoes phase inversion, there is a defect of interface delamination at the position where the defect is located; When the A-scanning waveform undergoes amplitude attenuation, there is a cavity or foreign matter at the position where the defect is located.
6. The semiconductor defect detection method according to claim 1, characterized in that, The step of performing backside processing on the flip-chip level package structure includes: Using an X-ray fluoroscopy system to position the chip to determine the size and position of the chip; Using a laser opening machine to perform laser thinning on the flip-chip level package structure to form a groove on the surface of part of the plastic package body located on the side of the chip away from the substrate, and the projection of the surface of the chip facing the substrate falls within the projection of the surface of the groove facing the substrate; Perform a preheating treatment on the flip chip level package structure, and drop an etching solution into the groove to expose the surface of the chip on the side away from the substrate.
7. The semiconductor defect detection method according to claim 6, characterized in that, After performing the preheating treatment on the flip chip level package structure, dropping the etching solution into the groove to expose the surface of the chip on the side away from the substrate, the semiconductor defect detection method further includes: Perform a cleaning treatment on the flip chip level package structure, and detect whether the surface of the chip on the side away from the substrate is completely exposed; If the surface of the chip on the side away from the substrate is not completely exposed, perform the preheating treatment again, drop the etching solution into the groove again, and perform the cleaning treatment again until the surface of the chip on the side away from the substrate is completely exposed.
8. The semiconductor defect detection method according to claim 6, wherein The etching solution includes a mixed acid formed by mixing fuming nitric acid and concentrated sulfuric acid.
9. The semiconductor defect detection method according to claim 1, characterized in that, The scanning of the first interface and the second interface by using the high-frequency transducer includes: Focus on the first interface and the second interface respectively and perform C-scans respectively, and judge whether there are defects on the first interface and the second interface according to the C-scan images of the first interface and the second interface; In the case where the image gray level change of the C-scan images of the first interface and the second interface is abnormal, perform an A-scan on the abnormal area. If the waveform amplitude of the A-scan waveform increases, there is a defect of interface delamination in the filling adhesive layer. If the waveform amplitude of the A-scan waveform decays, there are voids or foreign objects in the filling adhesive layer.
10. The semiconductor defect detection method according to claim 1, characterized in that, The frequency range of the medium and low frequency transducer includes 5 MHz to 100 MHz, and the frequency range of the high-frequency transducer includes 110 MHz to 230 MHz.