Mask and design method thereof, and semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a mask and a design method thereof, and a semiconductor structure and a manufacturing method thereof. The mask comprises a first area, a second area and a third area located between the first area and the second area; the mask plate comprises alignment mask patterns, and the alignment mask patterns comprise a plurality of first alignment patterns which are located in the first region and extend in the first direction and a plurality of second alignment patterns which are located in the second region and extend in the second direction; wherein the first direction and the second direction are both parallel to the mask plate, and the first direction and the second direction intersect with each other.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a mask and a design method thereof, a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the manufacturing process of a semiconductor structure, before exposure by an exposure machine, alignment needs to be performed according to alignment marks on a mask before exposure can be carried out. Current masks still cannot meet the usage requirements. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a mask and a design method thereof, a semiconductor structure and a manufacturing method thereof.

[0004] To achieve the above object, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, embodiments of the present disclosure provide a mask. The mask includes a first region, a second region, and a third region located between the first region and the second region; the mask includes an alignment mask pattern, and the alignment mask pattern includes a plurality of first alignment patterns located in the first region and extending along a first direction, and a plurality of second alignment patterns located in the second region and extending along a second direction; wherein, both the first direction and the second direction are parallel to the mask and the first direction and the second direction intersect.

[0006] In some embodiments, the alignment mask pattern includes an axisymmetric figure.

[0007] In some embodiments, the size of the third region in a third direction is less than 40 μm; wherein, the third direction is parallel to the mask and the first region, the third region, and the second region are arranged along the third direction.

[0008] In some embodiments, the axis of symmetry of the axisymmetric figure coincides with the midline of the third region and the axis of symmetry extends along a fourth direction, and the first alignment pattern and the second alignment pattern are axisymmetric about the axis of symmetry; wherein, the fourth direction is parallel to the mask and the fourth direction and the third direction are perpendicular to each other.

[0009] In some embodiments, the first alignment pattern includes a strip-shaped pattern extending along the first direction; the dimension of the first alignment pattern in the third direction is the same as the dimension of the spacing between any two adjacent first alignment patterns in the third direction; the second alignment pattern includes a strip-shaped pattern extending along the second direction; the dimension of the second alignment pattern in the third direction is the same as the dimension of the spacing between any two adjacent second alignment patterns in the third direction.

[0010] In some embodiments, the first alignment pattern includes a plurality of first marker patterns arranged at intervals along the first direction; the second alignment pattern includes a plurality of second marker patterns arranged at intervals along the second direction; wherein, the distribution density of the first marker patterns is the same as the distribution density of the second marker patterns.

[0011] In some embodiments, the first marker pattern and the second marker pattern are axisymmetric about the axis of symmetry.

[0012] In some embodiments, the angles between the first direction and the third direction, and the fourth direction are both 45 degrees; the angles between the second direction and the third direction, and the fourth direction are both 45 degrees.

[0013] In some embodiments, the alignment mask pattern is not included in the third region.

[0014] In some embodiments, the mask includes a chip region and a scribe lane region surrounding the chip region; wherein, the first region, the third region and the second region are all located in the scribe lane region.

[0015] In a second aspect, an embodiment of the present disclosure provides a design method for a mask, the design method includes: setting a first region, a second region and a third region located between the first region and the second region on the mask; setting an alignment mask pattern on the mask, the alignment mask pattern includes a plurality of first alignment patterns located in the first region and extending along the first direction, and a plurality of second alignment patterns located in the second region and extending along the second direction; wherein, the first direction and the second direction are both parallel to the mask and the first direction and the second direction intersect.

[0016] In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes: forming a first material layer, a second material layer, and a photoresist layer that are sequentially stacked; using the mask plate described in the above technical solution as a mask to expose and develop the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask to etch the second material layer to form a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction; filling the first grooves and the second grooves to form a first alignment mark and a second alignment mark respectively; wherein, the first alignment mark and the second alignment mark together form an alignment mark; the first direction and the second direction are both parallel to the first material layer and the first direction and the second direction intersect.

[0017] In a fourth aspect, an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first material layer and a second material layer located on the first material layer; the second material layer includes a first region, a second region, and a third region located between the first region and the second region; an alignment mark located in the second material layer; the alignment mark includes a plurality of first alignment marks located in the first region and extending in a first direction, and a plurality of second alignment marks located in the second region and extending in a second direction; wherein, the first direction and the second direction are both parallel to the first material layer and the first direction and the second direction intersect.

[0018] In some embodiments, the alignment mark includes an axisymmetric figure.

[0019] In some embodiments, the third region does not include the alignment mark.

[0020] Embodiments of the present disclosure provide a mask and a design method thereof, a semiconductor structure and a manufacturing method thereof. The mask includes a first region, a second region, and a third region located between the first region and the second region; the mask includes alignment mask patterns, and the alignment mask patterns include a plurality of first alignment patterns located in the first region and extending along a first direction, and a plurality of second alignment patterns located in the second region and extending along a second direction; wherein, both the first direction and the second direction are parallel to the mask and the first direction and the second direction intersect. In the embodiments of the present disclosure, the mask includes a first region, a second region, and a third region located between the first region and the second region, the mask includes alignment mask patterns, and the alignment mask patterns include first alignment patterns and second alignment patterns, wherein, a plurality of first alignment patterns extending along the first direction are provided in the first region, and a plurality of second alignment patterns extending along the second direction are provided in the second region; thus, using the above mask for a lithography process to form alignment marks can not only achieve the alignment function of the alignment marks, but also avoid problems such as cracking or fading of the alignment marks, thereby avoiding damage to the chip patterns in the chip region, and further improving the quality and performance of the semiconductor structure. Description of the Drawings

[0021] Figure 1 Schematic structural diagram of the mask provided by the embodiment of the present disclosure;

[0022] Figure 2 Schematic structural diagram of the mask provided by the first embodiment of the present disclosure;

[0023] Figure 3 Schematic structural diagram of the mask provided by the second embodiment of the present disclosure;

[0024] Figure 4 Schematic flow chart of the design method of the mask provided by the embodiment of the present disclosure;

[0025] Figure 5 Schematic flow chart of the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure;

[0026] Figures 6A to 6E Schematic cross-sectional structure diagram of the semiconductor structure provided by the embodiment of the present disclosure during manufacturing. Detailed Embodiments

[0027] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0028] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0029] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout the drawings denote like elements.

[0030] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be termed a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not necessarily imply that a first element, component, region, layer, or section exists in the present disclosure.

[0031] Spatial relationship terms such as “under,” “below,” “beneath,” “underneath,” “above,” “over,” etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as “under” or “beneath” or “underneath” another element or feature will be oriented “over” the other element or feature. Thus, the exemplary terms “under” and “beneath” can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0033] To thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other embodiments.

[0034] In the manufacturing process of semiconductor structures, it is necessary to place alignment marks on the front-layer reference layer as alignment identifiers before the exposure of the scanner to achieve alignment between the mask and the wafer and ensure accurate overlay of the patterns between the front and back layers after exposure. Among them, the periodic structural pattern of the alignment mark is designed in a fixed combination with the machine. In addition, in semiconductor devices such as 3D NAND-type memories, the number of stacked layers is increasing, and it is usually necessary to increase the thickness of the hard mask (HM) to reduce the etch loading, and these film layer structures bring many process limitations.

[0035] If the critical dimension (CD) of the alignment mark on the mask is large, due to the stress accumulation and release problems after various process steps, problems such as cracking or discoloration may easily occur. This not only results in wafer rejection but may also damage the chip pattern in the chip area. By segmenting the alignment mark on the mask and reducing the critical dimension of the alignment mark, the cracking problem can be alleviated. However, if the critical dimension of the alignment mark on the mask is small, the topological structure of the alignment mark cannot be clearly seen during the alignment of the back layer, which may affect the wafer quality and result in overlay deviation (OVL).

[0036] Therefore, the current mask cannot meet the usage requirements.

[0037] In view of this, the embodiments of the present disclosure provide a mask and its design method, a semiconductor structure and its manufacturing method.

[0038] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the mask provided in the embodiment of the present disclosure. Figure 1 As shown, the embodiment of the present disclosure provides a mask, the mask 100 includes a first area 102, a second area 104 and a third area 106 located between the first area 102 and the second area 104; the mask 100 includes an alignment mask pattern 108, the alignment mask pattern 108 includes a first area 102 and a second area 104 along a first direction (such as Figure 1 D1) extending in the plurality of first alignment patterns 110, and located in the second region 104 and along the second direction (eg Figure 1 Schematically shows a plurality of second alignment patterns 112 extending from D2); wherein the first direction and the second direction are both parallel to the mask 100 and the first direction and the second direction intersect.

[0039] In the embodiment of the present disclosure, a first direction and a second direction intersecting each other are defined in the plane where the mask is located. The present disclosure does not specifically limit the angle between the first direction and the second direction. For example, the first direction and the second direction may be perpendicular to each other.

[0040] Here, the plurality of first alignment patterns 110 in the first region 102 all extend along a first direction and are spaced apart in a direction perpendicular to the first direction; the plurality of second alignment patterns 112 in the second region 104 all extend along a second direction and are spaced apart in a direction perpendicular to the second direction. The present disclosure does not specifically limit the number of first alignment patterns 110 and second alignment patterns 112, and a flexible selection can be made based on practical needs.

[0041] In some specific embodiments, the first direction and the second direction are perpendicular to each other, so that the multiple first alignment patterns 110 in the first area 102 extend along the first direction and are arranged at intervals along the second direction, and the multiple second alignment patterns 112 in the second area 104 extend along the second direction and are arranged at intervals along the first direction.

[0042] In some embodiments, the third region 106 does not include an alignment mask pattern.

[0043] It should be noted that if the first alignment pattern 110 in the first region 102 continues to extend into the third region 106 along the first direction, and the second alignment pattern 112 in the second region 104 continues to extend into the third region 106 along the second direction, the first alignment pattern 110 and the second alignment pattern 112 intersect in the third region 106. The intersection point between the first alignment pattern 110 and the second alignment pattern 112 in the third region 106 will become a weak point where a crack defect is generated. Therefore, when performing a lithography process using the above-mentioned mask, the first alignment pattern in the first region on the mask can correspondingly form a first alignment mark, and the second alignment pattern in the second region on the mask can correspondingly form a second alignment mark. The intersection point between the first alignment mark and the second alignment mark is prone to stress concentration problems, there is a risk of cracking, and it may even damage the chip pattern in the chip region, thereby reducing the wafer quality and resulting in wafer rejection.

[0044] Here, the third region does not include an alignment mask pattern. When performing a lithography process using the mask provided by the embodiment of the present disclosure, the first alignment pattern in the first region on the mask can correspondingly form a first alignment mark, the second alignment pattern in the second region on the mask can correspondingly form a second alignment mark, and the third region on the mask does not include an alignment mask pattern. In this way, there is a certain distance between the first alignment mark and the second alignment mark, which can alleviate the stress concentration problem in the manufacturing process of the semiconductor structure and avoid problems such as cracking or fading of the alignment marks.

[0045] In addition, precisely because a lithography process is performed using the mask provided by the embodiment of the present disclosure, the stress concentration problem in the manufacturing process of the semiconductor structure can be alleviated. The mask provided by the embodiment of the present disclosure is particularly applicable to multiple application scenarios such as a high-temperature layer and a high-stress layer for packaging, and has a wide range of applications.

[0046] In addition, since the critical dimension of the alignment mark on the mask is relatively large and prone to problems such as cracking, the third region on the mask provided by the embodiment of the present disclosure does not include an alignment mask pattern, which can not only reduce the risk of cracking of the alignment mark, but also allow a larger-sized alignment mark to be placed on the previous layer to improve the wafer quality, enabling the alignment mark to provide the maximum signal strength and ensuring the alignment accuracy.

[0047] In some embodiments, the mask 100 includes a chip region and a scribe lane region surrounding the chip region; among them, the first region 102, the third region 106, and the second region 104 are all located in the scribe lane region.

[0048] Here, the mask may include a chip region and a scribe lane region surrounding the chip region; wherein, the chip region includes a chip pattern, and the scribe lane region includes a first region, a second region, and a third region; after performing a lithography process using the mask provided by the embodiments of the present disclosure, a chip region and a scribe lane region surrounding the chip region can be correspondingly formed on the wafer; wherein, the chip region on the wafer includes a chip pattern, and the scribe lane region on the wafer includes a first alignment mark and a second alignment mark. Since there is a certain distance between the first alignment mark and the second alignment mark, it is not only possible to alleviate problems such as cracking or fading that are prone to occur in the alignment marks, but also to avoid damaging the chip pattern in the chip region, reduce the manufacturing cost and increase the yield, thereby improving the quality and performance of the semiconductor structure.

[0049] In some specific embodiments, the mask may include a plurality of chip regions arranged in an array along a third direction and a fourth direction, and a scribe lane region located between any two adjacent chip regions; wherein, both the third direction and the fourth direction are parallel to the mask and the third direction and the fourth direction intersect.

[0050] Figure 1 The number of the first alignment pattern 110 and the second alignment pattern 112 shown is relatively large. To more clearly show the first alignment pattern 110 and the second alignment pattern 112, provided here Figure 2 . Refer to Figure 2 , Figure 2 is a schematic structural diagram of the mask provided by the first embodiment of the present disclosure. As Figure 2 shown, a first alignment pattern 110 is provided in the first region 102 of the mask 100, a second alignment pattern 112 is provided in the second region 104 of the mask 100, and the first alignment pattern 110 and the second alignment pattern 112 together form an alignment mask pattern 108.

[0051] As Figure 2 shown, in some embodiments, the size of the third region 106 along the third direction (such as Figure 2 shown as D3 in) is less than 40 μm, that is, L is less than 40 μm; wherein, the third direction is parallel to the mask and the first region 102, the third region 106, and the second region 104 are arranged along the third direction.

[0052] It should be noted that if the first alignment pattern 110 in the first region 102 continues to extend in the first direction into the third region 106, and the second alignment pattern 112 in the second region 104 continues to extend in the second direction into the third region 106, the first alignment pattern 110 and the second alignment pattern 112 intersect in the third region 106. In fact, the alignment signal intensity of the first region 102 and the second region 104 of the mask 100 is relatively strong, while the alignment signal of the third region 106 of the mask 100 is relatively weak. That is, alignment can be achieved by using the first alignment pattern 110 in the first region 102 of the mask 100 and the second alignment pattern 112 in the second region 104 of the mask 100, without using the third region 106 of the mask 100.

[0053] Here, the first region 102, the third region 106, and the second region 104 are arranged in sequence along the third direction. The first alignment pattern 110 is provided in the first region 102, the second alignment pattern 112 is provided in the second region 104, and the alignment mask pattern 108 is not provided in the third region 106. Considering that even if the third region of the mask includes an alignment mask pattern, its alignment signal is relatively weak. Therefore, not setting the alignment mask pattern in the third region of the mask will not affect the alignment signal of the mask, that is, not including the alignment mask pattern in the third region of the mask will not affect the alignment process.

[0054] As Figure 2 shown, in some embodiments, the alignment mask pattern 108 includes an axisymmetric figure.

[0055] Here, the alignment mask pattern 108 includes an axisymmetric figure, that is, the first alignment pattern 110 and the second alignment pattern 112 are axisymmetric about the axis of symmetry. The first alignment pattern 110 extends in the first direction and the second alignment pattern 112 extends in the second direction, that is, the first direction and the second direction are axisymmetric about the axis of symmetry 114.

[0056] In some specific embodiments, the included angle between the first direction and the second direction is 90 degrees, then the included angles between the first direction, the second direction, and the axis of symmetry are all 45 degrees. In some other specific embodiments, the included angle between the first direction and the second direction is 60 degrees, then the included angles between the first direction, the second direction, and the axis of symmetry are all 30 degrees. The axis of symmetry bisects the included angle between the first direction and the second direction.

[0057] In some embodiments, the sizes of different first alignment patterns 110 in the first region 102 along the third direction may be the same or different. Correspondingly, the sizes of different second alignment patterns 112 in the second region 104 along the third direction may be the same or different.

[0058] In some embodiments, the spacing between two adjacent first alignment patterns 110 in the first region 102 in the third direction may be the same or different. Correspondingly, the spacing between two adjacent second alignment patterns 112 in the second region 104 in the third direction may be the same or different.

[0059] As Figure 2 shown, in some embodiments, the axis of symmetry 114 of the axisymmetric figure (schematically shown by the dashed line in Figure 2 ) coincides with the midline of the third region 106, and the axis of symmetry 114 extends along the fourth direction (schematically shown as D4 in Figure 2 ). The first alignment pattern 110 and the second alignment pattern 112 are axisymmetric about the axis of symmetry 114. Among them, the fourth direction is parallel to the mask 100, and the fourth direction and the third direction are perpendicular to each other.

[0060] Here, the third region 106 may also be a quadrilateral. The third region 106 includes two opposite sides along the third direction and two opposite sides along the fourth direction. The midline of the third region 106 may extend along the fourth direction, and the midline divides the third region 106 into two equal parts.

[0061] Here, the alignment mask pattern 108 is a pair. A pair of alignment mask patterns 108 includes a first alignment pattern 110 and a second alignment pattern 112, and a pair of alignment mask patterns 108 forms an axisymmetric figure.

[0062] Here, the first alignment pattern 110 includes a strip-shaped figure extending along the first direction, and the lengths of multiple first alignment patterns 110 may be the same or different; the second alignment pattern 112 includes a strip-shaped figure extending along the second direction, and the lengths of multiple second alignment patterns 112 may be the same or different. The present disclosure has no special limitations on the lengths and shapes of the first alignment pattern 110 and the second alignment pattern 112.

[0063] As Figure 2 shown, in some embodiments, the angles between the first direction and the third direction and the fourth direction are both 45 degrees; the angles between the second direction and the third direction and the fourth direction are both 45 degrees.

[0064] Here, the third direction and the fourth direction are perpendicular to each other, and the first direction and the second direction are perpendicular to each other. The alignment mask pattern 108 includes a first alignment pattern 110 extending along the first direction in the first region 102 and a second alignment pattern 112 extending along the second direction in the second region 104. The extending directions of the first alignment pattern 110 and the second alignment pattern 112 are perpendicular to each other. In this way, the alignment process in two mutually perpendicular directions can be simultaneously achieved by using the alignment mask pattern 108 of the mask 100.

[0065] AsFigure 2 As shown, in some embodiments, the first alignment pattern 110 includes a strip-shaped pattern extending in the first direction; the dimension of the first alignment pattern 110 in the third direction (i.e., d1) and the dimension of the spacing (i.e., s1) between any two adjacent first alignment patterns 110 in the third direction are the same; the second alignment pattern 112 includes a strip-shaped pattern extending in the second direction; the dimension of the second alignment pattern 112 in the third direction (i.e., d2) and the dimension of the spacing (i.e., s2) between any two adjacent second alignment patterns 112 in the third direction are the same.

[0066] Here, the width of the first alignment pattern 110 (i.e., d1) and the spacing between any two adjacent first alignment patterns 110 (i.e., s1) are both 1 / 2 of the pitch; the width of the second alignment pattern 112 (i.e., d2) and the spacing between any two adjacent second alignment patterns 112 (i.e., s2) are both 1 / 2 of the pitch. For example, if the pitch is 3.2 μm, s1, d1, s2, and d2 are all 1.6 μm. Another example, if the pitch is 7.8 μm, s1, d1, s2, and d2 are all 3.9 μm. Another example, if the pitch is 9.0 μm, s1, d1, s2, and d2 are all 4.5 μm.

[0067] Reference Figure 3 , Figure 3 is a schematic structural diagram of a mask provided in the second embodiment of the present disclosure. As Figure 3 shown, in some embodiments, the first alignment pattern 110 (as Figure 3 schematically shown by the dotted strip-shaped pattern) includes a plurality of first marker patterns 116 arranged at intervals in the first direction; the second alignment pattern 112 (as Figure 3 schematically shown by the dotted strip-shaped pattern) includes a plurality of second marker patterns 118 arranged at intervals in the second direction; wherein, the distribution density of the first marker patterns 116 and the distribution density of the second marker patterns 118 are the same.

[0068] Here, the first alignment pattern 110 includes a plurality of first marker patterns 116 arranged at intervals in the first direction and the interval regions between any two adjacent first marker patterns 116; the second alignment pattern 112 includes a plurality of second marker patterns 118 arranged at intervals in the second direction and the interval regions between any two adjacent second marker patterns 118. For example, the first marker pattern 116 can be a filling unit for filling the first alignment pattern 110, and the second marker pattern 118 can be a filling unit for filling the second alignment pattern 112.

[0069] Here, the first marking pattern 116 may be arranged periodically along a first direction, and the second marking pattern 118 may be arranged periodically along a second direction. In some embodiments, the first marking pattern 116 may be uniformly arranged along the first direction, and the second marking pattern 118 may be uniformly arranged along the second direction. In other embodiments, the first marking pattern 116 may be non-uniformly arranged along the first direction, and the second marking pattern 118 may be non-uniformly arranged along the second direction.

[0070] Here, the first marking pattern 116 extends along a fourth direction, and the extending direction of the first marking pattern 116 is different from and forms an angle with the extending direction of the first alignment pattern 110; the second marking pattern 118 extends along the fourth direction, and the extending direction of the second marking pattern 118 is different from and forms an angle with the extending direction of the second alignment pattern 112.

[0071] Here, the shapes of the first marking pattern 116 and the second marking pattern 118 may be various. For example, Figure 3 schematically shows that the shapes of both the first marking pattern 116 and the second marking pattern 118 are strip-shaped graphics.

[0072] In some embodiments, the first marking pattern 116 and the second marking pattern 118 are axisymmetric about the axis of symmetry 114. Here, the first marking pattern 116 and the second marking pattern 118 are axisymmetric about the axis of symmetry 114, that is, the shapes, sizes, and distribution densities of the first marking pattern 116 and the second marking pattern 118 are the same.

[0073] Reference Figure 4 , Figure 4 is a schematic flow chart of a method for designing a mask provided by an embodiment of the present disclosure.

[0074] As Figure 4 shown, an embodiment of the present disclosure provides a method for designing a mask. The design method includes:

[0075] Step S401: Set a first region, a second region, and a third region located between the first region and the second region on the mask;

[0076] Step S402: Set alignment mask patterns on the mask. The alignment mask patterns include a plurality of first alignment patterns located in the first region and extending along a first direction, and a plurality of second alignment patterns located in the second region and extending along a second direction; wherein, both the first direction and the second direction are parallel to the mask and the first direction and the second direction intersect.

[0077] In an embodiment of the present disclosure, a photomask includes a first region, a second region, and a third region located between the first region and the second region. The photomask includes alignment photomask patterns, and the alignment photomask patterns include a first alignment pattern and a second alignment pattern. Among them, a plurality of first alignment patterns extending in a first direction are provided in the first region, and a plurality of second alignment patterns extending in a second direction are provided in the second region. By using the designed photomask for the lithography process to form alignment marks, not only can the alignment function of the alignment marks be realized, but also problems such as cracking or fading of the alignment marks can be avoided, thereby avoiding damage to the chip patterns in the chip region, and further improving the quality and performance of the semiconductor structure.

[0078] In an embodiment of the present disclosure, a Critical Dimension Scanning Electron Microscope (CDSEM) can be used to automatically take fixed-point photos (Auto Process Inspection, API) of the semiconductor structure to determine whether the photomask provided in the embodiment of the present disclosure is used for the lithography process.

[0079] Reference Figure 5 , Figure 5 is a schematic flow chart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure. As Figure 5 shown, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, and the manufacturing method includes:

[0080] Step S501: Form a first material layer, a second material layer, and a photoresist layer that are stacked in sequence;

[0081] Step S502: Using the photomask in the above technical solution as a mask, expose and develop the photoresist layer to form a patterned photoresist layer;

[0082] Step S503: Using the patterned photoresist layer as a mask, etch the second material layer to form a plurality of first grooves extending in the first direction and a plurality of second grooves extending in the second direction;

[0083] Step S504: Fill the first grooves and the second grooves to form a first alignment mark and a second alignment mark respectively; among them, the first alignment mark and the second alignment mark jointly form an alignment mark; both the first direction and the second direction are parallel to the first material layer and the first direction and the second direction intersect.

[0084] The photomask provided by the embodiment of the present disclosure has no special limitation on the process layer in the lithography process, nor on the material of the stacked film layer, and has a wide application range.

[0085] Reference Figures 6A to 6E , Figures 6A to 6EThis is a schematic cross-sectional structure diagram of a semiconductor structure during manufacturing. The following will be combined with Figure 5 and Figures 6A to 6E to describe in detail the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure.

[0086] As Figure 6A shown, in step S501, a first material layer 602, a second material layer 604, and a photoresist layer 612 are formed to be stacked in sequence.

[0087] The present disclosure does not have special limitations on the materials of the first material layer 602 and the second material layer 604. In some embodiments, the materials of the first material layer 602 and the second material layer 604 are the same or different.

[0088] Here, the second material layer 604 may include a first region 606, a second region 608, and a third region 610 located between the first region 606 and the second region 608. The first region 606, the third region 610, and the second region 608 are arranged in sequence along the third direction. The first alignment pattern in the first region of the mask plate, after the lithography process, correspondingly forms a first alignment mark in the first region 606 of the second material layer 604; the second alignment pattern in the second region of the mask plate, after the lithography process, correspondingly forms a second alignment mark in the second region 608 of the second material layer 604. That is, the first region of the mask plate corresponds to the first region 606 of the second material layer 604, the second region of the mask plate corresponds to the second region 608 of the second material layer 604, and the third region of the mask plate corresponds to the third region 610 of the second material layer 604.

[0089] In the embodiments of the present disclosure, the plane where the first material layer 602 is located is parallel to the plane where the mask plate is located. Therefore, the first direction, the second direction, the third direction, and the fourth direction defined in the plane where the first material layer 602 is located are the same as the first direction, the second direction, the third direction, and the fourth direction defined in the plane where the mask plate is located, respectively. Further, the thickness direction of the first material layer 602 is defined as the fifth direction (as Figure 6A schematically shows D5), and the fifth direction is perpendicular to the first material layer 602. Figures 6A to 6D Schematically shows a cross-sectional structure diagram of the plane formed by the third direction and the fifth direction.

[0090] As Figure 6A and Figure 6B shown, in step S502, using the mask plate in the above technical solution as a mask, the photoresist layer 612 is exposed and developed to form a patterned photoresist layer 614.

[0091] As Figure 6B and Figure 6CAs shown, in step S503, using the patterned photoresist layer 614 as a mask, the second material layer 604 is etched to form a plurality of first grooves 616 extending in a first direction and a plurality of second grooves 618 extending in a second direction.

[0092] Here, the depth of the first grooves 616 can be the same as the thickness of the second material layer 604; the depth of the second grooves 618 can be the same as the thickness of the second material layer 604.

[0093] As Figure 6C and Figure 6D shown, in step S504, the first grooves 616 and the second grooves 618 are filled to form a first alignment mark 622 and a second alignment mark 624 respectively; wherein, the first alignment mark 622 and the second alignment mark 624 together form an alignment mark 620; both the first direction and the second direction are parallel to the first material layer 602 and the first direction and the second direction intersect.

[0094] Here, the materials of the first alignment mark 622 and the second alignment mark 624 can be metal materials or non-metal materials. The materials of the first alignment mark 622 and the second alignment mark 624 are different from the material of the second material layer 604, so that the first alignment mark 622 and the second alignment mark 624 can be identified in the second material layer 604, and the alignment process is realized by using the alignment signals of the first alignment mark 622 and the second alignment mark 624.

[0095] Figure 6D is Figure 6E the schematic cross-sectional structure diagram along the D-D section in. As Figure 6D and Figure 6E shown, an embodiment of the present disclosure provides a semiconductor structure, and the semiconductor structure 600 includes: a first material layer 602 and a second material layer 604 located on the first material layer 602; the second material layer 604 includes a first region 606, a second region 608 and a third region 610 located between the first region 606 and the second region 608; an alignment mark 620 located in the second material layer 604; the alignment mark 620 includes a plurality of first alignment marks 622 located in the first region 606 and extending in the first direction, and a plurality of second alignment marks 624 located in the second region 608 and extending in the second direction; wherein, both the first direction and the second direction are parallel to the first material layer 602 and the first direction and the second direction intersect.

[0096] In some embodiments, the alignment mark 620 includes an axisymmetric figure.

[0097] Here, each first alignment mark 622 and a second alignment mark 624 are axisymmetric about the axis of symmetry.

[0098] In some embodiments, the third region 610 does not include alignment marks.

[0099] Embodiments of the present disclosure provide a mask and a design method thereof, a semiconductor structure and a manufacturing method thereof. The mask includes a first region, a second region, and a third region located between the first region and the second region; the mask includes an alignment mask pattern, the alignment mask pattern includes a plurality of first alignment patterns located in the first region and extending along a first direction, and a plurality of second alignment patterns located in the second region and extending along a second direction; wherein, both the first direction and the second direction are parallel to the mask and the first direction and the second direction intersect. In the embodiments of the present disclosure, the mask includes a first region, a second region, and a third region located between the first region and the second region, the mask includes an alignment mask pattern, the alignment mask pattern includes a first alignment pattern and a second alignment pattern, wherein, a plurality of first alignment patterns extending along the first direction are provided in the first region, and a plurality of second alignment patterns extending along the second direction are provided in the second region; thus, using the above mask for a lithography process to form alignment marks can not only achieve the alignment function of the alignment marks, but also avoid problems such as cracking or fading of the alignment marks, thereby avoiding damage to the chip patterns in the chip region, and further improving the quality and performance of the semiconductor structure.

[0100] It should be understood that the term "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of the phrase "in one embodiment" or "in an embodiment" throughout the specification are not necessarily referring to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution is prior or subsequent, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0101] The above are only the preferred embodiments of the present disclosure, and do not limit the patent scope of the present disclosure. Any equivalent structural transformation made under the inventive concept of the present disclosure by using the content of the specification and drawings of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A photomask, characterized in that, The mask includes a first region, a second region, and a third region located between the first region and the second region; The mask includes alignment mask patterns, the alignment mask patterns including a plurality of first alignment patterns located in the first region and extending along a first direction, and a plurality of second alignment patterns located in the second region and extending along a second direction; wherein, both the first direction and the second direction are parallel to the mask and the first direction and the second direction intersect.

2. The mask according to claim 1, wherein The alignment mask patterns include axisymmetric figures.

3. The photomask according to claim 2, wherein The dimension of the third region along a third direction is less than 40 μm; wherein, the third direction is parallel to the mask and the first region, the third region, and the second region are arranged along the third direction.

4. The mask according to claim 3, characterized in that, The axis of symmetry of the axisymmetric figure coincides with the midline of the third region and the axis of symmetry extends along a fourth direction, and the first alignment patterns and the second alignment patterns are axisymmetric about the axis of symmetry; wherein, the fourth direction is parallel to the mask and the fourth direction and the third direction are perpendicular to each other.

5. The photomask according to claim 4, wherein, The first alignment patterns include strip-shaped figures extending along the first direction; the dimension of the first alignment patterns along the third direction is the same as the dimension of the spacing between any two adjacent first alignment patterns along the third direction; The second alignment patterns include strip-shaped figures extending along the second direction; the dimension of the second alignment patterns along the third direction is the same as the dimension of the spacing between any two adjacent second alignment patterns along the third direction.

6. The photomask according to claim 4, wherein The first alignment patterns include a plurality of first marker patterns arranged at intervals along the first direction; the second alignment patterns include a plurality of second marker patterns arranged at intervals along the second direction; wherein, the distribution density of the first marker patterns is the same as the distribution density of the second marker patterns.

7. The photomask according to claim 6, wherein The first marker patterns and the second marker patterns are axisymmetric about the axis of symmetry.

8. The photomask according to claim 4, wherein The angles between the first direction and the third direction, the fourth direction are both 45 degrees; the angles between the second direction and the third direction, the fourth direction are both 45 degrees.

9. The mask according to claim 1, wherein The third region does not include the alignment mask patterns.

10. The photomask according to claim 1, wherein The mask includes a chip region and a scribe line region surrounding the chip region; wherein, the first region, the third region, and the second region are all located in the scribe line region.

11. A design method of a photomask, characterized in that, The design method includes: Setting a first region, a second region, and a third region located between the first region and the second region on the mask; Setting alignment mask patterns on the mask, the alignment mask patterns including a plurality of first alignment patterns located in the first region and extending along a first direction, and a plurality of second alignment patterns located in the second region and extending along a second direction; wherein, both the first direction and the second direction are parallel to the mask and the first direction and the second direction intersect.

12. A manufacturing method of a semiconductor structure, characterized in that, The manufacturing method includes: Forming a first material layer, a second material layer, and a photoresist layer stacked in sequence; Using the photomask according to any one of claims 1 to 10 as a mask, exposing and developing the photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching the second material layer to form a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction; Filling the first grooves and the second grooves to form first alignment marks and second alignment marks respectively; wherein, the first alignment marks and the second alignment marks together form alignment marks; the first direction and the second direction are both parallel to the first material layer and the first direction and the second direction intersect.

13. A semiconductor structure, characterized in that, The semiconductor structure includes: A first material layer and a second material layer located on the first material layer; the second material layer includes a first region, a second region, and a third region located between the first region and the second region; Alignment marks located in the second material layer; the alignment marks include a plurality of first alignment marks located in the first region and extending in a first direction, and a plurality of second alignment marks located in the second region and extending in a second direction; wherein, the first direction and the second direction are both parallel to the first material layer and the first direction and the second direction intersect.

14. The semiconductor structure according to claim 13, wherein The alignment marks include an axisymmetric figure.

15. The semiconductor structure according to claim 13, wherein, The third region does not include the alignment marks.

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