Three-dimensional integrated complete machine system of chip-scale atomic clock

Abstract

The invention relates to a three-dimensional integrated complete machine system of a chip-scale atomic clock. The device comprises an energy supply battery, a crystal oscillator and a stacking base which are arranged on a PCB (Printed Circuit Board), an integrated stacking assembly and a stacking upper cover are sequentially arranged on a stacking base, the integrated stacking assembly is of a hollow structure, the stacking base, the integrated stacking assembly and the stacking upper cover are stacked to form a stacking base body structure with a cavity, and a chip-level atomic clock physical system is placed in the cavity of the stacking base body. A magnetic isolation material layer is arranged on the surface of an inner cavity of the stacking base body, and IC chips and protective shells are arranged on the four surfaces of the outer side of the stacking base body. Electrical three-dimensional transmission is carried out in the stacked substrate through the through hole structure filled with the copper columns and the rewiring layer, and mutual communication among the PCB, the physical system and the IC chip is achieved. And three-dimensional integration of the atomic clock complete machine system structure is realized.

Description

Technical Field

[0001] This application relates to the technical field of atomic clocks, and particularly to a three-dimensional integrated whole machine system of a chip-level atomic clock. Background Art

[0002] An atomic clock is the current time-frequency system with the highest stability and accuracy, and is an essential device for navigation, aerospace, and satellite navigation. With the continuous development and progress of MEMS processing technology, atomic clocks have been miniaturized and chip-sized. Chip-level atomic clocks are small in size and low in power consumption, and have good application prospects in synchronous communication and individual combat.

[0003] However, the atomic clock system is divided into a physical system and a circuit system. The physical system is the core of the entire atomic clock, the place where quantum effects occur, and records the whole process of laser emission to reception. The circuit system provides suitable conditions for the generation of quantum effects, and at the same time processes the electrical signals converted by PD and outputs accurate time-frequency signals. Regarding the integration research of chip-level atomic clocks, since the United States NIST released the world's first chip-level atomic clock prototype in 2004 until now, most researchers' research focus has been on how to further integrate and optimize the physical system, achieving quite a breakthrough. However, there are few mentions about the integration of the whole atomic clock system, which restricts the chipization process of atomic clocks. Summary of the Invention

[0004] Based on this, it is necessary to provide a three-dimensional integrated whole machine system structure of an atomic clock that can be compatible with most atomic clock physical systems for the above technical problems.

[0005] This application provides a three-dimensional integrated whole machine system of a chip-level atomic clock. The whole machine system includes: a PCB, a crystal oscillator, an energy supply battery, a stacked substrate, an integrated stacked component, a stacked upper cover, an IC chip for the circuit part, a chip-level atomic clock physical system, and an IC chip protective case. The crystal oscillator, the stacked substrate, the stacked upper cover, the IC chip for the circuit part, the chip-level atomic clock physical system, and the IC chip protective case are sequentially arranged on the PCB board.

[0006] In one embodiment, pads are provided on the PCB board, corresponding to the connection and fixing positions of the energy supply battery, the crystal oscillator, and the stacked substrate on the PCB. And the pads on the PCB provide a connection relationship for the energy supply battery, the crystal oscillator, and the stacked substrate. There is also a connection relationship between the pads of the stacked substrate, making the PCB become a signal "hub" connecting each IC chip or physical system.

[0007] In one embodiment, a circular through-hole is provided on the stacked substrate, and the circular through-hole is filled with a copper pillar. A redistribution layer is also provided at the position of the circular through-hole on the upper and lower surfaces of the stacked substrate, and the redistribution layer can completely cover the circular through-hole. The stacked substrate and the PCB are connected and fixed by laser ball placement.

[0008] In one embodiment, the integrated system further includes an integrated stacked component, and the integrated stacked component is a multi-layer stacked structure, and the number of layers can be adjusted according to actual needs to meet the requirements. In this embodiment, the integrated stacked component is composed of two stacked layers. The stacked layers are defined as the first stacked layer and the second stacked layer from bottom to top. The stacked layers are both "rectangular hollow" structures; a circular through-hole is provided on the first stacked layer, and the position and size correspond to those of the stacked substrate. A circular through-hole is provided on the second stacked layer, and the position and size correspond to those of the first stacked layer. The through-hole structures in the integrated stacked component are all filled with copper pillars. The first stacked layer is disposed above the stacked substrate, and the second stacked layer is disposed above the first stacked layer. A redistribution layer is provided at the position of the through-hole on the upper surface and the side surface of the first stacked layer and the second stacked layer. The redistribution layer can completely cover the through-hole and is connected to the copper pillar to ensure normal electrical connection and transmission of the upper and lower stacked structures of the redistribution layer. At the same time, the redistribution layer on the outer side of the upper surface of the first stacked layer and the redistribution layer of the second stacked layer extend outward to the boundary, and redistribution layers are also provided at the corresponding positions on the side surfaces of the first and second stacked layers and are connected thereto, forming an "L"-shaped wiring structure.

[0009] In one embodiment, the chip-level atomic clock three-dimensional integrated whole machine system further includes a stacked upper cover, and the stacked upper cover is disposed above the integrated stacked component, that is, above the second stacked layer. The stacked substrate, the integrated stacked component and the stacked upper cover are connected and fixed to form a cuboid stacked matrix structure. Since the stacked layers in the integrated stacked component are "rectangular hollow" structures, there is a cuboid cavity inside the stacked matrix formed by stacking.

[0010] In one embodiment, the chip-level atomic clock three-dimensional integrated whole machine system further includes a magnetic isolation material, and the magnetic isolation material is disposed on the upper surface of the stacked substrate corresponding to the non-redistribution area of the "rectangular hollow" area of the integrated stacked component, and / or on the inner surface of the "hollow" structure of the integrated stacked component, that is, the inner cavity surface of the stacked matrix, and / or in the intersection area of the lower surface of the stacked upper cover and the upper surface of the inner cavity of the stacked matrix.

[0011] In one embodiment, the integrated system further includes a chip-level atomic clock physical system, which includes: a laser, optical elements, an atomic gas cell, a heating and temperature-measuring electrode, and a PD photodiode. It can realize functions such as laser emission, optical path adjustment, temperature measurement and control, atomic resonance, and signal acquisition. And the chip-level atomic clock physical system includes an integrated substrate, on which TSV and RDL are provided for integrating the input and output interfaces of all physical systems and circuit systems. The chip-level atomic clock physical system is arranged inside the hollow cuboid structure formed by connecting and fixing the stacked substrate, the integrated stacked component, and the stacked upper cover above the stacked substrate, and the integrated substrate of the chip-level atomic clock physical system is connected to the redistribution layer on the upper surface of the stacked substrate by means of laser ball implantation.

[0012] In one embodiment, the integrated system further includes a circuit system IC chip, which includes: a microwave circuit chip, an FPGA main control chip, a temperature control chip, and a laser driver chip, which are defined as the first chip, the second chip, the third chip, and the fourth chip in sequence. The first to fourth chips are surface-mounted and fixed on the four outer surfaces of the integrated stacked component.

[0013] In one embodiment, the integrated system further includes an IC chip protective case. In this embodiment, there are a total of four IC chip protective cases. The IC chip protective case has grooves and is arranged on the four outer sides of the cuboid structure formed by the integrated stacked component and the stacked upper cover. The groove surface is in contact and fixed with the stacked substrate, and the center position of the groove is consistent with the center of the IC chip.

[0014] The above chip-level atomic clock whole machine system structure includes: a PCB, a crystal oscillator, a power supply battery, a stacked substrate, an integrated stacked component, a stacked upper cover, a circuit part IC chip, a chip-level atomic clock physical system, and an IC chip protective case. The power supply battery, the crystal oscillator, and the stacked substrate are arranged at corresponding positions on the PCB. The integrated stacked component and the stacked upper cover are sequentially stacked on the stacked substrate to form a stacked substrate with a cuboid cavity inside; the chip-level atomic clock physical system is embedded inside the hollow stacked substrate; a magnetic shielding material is arranged on the inner hollow surface of the stacked substrate to form a magnetic shielding protective case to reduce the interference of the external magnetic field. Four circuit part IC chips are surface-mounted on the four outer sides of the stacked substrate, and at the same time, a protective case with a groove structure is arranged above the chips. Through holes filled with copper pillars and redistribution layers are arranged on the stacked substrate and the integrated stacked component to realize electrical connections in the vertical and horizontal planes, achieving integration and interconnection in multiple directions and effectively improving the system integration degree. Description of the Drawings

[0015] Figure 1 It is a schematic diagram of the chip-level atomic clock whole machine system structure in some embodiments of the present application; Figure 2 Schematic diagram of the structural disassembly of the chip-level atomic clock whole machine system in some embodiments of the present application; Figure 3 Schematic diagram of the stacked substrate, integrated stacked component and stacked upper cover in some embodiments of the present application; Figure 4 Schematic diagram of the stacked substrate in some embodiments of the present application; Figure 5 Schematic diagram of the first stacked layer in some embodiments of the present application; Figure 6 Schematic diagram of the second stacked layer in some embodiments of the present application; Figure 7 Schematic diagram of the stacked upper cover in some embodiments of the present application; Figure 8 Schematic diagram of the chip-level atomic clock physical system in some embodiments of the present application; Figure 9 System block diagram of the atomic clock whole machine system in some embodiments of the present application; Description of reference numerals: 0, PCB; 1, crystal oscillator; 2, power supply battery; 3, stacked substrate; 4, integrated stacked component; 5, stacked upper cover; 6, magnetic isolation material; 7, chip-level atomic clock physical system; 8, circuit part IC chip; 9, IC chip protective case; 31, first re-wiring layer; 41, first stacked layer; 42, second stacked layer; 411, second re-wiring layer; 421, third re-wiring layer; 71, lumped substrate; 72, laser; 73, atomic gas cell; 61, stacked substrate magnetic isolation material; 62, cavity side magnetic isolation material; 63, stacked upper cover magnetic isolation material; 81, microwave chip; 82, laser drive chip; 83, temperature control chip; 84, FPGA chip; 91, microwave chip protective case; 92, laser drive chip protective case; 93, temperature control chip protective case; 94, FPGA chip protective case Detailed implementation manners

[0016] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0017] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present application.

[0018] In the present application, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is at least two, for example, two, three, etc., unless otherwise specifically and clearly defined.

[0019] In the present application, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0020] In the present application, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0021] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are only for illustrative purposes and do not represent the only implementation.

[0022] Figure 1 As shown in the structural schematic diagram of the chip-level atomic clock whole machine system in an embodiment, Figure 1 As shown, the whole machine system includes: PCB, crystal oscillator, energy supply battery, stacked substrate, integrated stacked component, stacked upper cover, circuit part IC chip, chip-level atomic clock physical system and IC chip protective case. The energy supply battery, crystal oscillator and stacked substrate are arranged on the PCB; the integrated stacked component and the stacked upper cover are sequentially arranged on the stacked substrate; the chip-level atomic clock physical system is embedded in the integrated stacked component; the circuit part IC chip is mounted on the outer surface of the integrated stacked component; the IC chip protective case is arranged directly above the IC chip.

[0023] Specifically, for the chip-level atomic clock whole machine system in this embodiment, if the position where the PCB is located is regarded as the bottom of the whole system, then interconnected pads are arranged on the upper surface of the PCB, and the crystal oscillator and the energy supply battery are sequentially welded on the corresponding pads; the stacked substrate has a circular through hole, and the circular through hole is completely filled with copper pillars, and a redistribution layer is also provided at the through hole position on the upper and lower surfaces of the stacked substrate, and the redistribution layer can cover the through hole and be in contact connection with the copper pillars. The pads on the PCB are connected to the redistribution layer on the lower surface of the stacked substrate by means of laser ball placement to provide an electrical path and play a supporting role at the same time.

[0024] Furthermore, as Figure 3 shown, the first stacked layer and the second stacked layer of the integrated stacked component are sequentially arranged above the stacked substrate; the stacked layers are all hollow rectangular structures and are all provided with circular through holes filled with copper pillars. The through holes on the lower surface of the first stacked layer correspond to the redistribution layer on the upper surface of the stacked substrate, and the copper pillars are connected to the redistribution layer to ensure normal electrical transmission. At the same time, a redistribution layer is arranged on the upper surface of the first stacked layer, and the position of the redistribution layer is consistent with the through hole position and can cover the through hole. The redistribution layer located at the outer through hole extends towards the outer surface to the side, and at the same time, a redistribution layer is also arranged on the side of the first stacked layer to ensure that the redistribution layers in two directions are connected at the intersection, realizing three-dimensional electrical interconnection.

[0025] The vias on the lower surface of the second stacked layer correspond to the inner re - distribution layer on the upper surface of the first stacked layer, and the copper pillars are connected to the re - distribution layer to ensure the normal transmission of electrical signals from the stacked substrate to the first stacked layer and then to the second stacked layer. A re - distribution layer is provided on the upper surface of the second stacked layer. The starting position of the re - distribution layer is at its via position and extends towards the outer surface direction to the side. At the same time, a re - distribution layer is also provided on the side surface of the second stacked layer to ensure that the re - distribution layers in two directions are connected at the intersection.

[0026] Further, a stacked upper cover is provided above the integrated stacked component to protect the cavity formed by the hollow structure in the integrated stacked component.

[0027] Further, a magnetic shielding material is provided inside the cavity formed by the stacked substrate, the integrated stacked component, and the stacked upper cover. It should be noted that the magnetic shielding material on the lower surface of the cavity is set in the intersection part of the non - re - distribution layer area on the upper surface of the stacked substrate and the projection area of the cavity, because some magnetic shielding materials have conductivity and cannot be connected to the re - distribution layer; the magnetic shielding material on the upper surface of the cavity is set in the projection area of the cavity on the lower surface of the stacked upper cover. The magnetic shielding materials on the six surfaces are closely seamless at the intersections to shield the interference of the external magnetic field for the generation of quantum effects.

[0028] Specifically, the magnetic shielding material can be permalloy or other materials with higher magnetic permeability.

[0029] Further, the chip - level atomic clock physical system is embedded inside the cavity. Laser ball - mounting the RDL on the lower surface of the lumped substrate of the chip - level atomic clock physical system and the re - distribution layer on the upper surface of the stacked substrate realizes electrical connection and provides a supporting role.

[0030] Further, the circuit - part IC chips are arranged on the four side surfaces of the integrated stacked component. The pads on the chips are patch - connected to the re - distribution layers provided on the side surfaces of the first stacked layer and the second stacked layer; Further, the IC chip protection case has a grooved structure. The center of the groove corresponds to the center of the chip. The inner - side surface of the IC chip protection case contacts and fixes with the integrated stacked component. The IC chip protection case is fixed on the outer - side surface of the integrated stacked component by pasting.

[0031] When the system works, the communication transmission between each IC chip and the chip - level atomic clock physical system or between IC chips first transmits the signal to the PCB pads through connection components such as copper pillars, re - distribution layers, and solder balls. There is a preset connection relationship inside the PCB pads, and then the PCB pads transmit the signal back to the physical system or IC chips through copper pillars, re - distribution layers, and solder balls.

[0032] Such as Figure 5As shown in the system block diagram of the atomic clock whole machine system, the crystal oscillator first emits the clock signal to be measured, which is transmitted to the microwave chip for frequency synthesis. At the same time, the laser drive circuit generates the drive current required by the laser and couples it with the microwave signal output by the microwave chip, and then transmits the coupled signal to the physical system. In the physical system, the laser receives the coupled signal and outputs an optical field. The optical field is adjusted in terms of light intensity and polarization under the action of optical elements and then enters the atomic gas cell to cause atomic resonance. Then, the PD receives the optical signal, converts the optical signal into an electrical signal, outputs it to the FPGA chip for calculation and analysis, and outputs a feedback signal to the crystal oscillator to adjust the output frequency. At the same time, the temperature control chip continuously interacts with the physical system and the FPGA chip to keep the temperature of the physical system in the optimal state.

Claims

1. A three-dimensional integrated whole machine system of a chip-level atomic clock, characterized in that The chip-level atomic clock integration system includes: a power supply battery, a PCB board, a crystal oscillator, an atomic clock circuit system IC chip, a chip-level atomic clock physical system, an integrated stacking component, a stacking substrate, a stacking upper cover, and an IC chip protective case. The power supply battery, the crystal oscillator, and the stacking substrate component are arranged on the PCB board. The integrated stacking component is arranged above the stacking substrate, and the stacking upper cover is arranged above the integrated stacking component. The stacking substrate, the integrated stacking component, and the stacking upper cover are stacked from bottom to top to form a stacking matrix structure with a rectangular parallelepiped cavity structure inside. The chip-level atomic clock physical system is arranged inside the rectangular parallelepiped cavity of the stacking matrix and is fixedly connected to the stacking substrate. The atomic clock circuit system IC chip is arranged on the four side surfaces outside the stacking matrix, and the IC chip protective case is arranged above the IC chip and is fixedly connected to the outer surface of the stacking matrix.

2. The three-dimensional integrated system of a chip-scale atomic clock according to claim 1, characterized in that: The stacking substrate is provided with a circular through hole, and a copper column is arranged inside the circular through hole, and the copper column completely fills the through hole. Rewiring layers are arranged on the upper and lower surfaces of the stacking substrate at the position of the circular through hole, and the area of the rewiring layer is slightly larger than the area of the circular through hole and completely covers it.

3. The stacked substrate according to claim 1, wherein The upper surface of the stacking substrate further includes a magnetic isolation material layer, and the magnetic isolation material layer is arranged in the non-rewiring layer area of the upper surface of the stacking substrate, and there is a gap between the magnetic isolation material layer and the rewiring layer.

4. The three-dimensional integrated whole machine system of the chip-level atomic clock according to claim 1, characterized in that, The integrated stacking component includes at least one stacking layer, and the stacking layer is a "hollowed-out" structure in the middle. The solid part of the stacking layer is provided with a circular through hole, and the position of the through hole corresponds to the position of the through hole on the stacking substrate. A copper column is arranged inside the circular through hole, and the copper column completely fills the through hole.

5. The integrated stacked component according to claim 4, wherein The stacking layer further includes a rewiring layer. The rewiring layer is arranged at the position of the through hole on the upper surface of the stacking layer, and the area is slightly larger than the area of the circular through hole and completely covers it, and / or the rewiring layer is arranged on the outer surface of the stacking layer and is connected to the rewiring layer on the upper surface to form an "L" shape.

6. The three-dimensional integrated whole machine system of the chip-level atomic clock according to claim 1, characterized in that, The stacking upper cover is arranged above the integrated stacking component, and a magnetic isolation material layer is arranged on the lower surface of the stacking upper cover facing the integrated stacking component. The shape and position of the magnetic isolation material layer correspond to the "hollowed-out" structure of the integrated stacking component.

7. The stacked substrate, integrated stacked component, and stacked upper cover described in claims 1, 2, 3, 4, 5, and 6 are stacked, connected, and fixed to form a stacked substrate structure, characterized in that The inside of the stacking matrix is a rectangular parallelepiped cavity structure, and a magnetic isolation material layer is arranged on the side surface of the internal cavity.

8. The magnetic isolation material layer according to claim 6, characterized in that, The magnetic isolation material layer is arranged on the upper surface of the stacking substrate, and / or, on the side surface of the integrated matrix structure cavity, and / or, on the lower surface of the stacking upper cover by means of pasting, or is arranged on the upper surface of the stacking substrate, and / or, on the side surface of the integrated matrix structure cavity, and / or, on the lower surface of the stacking upper cover by means of magnetron sputtering, or is arranged on the upper surface of the stacking substrate by means of spraying, or is arranged on the upper surface of the stacking substrate, and / or, on the side surface of the integrated matrix structure cavity, and / or, on the lower surface of the stacking upper cover by means of electroplating.

9. The three-dimensional integrated system of a chip-level atomic clock according to claim 1 further comprises a chip-level atomic clock physical system, characterized in that: The chip-level atomic clock physical system includes a laser, optical elements, an atomic gas cell, heating and temperature-measuring electrodes, and a PD photodiode. Under the action of an external drive current, a temperature control potential signal, a temperature-measuring signal, and a PD potential signal, the laser emits laser light, the adjustment of the light intensity and polarization state is achieved in the optical elements, the "resonance" phenomenon occurs between the laser light and alkali metal atoms in the atomic gas cell, the light signal is converted into an electrical signal in the PD, the real-time temperature is fed back by measuring the resistance value of the temperature-measuring electrode, and the temperature is adjusted by applying the temperature control potential signal to the heating electrode. All the input and output signals in the chip-level atomic clock physical system are gathered on a lumped substrate, and the outer surface of the lumped substrate is fixedly connected to the redistribution layer of the stacked substrate through laser ball implantation. The physical system is embedded in the internal cavity of the stacked substrate.

10. The three-dimensional integrated whole machine system of the chip-level atomic clock according to claim 1, characterized in that, The circuit system IC chip includes: a microwave circuit chip, a temperature control chip, a laser driver chip, and an FPGA main control chip; the microwave circuit chip can perform frequency multiplication, modulation, amplification, and frequency synthesis operations on the signal output by the crystal oscillator and output a microwave signal; the laser driver chip can generate the drive current of the laser and couple and output the drive current and the microwave signal; the temperature control chip can measure and control the temperature of the physical system; the FPGA chip serves as the logic calculation chip of the entire system.

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