A low-power phased array ultrasonic transceiver switch control system

Abstract

The present invention relates to the technical field of transceiver switch circuit design, and in particular to a low-power phased array ultrasonic transceiver switch control system, comprising a control circuit, a transmitting circuit, and a T / R chipset; the control circuit being configured to receive an input clock signal CLK, output a high-voltage trigger signal to the transmitting circuit, and output a latch signal and an SPI communication signal to the T / R chipset; the transmitting circuit being configured to receive the high-voltage trigger signal and generate a high-voltage pulse signal synchronized with the high-voltage trigger signal to the T / R chipset; and the T / R chipset being configured to receive the latch signal, the SPI communication signal, and its high-voltage pulse signal, output a low-voltage echo signal to an amplifier circuit, and output a signal to a phased array ultrasonic transducer. The present invention utilizes a pre-storage and latching mechanism to achieve, in a ping-pong manner, closing the T / R switch during high-voltage transmission and opening the T / R switch during normal reception.

Description

Technical Field

[0001] The present invention relates to the technical field of transceiver switch circuit design, and in particular to a low-power phased array ultrasonic transceiver switch control system. Background Art

[0002] In the field of phased array ultrasonic testing, especially for portable instruments, power consumption is a key concern. Ultrasonic testing typically involves two processes: ultrasonic transmission and reception. For integrated transceivers, a high-voltage-to-low-voltage impulse is often achieved through a TR (transmitter-receiver) switch or a clamping diode circuit. However, since ultrasonic transmission typically involves voltages in the hundreds of volts, some of the transmitted energy is injected into the transceiver circuitry during the transmission phase, resulting in energy loss. For a 64-element phased array, for example, a 10mA current drawn by the TR transceiver switch, a 100ns pulse width, and a 10kHz pulse repetition frequency (PRF), the resulting energy loss is approximately 0.5W.

[0003] Specifically, in the field of phased array ultrasonic testing, isolation between high-voltage transmit pulses and low-voltage receive signals is typically achieved through a T / R transceiver switch chip. The T / R switch utilizes a constant-current source isolation bridge, leveraging the reverse-blocking and forward-conducting properties of a diode to effectively block the high-voltage ultrasonic transmit pulse while providing a path for the low-voltage signal. However, for integrated ultrasonic transceiver applications, to save energy or completely isolate the T / R circuit during retransmission, appropriate circuit control measures are required to ensure complete isolation during transmission and allow weak echo signals to pass during reception. Failure to implement this control can lead to several issues: 1) wasteful power consumption; 2) high-voltage pulse clamping circuits can cause full-amplitude spikes to be injected into subsequent amplification circuits, impacting reliability; and 3) precise timing control is required for channel T / R closing and opening. Ultrasonic signals typically range from tens to hundreds of volts, while echo signals typically range from microvolts to millivolts. However, for phased array systems, the time delay between each chip varies, and the transmission cycle dynamically changes, necessitating dynamic adjustment. At the same time, since the number of phased array circuit channels is large, such as 32 to 256, the channel configuration is often serial, resulting in a long configuration time and the inability to meet accurate switching time.

[0004] In view of this, the present invention provides a low-power phased array ultrasonic transceiver switch control system. Summary of the Invention

[0005] The object of the present invention is to provide a low-power phased array ultrasonic transceiver switch control system in response to the deficiencies of the prior art.

[0006] In order to solve the above technical problems, the following technical solutions are adopted:

[0007] A low-power phased array ultrasonic transceiver switch control system, comprising a control circuit, a transmitting circuit and a T / R chipset;

[0008] Control circuit: used to receive the input clock signal CLK, output a high-voltage trigger signal to the transmitter circuit, and output a latch signal and an SPI communication signal to the T / R chipset;

[0009] Transmitter circuit: used for receiving the high-voltage trigger signal and generating a high-voltage pulse signal synchronized with the high-voltage trigger signal to the T / R chipset;

[0010] T / R chipset: used to receive the Latch signal, SPI communication signal and its high-voltage pulse signal, output low-voltage echo signal to the amplifier circuit and output signal to the phased array ultrasonic transducer.

[0011] A further improvement based on the above technical solution is that the control circuit includes a control register group, a T / R control circuit and a transmission pulse generating circuit.

[0012] The control register group includes a delay window register, a T / R switch register, a control register CTRL, a PRF register and a pulse width register Width;

[0013] The delay window register is used to output the delay parameter to the T / R control circuit;

[0014] The T / R control circuit is used to output a T / R switch EN signal to the T / R control circuit;

[0015] The control register CTRL is used to output a transmit enable signal TxEn to the transmit pulse generating circuit;

[0016] The PRF register is used to output a pulse repetition frequency to the transmit pulse generating circuit;

[0017] The pulse width register Width outputs the pulse width Width to the transmit pulse generating circuit.

[0018] A further improvement based on the above technical solution is that the transmission pulse generating circuit includes a transmission pulse delay counter and a pulse width counter.

[0019] The transmit pulse delay counter is used to receive the input clock signal, the enable signal TxEn of the control register CTRL and the pulse repetition frequency of the PRF register; and the transmit pulse delay counter is used to output a delay trigger signal to the pulse width counter;

[0020] The pulse width counter is used to receive the input clock signal, the delay trigger signal and the pulse width Width of the pulse width register Width; and the pulse width counter is used to output a high voltage trigger signal to the transmitting circuit.

[0021] A further improvement based on the above technical solution is that the T / R control circuit includes a T / R delay counter, a control state machine, a data selector and an SPI configuration controller.

[0022] The T / R delay counter is used to receive the input clock signal, the delay parameter of the delay window register, the enable signal TxEn of the control register CTRL, and the high-voltage trigger signal of the transmit pulse generating circuit;

[0023] The control state machine is used to receive the input clock signal, the Delay_Finis signal of the T / R delay counter, the enable signal TxEn of the control register CTRL, the high-voltage trigger signal of the transmit pulse generating circuit and the Cfg_Finis signal of the SPI configuration controller; and output the SEL signal to the data selector, the start signal to the SPI configuration controller, and the Latch signal to the T / R chipset;

[0024] The data selector is used to receive the SEL signal of the control state machine, receive the DataA signal and the DataB signal; and output the Data signal to the SPI configuration controller;

[0025] The SPI configuration controller is used for inputting the clock signal, receiving the start signal of the control state machine and the Data signal of the data selector; and outputting the Cfg_Finis signal to the control state machine and the SPI communication signal to the T / R chipset.

[0026] A further improvement based on the above technical solution is that the SPI communication input by the T / R chipset can be implemented in parallel or in cascade.

[0027] A further improvement based on the technical solution is that the control circuit includes a communication interface for reading and writing the register group, the transmission pulse generating circuit and the transmission pulse generating circuit, and the communication interface includes an internal communication bus, an external Uart communication interface, an I2C communication interface or an SPI communication interface.

[0028] A further improvement based on the above technical solution is that the amplifier circuit is used to perform analog amplification on the low-voltage echo signal output by the T / R chipset.

[0029] The above technical solution has the following beneficial effects:

[0030] The present invention provides a novel phased array ultrasonic transceiver switch (T / R) control circuit, which achieves the purpose of reducing power consumption by closing the T / R switch during high-voltage transmission and opening the T / R switch during reception through timing coordination of high-voltage pulse trigger signals, T / R configuration communication and latching.

[0031] This invention uses a sequential circuit to implement the transmit / receive timing of the T / R switch chip, enabling it to be closed during transmission and open during the echo signal. It also proposes a load-latch mechanism to separate the configuration and activation times, giving the chip more time to configure. This allows the phased array pulse repetition frequency setting to be independent of the communication time required to configure the T / R chip.

[0032] The present invention mainly uses a timing control circuit to control the software configuration of a phased array ultrasonic transceiver chip, such as the MAX4936 chip, so that the TR transceiver is turned off during the high-voltage pulse transmitter period and the transceiver switch is turned on after the high-voltage pulse to ensure normal echo signal reception. This reduces energy loss during transmission in integrated transceiver applications.

[0033] The present invention proposes a pre-storage-lock mechanism that uses timing control to enable the TR chip to store information when idle, and then load, latch, and lock the output when the pulse is transmitted. This mechanism ensures communication time and can also output immediately when needed. This method not only ensures that the T / R transceiver is closed during the high-voltage pulse transmission time interval, but also reserves communication time for configuring the transceiver switch chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be further described below in conjunction with the accompanying drawings:

[0035] Figure 1 The figure is a schematic diagram of the three-dimensional structure of a low-power phased array ultrasonic transceiver switch control system according to an embodiment of the present invention.

[0036] Figure 2 Schematic diagram of the structure of the control circuit according to an embodiment of the present invention.

[0037] Figure 3 Schematic diagram of the structure of the transmission pulse generating circuit according to an embodiment of the present invention.

[0038] Figure 4 This is a timing diagram of the transmit pulse generating circuit according to an embodiment of the present invention.

[0039] Figure 5 Schematic diagram of the structure of the T / R control circuit according to an embodiment of the present invention.

[0040] Figure 64 is a timing diagram of the T / R control circuit according to an embodiment of the present invention.

[0041] Figure 7 2 is a working principle diagram of the control state machine of the T / R control circuit according to an embodiment of the present invention.

[0042] In the figure: 101 - control circuit; 102 - transmitting circuit; 103 - T / R chipset; 104 - amplifier circuit; 105 - phased array ultrasonic transducer. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the accompanying drawings and examples. However, it should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the scope of the present invention. In addition, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessary confusion of the present invention.

[0044] See Figure 1 A low-power phased array ultrasonic transceiver switch control system includes a control circuit, a transmitting circuit, a T / R chipset, an amplifying circuit and a phased array ultrasonic transducer.

[0045] Control circuit: used to receive the input clock signal CLK, output a high-voltage trigger signal to the transmitter circuit, and output a latch signal and an SPI communication signal to the T / R chipset.

[0046] Transmitter circuit: Receives the high-voltage trigger signal and generates a high-voltage pulse signal synchronized with the trigger signal to transmit to the T / R chipset. The high-voltage pulse signal can be a negative pulse, a positive / negative pulse, or a pulse train. The transmitter circuit is typically a high-voltage transmitter pulse integrated circuit, such as the Maxim MAX4940.

[0047] T / R chipset: used to receive the Latch signal, SPI communication signal and its high-voltage pulse signal, output low-voltage echo signal to the amplifier circuit and output signal to the phased array ultrasonic transducer.

[0048] Specifically, the T / R chipset is a multi-channel transceiver (T / R) switch chip, which can be composed of one chip or multiple chips cascaded together. Multiple chips can be directly controlled independently by the control circuit or controlled in a daisy-chain manner, such as Maxim's MAX4936 chip.

[0049] The amplifier circuit is used to perform analog amplification on the low-voltage echo signal output by the T / R chipset.

[0050] The amplification circuit is an echo circuit, which is generally composed of several stages of amplifiers. It can be built with discrete amplifiers or with an integrated analog front-end chip AFE, such as TI's AFE5816.

[0051] The phased array ultrasonic transducer is a 64-line array transducer, etc.

[0052] The present invention provides a novel phased array ultrasonic transceiver switch (T / R) control circuit, which achieves the purpose of reducing power consumption by closing the T / R switch during high-voltage transmission and opening the T / R switch during reception through timing coordination of high-voltage pulse trigger signals, T / R configuration communication and latching.

[0053] As a further explanation of this embodiment, the control circuit schematic diagram is as follows Figure 2 As shown, the control circuit includes a control register group, a T / R control circuit and a transmission pulse generating circuit inside the FPGA or CPLD.

[0054] The control register group includes a delay window register, a T / R switch register, a control register CTRL, a PRF register and a pulse width register Width.

[0055] The delay window register is used to output the delay parameter to the T / R control circuit.

[0056] The T / R control circuit is used to output a T / R switch EN signal to the T / R control circuit.

[0057] The control register CTRL is used to output a transmit enable signal TxEn to the transmit pulse generating circuit.

[0058] The PRF register is used to output a pulse repetition frequency to the transmit pulse generating circuit.

[0059] The pulse width register Width outputs the pulse width Width to the transmit pulse generating circuit.

[0060] As a further explanation of this embodiment, the control circuit also includes a communication interface for reading and writing the register group, transmit pulse generating circuit and transmit pulse generating circuit inside the FPGA or CPLD, and the communication interface includes an internal communication bus, an external Uart communication interface, an I2C communication interface or an SPI communication interface.

[0061] See Figure 2 , the trigger signal Trig is Figure 1 The Trig signal of the transmitting circuit is the high voltage trigger signal.

[0062] Latch and SPI communication as Figure 1The input of the T / R chipset is used to configure the T / R chipset and the T / R chipset latch signal input.

[0063] The SPI communication input by the T / R chip set can be in parallel or in cascade. This invention is described with only one T / R chip.

[0064] The control circuit includes the control register set within the FPGA or CPLD and its functional circuits (T / R control circuit and transmit pulse generation circuit). This circuit contains a high-voltage trigger signal, which can be used to set the pulse repetition frequency (PRF register) and pulse width (Pulse Width register), such as a 2 kHz PRF and a 100 ns pulse width. The T / R control circuit uses the delay window register value, the T / R switch enable register, and the switch enable signal as inputs. Using the Trig signal as a reference, it generates a timing circuit to configure the T / R chipset timing. It disables the T / R function during high-voltage pulse transmission, achieving low power consumption.

[0065] As a further illustration of this embodiment, the transmit pulse generating circuit includes a transmit pulse delay counter and a pulse width counter.

[0066] The transmit pulse delay counter is used to receive the input clock signal, the enable signal TxEn of the control register CTRL and the pulse repetition frequency of the PRF register; and the transmit pulse delay counter is used to output a delay trigger signal to the pulse width counter;

[0067] The pulse width counter is used to receive the input clock signal, the delay trigger signal and the pulse width Width of the pulse width register Width; and the pulse width counter is used to output a high voltage trigger signal to the transmitting circuit.

[0068] See Figure 3 This is the structural block diagram of the transmit pulse generation circuit. After the transmit enable TxEn is valid, the delay counter counts according to the clock count cycle obtained by the inverse conversion of the PRF register. After the counting is completed, a single-cycle delay trigger signal is generated. The pulse width counter starts counting according to the rising edge of the delay trigger signal based on the pulse width value and outputs a high level until the pulse width counter finishes counting and outputs a low level. Its timing diagram is shown as follows Figure 4 shown.

[0069] As a further explanation of this embodiment, see Figure 5The block diagram of the T / R control circuit is shown below. The T / R control circuit includes a T / R delay counter, a control state machine, a data selector, and an SPI configuration controller. The T / R delay counter starts counting at the rising edge of the Trig signal (high-voltage trigger signal) when EN is high. The count value is Delay[15:0] clock cycles. Assuming the PRF is 1KHz, the trigger period is 1ms, and the Delay value is 1ms-ta time ( Figure 6 In ta), the output is a single-cycle event pulse signal.

[0070] The T / R delay counter is used to receive the input clock signal, the delay parameter of the delay window register, the enable signal TxEn of the control register CTRL, and the high-voltage trigger signal of the transmit pulse generating circuit;

[0071] The control state machine is used to receive the input clock signal, the Delay_Finis signal of the T / R delay counter, the enable signal TxEn of the control register CTRL, the high-voltage trigger signal of the transmit pulse generating circuit and the Cfg_Finis signal of the SPI configuration controller; and output the SEL signal to the data selector, the start signal to the SPI configuration controller, and the Latch signal to the T / R chipset;

[0072] The data selector is used to receive the SEL signal of the control state machine, receive the DataA signal and the DataB signal; and output the Data signal to the SPI configuration controller;

[0073] The SPI configuration controller is used for inputting the clock signal, receiving the start signal of the control state machine and the Data signal of the data selector; and outputting the Cfg_Finis signal to the control state machine and the SPI communication signal to the T / R chipset.

[0074] As a further illustration of this embodiment, the SPI communication input by the T / R chipset may be implemented in a parallel manner or a cascade manner.

[0075] The control state machine is as follows Figure 7 As shown, the control state machine behavior can be established as:

[0076] IDLE: Idle state.

[0077] S0: When EN is high and the Trig signal is rising, it enters the high voltage trigger state, at which point the high voltage pulse is valid. When the Trig signal falls, it enters the S1 state.

[0078] S1: The S1 status is Figure 6 In the Latch_after state, the latch signal is output. At this time, the T / R chip will receive the T / R switch state control signal of DataA. Under normal circumstances, the T / R switch state of DataA is ON. The state machine directly enters the S2 state in the next beat.

[0079] S2: S2 is the wait state. The count value is the delay window register's count value, Delay[15:0]. When the count reaches 0, the Delay_Finis signal is generated. When the Delay_Finis signal is generated, the state machine enters state 3. Assuming a PRF of 1 kHz and a trigger period of 1 ms, the delay corresponding to Delay[15:0] is 1 ms minus ta. The SPI configuration communication time must be less than the sum of ta and the pulse width.

[0080] S3: S1 status is Figure 6 In the Latch_pre state, the latch signal will be output. At this time, the T / R chip will receive the T / R switch state control signal of DataB. Under normal circumstances, the T / R switch state of DataB is OFF. The state machine directly enters the S4 state in the next beat.

[0081] S4: S state is the waiting state. If the EN signal is inactive at a low level, it enters the IDLE state. If the Trig rising edge arrives, it enters the S0 state.

[0082] In this cycle, DataA and DataB are configured in a ping-pong manner. DataA is the T / R channel switch state of the T / R chip during high voltage triggering, and DataB is the T / R channel switch state of the T / R chip during echo reception.

[0083] As a further explanation of this embodiment, the two states of DataA and DataB can increase or decrease the number of states and adjust the control state machine.

[0084] The present invention utilizes a pre-storage and latching mechanism to achieve closing of the T / R switch during high voltage transmission and opening of the T / R switch during normal receiving state in a ping-pong manner.

[0085] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications based on the present invention to solve substantially the same technical problems and achieve substantially the same technical effects are included within the scope of protection of the present invention.

Claims

1. A low-power phased array ultrasonic transceiver switch control system, characterized in that Including control circuit, transmission circuit and T / R chipset; Control circuit: used to receive the input clock signal CLK, output a high-voltage trigger signal to the transmitter circuit, and output a latch signal and an SPI communication signal to the T / R chipset; Transmitter circuit: used for receiving the high-voltage trigger signal and generating a high-voltage pulse signal synchronized with the high-voltage trigger signal to the T / R chipset; T / R chipset: used to receive the latch signal, SPI communication signal and high-voltage pulse signal, output low-voltage echo signal to the amplifier circuit and output signal to the phased array ultrasonic transducer; The control circuit includes a control register group, a T / R control circuit and a transmission pulse generating circuit. The control register group includes a delay window register, a T / R switch register, and a control register CTRL; The delay window register is used to output the delay parameter to the T / R control circuit; The T / R control circuit is used to output a T / R switch EN signal to the T / R control circuit; The control register CTRL is used to output a transmit enable signal TxEn to the transmit pulse generating circuit; The T / R control circuit includes a T / R delay counter, a control state machine, a data selector and an SPI configuration controller. The T / R delay counter is used to receive the input clock signal, the delay parameter of the delay window register, the enable signal TxEn of the control register CTRL, and the high-voltage trigger signal of the transmit pulse generating circuit; The control state machine is used to receive the input clock signal, the Delay_Finis signal of the T / R delay counter, the enable signal TxEn of the control register CTRL, the high-voltage trigger signal of the transmit pulse generating circuit and the Cfg_Finis signal of the SPI configuration controller; and output the SEL signal to the data selector, the start signal to the SPI configuration controller, and the Latch signal to the T / R chipset; The data selector is used to receive the SEL signal of the control state machine, receive the DataA signal and the DataB signal; and output the Data signal to the SPI configuration controller; The SPI configuration controller is used for inputting the clock signal, receiving the start signal of the control state machine and the Data signal of the data selector; and outputting the Cfg_Finis signal to the control state machine and the SPI communication signal to the T / R chipset.

2. The low-power phased array ultrasonic transceiver switch control system according to claim 1, characterized in that: The control register group also includes a PRF register and a pulse width register. The PRF register is used to output a pulse repetition frequency to the transmit pulse generating circuit; The pulse width register Width outputs the pulse width Width to the transmit pulse generating circuit.

3. The low-power phased array ultrasonic transceiver switch control system according to claim 2, characterized in that: The transmitting pulse generating circuit includes a transmitting pulse delay counter and a pulse width counter. The transmit pulse delay counter is used to receive the input clock signal, the enable signal TxEn of the control register CTRL and the pulse repetition frequency of the PRF register; and the transmit pulse delay counter is used to output a delay trigger signal to the pulse width counter; The pulse width counter is used to receive the input clock signal, the delay trigger signal and the pulse width Width of the pulse width register Width; and the pulse width counter is used to output a high voltage trigger signal to the transmitting circuit.

4. A low-power phased array ultrasonic transceiver switch control system according to claim 1 or 2, characterized in that: The SPI communication input by the T / R chipset adopts a parallel mode or a cascade mode.

5. The low-power phased array ultrasonic transceiver switch control system according to claim 2, characterized in that: The control circuit includes a communication interface for reading and writing the register group, the transmit pulse generating circuit and the transmit pulse generating circuit, and the communication interface includes an internal communication bus, an external Uart communication interface, an I2C communication interface or an SPI communication interface.

6. The low-power phased array ultrasonic transceiver switch control system according to claim 2, characterized in that: The amplifier circuit is used to perform analog amplification on the low-voltage echo signal output by the T / R chipset.

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