High-performance reference voltage implementation method and circuit

Abstract

The invention discloses a high-performance reference voltage implementation method and circuit. The method comprises the following steps: constructing a framework adaptive to low power supply voltage, and determining initial working parameters by selecting a conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process device; a low reference voltage value generation module is designed, a low-voltage NMOS device in a sub-threshold region is matched with a current mirror and a resistance network to output accurate low voltage, and interference is suppressed. First-order and second-order temperature compensation is implemented, and the temperature stability of the reference voltage is improved by utilizing devices with different temperature characteristics and specific NMOS electric leakage characteristics at high temperature. An ultra-low power consumption OP is designed, a low-voltage NMOS and a high-voltage native device are combined, and a bias circuit is optimized. The circuit integrates a low reference voltage module, a first-order temperature compensation module, a second-order temperature compensation module, an ultra-low power consumption OP module and the like. Finally, the working power supply voltage as low as 1V, the power consumption smaller than 100nA and the excellent second-order temperature compensation effect in the full-temperature range are achieved, and stable and accurate reference voltage is provided for related circuits.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a method and circuit for realizing a high-performance reference voltage. Background Art

[0002] In today's electronics, mixed-signal processing is widely used in various systems, where reference voltages play a crucial role. Common SOC systems often rely on analog power supplies for their digital cores, such as LDOs, which require stable reference voltage inputs. Power-on circuits such as the POR, LVR, and LVD in power-up systems also rely on reference voltages. Furthermore, high precision is required for the reference voltage, requiring excellent temperature and voltage characteristics. In low-power systems, due to stringent power requirements for LDOs, PORs, and other components, the power consumption of the reference voltage is also a concern. Furthermore, the reference voltage design must meet power-on requirements to ensure stable and controllable power-up of each module, especially in low-supply voltage ranges.

[0003] However, existing technologies have numerous shortcomings. In terms of operating power supply voltage range, existing reference voltage circuits have a narrow operating power supply voltage range, and the minimum operating power supply voltage is not low enough. For example, in common processes, the reference voltage is often designed to be around 1.25V. In linear systems, to output this reference voltage, the power supply voltage often needs to be much higher, such as 1.5V. This leads to uncertainty in system detection during the power-on period when the power supply is below 1.5V, and may even cause control errors.

[0004] There are also issues with the reference voltage value and accuracy. Existing reference voltages are relatively high, making control in the low-voltage range during system power-up complex and risky. Furthermore, their accuracy is insufficient. Common reference voltages only feature first-order temperature compensation, resulting in significant fluctuations in the reference voltage at high and low temperatures, failing to meet high-precision requirements. Existing reference voltage circuits consume a high amount of power, making it difficult to meet the ultra-low power requirements of SOC systems. This inability to effectively address these issues in battery-powered systems or ultra-low-power MCU products with extremely high power requirements poses a significant limitation to system performance. These shortcomings severely restrict the development of electronic systems, necessitating a new, high-performance reference voltage implementation method and circuit to address these issues. Summary of the Invention

[0005] In order to overcome the shortcomings and deficiencies of the prior art, the present invention provides a high-performance reference voltage implementation method and circuit.

[0006] A method for implementing a high-performance reference voltage, the method comprising the following steps:

[0007] S1: Build an infrastructure suitable for operating at low power supply voltages. Select devices compatible with the CMOS process and construct a circuit in a preset connection manner. This infrastructure starts and maintains its operating state at the preset power supply voltage, and at the same time, determine the initial operating parameters of each device in the low power supply voltage environment;

[0008] S2: Design a low reference voltage value generation module. Through the analysis of device characteristics, utilize devices operating in a specific region, combined with the designed current mirror structure and resistor network. This module outputs a low reference voltage value that meets the design requirements, and during the output process, suppress the factors affecting the stability of the reference voltage value;

[0009] S3: Perform first-order temperature compensation. Use a combination of devices with different temperature characteristics to construct a temperature compensation circuit. In the circuit, adjust the current or voltage of the branch according to the influence law of temperature change on the reference voltage;

[0010] S4: Perform second-order temperature compensation. For the reference voltage after first-order temperature compensation in the high or low temperature section, use a specially designed second-order temperature compensation circuit. This circuit utilizes the different electrical characteristics of devices at different temperatures. When the temperature changes, adjust the output of the reference voltage through the change in the leakage current of this device;

[0011] S5: Design an ultra-low power operational amplifier OP. Combine high-voltage native devices with zero threshold for isolation protection, optimize the bias circuit design of the OP, use the method of generating tail current with resistors, reduce the additional bias current generation circuit, and reduce the overall power consumption;

[0012] S6: Integrate the low reference voltage and the first-order temperature compensation module, the second-order temperature compensation module, the ultra-low power operational amplifier OP, and the devices in the core part of the reference voltage in a preset connection manner to form a complete high-performance reference voltage circuit.

[0013] Further, for the low reference voltage value generation module, the adopted low reference voltage value generation model formula is: V ref-low =f(V gs1 ,V gs2 ,R a ,R b ,k1), where V gs1 and V gs2 are the gate-source voltages of two low-voltage NMOS devices operating in the subthreshold region respectively, R a and R b are resistors with specific resistance values, k1 is a coefficient related to the current mirror ratio. The width-to-length ratio W / L of the low-voltage NMOS device ranges from 5 to 10, the value of R a is between 10 kΩ and 20 kΩ, and R bThe value is between 5kΩ-10kΩ, and the value of k1 is 0.8-1.2.

[0014] Furthermore, the temperature compensation model formula of the first-order temperature compensation module is: ΔV comp1 =g(T,I ptat1 , R c , R d , n1), where T is the ambient temperature, I ptat1 is the positive temperature coefficient current related to the first-order temperature compensation, R c and R d is a resistor with a specific temperature coefficient, n1 is a parameter related to the temperature compensation circuit structure, and the resistor R with a specific temperature coefficient c The temperature coefficient is 100-200ppm / ℃, R d The temperature coefficient is -50-100ppm / ℃, and the value of n1 is between 1.5 and 2.5.

[0015] Furthermore, the second-order temperature compensation module has a second-order temperature compensation model formula of: ΔV comp2 =h(T,I leak , R e , k2), where T is the ambient temperature, I leak is the leakage current of a specific NMOS device at high temperature, R e is a specific resistor, k2 is a coefficient related to the gain of the second-order temperature compensation circuit, the specific NMOS device is a high-voltage NMOS, and the leakage current I leak Changing in the range of 1nA-10nA, R e The value is between 5kΩ-15kΩ, and the value of k2 is 0.5-1.5.

[0016] Furthermore, the ultra-low power operational amplifier OP has a model formula for calculating the power consumption of OP: OP =I total ×V supply－OP +I bias－OP ×V bias－OP， Among them, I total is the total operating current of OP, V supply-OP is the OP supply voltage, I bias-OP is the bias current of OP, V bias-OP is the bias voltage, I total Controlled at 20nA-50nA, V supply－OP 0.8V-1.2V, I bias-OP 5nA-15nA, V bias-OP It is 0.3V-0.6V.

[0017] Further, in the step S1, the formula of the infrastructure stability model is: S infra = j(V min , I min , R f , C f , k3), where V min is the minimum power supply voltage at which the infrastructure can work properly, I min is the minimum operating current, R f and C f are the feedback resistor and capacitor for stabilizing the circuit, k3 is a coefficient related to the infrastructure stability. The value of the feedback resistor R f is between 100 kΩ and 500 kΩ, the value of the feedback capacitor C f is between 1 pF and 5 pF, and the value of k3 is 0.6 - 1.0.

[0018] Further, in the step S6, the formula of the inter-module interference suppression model is: I interference = m(V coupling , C coupling , f signal , R isolation , k4), where V coupling is the coupling voltage between modules, C coupling is the parasitic capacitance between modules, f signal is the signal frequency, R isolation is the resistor for isolation, k4 is a coefficient related to the interference suppression effect. The value of the resistor for isolation R isolation is between 500 Ω and 1000 Ω.

[0019] Further, in the design of the low reference voltage and first-order temperature compensation module, the comprehensive model formula for generating the first-order temperature compensation in combination with the low reference voltage value is: V LVVREF-FOTC = n(V ref－low , ΔV comp1 , R g , R h , k5), where V ref-low is the low reference voltage value, ΔV comp1 is the first-order temperature compensation voltage, R g and R h are related resistors, k5 is a comprehensive adjustment coefficient. The value of the related resistor R g is between 8 kΩ and 12 kΩ, the value of R h is between 3 kΩ and 7 kΩ, and the value of k5 is 0.9 - 1.1.

[0020] Further, considering the process deviation, the formula of the overall accuracy model of the reference voltage is: V error = p(ΔV process , ΔT, Vref－ideal , k6), where ΔV process is the change in the reference voltage caused by process deviation, ΔT is the temperature change range, and V ref-ideal is the ideal reference voltage value, k6 is the coefficient related to precision compensation, and ΔV process is controlled within ±5 mV, ΔT is -40°C - 125°, and k6 ranges from 0.8 to 1.2.

[0021] A high-performance reference voltage implementation circuit includes a low reference voltage and first-order temperature compensation module, a second-order temperature compensation module, an ultra-low power operational amplifier OP module, and N1 and N2 devices in the core part of the reference voltage. Each module is connected according to the preset connection method described in step S6.

[0022] Beneficial effects: The present invention proposes a high-performance reference voltage implementation method and circuit. In terms of low power supply voltage adaptability, by constructing an infrastructure suitable for operating at low power supply voltages, selecting specific devices and reasonably setting parameters, the lowest operating power supply voltage of this circuit is about 1V. In the POR detection of some SOC systems, when the power supply is in the low voltage range, the reference voltage required by the POR circuit can be ready, effectively detecting the power-on situation of the power supply and ensuring that the system is stably controlled during the low power supply voltage period. In terms of power consumption, the ultra-low power design concept is adopted, and the branch currents of each branch are carefully designed. For example, the START, P1 - P4 branch currents are set to 10 nA, and the LPOP is designed as a self-biased current OP with a power consumption of 20 nA. The power consumption of the entire reference voltage circuit can be as low as 70 nA, meeting the ultra-low power consumption requirements, and having obvious advantages in battery-powered systems or the sleep mode of ultra-low power MCU products. In terms of accuracy, the combination of first-order and second-order temperature compensation technologies is highly effective. The first-order temperature compensation initially suppresses the change of the reference voltage within a certain temperature range, and the second-order temperature compensation further optimizes it for the high-temperature section. After introducing the second-order temperature compensation, the full-temperature characteristic is improved from 0.48% of the first-order compensation to 0.11%, and the change of the reference voltage within the range of -40 to 125°C is significantly reduced, ensuring that the reference voltage can maintain high precision in different temperature environments. Moreover, through a series of innovative model formulas, each module is accurately designed and optimized, comprehensively considering various factors such as process deviation and temperature change, further ensuring the stability and accuracy of the reference voltage. This high-performance reference voltage implementation method and circuit provide a reliable solution for SOC systems that require a reference voltage, effectively improving the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is the flowchart of the method steps of the present invention;

[0024] Figure 2 is the schematic diagram of the method implementation circuit of the present invention;

[0025] Figure 3 Circuit implementation example diagram for the method of the present invention;

[0026] Figure 4 OP circuit diagram of the low-power operational amplifier of the present invention;

[0027] Figure 5 Simulation comparison diagram of temperature characteristics before and after introducing second-order temperature compensation of the present invention;

[0028] Figure 6 Relationship diagram of the reference voltage of the present invention with respect to the power supply voltage during power-on. Detailed implementation manners

[0029] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The following further describes the present application in detail with reference to the drawings and specific embodiments.

[0030] As Figure 1 shown, a method for implementing a high-performance reference voltage includes the following steps:

[0031] S1: Construct an infrastructure suitable for operating at a low power supply voltage, select devices adapted to the conventional CMOS process, and build a circuit in a preset connection manner so that the infrastructure can start and maintain a basic operating state at the preset power supply voltage. At the same time, determine the initial operating parameters of each device in a low power supply voltage environment, including but not limited to the initial setting values of parameters such as the threshold voltage and on-resistance of the device, laying a foundation for subsequent precise control of the circuit operation.

[0032] Specifically, in the trend of continuous miniaturization and low power consumption of electronic devices, it is crucial to construct an infrastructure that can operate stably at a low power supply voltage. The devices selected in this step are adapted to the conventional CMOS process because the conventional CMOS process is widely used and has a low cost. For example, low-voltage NMOS devices operating in the subthreshold region are selected, which can work at a relatively low gate-source voltage and can effectively reduce the power supply voltage requirement of the entire circuit. The threshold voltage of these devices is generally between 0.3V and 0.6V, which greatly reduces the startup voltage compared with traditional devices.

[0033] Build a circuit in a specific connection manner, which is carefully designed. Connect multiple low-voltage NMOS devices according to a specific topology to form basic circuit units such as current mirrors and amplifiers. Through such connections, the circuit can stably distribute current and voltage under low power supply voltages. Determine the initial operating parameters of each device in a low power supply voltage environment, including the threshold voltage and on-resistance of the device. For example, for an NMOS device with an on-resistance of 50Ω - 100Ω, under low power supply voltages, this resistance value can ensure that the current consumption of the circuit is within a reasonable range while ensuring the stable transmission of signals. The setting of these initial operating parameters lays a solid foundation for the subsequent precise control of the circuit operation, just like laying a solid foundation for a building.

[0034] S2: Design a low reference voltage value generation module. Through in-depth analysis of device characteristics, use devices operating in a specific region, such as low-voltage NMOS devices operating in the subthreshold region, combined with a carefully designed current mirror structure and resistor network, so that this module can output a low reference voltage value that meets the design requirements, and during the output process, effectively suppress the factors affecting the stability of the reference voltage value. For example, reduce the influence of parasitic effects by optimizing the device layout.

[0035] Specifically, the design of the low reference voltage value generation module is to meet the circuit requirements with more stringent voltage requirements. It is realized by using low-voltage NMOS devices operating in the subthreshold region combined with a carefully designed current mirror structure and resistor network. Take a practical example. Suppose there are two low-voltage NMOS devices N1 and N2 with different sizes, and they operate in the subthreshold region. By adjusting their width-to-length ratios, for example, the width-to-length ratio of N1 is 5 and that of N2 is 10, and then combined with the current mirror structure, the current is mirrored and copied in a certain proportion. At the same time, match a suitable resistor network, such as two resistors R1 and R2, where R1 has a value of 10kΩ and R2 has a value of 5kΩ. Such a combination can precisely control the magnitude and direction of the current, and finally enable this module to output a low reference voltage value that meets the design requirements.

[0036] During the output process, there will be various factors affecting the stability of the reference voltage value, such as the existence of parasitic capacitance and parasitic resistance. To effectively suppress these influences, the method of optimizing the device layout will be adopted. Separate the devices with larger parasitic effects to reduce their mutual influence. Shielding technology will also be used. Set a shielding layer around the key devices to prevent the influence of external interference signals on the reference voltage. Through these measures, ensure that the output low reference voltage value is stable and reliable, just like opening a stable transmission channel for signals in a noisy environment.

[0037] S3: Perform first-order temperature compensation. Based on the research on the physical mechanism of temperature affecting the reference voltage, use a combination of devices with different temperature characteristics to construct a temperature compensation circuit. In the circuit, according to the influence law of temperature change on the reference voltage, adjust the current or voltage of the relevant branch to achieve the first-order temperature compensation of the reference voltage, so as to initially suppress the change of the reference voltage within a certain temperature range.

[0038] Specifically, the influence of temperature on the reference voltage cannot be ignored. The purpose of implementing first-order temperature compensation is to reduce this influence. Based on the research on the physical mechanism of temperature affecting the reference voltage, we know that the electrical characteristics of different devices will change when the temperature changes. Use a combination of devices with different temperature characteristics to construct a temperature compensation circuit. For example, select a resistor R3 with a positive temperature coefficient and a transistor T1 with a negative temperature coefficient. When the temperature rises, the resistance value of the resistor R3 will increase, while the conduction voltage of the transistor T1 will decrease.

[0039] By reasonably designing the circuit, combine these two devices with the reference voltage generation circuit. When the temperature changes, according to the influence law of temperature change on the reference voltage, adjust the current or voltage of the relevant branch. Assume that the temperature rises, the resistance value of the resistor R3 increases, resulting in a decrease in the current passing through it, while the conduction voltage of the transistor T1 decreases, causing an increase in the current of another branch. In this way, the first-order temperature compensation of the reference voltage is achieved. Within a certain temperature range, such as between -20°C and 80°C, the change of the reference voltage can be initially suppressed, making the reference voltage remain relatively stable within this temperature range, just like adding a "temperature protection coat" to the reference voltage to resist the fluctuations caused by temperature changes.

[0040] S4: Perform second-order temperature compensation. For the problem that there are still large changes in the reference voltage after the first-order temperature compensation in the high-temperature or low-temperature section, use a specially designed second-order temperature compensation circuit. This circuit uses the different electrical characteristics of specific devices at different temperatures, such as the leakage characteristics of a specific NMOS device at high temperatures. When the temperature changes, adjust the output of the reference voltage through the change of the leakage current of this device to further improve the stability of the reference voltage within the full temperature range.

[0041] Specifically, although the first-order temperature compensation can suppress the temperature change of the reference voltage to a certain extent, there may still be large changes in the reference voltage in the high-temperature or low-temperature section. The introduction of second-order temperature compensation is to further improve the stability of the reference voltage within the full temperature range. Use a specially designed second-order temperature compensation circuit that utilizes the different electrical characteristics of specific devices at different temperatures. For example, use a high-voltage NMOS device as a temperature-sensitive element. At low temperatures and normal temperatures, it has almost no leakage current and has no influence on the reference voltage.

[0042] When the temperature rises, according to the principles of subthreshold leakage current model, gate-induced drain leakage, and PN junction reverse leakage, etc., this high-voltage NMOS device will generate a leakage current. This leakage current will increase exponentially with the increase of temperature. Introduce this leakage current into the reference voltage generation circuit. When the temperature rises and the reference voltage would originally decrease, the increase of the leakage current will compensate the reference voltage, thus improving the stability of the reference voltage in the high-temperature range. In the full temperature range from -40°C to 125°C, through second-order temperature compensation, the temperature characteristics of the reference voltage are significantly improved, greatly reducing the influence of temperature on the reference voltage, just like upgrading the "temperature protection suit" to enable it to effectively protect the stability of the reference voltage in a more severe temperature environment.

[0043] S5: Design an ultra-low-power operational amplifier (OP). Select a low-voltage NMOS device suitable for conventional CMOS process and operating in the subthreshold region as the input-stage device of the OP. At the same time, combine high-voltage native devices with zero threshold for isolation protection, optimize the bias circuit design of the OP, adopt the method of using a resistor to generate the tail current, reduce the additional bias current generation circuit, and lower the overall power consumption, so that the OP can achieve ultra-low-power operation while meeting the performance requirements.

[0044] Specifically, today with the increasingly strict requirements for low power consumption, designing an ultra-low-power operational amplifier (OP) is a key link to achieve a high-performance reference voltage. Select a low-voltage NMOS device suitable for conventional CMOS process and operating in the subthreshold region as the input-stage device of the OP. When these devices operate in the subthreshold region, the current consumption is very low. For example, a low-voltage NMOS device operating in the subthreshold region can have a static current as low as below 10 nA. At the same time, combine high-voltage native devices with zero threshold for isolation protection. These high-voltage native devices can withstand higher voltages and isolate the input stage of the OP from other high-voltage parts, ensuring that the OP operates within a safe voltage range.

[0045] Optimize the bias circuit design of the OP, adopt the method of using a resistor to generate the tail current, and reduce the additional bias current generation circuit. For example, use a resistor with a resistance value of 5 kΩ to generate the tail current. This method is simple and effective, avoiding the additional power consumption brought by a complex bias circuit. Through these designs, the OP can achieve ultra-low-power operation while meeting the amplification performance requirements. In the entire reference voltage circuit, the power consumption of the OP is controlled at a very low level. For example, the total power consumption can be as low as 20 nA, greatly reducing the power consumption of the entire circuit, providing strong support for achieving an ultra-low-power reference voltage, just like carrying out an energy-saving transformation on the "big power consumer" in the circuit.

[0046] S6: Integrate each module. Combine the devices of the low reference voltage and first-order temperature compensation module, the second-order temperature compensation module, the ultra-low power operational amplifier OP, and the core part of the reference voltage according to the preset connection method to form a complete high-performance reference voltage circuit. During the integration process, optimize the electrical connections between the modules to reduce signal transmission interference and ensure that the entire circuit can stably and efficiently output a high-performance reference voltage.

[0047] Specifically, integrating each module means combining the previously designed low reference voltage and first-order temperature compensation module, the second-order temperature compensation module, the ultra-low power OP, and the devices of the core part of the reference voltage into a complete and efficient high-performance reference voltage circuit. During the integration process, it is crucial to optimize the electrical connections between the modules. For example, when connecting the low reference voltage and first-order temperature compensation module and the second-order temperature compensation module, use wires with low resistance and low capacitance for connection to reduce losses and interference during signal transmission.

[0048] The mutual influence between the modules needs to be considered. For instance, the output signal of the ultra-low power OP may be affected by the noise of other modules. In this case, a filter circuit needs to be added to the line connecting the output terminal of the OP to filter out the noise signal. Through careful integration, the entire circuit can stably and efficiently output a high-performance reference voltage. After integration, the circuit can operate stably under a low power supply voltage, with a high-precision output reference voltage, good temperature characteristics, and low power consumption, just like assembling various independent excellent components into a perfectly operating precision machine, providing a reliable voltage reference for various electronic systems that require a reference voltage.

[0049] Preferably, in the design of the low reference voltage value generation module, the low reference voltage value generation model formula used is: V ref-low = f(V gs1 , V gs2 , R a , R b , k1), where V gs1 and V gs2 are the gate-source voltages of two low-voltage NMOS devices operating in the subthreshold region respectively, R a and R b are resistors with specific resistance values, and k1 is a coefficient related to the current mirror ratio. The width-to-length ratio W / L of the low-voltage NMOS device ranges from 5 to 10, R a ranges from 10 kΩ to 20 kΩ, R b ranges from 5 kΩ to 10 kΩ, and k1 ranges from 0.8 to 1.2. By adjusting these parameters, precisely control the output of the low reference voltage value.

[0050] Preferably, in the first-order temperature compensation module, the temperature compensation model formula is: ΔV comp1 = g(T, I ptat1 , R c , R d , n1), where T is the ambient temperature, I ptat1 is the positive temperature coefficient current related to the first-order temperature compensation, R c and R d are resistors with specific temperature coefficients, and n1 is a parameter related to the temperature compensation circuit structure. The temperature coefficient of the resistor R c with specific temperature coefficient is 100 - 200 ppm / °C, the temperature coefficient of R d is -50 - -100 ppm / °C, and n1 ranges from 1.5 to 2.5. Using this model formula, the compensation voltage is precisely adjusted according to the temperature change to optimize the temperature characteristics of the reference voltage.

[0051] Preferably, in the second-order temperature compensation module, the second-order temperature compensation model formula is: ΔV comp2 = h(T, I leak , R e , k2), where T is the ambient temperature, I leak is the leakage current of a specific NMOS device at high temperature, R e is a specific resistor, and k2 is a coefficient related to the gain of the second-order temperature compensation circuit. The specific NMOS device is a high-voltage NMOS, and its leakage current I leak varies in the range of 1 nA - 10 nA at high temperature, R e ranges from 5 kΩ to 15 kΩ, and k2 ranges from 0.5 to 1.5. More precise compensation of the reference voltage in the high-temperature section is achieved through this model formula.

[0052] Preferably, in the design of the ultra-low power operational amplifier OP, the model formula for calculating the power consumption of OP is: P OP = I total × V supply－OP + I bias－OP × V bias－OP，其中， I total is the total operating current of OP, V supply-OP is the supply voltage of OP, I bias-OP is the bias current of OP, and V bias-OP is the bias voltage. In this design, I total is controlled within 20 nA - 50 nA, V supply－OP is 0.8 V - 1.2 V, I bias-OP is 5 nA - 15 nA, and V bias-OP is 0.3 V - 0.6 V, thereby achieving the ultra-low power design of OP.

[0053] Preferably, in step S1 of constructing an infrastructure suitable for operating at a low power supply voltage, the infrastructure stability model formula is: S infra = j(V min , I min , R f , C f , k3), where V min is the lowest power supply voltage at which the infrastructure can operate properly, I min is the lowest operating current, R f and C f are the feedback resistor and capacitor for stabilizing the circuit, and k3 is a coefficient related to the infrastructure stability. The feedback resistor R f has a value between 100 kΩ and 500 kΩ, the feedback capacitor C f has a value between 1 pF and 5 pF, and k3 has a value between 0.6 and 1.0. Through this model formula, it is ensured that the infrastructure operates stably at a low power supply voltage.

[0054] Preferably, in step S6 of integrating each module, the inter-module interference suppression model formula is: I interference = m(V coupling , C coupling , f signal , R isolation , k4), where V coupling is the coupling voltage between modules, C coupling is the parasitic capacitance between modules, f signal is the signal frequency, R isolation is the resistor for isolation, and k4 is a coefficient related to the interference suppression effect. The resistor R isolation for isolation has a value between 500 Ω and 1000 Ω. By adjusting the parameters in this model formula, the inter-module interference is effectively reduced, ensuring the stable output of the reference voltage circuit.

[0055] Preferably, in the design of the low reference voltage and first-order temperature compensation module (LVVREF - FOTC), the comprehensive model formula for generating the low reference voltage value combined with the first-order temperature compensation is: V LVVREF-FOTC = n(V ref－low , ΔV comp1 , R g , R h , k5), where V ref-low is the low reference voltage value, ΔV comp1 is the first-order temperature compensation voltage, R g and R h are the relevant resistors, and k5 is the comprehensive adjustment coefficient. The relevant resistor R g has a value between 8 kΩ and 12 kΩ, and R hThe value ranges from 3 kΩ to 7 kΩ, and the value of k5 ranges from 0.9 to 1.1. Using this formula, a more accurate low reference voltage and first-order temperature compensation function can be achieved.

[0056] Preferably, considering process variations, the overall accuracy model formula for the reference voltage is: V error = p(ΔV process , ΔT, V ref－ideal , k6), where ΔV process is the change in the reference voltage caused by process variations, ΔT is the temperature change range, V ref-ideal is the ideal reference voltage value, and k6 is a coefficient related to accuracy compensation. In actual processes, ΔV process is controlled within ±5 mV, ΔT is -40°C - 125°, and the value of k6 ranges from 0.8 to 1.2. Through this model formula, comprehensive compensation for process variations and temperature changes is performed to improve the accuracy of the reference voltage.

[0057] A high-performance reference voltage implementation circuit, which includes a low reference voltage and first-order temperature compensation module (LVVREF - FOTC), a second-order temperature compensation module (SOTC), an ultra-low-power operational amplifier OP module, and N1 and N2 devices in the core part of the reference voltage. The modules are connected according to the specific connection method described in step S6 to form a complete high-performance reference voltage circuit, so as to achieve a stable reference voltage output under low power supply voltage, ultra-low-power operation, and high-precision temperature characteristics.

[0058] A high-performance reference voltage implementation method and circuit, with its innovative design concept and technical means, exhibits many remarkable advantages and effectively overcomes many drawbacks of the existing technology.

[0059] In terms of power supply voltage adaptability, the existing reference voltage circuit has a narrow operating power supply voltage range and a relatively high minimum operating power supply voltage, which makes the detection in the low-voltage power-on interval of the system uncertain. However, this high-performance reference voltage implementation method builds an infrastructure suitable for working under low power supply voltage, selects specific devices and optimizes the connection method, and reduces the minimum operating power supply voltage to about 1 V. This improvement enables the POR circuit to obtain the reference voltage when the power supply voltage is low, so as to effectively detect in the low-voltage power-on interval of the power supply, ensure that the system is stably controlled during low voltage, greatly improve the reliability and stability of the system, and effectively solve the problem of poor power supply voltage adaptability in the existing technology.

[0060] From the perspective of power consumption, the existing reference voltage circuit has a high power consumption and is difficult to meet the application scenarios with strict power consumption requirements, such as battery-powered systems or ultra-low-power MCU products. This high-performance reference voltage implementation method adopts an ultra-low-power design strategy, precisely distributes the branch currents. For example, the branch currents of START, P1 - P4 are set to 10 nA, and the LPOP is designed as a self-biased current OP with a power consumption of 20 nA, making the power consumption of the entire reference voltage circuit as low as 70 nA, far lower than the existing technology level. It can easily meet the ultra-low-power requirements, significantly extend the battery life of battery-powered devices, and overcome the shortcoming of excessive power consumption in the existing technology.

[0061] In terms of the accuracy and temperature characteristics of the reference voltage, the existing reference voltage not only has insufficient accuracy and only performs first-order temperature compensation, but also has a relatively high reference voltage, resulting in complex control in the low-voltage range during system power-on. This high-performance reference voltage implementation method adopts a second-order temperature compensation technology, utilizes the electrical characteristics of specific devices at different temperatures, such as the leakage characteristics of specific NMOS devices at high temperatures, to compensate the reference voltage more precisely. After practical verification, after introducing the second-order temperature compensation, the full-temperature characteristic is improved from 0.48% of the first-order compensation to 0.11%, and the change in the reference voltage within the range of -40 to 125 °C is significantly reduced, achieving high-precision temperature characteristics. At the same time, the design of a low reference voltage value also reduces the control difficulty in the low-voltage range during system power-on, improves the stability and reliability of system control, and successfully overcomes the deficiencies of the existing technology in terms of the accuracy and temperature characteristics of the reference voltage.

[0062] As Figure 2 shown, the present invention adopts an ultra-low-power design, replaces the BJT with an NMOS, adopts a low-output reference voltage architecture with first-order temperature compensation (LVVREF - FOTC), adds a second-order temperature compensation circuit (SOTC), and adopts a low-power OP circuit (LPOP).

[0063] As Figure 3 shown, the conventional CMOS process does not provide NPN-type BJT devices. The reference voltage circuit of the present invention needs to operate at a lower power supply voltage, so NMOS devices are used as the core devices of the reference voltage and jointly complete the design of the OP operating at a low power supply voltage with the LPOP. This circuit can achieve a power consumption of less than 100 nA. In the design, the branch currents of START, P1, P2, P3, and P4 are first allocated to 10 nA each, and the LPOP is designed as a self-biased current OP with a power consumption of 20 nA. There is no need for an additional bias current supply circuit, and the number of current branches is minimized. Only 6 branch currents need to be considered, that is, the power consumption of the entire reference voltage circuit is 70 nA, realizing an ultra-low-power design. At the same time, IPTAT bias current can be provided for other circuit modules to use.

[0064] The current formula in the subthreshold region of the MOS device is

[0065] Can be obtained Wherein, I D0 Is a process-related constant (related to mobility and doping concentration), n is the subthreshold slope factor (the ideal value of n = 1, and the actual value of n = 1.2 to 2), V T = kT / q is the thermal voltage (about 26mV@300K).

[0066] Principle of generating positive temperature coefficient current IPTAT: Since the ultra-low power consumption LPOP clamps the X and Y points to be equal, the current flowing through R1 is Wherein, N1 and N2 are low-voltage NMOS devices with the same unit size and different numbers, operating in the subthreshold region.

[0067] From the subthreshold region current and voltage formulas, it can be obtained that:

[0068]

[0069] Wherein, m is the total W / L ratio of the N2 and N1 devices. It can be seen that the current flowing through R1 is proportional to V T In a proportional relationship, that is, I R1 Is a current with a positive temperature coefficient.

[0070] Principle of generating zero temperature coefficient low reference voltage: This positive temperature coefficient current passes through the mirror tubes P2, P3, and P4 to generate k*I PTAT Current to LVVREF-FOTC. According to the basic principles of circuit analysis, the VREF output expression can be obtained as

[0071] When Q1 is an NMOS device:

[0072]

[0073] When Q1 is a parasitic or lateral PNP device:

[0074]

[0075] From the above formula, a reference voltage with zero temperature coefficient can be obtained. By designing R1, R2, R3, m, and k, for example, a zero temperature coefficient voltage of VREF = 0.8V can be obtained. The subsequent simulation waveforms will use this voltage as the design target. Among them, Q1 can be selected as an NMOS, or a parasitic or lateral PNP device in the CMOS process.

[0076] Such as Figure 4 Shown, principle of low operating power supply voltage and ultra-low power consumption OP:

[0077] From the above analysis, it can be seen that among the four branches P1, P2, P3, and P4, the branch that determines the lowest operating power supply is the P4 branch. The lowest operating power supply of this branch is VREF + Vdsat(P4), that is, the lowest operating voltage is about 1V.

[0078] Next, look at the lowest operating voltage of the ultra-low power LPOP. In order to reduce the lowest operating power supply voltage of LPOP, the input of LPOP uses low-voltage NMOS devices that are suitable for conventional CMOS processes and operate in the subthreshold region (conventional CMOS processes do not provide NPN-structured triodes). Among them, NOP1, NOP2, and N1, N2 in the core part of the reference voltage IPTAT are the same type of low-voltage devices (ensuring that the reference voltage can work at a lower power supply voltage), while NOP1A and NOP2A are high-voltage native devices with zero threshold. Adding these devices can isolate POP1, POP2 from the low-voltage NMOS devices NOP1 and NOP2, ensuring a safe operating voltage range. The tail current of the NOP1 and NOP2 pair of transistors is generated by the resistor ROP1, eliminating the need for an additional bias current generation circuit. The lowest operating voltage of LPOP is Vgs(P1) + Vds(NOP1A) + Vds(NOP1) + V(ROP1). Among them, the P1 device operates in the subthreshold region, Vgs(P1) is about three or four hundred mV, Vds(NOP1A) + Vds(NOP1) is about two or three hundred mV, and V(ROP1) is about several tens of mV. From the above analysis, it can be seen that the lowest operating power supply voltage of LPOP can be less than 1V.

[0079] In summary, it can be seen that the lowest operating power supply voltage of the entire LVVREF is about 1V. Such a low operating power supply voltage is very beneficial for the POR detection in some SOC systems, that is, at a lower power supply, the reference voltage required by the POR circuit is already ready, and the low-voltage range where the power supply can be powered on can be effectively detected, ensuring that the system is controlled during the period of low power supply voltage of the system.

[0080] Principle of second-order temperature compensation:

[0081] From the above VREF formula, it can be seen that VREF is a first-order temperature compensation structure. The reference voltage is relatively low at high and low temperatures, especially at high temperatures, the reference voltage will drop sharply. In the present invention, a second-order temperature compensation SOTC circuit is introduced. Figure 3 The second-order temperature compensation is implemented in the simplest way.

[0082] The NTC is a high-voltage NMOS or low-voltage NMOS device, with the gate grounded. At low and normal temperatures, there is no leakage in the NTC. When the temperature is high, the NTC gradually starts to generate leakage current.

[0083] According to the subthreshold leakage model, This leakage increases exponentially with the increase of temperature.

[0084] According to the gate-induced drain leakage GIDL: Where E is the drain-gate electric field strength, B is the material-related constant, the number of thermally excited carriers increases at high temperatures, the tunneling probability increases, and I GIDL Increase.

[0085] According to the reverse leakage of PN junction,

[0086] In summary, the total leakage current of the NTC device at high temperature is I leak =I sub +I GIDL +I junction

[0087] In the present invention, this leakage current will be added to the positive temperature current I PTAT branch, ultimately achieving voltage compensation for VREF in the high temperature range.

[0088] like Figure 5 As shown in the present invention Figure 3 The circuit example uses data from before and after second-order temperature compensation. During the first-order temperature test, VREF_FOTC varied by 3.86mV from -40 to 125°C, while during the second-order temperature test, VREF_SOTC varied by 0.86mV from -40 to 125°C. This shows that second-order temperature compensation significantly improves the reference voltage's high-temperature range, improving the full-temperature characteristic from 0.48% of first-order compensation to 0.11%.

[0089] like Figure 6 Figure 2 shows the relationship between the reference voltage and power-up. The simulation results show that the reference voltage closely tracks power-up even when the power supply is low. When the power supply voltage VDD is 0.8V, VREF can already output 0.74V, and when the power supply voltage VDD is 1.1V, VREF can already stably output 0.8V. This achieves the goal of outputting a reference voltage at low power supply voltages. This voltage can provide a reference for circuits such as PORs and LDOs, ensuring more stable system control.

[0090] While embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various equivalent changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for implementing a high-performance reference voltage, characterized in that It includes the following steps: S1: Construct an infrastructure suitable for operating at a low power supply voltage. Select devices compatible with the CMOS process and build a circuit in a preset connection manner. This infrastructure starts and maintains the operating state at the preset power supply voltage, and at the same time determines the initial operating parameters of each device in the low power supply voltage environment; S2: Design a low reference voltage value generation module. Through the analysis of device characteristics, use devices operating in a specific region, combined with the designed current mirror structure and resistor network. This module outputs a low reference voltage value that meets the design requirements, and during the output process, suppresses the factors affecting the stability of the reference voltage value; S3: Perform first-order temperature compensation. Use a combination of devices with different temperature characteristics to construct a temperature compensation circuit. In the circuit, adjust the current or voltage of the branch according to the influence law of temperature change on the reference voltage; S4: Perform second-order temperature compensation. For the reference voltage after first-order temperature compensation in the high-temperature or low-temperature section, use a specially designed second-order temperature compensation circuit. This circuit utilizes the different electrical characteristics of the device at different temperatures. When the temperature changes, adjust the output of the reference voltage through the change in the leakage current of the device; S5: Design an ultra-low-power operational amplifier OP. Combine high-voltage native devices with zero threshold for isolation protection, optimize the bias circuit design of the OP, and use resistors to generate the tail current to reduce the additional bias current generation circuit and lower the overall power consumption; S6: Integrate the low reference voltage and the first-order temperature compensation module, the second-order temperature compensation module, the ultra-low-power operational amplifier OP, and the devices in the core part of the reference voltage in a preset connection manner to form a complete high-performance reference voltage circuit.

2. The method for implementing a high-performance reference voltage according to claim 1, wherein, The low reference voltage value generation module uses the following formula for the low reference voltage value generation model: V ref-low = f(V gs1 , V gs2 , R a , R b , k1), where V gs1 and V gs2 are the gate-source voltages of two low-voltage NMOS devices operating in the subthreshold region, R a and R b are resistors with specific resistance values, k1 is a coefficient related to the current mirror ratio, the aspect ratio W / L of the low-voltage NMOS device ranges from 5 to 10, R a ranges from 10 kΩ to 20 kΩ, R b ranges from 5 kΩ to 10 kΩ, and k1 ranges from 0.8 to 1.

2.

3. The method for implementing a high-performance reference voltage according to claim 1, wherein The first-order temperature compensation module has a temperature compensation model formula: ΔV comp1 = g(T, I ptat1 , R c , R d , n1), where T is the ambient temperature, I ptat1 is a positive temperature coefficient current related to the first-order temperature compensation, R c and R d are resistors with specific temperature coefficients, n1 is a parameter related to the temperature compensation circuit structure, and the resistor R c has a temperature coefficient of 100 - 200 ppm / °C, R d has a temperature coefficient of -50 - -100 ppm / °C, and n1 ranges from 1.5 to 2.

5.

4. A method for implementing a high-performance reference voltage according to claim 1, characterized in that The second-order temperature compensation module, the second-order temperature compensation model formula is: ΔV comp2 = h(T, I leak , R e , k2), where T is the ambient temperature, I leak is the leakage current of a specific NMOS device at high temperature, R e is a specific resistor, k2 is a coefficient related to the gain of the second-order temperature compensation circuit, the specific NMOS device is a high-voltage NMOS, and the leakage current I leak varies in the range of 1 nA - 10 nA at high temperature, R e takes values between 5 kΩ - 15 kΩ, and k2 takes values of 0.5 - 1.

5.

5. A method for implementing a high-performance reference voltage according to claim 1, characterized in that The ultra-low power operational amplifier OP, the model formula for calculating the power consumption of OP is: P OP = I total × V supply－OP + I bias－OP × V bias－OP， Where, I total is the total working current of OP, V supply-OP is the supply voltage of OP, I bias-OP is the bias current of OP, V bias-OP is the bias voltage, I total is controlled at 20 nA - 50 nA, V supply－OP is 0.8 V - 1.2 V, I bias-OP is 5 nA - 15 nA, V bias-OP is 0.3 V - 0.6 V.

6. The method for implementing a high-performance reference voltage according to claim 1, characterized in that, In step S1, the formula for the basic infrastructure stability model is: S infra = j(V min , I min , R f , C f , k3), where V min is the minimum power supply voltage at which the basic infrastructure can work properly, I min is the minimum operating current, R f and C f are the feedback resistor and capacitor for stabilizing the circuit, k3 is a coefficient related to the infrastructure stability. The value of the feedback resistor R f is between 100 kΩ and 500 kΩ, the value of the feedback capacitor C f is between 1 pF and 5 pF, and the value of k3 is 0.6 - 1.

0.

7. A method for implementing a high-performance reference voltage according to claim 1, characterized in that In step S6, the formula of the inter-module interference suppression model is: I interference = m(V coupling , C coupling , f signal , R isolation , k4), where V coupling is the coupling voltage between modules, C coupling is the parasitic capacitance between modules, f signal is the signal frequency, R isolation is the resistor for isolation, k4 is the coefficient related to the interference suppression effect, and the value of the resistor R isolation for isolation is between 500Ω and 1000Ω.

8. A method for implementing a high-performance reference voltage according to claim 1, characterized in that, In the design of the low reference voltage and first-order temperature compensation module, the comprehensive model formula for generating the first-order temperature compensation in combination with the low reference voltage value is: V LVVREF-FOTC = n(V ref－low , ΔV comp1 , R g , R h , k5), where V ref-low is the low reference voltage value, ΔV comp1 is the first-order temperature compensation voltage, R g and R h are related resistors, k5 is the comprehensive adjustment coefficient, the value of the related resistor R g ranges from 8 kΩ to 12 kΩ, the value of R h ranges from 3 kΩ to 7 kΩ, and the value of k5 ranges from 0.9 to 1.

1.

9. A method for implementing a high-performance reference voltage according to claim 1, characterized in that In consideration of process deviations, the overall accuracy model formula for the reference voltage is: V error = p(ΔV process , ΔT, V ref－ideal , k6), where ΔV process is the change in the reference voltage caused by process deviations, ΔT is the temperature change range, V ref-ideal is the ideal reference voltage value, k6 is the coefficient related to accuracy compensation, ΔV process is controlled within ±5mV, ΔT is -40°C - 125°, and the value of k6 ranges from 0.8 to 1.

2.

10. A circuit adopting a method for realizing a high-performance reference voltage according to any one of claims 1-9, characterized in that, It includes a low reference voltage and a first-order temperature compensation module, a second-order temperature compensation module, an ultra-low-power operational amplifier OP module, and devices N1 and N2 in the core part of the reference voltage. Each module is connected in the preset connection manner described in step S6.

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